Datasheet AD9868 Datasheet (ANALOG DEVICES)

Broadband Modem Mixed-Signal Front End

FEATURES

Low cost 3.3 V CMOS MxFE for broadband modems 10-bit DAC converter

2×/4× interpolation filter

200 MSPS DAC update rate Integrated 17 dBm line driver with 19.5 dB gain control 10-bit, 80 MSPS, ADC converter

−12 dB to +48 dB low noise RxPGA (<3 nV/√Hz) Third-order, programmable low-pass filter Flexible digital data path interface

Half- and full-duplex operation

Pin compatible with the

Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in a 64-lead LFCSP_VQ

APPLICATIONS

Broadband wireline networking

GENERAL DESCRIPTION

The AD9868 is a mixed-signal front-end (MxFE®) IC for transceiver applications requiring Tx path and Rx path functionality with data rates up to 80 MSPS. A lower cost, pincompatible version of the current amplifier (IAMP) IOUTP functionality and limits the PLL VCO operating range of 80 MHz to 200 MHz.

The part is well-suited for half- and full-duplex applications. The digital interface is extremely flexible, allowing simple interfacing to digital back ends that support half- or full-duplex data transfers, often allowing the AD9868 to replace discrete ADC and DAC solutions. Power-saving modes include the ability to reduce power consumption of individual functional blocks or power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks, from a single crystal or clock source.

The Tx signal path consists of a 2×/4× low-pass interpolation filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate

AD9865

AD9865, the AD9868 removes the

AD9868

FUNCTIONAL BLOCK DIAGRAM

IOUTP+

IOUTP–

AD9868

ADC

80MSPS

2-4X

CLK SYNC.

0 TO 6dB Δ = 1dB

TxDAC

0 TO –7.5dB

2M CLK

MULTIPLIER

2-POLE

LPF

–6 TO +18dB Δ = 6dB

IAMP

0 TO –12dB

1-POLE

LPF

–6 TO +24dB Δ = 6dB

PWRDWN

MODE

TXEN/TXSYNC

TXCLK/T XQUIET

ADIO[9:4]/

Tx[5:0]

ADIO[3:0]/

Rx[5:0]

RXEN/RXSYNC

RXCLK

AGC[5:0]

PORT

SPI

PORT

Figure 1.

of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier (IAMP) capable of delivering 17 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The low noise RxPGA has a programmable gain range of

−12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/√Hz for gain settings beyond 36 dB. The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or it can be simply bypassed. The 10-bit ADC achieves excellent dynamic performance up to an 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.

The AD9868 provides a highly integrated solution for many broadband modems. It is available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature range (−40°C to +85°C).

IOUT N+

IOUT N–

CLKOUT1 CLKOUT2

OSCIN XTAL

RX+

RX–

6733-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9868

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Tx Path Specifications.................................................................. 3

Rx Path Specifications.................................................................. 4

Power Supply Specifications........................................................ 6

Digital Specifications ................................................................... 7

Serial Port Timing Specifications............................................... 7

Half-Duplex Data Interface (ADIO Port) Timing

Specifications ................................................................................ 8

Full-Duplex Data Interface (Tx and Rx Port) Timing

Specifications ................................................................................ 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics ..............................................................9

Explanation of Test Levels........................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Serial Port ........................................................................................12

Serial Port Interface (SPI)..........................................................14

Digital Interface .............................................................................. 16

Half-Duplex Mode ..................................................................... 16

Full-Duplex Mode...................................................................... 17

RxPGA Control .......................................................................... 19

TxPGA Control .......................................................................... 20

Transmit Path.................................................................................. 21

Digital Interpolation Filters...................................................... 21

TxDAC and IAMP Architecture.............................................. 22

Tx Programmable Gain Control.............................................. 23

TxDAC Output Operation........................................................ 23

IAMP Current-Mode Operation.............................................. 23

Receive Path ....................................................................................24

Rx Programmable Gain Amplifier........................................... 24

Low-Pass Filter............................................................................ 25

Analog-to-Digital Converter (ADC)....................................... 26

AGC Timing Considerations.................................................... 27

Clock Synthesizer ........................................................................... 28

Power Control and Dissipation.................................................... 30

Power-Down ............................................................................... 30

Half-Duplex Power Savings ...................................................... 30

Power Reduction Options......................................................... 31

Power Dissipation....................................................................... 33

Mode Select upon Power-Up and Reset.................................. 33

Analog and Digital Loopback Test Modes.............................. 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9868

SPECIFICATIONS

Tx PATH SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, f

= 50 MHz, f

OSCIN

= 200 MHz, R

DAC

= 2.0 kΩ, unless otherwise noted.

SET

Table 1.

Parameter Temp Test Level

Min Typ Max Unit

TxDAC DC CHARACTERISTICS

Resolution Full 10 Bits Update Rate Full II 200 MSPS Full-Scale Output Current (IOUTP_FS) Full IV 2 25 mA Gain Error

25°C I ±2 % FS Offset Error 25°C V 2 μA Voltage Compliance Range Full −1 +1.5 V

TxDAC GAIN CONTROL CHARACTERISTICS

Minimum Gain 25°C V −7.5 dB Maximum Gain 25°C V 0 dB Gain Step Size 25°C V 0.5 dB Gain Step Accuracy 25°C IV Monotonic dB Gain Range Error 25°C V ±2 dB

TxDAC AC CHARACTERISTICS

Fundamental 0.5 dBm Signal-to-Noise and Distortion (SINAD) Full IV 62.0 63.1 dBc Signal-to-Noise Ratio (SNR) Full IV 62.5 63.2 dBc Total Harmonic Distortion (THD) Full IV −77.7 −67.0 dBc Spurious-Free Dynamic Range (SFDR) Full IV 67.1 79.3 dBc

IAMP DC CHARACTERISTICS

IOUTN Full-Scale Current = IOUTN+ + IOUTN− Full IV 2 105 mA AC Voltage Compliance Range Full IV 1 3.9 V

IAMPN AC CHARACTERISTICS

Fundamental 25°C 13 dBm IOUTN SFDR (Third Harmonic) Full IV 43.3 45.2 dBc

REFERENCE

Internal Reference Voltage

25°C I 1.23 V Reference Error Full V 0.7 3.4 % Reference Drift Full V 30 ppm/oC

Tx DIGITAL FILTER CHARACTERISTICS (2× Interpolation)

Latency (Relative to 1/f

−0.2 dB Bandwidth Full V 0.2187 f

−3 dB Bandwidth Full V 0.2405 f Stop-Band Rejection (0.289 f

) Full V 43 Cycles

DAC

OUT/fDAC

to 0.711 f

DAC

) Full V 50 dB

DAC

Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation)

Latency (Relative to 1/f

−0.2 dB Bandwidth Full V 0.1095 f

−3 dB Bandwidth Full V 0.1202 f Stop Band Rejection (0.289 f

) Full V 96 Cycles

DAC

OUT/fDAC

OSCIN

to 0.711 f

) Full V 50 dB

OSCIN

PLL CLK MULTIPLIER

OSCIN Frequency Range

PLL M Factor Set to 2 Full IV 40 80 MHz PLL M Factor Set to 4 Full IV 20 50 MHz

PLL M Factor Set to 8 Full IV 10 25 MHz Internal VCO Frequency Range Full IV 80 200 MHz Duty Cycle Full II 40 60 %

Rev. 0 | Page 3 of 36

AD9868

Parameter Temp Test Level

Min Typ Max Unit

OSCIN Impedance 25°C V 10||03 ΜΩ||pF CLKOUT1 Jitter CLKOUT2 Jitter CLKOUT1 and CLKOUT2 Duty Cycle

See the Explanation of Test Levels section.

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).

TxDAC IOUTP_FS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, f

IOUTN full-scale current = 80 mA, f

Use external amplifier to drive additional load.

Internal VCO operates at 200 MHz; set to divide-by-1.

Because CLKOUT2 is a divided-down version of OSCIN, its jitter is typically equal to OSCIN.

CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.

= 80 MHz, f

OSCIN

=160 MHz, 2x interpolation.

DAC

25°C III 12 ps rms 25°C III 6 ps rms Full III 45 55 %

= 5 MHz, 4x interpolation.

OUT

Rx PATH SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, half- or full-duplex operation with CONFIG = 0 default power bias settings, unless otherwise noted.

Table 2.

Parameter Temp Test Level1Min Typ Max Unit

Rx INPUT CHARACTERISTICS

Input Voltage Span

RxPGA Gain = −10 dB Full III 6.33 V p-p

RxPGA Gain = +48 dB Full III 8 mV p-p Input Common-Mode Voltage 25°C III 1.3 Differential Input Impedance 25°C III 400||4.0 Ω||pF Input Bandwidth with RxLPF Disabled, RxPGA = 0 dB 25°C III 53 MHz Input Voltage Noise Density

RxPGA Gain = 36 dB, f

RxPGA Gain = 48 dB, f

= 26 MHz 25°C III 3.0 nV/√Hz

−3 dBF

= 26 MHz 25°C III 2.4 nV/√Hz

−3 dBF

RxPGA CHARACTERISTICS

Minimum Gain 25°C III −12 dB Maximum Gain 25°C III 48 dB Gain Step Size 25°C III 1 dB Gain Step Accuracy 25°C III Monotonic dB Gain Range Error 25°C III 0.5 dB

RxLPF CHARACTERISTICS

Cutoff Frequency (f Attenuation at 55.2 MHz with f

) Range Full III 15 35 MHz

−3 dBF

= 21 MHz 25°C III 20 dB

−3 dBF

Pass-Band Ripple 25°C III ±1 dB Settling Time

5 dB RxPGA Gain Step @ f

60 dB RxPGA Gain Step @ f

= 50 MSPS 25°C III 20 ns

ADC

= 50 MSPS 25°C III 100 ns

ADC

ADC DC CHARACTERISTICS

Resolution N/A N/A 10 Bits Conversion Rate Full II 20 80 MSPS

Rx PATH LATENCY2

Full-Duplex Interface Full V 10.5 Cycles Half-Duplex Interface Full V 10.0 Cycles

Rx PATH COMPOSITE AC PERFORMANCE @ f

= 50 MSPS

ADC

RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)

Signal-to-Noise and Distortion (SINAD) 25°C III 43.7 dBc

Total Harmonic Distortion (THD) 25°C III −71 dBc

Rev. 0 | Page 4 of 36

AD9868

Parameter Temp Test Level1Min Typ Max Unit

RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)

Signal-to-Noise Ratio (SNR) 25°C III 59 dBc Total Harmonic Distortion (THD) 25°C III −67.2 dBc

RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)

Signal-to-Noise and Distortion (SINAD) Full IV 58 59 dBc Total Harmonic Distortion (THD) Full IV −66 −62.9 dBc

Rx PATH COMPOSITE AC PERFORMANCE @ f

= 80 MSPS4

ADC

RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)

Signal-to-Noise Ratio (SNR) 25°C III 41.8 dBc Total Harmonic Distortion (THD) 25°C III −67 dBc

RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)

Signal-to-Noise Ratio (SNR) 25°C III 58.6 dBc Total Harmonic Distortion (THD) 25°C III −62.9 dBc

RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)

Signal-to-Noise Ratio (SNR) 25°C II 58.9 59.6 dBc Total Harmonic Distortion (THD) 25°C II −69.7 −59.8 dBc

Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output)

RxPGA Gain = 40 dB

IOUTP± Pins to RX± Pins 25°C III 83 dBc

RxPGA Gain = 0 dB

IOUTP± Pins to RX± Pins 25°C III 123 dBc

See the Explanation of Test Levels section.

Includes RxPGA, ADC pipeline, and ADIO bus delay relative to f

fIN = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 15.5 MHz with Register 0x08 = 0x80.

fIN = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 26 MHz with Register 0x08 = 0x80.

ADC

Rev. 0 | Page 5 of 36

AD9868

POWER SUPPLY SPECIFICATIONS

AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V, R

Table 3.

Parameter Temp Test Level2 Min Typ Max Unit

SUPPLY VOLTAGES

AVDD Full V 3.135 3.3 3.465 V CLKVDD Full V 3.0 3.3 3.6 V DVDD Full V 3.0 3.3 3.6 V DRVDD Full V 3.0 3.3 3.6 V IS_TOTAL (Total Supply Current) Full II 406 475 mA

POWER CONSUMPTION

AVDD

DVDD

+ I + I

(Analog Supply Current) Full IV 311 342 mA

CLKVDD

(Digital Supply Current) Full IV 95 133 mA

DRVDD

POWER CONSUMPTION (Half-Duplex Operation with f

Tx Mode

AVDD

DVDD

+ I + I

25°C IV 112 130 mA

CLKVDD

25°C IV 46 49.5 mA

DRVDD

Rx Mode

+ I

AVDD

+ I

DVDD

POWER CONSUMPTION OF FUNCTIONAL BLOCKS1 (I

25°C IV 225 253 mA

CLKVDD

25°C IV 36.5 39 mA

DRVDD

AVDD

RxPGA and LPF 25°C III 87 mA ADC 25°C III 108 mA TxDAC 25°C III 38 mA IAMP (Programmable) 25°C III 10 100 mA Reference 25°C III 170 mA CLK PLL and Synthesizer 25°C III 107 mA

MAXIMUM ALLOWABLE POWER DISSIPATION Full IV 1.66 W STANDBY POWER CONSUMPTION

IS_TOTAL (Total Supply Current) Full

POWER-DOWN DELAY (Using PWRDWN Pin)

RxPGA and LPF 25°C III 440 ns ADC 25°C III 12 ns TxDAC 25°C III 20 ns IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 27 ns

POWER-UP DELAY (Using PWRDWN Pin)

RxPGA and LPF 25°C III 7.8 μs ADC 25°C III 88 ns TxDAC 25°C III 13 μs IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 20 μs

Default power-up settings for MODE = high and CONFIG = low, IOUTP_FS = 20 mA, does not include IAMP current consumption, which is application dependent.

See the Explanation of Test Levels section.

Default power-up settings for MODE = low and CONFIG = low.

= 2 kΩ, full-duplex operation with f

SET

= 50 MSPS)

DATA

+ I

CLKVDD

)

= 80 MSPS1, unless otherwise noted.

DATA

13 mA

Rev. 0 | Page 6 of 36

AD9868

DIGITAL SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, R

= 2 kΩ, unless otherwise noted.

SET

Table 4.

Parameter Temp Test Level

Min Typ Max Unit

CMOS LOGIC INPUTS

High Level Input Voltage Full VI DRVDD − 0.7 V Low Level Input Voltage Full VI 0.4 V Input Leakage Current 12 μA Input Capacitance Full VI 3 pF

CMOS LOGIC OUTPUTS (C

= 5 pF)

LOAD

High Level Output Voltage (IOH = 1 mA) Full VI DRVDD − 0.7 V Low Level Output Voltage (IOH = 1 mA) Full VI 0.4 V Output Rise/Fall Time

High Strength Mode and C Low Strength Mode and C High Strength Mode and C Low Strength Mode and C

= 15 pF Full VI 1.5/2.3 ns

LOAD

= 15 pF Full VI 1.9/2.7 ns

LOAD

= 5 pF Full VI 0.7/0.7 ns

LOAD

= 5 pF Full VI 1.0/1.0 ns

LOAD

RESET

Minimum Low Pulse Width (Relative to f

See the Explanation of Test Levels section.

) 1 Clock cycles

ADC

SERIAL PORT TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 5.

Parameter Temp Test Level

Min Typ Max Unit

WRITE OPERATION (See Figure 5)

SCLK Clock Rate (f

) Full IV 32 MHz

SCLK

SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (t

) Full IV 14 ns

LOW

SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SEN to SCLK Setup Time (tS)

SCLK to SEN Hold Time (tH)

Full IV 14 ns Full IV 0 ns

READ OPERATION (See Figure 6 and Figure 7)

SCLK Clock Rate (f

) Full IV 32 MHz

SCLK

SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (t

) Full IV 14 ns

LOW

SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SCLK to SDIO (or SDO) Data Valid Time (tDV) Full IV 14 ns SEN to SDIO Output Valid to High-Z (tEZ)

See the Explanation of Test Levels section.

Full IV 2 ns

Rev. 0 | Page 7 of 36

AD9868

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 6.

Parameter Temp Test Level

READ OPERATION2 (See Figure 9)

Min Typ Max Unit

Output Data Rate Full II 20 80 MSPS Three-State Output Enable Time (t Three-State Output Disable Time (t

) Full II 3 ns

PZL

) Full II 3

PLZ

Rx Data Valid Time (tVT) Full II 1.5 ns Rx Data Output Delay (tOD) Full II 4 ns

WRITE OPERATION (See Figure 8)

Input Data Rate (2× Interpolation) Full II 40 80 MSPS Input Data Rate (4× Interpolation) Full II 20 50 MSPS Tx Data Setup Time (tDS) Full II 1 ns Tx Data Hold Time (tDH) Full II 2.5 ns Latch Enable Time (tEN) Full II 3 ns Latch Disable Time (t

See the Explanation of Test Levels section.

= 5 pF for digital data outputs.

LOAD

) Full II 3 ns

DIS

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter Temp Test Level

Tx PATH INTERFACE (See Figure 12)

Input Nibble Rate (2× Interpolation) Full II 80 160 MSPS Input Nibble Rate (4× Interpolation) Full II 40 100 MSPS Tx Data Setup Time (tDS) Full II 2.5 ns Tx Data Hold Time (tDH) Full II 1.5 ns

Rx PATH INTERFACE2 (See Figure 13)

Output Nibble Rate Full II 40 160 MSPS Rx Data Valid Time (tDV) Full II 3 ns Rx Data Hold Time (tDH) Full II 0 ns

See the Explanation of Test Levels section.

= 5 pF for digital data outputs.

LOAD

Min Typ Max Unit

Rev. 0 | Page 8 of 36

AD9868

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

ELECTRICAL

AVDD, CLKVDD Voltage 3.9 V maximum DVDD, DRVDD Voltage 3.9 V maximum RX+, RX−, REFT, REFB −0.3 V to AVDD + 0.3 V IOUTP+, IOUTP− −1.5 V to AVDD + 0.3 V IOUTN+, IOUTN− −0.3 V to +3.9 V OSCIN, XTAL −0.3 V to CLVDD + 0.3 V REFIO, REFADJ −0.3 V to AVDD + 0.3 V Digital Input and Output Voltage −0.3 V to DRVDD + 0.3 V Digital Output Current 5 mA maximum

ENVIRONMENTAL

Operating Temperature Range

(Ambient) Maximum Junction Temperature 125°C Lead Temperature (Soldering, 10 sec) 150°C Storage Temperature Range (Ambient) −65°C to +150°C

−40°C to +85°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance: 64-lead LFCSP (4-layer board).

= 24°C/W (paddle soldered to ground plane, 0 LPM air).

= 30.8°C/W (paddle not soldered to ground plane, 0 LPM air).

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and guaranteed by design

and characterization at specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C and guaranteed by design

and characterization for industrial temperature range.

ESD CAUTION

Rev. 0 | Page 9 of 36

AD9868

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVDD

DRVSS

PWRDWN

CLKOUT2

DVDD

DVSS

CLKVDD

OSCIN

XTAL

CLKVSS

CONFIG

ADIO9/Tx[5]

ADIO8/Tx[4]

ADIO7/Tx[3]

ADIO6/Tx[2]

ADIO5/Tx[1]

ADIO4/Tx[0]

ADIO3/Rx[5]

ADIO2/Rx[4]

ADIO1/Rx[3]

ADIO0/Rx[2]

NC/Rx[1]

NC/Rx[0]

RXEN/RXSYNC

TXEN/TXSYNC

XCLK/TXQUIET

RXCLK

MODE

63 62 61 60 595857 56 55 54 535251 50

PIN 1 IDENTIFIER

AD9868

TOP VIEW

(Not to Scale)

IOUTP+

IOUTN+

IOUTP–

AVSS

IOUTN–

AVS S

AVD D

REFIO

REFADJ

AVD D

AVSS

RX+

RX–

AVSS

AVD D

AVSS

REFT

3217 18 19 20 21 22 23 24 25 26 27 282930 31

SDIO

DRVSS

DRVDD

CLKOUT 1

SCLK

PGA[4]

PGA[3]

PGA[2]

PGA[1]

GAIN/PGA[5]

AVSS

REFB

RESET

PGA[0]

SEN

SDO

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Mode

Description

1 ADIO9 HD MSB of ADIO Buffer. Tx[5] FD MSB of Tx Nibble Input. 2 to 5 ADIO8 to ADIO5 HD Bit 8 to Bit 5 of ADIO Buffer. Tx[4:1] FD Bit 4 to Bit 1 of Tx Nibble Input. 6 ADIO4 HD Bit 4 of ADIO Buffer. Tx[0] FD LSB of Tx Nibble Input. 7 ADIO3 HD Bit 3 of ADIO Buffer. Rx[5] FD MSB of Rx Nibble Output. 8, 9 ADIO2, ADIO1 HD Bit 2 to Bit 1 of ADIO Buffer. Rx[4:3] FD Bit 4 to Bit 3 of Rx Nibble Output. 10 ADIO0 HD LSB of ADIO Buffer. Rx[2] FD Bit 2 of Rx Nibble Output. 11 NC HD No Connect. Rx[1] FD Bit 1 of Rx Nibble Output. 12 NC HD No Connect. Rx[0] FD LSB of Rx Nibble Output. 13 RXEN HD ADIO Buffer Control Input. RXSYNC FD Rx Data Synchronization Output. 14 TXEN HD Tx Path Enable Input. TXSYNC FD Tx Data Synchronization Input. 15 TXCLK HD ADIO Sample Clock Input.

TXQUIET

FD Fast TxDAC/IAMP Power-Down.

16 RXCLK HD ADIO Request Clock Input. FD Rx and Tx Clock Output at 2 x f

ADC

06733-002

Rev. 0 | Page 10 of 36

AD9868

Pin No. Mnemonic Mode

Description

17, 64 DRVDD Digital Output Driver Supply Input. 18, 63 DRVSS Digital Output Driver Supply Return. 19 CLKOUT1

/N Clock Output (R = 1, 2, or 3).

ADC

20 SDIO Serial Port Data Input/Output. 21 SDO Serial Port Data Output. 22 SCLK Serial Port Clock Input. 23

SEN

Serial Port Enable Input. 24 GAIN FD Tx Data Port (Tx[5:0]) Mode Select. PGA[5] HD or FD MSB of PGA Input Data Port. 25 to 29 PGA[4:0] HD or FD Bit 4 to Bit 0 of PGA Input Data Port. 30

RESET

Reset Input (Active Low). 31, 34, 36, 39, 44, 47, 48 AVSS Analog Supply Return.

32, 33 REFB, REFT ADC Reference Decoupling Nodes. 35, 40, 43 AVDD Analog Power Supply Input. 37, 38 RX−, RX+ Receive Path − and + Analog Inputs. 41 REFADJ TxDAC Full-Scale Current Adjust. 42 REFIO TxDAC Reference Input/Output. 45, 49 NC Do Not Connect; Leave Open. 46 IOUTN− −Tx Mirror Current Output Sink. 50 IOUTN+ +Tx Mirror Current Output Sink. 51 IOUTP− −TxDAC Current Output Source. 52 IOUTP+ +TxDAC Current Output Source. 53 MODE Digital Interface Mode Select Input, Low = HD, High = FD. 54 CONFIG Power-Up SPI Register Default Setting Input. 55 CLKVSS Clock Oscillator/Synthesizer Supply Return. 56 XTAL Crystal Oscillator Inverter Output. 57 OSCIN Crystal Oscillator Inverter Input. 58 CLKVDD Clock Oscillator/Synthesizer Supply. 59 DVSS Digital Supply Return. 60 DVDD Digital Supply Input. 61 CLKOUT2

/L Clock Output (L = 1, 2, or 4).

OSCIN

62 PWRDWN Power-Down Input.

HD = half-duplex mode; FD = full-duplex mode.

Rev. 0 | Page 11 of 36

AD9868

SERIAL PORT

Table 10. SPI Register Mapping

Power-Up Default Value

MODE = 0

Address

Bit

(Hex)

SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 7 4-Wire SPI 1 0 0 0 6 SPI LSB First 1 0 0 0 5 Software Reset 1 0 0 0 POWER CONTROL REGISTERS (Via PWRDWN Pin) 0x01 7 CLK Synthesizer 1 0 0 0 6 TxDAC/IAMP 1 0 0 0 5 Tx Digital 1 0 0 0 4 REF 1 0 0 0 3 ADC CML 1 0 0 0 2 ADC 1 0 0 0 1 PGA Bias 1 0 0 0 0 RxPGA 1 0 0 0 0x02 7 CLK Synthesizer 1 0 0 0 6 TxDAC/IAMP 1 1 1 1 5 Tx Digital 1 1 1 1 4 REF 1 1 1 1 3 ADC CML 1 1 1 1 2 ADC 1 1 1 1 1 PGA Bias 1 1 1 1 0 RxPGA 1 1 1 1 HALF-DUPLEX POWER CONTROL 0x03 7:3 Tx OFF Delay 5 0xFF 0xFF N/A 2 Rx_TXEN 1 0xFF 0xFF N/A 1 Tx PWRDN 1 0xFF 0xFF N/A 0 Rx PWRDN 1 0xFF 0xFF N/A PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL 0x04 4 f 3:2 PLL Divide-N 2 00 00 00 1:0 PLL Multiplier-M 2 01 10 01 0x05 2 OSCIN to RXCLK 1 0 0 0 1 Invert RXCLK 1 0 0 0 0 Disable RXCLK 1 0 0 0 0x06 7:6 CLKOUT2 Divide 2 01 01 01 5 CLKOUT2 Invert 1 0 0 0 4 CLKOUT2 Disable 1 0 0 0 3:2 CLKOUT1 Divide 2 01 01 01 1 CLKOUT1 Invert 1 0 0 0 0 CLKOUT1 Disable 1 0 0 0 Rx PATH CONTROL 0x07 5 Initiate Offset Cal. 1 0 0 0 4 Rx Low Power 1 0 1 0 0 Enable Rx LPF 1 1 1 1 0x08 7:0

Description Width

from PLL 1 0 0 0

ADC

Rx Filter Target Cutoff Frequency

8 0x80 0x61 0x80 Refer to the

(Half-Duplex)

CONFIG = 0 CONFIG = 1 CONFIG = 0

MODE = 1

(Full-Duplex)

Comments

Default SPI configuration is 3-wire, MSB first.

PWRDWN = 0. Default setting is for all blocks powered on.

PWRDWN = 1. Default setting is for all functional blocks powered down except PLL.

Default setting is for TXEN input to control power-on/power-off of Tx/Rx path. Tx driver delayed by 31 1/f

Full-duplex RXCLK normally at nibble rate.

Default setting is CLKOUT2 and CLKOUT1 enabled with divide-by-2.

Default setting has LPF on. Rx path at nominal power bias setting for CONFIG = 0 and low power for CONFIG = 1.

clock cycles.

DATA

Low-Pass Filter section.

Rev. 0 | Page 12 of 36

AD9868

Power-Up Default Value

MODE = 0

Address

Bit

(Hex)

Description Width

(Half-Duplex)

CONFIG = 0 CONFIG = 1 CONFIG = 0

Tx/Rx PATH GAIN CONTROL 0x09 6 Enable SPI Rx Gain 1 0x00 0x00 0x00 5:0 Rx Gain Code 6 0x00 0x00 0x00 0x0A 6 Enable SPI Tx Gain 1 0x7F 0x7F 0x7F 5:0 Tx Gain Code 6 0x7F 0x7F 0x7F TxPGA AND RxPGA CONTROL 0x0B 6 PGA Code for Tx 1 0 0 0 5 PGA Code for Rx 1 1 1 1 3 Force Gain Strobe 1 0 0 0 2 Rx Gain on Tx Port 1 0 0 1 1 3-Bit RxPGA Port 1 0 1 0 Tx DIGITAL FILTER AND INTERFACE 0x0C 7:6

Interpolation

2 01 00 01

Fac tor

Invert

1 0 0 0

TXEN/TXSYNC 3 Tx 5/5 Nibble 2 LS Nibble First

1 N/A N/A 0

1 N/A N/A 0 1 TXCLK Neg. Edge 1 0 0 0 0 Twos Complement 1 0 0 1 Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK 0x0D 7 Analog Loopback 1 0 0 0 6 Digital Loopback21 0 0 0 5 Rx Port Three-State 1 N/A N/A 0 4

Invert

1 0 0 0

RXEN/RXSYNC 3 Rx 5/5 Nibble 1 N/A N/A 0 2 LS Nibble First 1 N/A N/A 0 1 RXCLK Neg. Edge 1 0 0 0 0 Twos Complement 1 0 0 1 DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID 0x0E 7

Low Digital Drive

1 0 0 0

Strength 0 TxDAC Output 1 0 0 0 0x0F 3:0 REV ID Number 4 0x00 0x00 0x00 Tx IAMP GAIN AND BIAS CONTROL 0x10 7 Select Tx Gain 1 0x04 0x04 0x04 2:0 N 3 0x04 0x04 0x04 0x12 6:4 Standing Current 3 0x01 0x01 0x01 Standing current. 2:0

OFF1

Standing

3 0x01 0x01 0x01

Current 0x13

7:5 CPGA Bias Adjust 3

0x00 0x00 0x00 4:3 SPGA Bias Adjust 2 2:0 ADC Bias Adjust 4

Bits that are undefined should always be assigned a 0.

Full-duplex only.

MODE = 1

(Full-Duplex)

Comments

Default setting is for hardware Rx gain code via PGA or Tx data port.

Default setting is for Tx gain code via SPI control.

Default setting is RxPGA control active via PGA port.

Default setting is 2× interpolation with LPF response. Data format is straight binary for half-duplex and twos complement for full-duplex interface.

Data format is straight binary for half-duplex and twos complement for full-duplex interface. Analog loopback: ADC Rx data fed back to TxDAC. Digital loopback: Tx input data to Rx output port.

Default setting is for high drive strength and IAMP enabled.

N = 0, 1, 2, 3, 4.

Current bias setting for Rx path’s functional blocks. Refer to the Reduction Options

section.

Power

Rev. 0 | Page 13 of 36

AD9868

REGISTER MAP DESCRIPTION

The AD9868 contains a set of programmable registers (see Table 10 ) that are used to optimize its numerous features, interface options, and performance parameters from its default register settings. Registers pertaining to similar functions have been grouped together and assigned adjacent addresses to minimize the update time when using the multibyte serial port interface (SPI) read/write feature. Bits that are undefined within a register should be assigned a 0 when writing to that register.

An 8-bit instruction header must accompany each read and write operation. The instruction header is shown in The MSB is an R/

indicator bit with logic high indicating a

Table 12.

read operation. The next two bits, N1 and N0, specify the number of bytes (one to four bytes) to be transferred during the data transfer cycle. The remaining five bits specify the address bits to be accessed during the data transfer portion. The data bits immediately follow the instruction header for both read and write operations.

The default register settings are intended to allow some applications to operate without using an SPI. The AD9868 can be configured to support a half- or full-duplex digital interface via the MODE pin, with each interface having two possible default register settings determined by the setting of the CONFIG pin.

For instance, applications that need to use only the Tx or Rx path functionality can configure the AD9868 for a half-duplex interface (MODE = 0), and use the TXEN pin to select between the Tx or Rx signal path with the unused path remaining in a reduced power state. The CONFIG pin can be used to select the default interpolation ratio of the Tx path and RxPGA gain mapping.

SERIAL PORT INTERFACE (SPI)

The serial port of the AD9868 has 3-wire or 4-wire SPI capability allowing read/write access to all registers that configure the device’s internal parameters. Registers pertaining to the SPI are listed in Table 11 . The default 3-wire serial communication port consists of a clock (SCLK), serial port enable ( data (SDIO) signal. and write cycle. When stated. The inputs to SCLK,

SEN

is an active low, control gating, read

SEN

is high, SDO and SDIO are three-

SEN

trigger with a nominal hysteresis of 0.4 V centered about DRVDD/2. The SDO pin remains three-stated in a 3-wire SPI interface.

Table 11. SPI Registers Pertaining to SPI Options

Address (Hex) Bit Description

0x00 7 Enable 4-wire SPI. 6 Enable SPI LSB first.

A 4-wire SPI can be enabled by setting the 4-wire SPI bit high, causing the output data to appear on the SDO pin instead of on the SDIO pin. The SDIO pin serves as an input-only throughout the read operation. Note that the SDO pin is active only during the transmission of data and remains three-stated at any other time.

SEN

), and a bidirectional

, and SDIO contain a Schmitt

Table 12. Instruction Header Information

MSB

LSB

17 16 15 14 13 12 11 10

R/W

N1 N0 A4 A3 A2 A1 A0

The AD9868 serial port can support both MSB (most significant bit) first and LSB (least significant bit) first data formats.

Figure 3 illustrates how the serial port words are built for the MSB first and

Figure 4 illustrates LSB first modes. The bit order is controlled by the SPI LSB first bit (Register 0x00, Bit 6). The default value is 0, MSB first. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the last address to be accessed. The AD9868 automatically decrements the address for each successive byte required for the multibyte communication cycle.

SEN

SCLK

SDATA

SEN

SCLK

SDATA

INSTRUCTIO N CYCLE

Figure 3. SPI Timing, MSB First

INSTRUCTION CYCLE

A1A0 A2 A3 A4 N2 N1 R/W D01D1

Figure 4. SPI Timing, LSB First

DATA TRANSFER CYCLE

A1 A0A2A3A4N2N1R/W D71D6

DATA TRANSFER CYCLE

D6ND7

D0ND1

6733-003

6733-004

When the SPI LSB first bit is set high, the serial port interprets both instruction and data bytes LSB first. Multibyte data transfers in LSB format can be completed by writing an instruction byte that includes the register address of the first address to be accessed. The AD9868 automatically increments the address for each successive byte required for the multibyte communication cycle.

Rev. 0 | Page 14 of 36

AD9868

Figure 5 illustrates the timing requirements for a write opera-

SEN

tion to the SPI port. After the serial port enable (

) signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of the clock (SCLK). To initiate a write operation, the read/not-write bit is set low. After the instruction header is read, the eight data bits pertaining to the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles. If a multibyte communication cycle is specified, the destination address is decremented (MSB first) and shifts in another eight bits of data. This process repeats until all the bytes specified in the instruction header (N1 bit, N0 bit) are shifted into the SDIO pin.

SEN

must remain low during the data transfer operation, only going high after the last bit is shifted into the SDIO pin.

SEN

SCLK

SDIO

SCLK

R/W

LOW

N1 N0

Figure 5. SPI Write Operation Timing

Figure 6 illustrates the timing for a 3-wire read operation to the

SEN

SPI port. After

goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles. If a multibyte communication cycle is specified in the instruction header, a similar process as previously described for a multibyte SPI write operation applies. The SDO pin remains three-stated in a 3-wire read operation.

Figure 7 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation with the exception of the data appearing at the SDO pin, while the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times.

6733-005

SEN

CLK

SDIO

SCLK

R/W

LOW

06733-006

Figure 6. SPI 3-Wire Read Operation Timing

SEN

SCLK

SDIO

SDO

SCLK

R/W

LOW

06733-007

Figure 7. SPI 4-Wire Read Operation Timing

Rev. 0 | Page 15 of 36

AD9868

DIGITAL INTERFACE

The digital interface port is configurable for half-duplex or fullduplex operation by pin strapping the MODE pin low or high, respectively. In half-duplex mode, the digital interface port becomes a 10-bit bidirectional bus called the ADIO port. In full-duplex mode, the digital interface port is divided into two 6-bit ports called Tx[5:0] and Rx[5:0] for simultaneous Tx and Rx operations. In this mode, data is transferred between the ASIC and AD9868 in 6-bit (or 5-bit) nibbles. The AD9868 also features a flexible digital interface for updating the RxPGA and TxPGA gain registers via a 6-bit PGA port or Tx[5:0] port for fast updates, or via the SPI port for slower updates. See the RxPGA Control section for more information.

HALF-DUPLEX MODE

The half-duplex mode is selected when the MODE pin is tied low. In this mode, the bidirectional ADIO port is typically shared in burst fashion between the transmit path and receive path. Two control signals, TXEN and RXEN, from a DSP (or digital ASIC) control the bus direction by enabling the ADIO port’s input latch and output driver, respectively. Two clock signals are also used, TXCLK to latch the Tx input data, and RXCLK to clock the Rx output data. The ADIO port can be disabled by setting TXEN and RXEN low (default setting), thus allowing it to be connected to a shared bus.

Internally, the ADIO port consists of an input latch for the Tx path in parallel with an output latch with three-state outputs for the Rx path. TXEN is used to enable the input latch; RXEN is used to three-state the output latch. A five-sample-deep FIFO is used on the Tx and Rx paths to absorb any phase difference between the AD9868 internal clocks and the externally supplied clocks (TXCLK, RXCLK). The ADIO bus accepts input datawords into the transmit path when the TXEN pin is high, the RXEN pin is low, and a clock is present on the TXCLK pin, as shown in

The Tx interpolation filter(s) following the ADIO port can be flushed with zeros if the clock signal into the TXCLK pin is present for 33 clock cycles after TXEN goes low. Note that the data on the ADIO bus is irrelevant over this interval.

TXCLK

TXEN

ADIO[9:0]

RXEN

Figure 8.

TX0

Figure 8. Transmit Data Input Timing Diagram

TX2

TX3 TX4TX1

DIS

06733-008

The output from the receive path is driven onto the ADIO bus when the RXEN pin is high and when a clock is present on the RXCLK pin. While the output latch is enabled by RXEN, valid data appears on the bus after a 6-clock-cycle delay due to the internal FIFO delay. Note that Rx data is not latched back into the Tx path if TXEN is high during this interval with TXCLK present. The ADIO bus becomes three-stated once the RXEN pin returns low.

RXCLK

RXEN

ADIO[9:0]

Figure 9 shows the receive path output timing.

PZL

Figure 9. Receive Data Output Timing Diagram

RX0 RX1 RX2 RX3

PLZ

To add flexibility to the digital interface port, several programming options are available in the SPI registers. These options are listed in

Table 13. The default Tx and Rx data input formats are straight binary, but can be changed to twos complement. The default TXEN and RXEN settings are active high, but can be set to opposite polarities, thus allowing them to share the same control. In this case, the ADIO port can still be placed onto a shared bus by disabling its input latch via the control signal, and disabling the output driver via the SPI register. The clock timing can be independently changed on the transmit and receive paths by selecting either the rising or falling clock edge as the validating/sampling edge of the clock. Lastly, the output driver strength can be reduced for lower data rate applications.

Table 13. SPI Registers for Half-Duplex Interface

Address (Hex) Bit Description

0x0C 4 Invert TXEN. 1 TXCLK negative edge. 0 Twos complement. 0x0D 5 Rx port three-state. 4 Invert RXEN. 1 RXCLK negative edge. 0 Twos complement. 0x0E 7 Low digital drive strength.

The half-duplex interface can be configured to act as a slave or a master to the digital ASIC. An example of a slave configuration is shown in

Figure 10. In this example, the AD9868 accepts all the clock and control signals from the digital ASIC. Because the sampling clocks for the DAC and ADC are derived internally from the OSCIN signal, the TXCLK and RXCLK signals must be at exactly the same frequency as the OSCIN signal. The phase relationships among the TXCLK, RXCLK, and OSCIN signals can be arbitrary. If the digital ASIC cannot provide a low jitter clock source to OSCIN, use the AD9868 to generate the clock for its DAC and ADC and to pass the desired clock signal to the digital ASIC via CLKOUT1 or CLKOUT2.

06733-009

Rev. 0 | Page 16 of 36

AD9868

ADIO

[9:0]

RXEN

TXEN

TXCLK

RXCLK

OSCIN

ADIO [9:0]

RXEN

TXEN

TXCLK

RXCLK

CLKOUT1

OSCIN

AD9868

In either application, Tx data and Rx data are transferred

TO Tx DIGITAL FILTER

FROM Rx ADC

between the ASIC and AD9868 in 6-bit (or 5-bit) nibbles at twice the internal input/output word rates of the Tx interpolation filter and ADC. Note that the TxDAC update rate must not be less than the nibble rate. Therefore, the 2× or 4× interpolation filter must be used with a full-duplex interface.

The AD9868 acts as the master, providing RXCLK as an output clock that is used for the timing of both the Tx[5:0] and Rx[5:0] ports. RXCLK always runs at the nibble rate and can be inverted or disabled via an SPI register. Because RXCLK is derived from

06733-010

the clock synthesizer, it remains active provided that this functional block remains powered on. A buffered version of the signal appearing at OSCIN can also be directed to RXCLK by setting Bit 2 of Register 0x05. This feature allows the AD9868 to be completely powered down (including the clock synthesizer) while serving as the master.

The Tx[5:0] port operates in the following manner with the SPI register default settings:

1. Two consecutive nibbles of the Tx data are multiplexed

together to form a 10-bit data-word in twos complement format.

TO Tx DIGITAL FILTER

FROM Rx ADC

2. The clock appearing on the RXCLK pin is a buffered

version of the internal clock used by the Tx[5:0] port’s input latch with a frequency that is always twice the ADC sample rate (2 × f

ADC

3. Data from the Tx[5:0] port is read on the rising edge of this

sampling clock, as illustrated in the timing diagram shown in

Figure 12. Note that

TXQUIET

must remain high for the reconstructed Tx data to appear as an analog signal at the output of the TxDAC or IAMP.

4. The TXSYNC signal is used to indicate which word

belongs to which nibble. While TXSYNC is low, the first nibble of every word is read as the most significant nibble.

06733-011

The second nibble of that same word is read on the following TXSYNC high level as the least significant nibble. If TXSYNC is low for more than one clock cycle, the last transmit data is read continuously until TXSYNC is brought high for the second nibble of a new transmit word. This feature can be used to flush the interpolator filters with zeros. Note that the GAIN signal must be kept low during a Tx operation.

RXCLK

TXSYNC

Tx[5:0]

Tx1MSB Tx1L SB

Tx0LSB

Figure 12. Tx[5:0] Port Full-Duplex Timing Diagram

Tx2MSB

Tx3LSB

Tx 2 LSB

Tx3MSB

DIGITAL ASIC

Tx/Rx

DATA[9:0]

RXEN

TXEN

DACCLK

ADCCLK

CLKOUT

Figure 10. Example of a Half-Duplex Digital Interface

with AD9868 Serving as the Slave

Figure 11 shows a half-duplex interface with the AD9868 acting as the master, generating all the required clocks. CLKOUT1 provides a clock equal to the bus data rate that is fed to the ASIC as well as back to the TXCLK and RXCLK inputs. This interface has the advantage of reducing the digital ASIC pin count by three. The ASIC needs only to generate a bus control signal that controls the data flow on the bidirectional bus.

DIGITAL ASIC

Tx/Rx

DATA[9:0]

BUS_CTR

CLKIN

FROM CRYSTAL OR MASTER CLK

Figure 11. Example of a Half-Duplex Digital Interface

with AD9868 Serving as the Master

FULL-DUPLEX MODE

The full-duplex mode interface is selected when the MODE pin is tied high. It can be used for full- or half-duplex applications. The digital interface port is divided into two 6-bit ports called Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx operations for full-duplex applications. In half-duplex applications, the Tx[5:0] port can also be used to provide a fast update of the RxPGA during an Rx operation. This feature is enabled by default and can be used to reduce the required pin count of the ASIC (refer to

RxPGA Control section for details).

06733-012

Rev. 0 | Page 17 of 36

AD9868

The Rx[5:0] port operates in the following manner with the SPI register default settings:

1. Two consecutive nibbles of the Rx data are multiplexed

together to form a 10-bit data-word in twos complement format.

2. The Rx data is valid on the rising edge of RXCLK, as

illustrated in the timing diagram shown in

Figure 13.

3. The RXSYNC signal is used to indicate which word belongs

to which nibble. While RXSYNC is low, the first nibble of every word is transmitted as the most significant nibble. The second nibble of that same word is transmitted on the following RXSYNC high level as the least significant nibble.

RXCLK

RXSYNC

Rx[5:0]

Rx0LSB

Rx1MSB Rx1LSB

Rx2MSB

Rx3LSB

Rx3MSB

Figure 13. Full-Duplex Rx Port Timing

To add flexibility to the full-duplex digital interface port, several programming options are available in the SPI registers. These options are listed in

Table 14. The timing for the Tx[5:0] and/or Rx[5:0] ports can be independently changed by selecting either the rising or falling clock edge as the sampling/validating edge of the clock. Inverting RXCLK (via Bit 1 of Register 0x05) affects both the Rx and Tx interface because they both use RXCLK.

06733-013

The default Tx and Rx data input formats are twos complement, but can be changed to straight binary. The default TXSYNC and RXSYNC settings can be changed such that the first nibble of the word appears while either TXSYNC, RXSYNC, or both are high. In addition, the least significant nibble can be selected as the first nibble of the word (least significant nibble first). The output driver strength can also be reduced for lower data rate applications.

For the AD9868, the most significant nibble defaults to 6 bits, and the least significant nibble defaults to 4 bits. This can be changed so that the least significant nibble and most significant nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit (Bit 3 in Register 0x0C and Bit 3 in Register 0x0D), and use the Tx[5:1] and Rx[5:1] data pins.

Figure 14 shows a possible digital interface between an ASIC and the AD9868. The AD9868 serves as the master generating the required clocks for the ASIC. This interface requires that the ASIC reserve 16 pins for the interface, assuming a 6-bit nibble width and the use of the Tx port for RxPGA gain control. Note that the ASIC pin allocation can be reduced by 3 if a 5-bit nibble width is used and the gain (or gain strobe) of the RxPGA is controlled via the SPI port.

DIGITAL ASIC

OPTIONAL

Tx DATA[5:0]

AD9868/AD9869

GAIN

Tx[5:0]

DEMUX

10/12

TO RxPGA

TO Tx DIGITAL FILTER

Table 14. SPI Registers for Full-Duplex Interface

Address (Hex) Bit Description

0x05 2 OSCIN to RXCLK. 1 Invert RXCLK. 0 Disable RXCLK. 0x0B 2 Rx gain on Tx port. 0x0C 4 Invert TXSYNC. 3 Tx 5/5 nibble. 2 LS nibble first. 1 TXCLK negative edge. 0 Twos complement. 0x0D 5 Rx port three-state. 4 Invert RXSYNC. 3 Rx 5/5 nibble. 2 LS nibble first. 1 RXCLK negative edge. 0 Twos complement. 0x0E 7 Low digital drive strength.

Rx DATA[5:0]

RX_SYNC

TX_SYNC

CLKIN

FROM CRYSTAL OR MASTER CLK

Rx[5:0]

RXSYNC

TXSYNC

RXCLK

CLKOUT1

CLKOUT2

OSCIN

Figure 14. Example of a Full-Duplex Digital Interface

with Optional RxPGA Gain Control via Tx[5:0]

10/12

MUX

FROM RxADC

06733-014

Rev. 0 | Page 18 of 36

AD9868

RxPGA CONTROL

The AD9868 contains a digital PGA in the Rx path that is used to extend the dynamic range. The RxPGA can be programmed over −12 dB to +48 dB with 1 dB resolution using a 6-bit word, and with a 0 dB setting corresponding to a 2 V p-p input signal. The 6-bit word is fed into a look-up table (LUT) that is used to distribute the desired gain over three amplification stages within the Rx path. Upon power-up, the RxPGA gain register is set to its minimum gain of −12 dB. The RxPGA gain mapping is shown in

Table 15 lists the SPI registers pertaining to the RxPGA.

Table 15. SPI Registers for RxPGA Control

Address (Hex)

0x09 6 Enable RxPGA update via SPI. 5:0 RxPGA gain code. 0x0B 6 Select TxPGA via PGA[5:0]. 5 Select RxPGA via PGA[5:0]. 3 Enable software gain strobe, full-duplex. 2 Enable RxPGA update via Tx[5:0], full-duplex. 1 3-Bit RxPGA gain mapping, half-duplex.

The RxPGA gain register can be updated via the Tx[5:0] port, the PGA[5:0] port, or the SPI port. The first two methods allow fast updates of the RxPGA gain register and should be considered for digital AGC functions requiring a fast closed-loop response. The SPI port allows direct update and readback of the RxPGA gain register via Register 0x09 with an update rate limited to

1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6 of Register 0x09 must be set for a read or write operation.

Figure 15.

GAIN (dB)

–6

–12

6-BIT DIGITAL WORD-DECIMAL EQUIVALENT

Figure 15. Digital Gain Mapping of RxPGA

24 60 66

Bit Description

5442 4830 3661218

06733-015

Updating the RxPGA via the Tx[5:0] port is an option only in

full-duplex mode

. In this case, a high level on the GAIN pin2 with TXSYNC low programs the PGA setting on either the rising edge or falling edge of RXCLK, as shown in

Figure 16. The GAIN pin must be held high, TXSYNC must be held low, and gain data must be stable for one or more clock cycles to update the RxPGA gain setting.

A low level on the GAIN pin enables data to be fed to the digital interpolation filter. This interface should be considered when upgrading existing designs from the AD9875/AD9876 MxFE products or from half-duplex applications trying to minimize an ASIC pin count.

RXCLK

TXSYN

Tx [5:0 ]

GAIN

Figure 16. Updating RxPGA via Tx[5:0] in Full-Duplex Mode

GAIN

06733-016

Updating the RxPGA (or TxPGA) via the PGA[5:0] port is

an option for both the half-duplex

and full-duplex interface. The PGA port consists of an input buffer that passes the 6-bit data appearing at its input directly to the RxPGA (or TxPGA) gain register with no gating signal required. Bit 5 or Bit 6 of Register 0x0B is used to select whether the data updates the RxPGA or TxPGA gain register. In applications that switch between RxPGA and TxPGA gain control via PGA[5:0], be sure that the RxPGA (or TxPGA) is not inadvertently loaded with the wrong data during a transition. In the case of an RxPGA-to-TxPGA transition, first deselect the RxPGA gain register, update the PGA[5:0] port with the desired TxPGA gain setting, and then select the TxPGA gain register.

Note that a silicon bug exists with the full-duplex interface (MODE = 1), which requires that the GAIN/PGA[5] pin remains low for the digital Tx path to remain enabled. Fullduplex protocol applications must use the SPI port to control the Tx and Rx gain. Half-duplex protocol applications using the function can use an AND gate with

TXQUIET

and the PGA5 bit serving as inputs to ensure that the GAIN/PGA[5] pin remains low during a Tx operation.

Default setting for full-duplex mode (MODE = 1).

The gain strobe can also be set in software via Register 0x0B, Bit 3 for

continuous updating. This eliminates the requirement for the external gain signal, reducing the ASIC pin count by 1.

Default setting for half-duplex mode (MODE = 0).

Rev. 0 | Page 19 of 36

AD9868

TxPGA CONTROL

The AD9868 also contains a digital PGA in the Tx path distributed between the TxDAC and IAMP. The TxPGA is used to control the peak current from the TxDAC and IAMP over a

7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. A 6-bit word is used to set the TxPGA attenuation according to the mapping shown in applicable only when Bit 0 of Register 0x0E is set, and only when the 4 LSBs of the 6-bit gain word are relevant.

0 –1 –2 –3 –4 –5 –6 –7 –8 –9

–10 –11 –12 –13 –14

Tx ATTENUATION (dBFS)

–15 –16 –17 –18 –19 –20

0 8 16 24 32 40 48 56 64

Figure 17. Digital Gain Mapping of TxPGA

Figure 17. The TxDAC gain mapping is

TxDACs IOUTP OUTPUT HAS 7.5dB RANGE

IAMPs IOUTN OUTPUT HAS 19.5dB RANGE

6-BIT DIG ITAL CODE (Decimal Eq uival ent)

06733-017

The TxPGA register can be updated via the PGA[5:0] port or SPI port. The first method should be considered for fast updates of the TxPGA register. Its operation is similar to the description in the

RxPGA Control section. The SPI port allows direct update and readback of the TxPGA register via Register 0x0A with an update rate limited to 1.6 MSPS (SCLK = 32 MHz). Bit 6 of Register 0x0A must be set for a read or write operation.

Table 16 lists the SPI registers pertaining to the TxPGA. The TxPGA control register default setting is for minimum attenuation (0 dBFS) with the PGA[5:0] port disabled for Tx gain control.

Table 16. SPI Registers TxPGA Control

Address (Hex) Bit Description

0x0A 6 Enable TxPGA update via SPI. 5:0 TxPGA gain code. 0x0B 6 Select TxPGA via PGA[5:0]. 5 Select RxPGA via PGA[5:0]. 0x0E 0 TxDAC output (IAMP disabled).

Rev. 0 | Page 20 of 36

AD9868

–

TRANSMIT PATH

The transmit path of the AD9868 (or its related part, the AD9869) of a selectable digital 2×/4× interpolation filter, a 10-bit (or12-bit) TxDAC, and a current-output amplifier, IAMP (see Figure 18). Note that the additional two bits of resolution offered by the AD9869 result in a 10 dB to 12 dB reduction in the pass-band noise floor. The digital interpolation filter relaxes the Tx analog filtering requirements by simultaneously reducing the images from the DAC reconstruction process while increasing the analog filter’s transition band. The digital interpolation filter can also be bypassed, resulting in lower digital current consumption.

IOUTP+IOUTP–

ADIO[9:4]/

Tx[5:0]

ADIO[3:0]/

Rx[5:2]

2-4×

TxDAC

0 TO –7.5dB

IAMP

0 TO –12dB

IOUTN+ IOUTN

AD9868

TXEN/SYNC

TXCLK

Figure 18. Functional Block Diagram of Tx Path

DIGITAL INTERPOLATION FILTERS

The input data from the Tx port can be fed into a selectable 2×/4× interpolation filter. The interpolation factor for the digital filter is set via SPI Register 0x0C with the settings shown in Tabl e 17 . The maximum input word rate, f interpolation filter is 80 MSPS; the maximum DAC update rate is 200 MSPS. Therefore, applications with input word rates at or below 50 MSPS can benefit from 4× interpolation, whereas applications with input word rates between 50 MSPS and 80 MSPS can benefit from 2× interpolation.

Table 17. Interpolation Factor Set via SPI Register 0x0C

Bits 7:6] Interpolation Factor

00 4 01 2 10 Do not use 11 Do not use

The interpolation filter consists of two cascaded half-band filter stages with each stage providing 2× interpolation. The first stage filter consists of 43 taps. The second stage filter, operating at the higher data rate, consists of 11 taps. The normalized wideband and pass-band filter responses (relative f 2× low-pass interpolation filter and 4× low-pass interpolation filter are shown in Figure 19 and Figure 20, respectively.

DATA

, into the

) for the

DATA

06733-018

These responses also include the inherent sinc(x) from the TxDAC reconstruction process and can be used to estimate any post analog filtering requirements.

The pipeline delays of the 2× and 4× filter responses are

21.5 clock cycles and 24 clock cycles, respectively, relative to f

. The filter delay is also taken into consideration for

DATA

applications configured for a half-duplex interface with the halfduplex power-down mode enabled. This feature allows the user to set a programmable delay that powers down the TxDAC and IAMP only after the last Tx input sample has propagated through the digital filter. See the Power Control and Dissipation section for more details.

WIDE BAND

–10

–20

–30

PASS BAND

–40

–50

–60

WIDEBAND RESPONSE (dB)

–70

–80

–90

NORMALIZ ED FREQUENCY (Relative t o

0.500.25

–1.0dB @ 0.441

DATA

1.25 2.00

1.50

Figure 19. Frequency Response of 2× Interpolation Filter

)

DATA

2.5 4.0

3.0

–10

–20

–30

–40

–50

–60

WIDEBAND RESPONSE (dB)

–70

–80

–90

(Normalized to f

WIDE BAND

PASS BAND

–1.0dB @ 0.45

1.00.5

NORMALIZ ED FREQUENCY (Relative t o

DATA

Figure 20. Frequency Response of 4× Interpolation Filter

(Normalized to f

DATA

)

DATA

1.750.75 1.00 )

3.51.5 2.0 )

2.5

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

–2.5

2.5

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

–2.5

PASS-BAND RESPONSE (dB)

06733-019

PASS-BAND RESPONSE (dB)

06733-020

Rev. 0 | Page 21 of 36

AD9868

)

TxDAC AND IAMP ARCHITECTURE

The Tx path contains a TxDAC with a current amplifier, IAMP. The TxDAC reconstructs the output of the interpolation filter and sources a differential current output that can be directed to an external load or fed into the IAMP for further amplification. The TxDAC and IAMP peak current outputs are digitally programmable over a 0 dB to −7.5 dB and 0 dB to −19.5 dB range, respectively, in 0.5 dB increments. Note that this assumes default register settings for Register 0x10 and Register 0x11.

Applications demanding the highest spectral performance and/or lowest power consumption can use the TxDAC output directly. The TxDAC is capable of delivering a peak signal power-up to 10 dBm while maintaining respectable linearity performance. For power-sensitive applications requiring the highest Tx power efficiency, the TxDAC full-scale current output can be reduced to as low as 2 mA, and its load resistors sized to provide a suitable voltage swing that can be amplified by a low power, op amp-based driver.

Most applications requiring higher peak signal powers (up to 17 dBm) should use the IAMP. The IAMP can be configured as a current source for loads having a well-defined impedance (50 Ω or 75 Ω systems).

Figure 21 shows the equivalent schematic of the TxDAC and IAMP. The TxDAC provides a differential current output appearing at IOUTP+ and IOUTP−. The TxDAC can also be modeled as a differential current source generating a signaldependent ac current, when ΔI with two dc current sources, sourcing a standing current equal to I. The full-scale output current, IOUTP_FS, is equal to the sum of these standing current sources (IOUTP_FS = 2 × I).

REFADJ

0.1µF

SET

REFIO

IOUTP+

I + ΔI

I – ΔI

IOUTP–

Figure 21. Equivalent Schematic of TxDAC and IAMP

has a peak current of I along

N × (I + ΔI

N × (I – ΔI)

TxDAC

±ΔI

OFF1

IAMP

IOUTN–

IOUTN+

06733-021

The value of I is determined by the R pin along with the Tx path’s digital attenuation setting. With 0 dB attenuation, the value of I is

I = 16 × (1.23/R

For example, an R

) (1)

SET

value of 1.96 kΩ results in I equal to 10.0 mA

SET

with IOUTP_FS equal to 20.0 mA. Note that the REFIO pin provides a nominal band gap reference voltage of 1.23 V and should be decoupled to analog ground via a 0.1 μF capacitor.

The differential current output of the TxDAC is always connected to the IOUTP pins, but it can be directed to the IAMP by clearing Bit 0 of Register 0x0E. As a result, the IOUTP pins must remain completely open if the IAMP is to be used. The IAMP consists of programmable current mirrors providing a gain factor of N that is programmable from 0 to 4 in steps of 1 (via Bits[2:0] of Register 0x10 with a default setting of N = 4). Bit 7 of this register must be set to overwrite the default settings of this register. The maximum peak current per output is 100 mA and occurs when the TxDAC standing current, I, is set for 12.5 mA (IOUTP_FS = 25 mA).

Because the current mirrors consist of NMOS devices, they sink current. Therefore, each output pin requires a dc current path to a positive supply. The voltage output of each output pin is allowed to swing between 0.5 V and 3.9 V. Lastly, both the standing current, I, and the ac current, ΔI amplified by the gain factor (N) with the total standing current drawn from the positive supply being equal to

2 × (N) × I (2)

Programmable current sources, I used to improve the linearity performance under certain conditions by increasing their signal-to-standing current ratios. This feature provides a marginal improvement in distortion performance under large signal conditions when the peak ac current of the reconstructed waveform frequently approaches the dc standing current within the TxDAC (0 dBFS to −1 dBFS sine wave) causing the internal mirrors to turn off. However, the improvement in distortion performance diminishes as the crest factor (peak-to-rms ratio) of the ac signal increases. Most applications can disable these current sources (set to 0 mA via Register 0x12) to reduce the IAMP current consumption.

Table 18. SPI Registers for TxDAC and IAMP

Address (Hex) Bit Description 0x0E 0 TxDAC output. 0x10 7 Enable current mirror gain settings. 2:0

Primary path NMOS gain of 0 to 4 with ∆ = 1.

0x12 2:0 I

standing current.

OFF1

value at the REFADJ

SET

, from the TxDAC are

via Register 0x12, can be

OFF1

Rev. 0 | Page 22 of 36

AD9868

Tx PROGRAMMABLE GAIN CONTROL

TxPGA functionality is also available to set the peak output current from the TxDAC or IAMP. The TxDAC and IAMP are digitally programmable via the PGA[5:0] port or SPI over a 0 dB to −7.5 dB range and 0 dB to −19.5 dB range, respectively, in

0.5 dB increments.

The TxPGA can be considered as two cascaded attenuators with the TxDAC providing a 7.5 dB range in 0.5 dB increments, and the IAMP providing a 12 dB range in 6 dB increments. As a result, the IAMP composite 19.5 dB span is valid only if Register 0x10 remains at its default setting of 0x04. Modifying this register setting corrupts the LUT and results in an invalid gain mapping.

TxDAC OUTPUT OPERATION

The differential current output of the TxDAC is available at the IOUTP+ and IOUTP− pins, and the IAMP should be disabled by setting Bit 0 of Register 0x0E. Any load connected to these pins must be ground referenced to provide a dc path for the current sources. Figure 22 shows the outputs of the TxDAC driving a doubly terminated 1:1 transformer with its center tap tied to ground. The peak-to-peak voltage, V p-p, across R IOUTP+ to IOUTP−) is equal to 2 × I × (R and R

= RS = 50 Ω, V p-p is equal to 0.5 V with 1 dBm of peak

power being delivered to R

0.1µF

and 1 dBm being dissipated in RS.

SET

REFIO

REFADJ

IOUTP+

||RS). With I = 10 mA

1:1

IOUTP–

IOUTN+

(and

Optimum distortion performance can typically be achieved by performing both of the following:

• Limiting the peak positive V

IOUTP+

and V

IOUTP

to 0.8 V to

−

avoid onset of TxDAC output compression (TxDAC voltage compliance is around 1.2 V).

• Limiting V p-p seen at IOUTP+ and IOUTP− to less

than 1.6 V.

Applications demanding higher output voltage swings and power drive capabilities can benefit from using the IAMP.

IAMP CURRENT-MODE OPERATION

The IAMP can be configured for the current-mode operation (see Figure 23) for loads remaining relatively constant. In this mode, the IAMP delivers the signal-dependent current to the load via a center-tap transformer. Because the mirrors exhibit a high output impedance, they can be easily back-terminated (if required).

0.1µF

REFIO

REFADJ

TxDAC

0 TO –7.5dB

SET

IOUTP+

IOUTP–

0 TO –12dB

IOUTN+

IAMP

IOUTN–

Figure 23. Current-Mode Operation

0.1µF

IOUT

= N × I

IOUT

POUT

= (IOUTPK)2 × T2 × R

BIAS

T:1

= 2 × N × I

06733-023

TxDAC

0TO –7.5dB

IAMP

0 TO –12dB

IOUTN–

06733-022

Figure 22. TxDAC Output Directly via Center-Tap Transformer

The TxDAC is capable of delivering up to 10 dBm peak power to a load, R

. To increase the peak power for a fixed standing

current, users must increase V p-p across IOUTP+ and IOUTP− by increasing one or more of the following parameters: R

, RL

(if possible), and/or the turns ratio, N, of the transformer. For example, removing the R

from Figure 22 and applying a 2:1

impedance ratio transformer results in 10 dBm of peak power capabilities to the load. Note that increasing the power output capabilities of the TxDAC reduces the distortion performance due to the higher voltage swings seen at IOUTP+ and IOUTP−.

Rev. 0 | Page 23 of 36

The IAMP gain, N, can be set between 0 and 4, while the TxDAC standing current, I, can be set between 2 mA and

12.5 mA (with the IOUTP outputs left open). The IOUTN outputs should be connected to the transformer, which needs to be specified to handle the dc standing current, I drawn by the IAMP. In addition, because I

BIAS

, that is

BIAS

remains signal independent, a series resistor should be inserted between AVDD and the center-tap transformer to provide provisions such that the IAMP common-mode voltage, V

, can be

reduced since its optimum linearity performance is sensitive to both the Tx signal’s peak-to-rms characteristics as well as the IAMP V

. Note that the VCM bias should not exceed 3.3 V. The

power dissipated in the IAMP alone is as follows:

= 2 × N × I × VCM (3)

IAMP

AD9868

RECEIVE PATH

The receive signal path for the AD9868 (or its related part, the AD9869) consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 10-bit (or 12-bit) ADC (see Figure 24). Note that the additional two bits of resolution offered by the AD9869 result in a 3 dB to 5 dB lower noise floor, depending on the RxPGA gain setting and LPF cutoff frequency. Also working in conjunction with the receive path is an offset correction circuit. These blocks are discussed in detail in the following sections. Note that the power consumption of the RxPGA can be modified via Register 0x13 as discussed in the Power Control and Dissipation section.

ADIO[9:4]/

Tx[5:0]

ADIO[3:0]/

Rx[5:2]

RXEN/SYNC

RXCLK

PGA[5:0]

PORT

SPI

PORT

10/12

ADC

80MSPS

CLK SYNC.

0TO 6dB Δ = 1dB

GAIN

MAPPING

LUT

2M CLK

MULTIPLIER

SPGA

–6 TO 18dB Δ = 6dB

2-POLE

LPF

1-POLE

LPF

–6 TO 24dB Δ = 6dB

AD9868

CLKOUT1 CLKOUT2

OSCIN XTAL

RX+

RX–

Figure 24. Functional Block Diagram of Rx Path

Rx PROGRAMMABLE GAIN AMPLIFIER

The RxPGA has a digitally programmable gain range from

−12 dB to +48 dB with 1 dB resolution via a 6-bit word. Its purpose is to extend the dynamic range of the Rx path such that the input of the ADC is presented with a signal that scales within its fixed 2 V input span. There are multiple ways of setting the RxPGA gain as discussed in the RXPGA Control section, as well as an alternative 3-bit gain mapping having a range of −12 dB to +36 dB with a +8 dB resolution.

The RxPGA is comprised of two sections: a continuous time PGA (CPGA) for course gain and a switched capacitor PGA (SPGA) for fine gain resolution. The CPGA consists of two cascaded gain stages providing a gain range of −12 dB to +42 dB with a 6 dB resolution. The first preamplifier (<3.0 nV/√Hz), thereby eliminating the need for an external preamplifier. The SPGA provides a gain range of 0 dB to 6 dB with a 1 dB resolution. A look-up table (LUT) is used to select the appropriate gain setting for each stage.

The nominal differential input impedance of the RxPGA input appearing at the device RX+ and RX− input pins is 400 Ω||4 pF (±20%) and remains relatively independent of gain setting.

stage features a low noise

6733-024

The PGA input is self-biased at a 1.3 V common-mode level, allowing maximum input voltage swings of ±1.5 V at RX+ and RX−.

AC-coupling the input signal to this stage via 0.1 μF coupling capacitors is recommended to ensure that any external dc offset does not become amplified with high RxPGA gain settings, potentially exceeding the ADC input range.

To limit the RxPGA self-induced input offset, an offset cancellation loop is included. This cancellation loop is automatically performed upon power-up and can also be initiated via the SPI. During calibration, the RxPGA first stage is internally shorted, and each gain stage set to a high gain setting. A digital servo loop slaves a calibration DAC, which forces the Rx input offset to be within ±32 LSBs for this particular high gain setting. Although the offset varies for other gain settings, the offset is typically limited to ±5% of the ADC 2 V input span. Note that the offset cancellation circuitry is intended to reduce the voltage offset attributed to only the RxPGA input stage, not to any dc offsets attributed to an external source.

The gain of the RxPGA should be set to minimize clipping of the ADC while utilizing most of its dynamic range. The maximum peak-to-peak differential voltage that does not result in ADC clipping is shown in Figure 25. Although the graph suggests that the maximum input signal for a gain setting of −12 dB is 8.0 V p-p, the maximum input voltage into the PGA should be limited to less than 6 V p-p to prevent turning on ESD protection diodes. For applications having higher maximum input signals, consider adding an external resistive attenuator network. While the input sensitivity of the Rx path is degraded by the amount of attenuation on a dB-to-dB basis, the low noise characteristics of the RxPGA provide some design margin such that the external line noise remains the dominant source.

8.0000

4.0000

2.0000

1.0000

0.5000

0.2500

0.1250

0.0625

0.0312

0.0156

FULL-SCAL E PEAK-TO-P EAK INPUT SPAN (V)

0.0100 –12 –6 0 6 12 18 24 30 36 42 48

GAIN (dB)

Figure 25. Maximum Peak-to-Peak Input vs. RxPGA Gain Setting that

Does Not Result in ADC Clipping

06733-025

Rev. 0 | Page 24 of 36

AD9868

LOW-PASS FILTER

The low-pass filter (LPF) provides a third-order response with a cutoff frequency that is typically programmable over a 15 MHz to 35 MHz span. The first real pole is implemented within the first CPGA gain stage (see is implemented in the second CPGA gain stage. Capacitor arrays are used to vary the different RC time constants within these two stages in a manner that changes the cutoff frequency while preserving the normalized frequency response. Because absolute resistor and capacitor values are process-dependent, a calibration routine lasting less than 100 μs automatically occurs each time the target cutoff frequency register (Register 0x08) is updated, ensuring a repeatable cutoff frequency from device to device.

Although the default setting specifies that the LPF be active, it can also be bypassed providing a nominal f Table 19 shows the SPI registers pertaining to the LPF.

Table 19. SPI Registers for Rx Low-Pass Filter

Address (Hex) Bit Description

0x07 0 Enable Rx LPF. 0x08 7:0 Target value.

The normalized wideband gain response is shown in Figure 26. The normalized pass-band gain and group delay responses are shown in Figure 27. The −3 dB cutoff frequency, f

−3 dB attenuation. In addition, the actual group delay time (GDT) response can be calculated given a programmed cutoff frequency using the following equation:

Actual GDT = Normalized GDT/(2.45 × f

–5

–10

–15

GAIN (dB)

–20

–25

–30

–35

Figure 26. LPF Normalized Wideband Gain Response

Figure 24), and the complex pole pair

of 55 MHz.

−3 dB

, results in

−3 dB

) (4)

−3dB

1.0 3.0 FREQUENCY

2.52.01.50.5

06733-026

0.25

NORMALIZED GAIN RESPONSE

–0.25

–0.50

–0.75

–1.00

–1.25

–1.50

GAIN (dB)

–1.75

–2.00

–2.25

NORMAL IZED G ROUP DE LAY

–2.50

–2.75

–3.00

00.51.00.90.3 0.4 0.80.20. 1

NORMALIZED FREQUENCY

0.6 0.7

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

NORMALIZED GROUP DELAY

Figure 27. LPF Normalized Pass-Band Gain and Group Delay Responses

The f

is programmable by writing an 8-bit word, referred to

−3 dB

as the target, to Register 0x08. The cutoff frequency is a function of the ADC sample rate, f gain setting (in dB). Figure 28 shows how f

, and to a lesser extent, the RxPGA

ADC

varies as a

−3 dB

function of the RxPGA gain setting.

–3

–6

–9

FUNDAMENTAL (dB)

–12

–15

–18

010 5030255

15 20

INPUT FREQUENCY (MHz)

Figure 28. Effects of RxPGA Gain on LPF Frequency Response

= 32 MHz @ 0 dB and f

−3 dB

ADC

The following formula1 can be used to estimate f

–6dB GAIN 0dB GAIN +6dB GAIN +18dB GAIN +30dB GAIN +42dB GAIN

= 80 MSPS)

−3 dB

for a

06733-028

RxPGA gain setting of 0 dB:

= (128/target) × (f

−3dB_0dB

Figure 29 compares the measured and calculated f

ADC

/80) ×(f

/30 + 23.83) f (5)

ADC

using this

−3 dB

formula.

Empirically derived for an f

40 MSPS to 80 MSPS with an RxPGA = 0 dB.

range of 15 MHz to 35 MHz and an f

−3 dB

ADC

TIME RESPONSE (GDT)

06733-027

Rev. 0 | Page 25 of 36

AD9868

Y (MHz)

FREQUEN

50MSPS MEASURED

50MSPS CALCULATED

48 128 22419296 112 1768064

TARGET-DECIMAL EQUIVALENT

Figure 29. Measured and Calculated f

= 50 MSPS and 80 MSPS

ADC

80MSPS MEASURED

80MSPS CALCUL ATED

144 160 208

vs. Target Value for

−3 dB

06733-029

The following scaling factor can be applied to the previous formula to compensate for the RxPGA gain setting on f

−3 dB

Scale Factor = 1 − (RxPGA in dB)/382 (6)

This scaling factor reduces the calculated f

as the RxPGA

−3 dB

increases. Applications that need to maintain a minimum cutoff frequency, f

, for all RxPGA gain settings should first

−3 dB_MIN

determine the scaling factor for the highest RxPGA gain setting to be used. Next, the f factor to normalize to the 0 dB RxPGA gain setting, f

should be divided by this scale

−3 dB_MIN

−3 dB_0 dB

Equation 5 can then be used to calculate the target value.

The LPF frequency response shows a slight sensitivity to temperature, as shown in Figure 30. Applications sensitive to temperature drift can recalibrate the LPF by rewriting the target value to Register 0x08.

ACTUAL 80MHz AND –40°C

Y (MHz)

FREQUEN

OUT

ACTUAL 80MHz AND +25°C

OUT

ACTUAL 80MHz AND +85°C

OUT

ANALOG-TO-DIGITAL CONVERTER (ADC)

The AD9868 features a 10-bit analog-to-digital converter (ADC) capable of up to 80 MSPS. As shown in Figure 24, the ADC is driven by the SPGA stage, which performs both the sample-and-hold and the fine gain adjust functions. A buffer amplifier (not shown) isolates the last CPGA gain stage from the dynamic load presented by the SPGA stage. The full-scale input span of the ADC is 2 V p-p, and depending on the PGA gain setting, the full-scale input span into the SPGA is adjustable from 1 V to 2 V in 1 dB increments.

A pipelined, multistage ADC architecture is used to achieve high sample rates while consuming low power. The ADC distributes the conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage on each clock edge. The ADC typically performs best when driven internally by a 50% duty cycle clock.

The ADC power consumption can be reduced by 25 mA with minimal effect on its performance by setting Bit 4 of Register 0x07. Alternative power bias settings are also available via Register 0x13, as discussed in the Lastly, the ADC can be completely powered down for half-duplex operation, further reducing the peak power consumption of the AD9868.

The ADC has an internal voltage reference and reference amplifier as shown in Figure 31. The internal band gap reference generates a stable 1 V reference level that is converted to a differential 1 V reference centered about midsupply (AVDD/2). The outputs of the differential reference amplifier are available at the REFT and REFB pins and must be properly decoupled for optimum performance. The REFT and REFB pins are conveniently situated at the corners of the LFCSP package such that C1 (0603 type) can be placed directly across its pins. C3 and C4 can be placed underneath C1, and C2 (10 μF tantalum) can be placed furthest from the package.

Power Control and Dissipation section.

REFT

0.1µF

C2 10µF

1.0V

ADCs

REFB

0.1µF

96 128 240192176112

Figure 30. f

Temperature Drift for f

−3 dB

144 160

TARGET-DECIMAL EQUIVALENT

= 80 MSPS and RxPGA = 0 dB

ADC

208

224

06733-030

TOP

VIEW

06733-031

Figure 31. ADC Reference and Decoupling

Rev. 0 | Page 26 of 36

AD9868

Table 20 shows the SPI registers pertaining to the ADC.

Table 20. SPI Registers for Rx ADC

Address (Hex) Bit Description

0x04 4 ADC clock from PLL. 0x07 4 ADC low power mode. 0x13 2:0 ADC power bias adjust.

AGC TIMING CONSIDERATIONS

When implementing a digital AGC timing loop, it is important to consider the Rx path latency and settling time of the Rx path in response to a change in gain setting. While the RxPGA settling time may also show a slight dependency on the LPF cutoff frequency, the ADC pipeline delay, along with the ADIO bus interface, presents a more significant delay. The amount of delay or latency is dependent on whether a half-duplex or fullduplex is selected. An impulse response at the RxPGA input can be observed after 10.0 ADC clock cycles (1/f half-duplex interface, and 10.5 ADC clock cycles in the case of a full-duplex interface. This latency, along with the RxPGA settling time, should be considered to ensure stability of the AGC loop.

) in the case of a

ADC

Rev. 0 | Page 27 of 36

AD9868

CLOCK SYNTHESIZER

The AD9868 generates all its internal sampling clocks, as well as two user-programmable clock outputs appearing at CLKOUT1 and CLKOUT2, from a single reference source (see Figure 32). The reference source can either be a fundamental frequency or an overtone quartz crystal connected between OSCIN and XTAL, with the parallel resonant load components specified by the crystal manufacturer. It can also be a TTL-level clock applied to OSCIN with XTAL left unconnected.

RXCLK

TO ADC

TO TxDAC

06733-032

XTAL

÷2

2M CLK

MULTIPLIER

OSCIN

CLKOUT2

CLKOUT1

Figure 32. Clock Oscillator and Synthesizer

÷2

÷F/2

(FULL-DUPLEX ONLY)

Special consideration should be given to the design of crystal oscillators using the AD9868 internal CMOS inverter. This is especially true when designing third overtone oscillators where crystal power dissipation and negative resistance upon start-up are a few of the issues to consider. For this reason, a 40 MHz or lower fundamental crystal is preferred with the AD9868.

The CMOS inverter device characteristics are listed in Tabl e 21. It is recommended to consult with the selected crystal manufacturer to ensure that a robust design can be realized with the selected crystal and AD9868 CMOS inverter.

Table 21. CMOS Inverter Device Characteristics

Nominal

Parameter

Value

Tolerance % Description

RF 1.2 MΩ ±25 Feedback resistor. gm 17 mA/V ±20 At midsupply. Z

OUT

1.6 kΩ

±50 At midsupply.

CIN 2.5 pF ±25 Parasitic capacitance. C

2.0 pF ±25 Parasitic capacitance.

OUT

The data rate, f equal. Therefore, the ADC sample rate, f f

, while the TxDAC update rate is a factor of 1, 2, or 4 of

DATA

, depending on the selected interpolation factor. The data

DATA

, for the Tx and Rx data paths must always be

DATA

, is always equal to

ADC

rate refers to the word rate and should not be confused with the nibble rate in full-duplex interface.

CLK multiplier contains a PLL (with integrated loop

The 2 filter) and a VCO capable of generating an output frequency that is a multiple of 1, 2, 4, or 8 of its input reference frequency, f

, appearing at OSCIN. The input frequency range of f

OSCIN

is between 20 MHz and 80 MHz, and the VCO can operate over an 80 MHz to 200 MHz span. For the best phase noise/jitter characteristics, it is advisable to operate the VCO with a

Rev. 0 | Page 28 of 36

frequency between 100 MHz and 200 MHz. The VCO output drives the TxDAC directly such that its update rate, f related to f

DAC

by the following equation:

OSCIN

= 2M × f

(7)

OSCIN

DAC

, is

where M = 0, 1, 2, or 3.

M is the PLL multiplication factor set in Register 0x04. The value of M is determined by the Tx path’s word rate, f

DATA

, and digital interpolation factor, F, as shown in the following equation:

M = log

(F × f

DATA/fOSCIN

) (8)

Note that if the reference frequency appearing at OSCIN is chosen to be equal to the Tx path and Rx path word rates, M is equal to log

(F). Also note that the RXCLK frequency for full-duplex

mode (MODE = 1) is a function of the 2

CLK multiplier setting, as well as the interpolation factor, F. Full-duplex mode requires that RXCLK be equal to 2 × f

because data is

DATA

transferred in nibbles.

The clock source for the ADC can be selected in Register 0x04 as a buffered version of the reference frequency appearing at OSCIN (default setting) or a divided version of the VCO output, f desirable if f

. The first option is the default setting and most

DAC

is equal to f

OSCIN

. This option typically results in

ADC

the best jitter/phase noise performance for the ADC sampling clock. The second option is suitable in cases where f factor of 2 or 4 less than the f

. In this case, the divider ratio,

ADC

OSCIN

is a

N, is chosen such that the divided down VCO output is equal to the ADC sample rate, as shown in the following equation:

DAC

(9)

ADC

= f

where N = 0, 1, or 2.

The CLK synthesizer also has two clock outputs appearing at CLKOUT1 and CLKOUT2. They are programmable via Register 0x06. Both outputs can be inverted or disabled. The voltage levels appearing at these outputs are relative to DRVDD and remain active during a hardware or software reset. Tab le 2 2 shows the SPI registers pertaining to the CLK synthesizer.

Table 22. SPI Registers for CLK Synthesizer

Address (Hex) Bit Description

0x04 4 ADC CLK from PLL.

3:2 PLL divide factor (N). 1:0 PLL multiplication factor (M).

0x06 7:6 CLKOUT2 divide number.

5 CLKOUT2 invert. 4 CLKOUT2 disable. 3:2 CLKOUT1 divide number. 1 CLKOUT1 invert. 0 CLKOUT1 disable.

AD9868

CLKOUT1 is a divided version of the VCO output and can be

set to be a submultiple integer of f

DAC

/2R, where R = 0, 1, 2,

DAC

or 3). Because this clock is derived from the same set of dividers used within the PLL core, it is phase-locked to the dividers such that its phase relationship relative to the signal appearing at OSCIN (or RXCLK) can be determined upon power-up. In addition, this clock has a near 50% duty cycle because it is derived from the VCO. As a result, CLKOUT1 should be selected before CLKOUT2 as the primary source for system clock distribution.

CLKOUT2 is a divided version of the reference frequency, f and can be set to be a submultiple integer of f

OSCIN

/2L, where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is a delayed version of the signal appearing at OSCIN, exhibiting the same duty cycle characteristics. With L set to 1 or 2, the output of CLKOUT2 is a divided version of the OSCIN signal, exhibiting a near 50% duty cycle, but without having a deterministic phase relationship relative to CLKOUT1 (or RXCLK).

Rev. 0 | Page 29 of 36

AD9868

POWER CONTROL AND DISSIPATION

POWER-DOWN

The AD9868 provides the ability to control the power-on state of various functional blocks. The state of the PWRDWN pin, along with the contents of Register 0x01 and Register 0x02, allow two user-defined power settings that are pin-selectable. The default settings powered on (all bits 0), while Register 0x02 has all blocks powered down (excluding the PLL) such that the clock signal remains available at CLKOUT1 and CLKOUT2. When the PWRDWN pin is low, the functional blocks corresponding to the bits in Register 0x01 are powered down. When the PWRDWN is high, the functional blocks corresponding to the bits in Register 0x02 are powered down. PWRDWN immediately affects the designated functional blocks with minimum digital delay.

Table 23. SPI Registers Associated with Power-Down and Half-Duplex Power Savings

Address (Hex) Bit Description Comments

0x01 7 CLK Synthesizer 6 TxDAC/IAMP 5 Tx Digital 4 REF 3 ADC CML 2 ADC 1 PGA Bias 0 RxPGA 0x02 7 CLK Synthesizer 6 TxDAC/IAMP 5 Tx Digital 4 REF 3 ADC CML 2 ADC 1 PGA Bias 0 RxPGA 0x03 7:3 Tx OFF Delay 2

1 Enable Tx PWRDWN 0 Enable Rx PWRDWN

With MODE = 1 and CONFIG =1, Register 0x02 default settings are with all blocks

powered off, with RXCLK providing a buffered version of the signal appearing at OSCIN. This setting results in the lowest power consumption upon powerup, while still allowing AD9868 to generate the system clock via a crystal.

are such that Register 0x01 has all blocks

PWRDWN = 0. Default setting is all functional blocks powered on.

PWRDWN = 1. Default setting is all functional blocks powered off excluding PLL.

Half-duplex power

Rx PWRDWN via TXEN

savings.

HALF-DUPLEX POWER SAVINGS

Significant power savings can be realized in applications having a half-duplex protocol, allowing only the Rx path or Tx path to be operational at one time. The power-savings method depends on whether the AD9868 is configured for a full-duplex or halfduplex interface. Functional blocks having fast power-on/power-off times for the Tx path and Rx path are controlled by the following bits: TxDAC/IAMP, Tx Digital, ADC, and RxPGA (see Table 23).

In the case of a full-duplex digital interface (MODE = 1), users can set Register 0x01 to Register 0x60 and Register 0x02 to Register 0x05 (or vice versa) such that the Tx path and Rx path are never powered on simultaneously. The PWRDWN pin can then be used to control which path is powered on, depending on the burst type. During a Tx burst, the Rx path PGA and ADC blocks can typically be powered down within 100 ns, while the Tx path DAC, IAMP, and digital filter blocks are powered up within

0.5 μs. For an Rx burst, the Tx circuitry can be powered down within 100 ns, while the Rx circuitry is powered up within 2 μs.

Setting the

TXQUIET

duplex interface to quickly power down the IAMP and disable the interpolation filter. This is meant to maintain backward compatibility with the AD9875/AD9876 MxFEs, except that the TxDAC remains powered if its IOUTP outputs are used. In most applications, the interpolation filter needs to be flushed with 0s before or after being powered down. This ensures that upon power-up, the TxDAC (and IAMP) have a negligible differential dc offset, thus preventing spectral splatter due to an impulse transient.

Applications using a half-duplex interface (MODE = 0) can benefit from an additional power-savings feature available in Register 0x03. This register is effective only for a half-duplex interface. In addition to providing power savings for half-duplex applications, this feature allows the AD9868 to be used in applications that need only its Rx (or Tx) path functionality through pin strapping, making a serial port interface (SPI) optional. This feature also allows the PWRDWN pin to retain its default function as a master power control, as defined in Table 10.

The default settings for Register 0x03 provide fast power control of the functional blocks in the Tx signal path and Rx signal path (outlined previously) using the TXEN pin. The TxDAC remains powered on in this mode, while the IAMP is powered down. Significant current savings are typically realized when the IAMP is powered down.

pin low allows it to be used with the full-

Rev. 0 | Page 30 of 36

AD9868

For a Tx burst, the falling edge of TXEN is used to generate an internal delayed signal for powering down the Tx circuitry. Upon receipt of this signal, power-down of the Tx circuitry occurs within 100 ns. The user-programmable delay for the Tx path power-down is meant to match the pipeline delay of the last Tx burst sample such that power-down of the TxDAC and IAMP does not impact its transmission. A 5-bit field in Register 0x03 sets the delay from 0 to 31 TXCLK clock cycles, with the default being 31 (0.62 μs with f

= 50 MSPS). The digital interpolation

TXCLK

filter is automatically flushed with midscale samples prior to power-down if the clock signal into the TXCLK pin is present for 33 additional clock cycles after TXEN returns low. For an Rx burst, the rising edge of TXEN is used to generate an internal signal (with no delay) that powers up the Tx circuitry within 0.5 μs.

The Rx path power-on/power-off can be controlled by either TXEN or RXEN by setting Bit 2 of Register 0x03. In the default setting, the falling edge of TXEN powers up the Rx circuitry within 2 μs, while the rising edge of TXEN powers down the Rx circuitry within 0.5 μs. If RXEN is selected as the control signal, its rising edge powers up the Rx circuitry, and the falling edge powers it down. To disable the fast power-down of the Tx circuitry and/or Rx circuitry, set Bit 1 and/or Bit 0 to 0.

POWER REDUCTION OPTIONS

The power consumption of the AD9868 can be significantly reduced from its default setting by optimizing the power consumption vs. performance of the various functional blocks in the Tx signal path and Rx signal path. On the Tx path, minimum power consumption is realized when the TxDAC output is used directly and its standing current is reduced to as low as 1 mA. Although a slight degradation in THD performance results at reduced standing currents, it often remains adequate for most applications because the op amp driver typically limits the overall linearity performance of the Tx path. The load resistors used at the TxDAC outputs (IOUTP+ and IOUTP−) can be increased to generate an adequate differential voltage that can be further amplified via a power efficient op ampbased driver solution. Figure 33 shows how the supply current for the TxDAC is reduced from 55 mA to 14 mA as the standing current is reduced from 12.5 mA to 1.25 mA. Further Tx power savings can be achieved by bypassing or reducing the interpolation factor of the digital filter as shown in Figure 34.

(mA)

TxDAC

IAVDD

012345678910111213

Figure 33. Reduction in TxDAC Supply Current vs. Standing Current

4× INTERPOLATION

(mA)

DVDD

20 30 40 50 60 70 80

Figure 34. Digital Supply Current Consumption vs. Input Data Rate

(DVDD = DRVDD = 3.3 V and f

(mA)

STANDING

2× INTERPOLATION

1× (HALF-DUPL EX ONLY)

INPUT DATA RATE (MSPS)

= f

OUT

DATA

/10)

06733-033

06733-034

Power consumption on the Rx path can be achieved by reducing the bias levels of the various amplifiers contained within the RxPGA and ADC. As previously noted, the RxPGA consists of two CPGA amplifiers and one SPGA amplifier. The bias levels of each of these amplifiers, along with the ADC, can be controlled via Register 0x13 as shown in Table 2 4. The default setting for Register 0x13 is 0x00.

Table 24. SPI Register for RxPGA and ADC Biasing

Address (Hex) Bit Description

0x07 4 ADC low power. 0x13 7:5 CPGA bias adjust. 4:3 SPGA bias adjust. 2:0 ADC power bias adjust.

Rev. 0 | Page 31 of 36

AD9868

–

Because the CPGA processes signals in the continuous time domain, its performance vs. bias setting remains mostly independent of the sample rate. Table 25 shows how the typical current consumption seen at AVDD varies as a function of Register 0x13, Bits [7:5], while the remaining bits are maintained at their default settings of 0. Only four of the possible settings result in any reduction in current consumption relative to the default setting. Reducing the bias level typically results in degradation in the THD vs. frequency performance as shown in Figure 35. This is due to a reduction of the amplifier’s unity gain bandwidth, while the SNR performance remains relatively unaffected.

Table 25. Analog Supply Current vs. CPGA Bias Settings at

= 65 MSPS

ADC

Bit 7 Bit 6 Bit 5 ∆mA

0 0 0 0 0 0 1 −27 0 1 0 −42 0 1 1 −51 1 0 0 −55 1 0 1 +27 1 1 0 +69 1 1 1 +27

65.0

62.5

60.0

57.5

55.0

52.5

50.0

SNR (dBFS)

47.5

45.0

42.5

40.0 000 100010 011001

Figure 35. THD vs. f

SNR_RxPGA = 0dB

SNR_RxPGA = 36dB

THD_RxPGA = 0dB

THD_RxPG A = 36dB

CPGA BIAS SETT ING-BITS (7:5)

Performance and CPGA Bias Settings (000, 001, 010, 100

with RxPGA = 0 and +36 dB, AIN = −1 dBFS, LPF set to 26 MHz, f

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

= 50 MSPS)

ADC

THD (dBc)

06733-035

The SPGA is implemented as a switched capacitor amplifier, therefore, its performance vs. bias level is mostly dependent on the sample rate. Figure 36 shows how the typical current consumption seen at AVDD varies as a function of Register 0x13, Bits [4:3] and sample rate, while the remaining bits are maintained at the default setting of 0. Figure 37 shows how the SNR and THD performance is affected for a 10 MHz sine wave input as the ADC sample rate is swept from 20 MHz to 80 MHz. The SNR and THD performance remains relatively stable, suggesting that the SPGA bias can often be reduced from its default setting without impacting the device’s overall performance.

210

205

200

195

(mA)

190

AVDD

185

180

175

170

20 30 40 50 60 70 80

Figure 36. AVDD Current vs. SPGA Bias Setting and Sample Rate

SNR (dBc)

20 8060 7030 40 50

Figure 37. SNR and THD Performance vs. f

RxPGA = 0 dB, f

= 10 MHz, LPF set to 26 MHz, AIN = −1 dBFS

ADC SAMPLE RATE (MSPS)

THD-00 THD-01 THD-10 THD-11

SAMPLE RATE (MSPS)

and SPGA Bias Setting with

ADC

SNR-00 SNR-01 SNR-10 SNR-11

–56

–58

–60

–62

–64

–66

–68

–70

–72

–74

06733-036

THD (dBc)

06733-037

Rev. 0 | Page 32 of 36

AD9868

–

The ADC is based on a pipeline architecture with each stage consisting of a switched capacitor amplifier. Therefore, its performance vs. bias level is mostly dependent on the sample rate. Figure 38 shows how the typical current consumption seen at AVDD varies as a function of Register 0x13, Bits [2:0] and sample rate, while the remaining bits are maintained at the default setting of 0. Setting Bit 4 or Register 0x07 corresponds to the 011 setting, and the settings of 101 and 111 result in higher current consumption. Figure 39 shows how the SNR and THD performance are affected for a 10 MHz sine wave input for the lower power settings as the ADC sample rate is swept from 20 MHz to 80 MHz.

220

210

200

190

180

(mA)

170

AVDD

160

150

140

130

120

20 30 40 50 60 70 80

Figure 38. AVDD Current vs. ADC Bias Setting and Sample Rate

SNR (dBc)

20 8060 7030 40 50

Figure 39. SNR and THD Performance vs. f

RxPGA = 0 dB, f

101 OR 111

000

001

010

011

100

SAMPLE RATE (MSPS)

THD-00 THD-01 THD-10 THD-11

SAMPLE RATE (MSPS)

= 10 MHz, AIN = −1 dBFS

ADC

101

06733-038

–56

–58

SNR-00 SNR-01 SNR-10 SNR-11

–60

–62

–64

–66

–68

–70

–72

–74

and ADC Bias Setting with

THD (dBc)

06733-039

A sine wave input is a standard and convenient method of analyzing the performance of a system. However, the amount of power reduction that is possible is application dependent, based on the nature of the input waveform (such as frequency content, and peak-to-rms ratio), the minimum ADC sample, and the minimum acceptable level of performance. Thus, it is advisable that power-sensitive applications optimize the power bias setting of the Rx path using an input waveform that is representative of the application.

POWER DISSIPATION

The power dissipation of the AD9868 can become quite high in full-duplex applications in which the Tx path and Rx path are simultaneously operating with nominal power bias settings. In fact, some applications that use the IAMP may need to either reduce its peak power capabilities or reduce the power consumption of the Rx path so that the device’s maximum allowable power consumption, P

is specified at 1.66 W to ensure that the die temperature

MAX

, is not exceeded.

MAX

does not exceed 125°C at an ambient temperature of 85°C. This specification is based on the 64-lead LFSCP having a thermal resistance, θ

, of 24°C/W with its heat slug soldered. (The θJA is

30.8°C/W if the heat slug remains unsoldered.) If a particular application’s maximum ambient temperature, T

, falls below

85°C, the maximum allowable power dissipation can be determined by the following equation:

= 1.66 + (85 − TA)/24 (10)

MAX

Assuming the IAMP common-mode bias voltage is operating off the same analog supply as the AD9868, the following equation can be used to calculate the maximum total current consumption, I

= (P

MAX

With an ambient temperature of up to 85°C, I

MAX

− P

, of the IC:

)/3.47 (11)

IAMP

is 478 mA.

MAX

If the IAMP is operating off a different supply or in the voltage mode configuration, first calculate the power dissipated in the IAMP, P

, using Equation 3, and then recalculate I

IAMP

MAX

using

Equation 11.

Figure 33, Figure 34, Figure 36, and Figure 38 can be used to calculate the current consumption of the Rx and Tx paths for a given setting.

MODE SELECT UPON POWER-UP AND RESET

The AD9868 power-up state is determined by the logic levels appearing at the MODE and CONFIG pins. The MODE pin is used to select a half- or full-duplex interface by pin strapping it low or high, respectively. The CONFIG pin is used in conjunction with the MODE pin to determine the default settings for the SPI registers as outlined in Tabl e 10.

The intent of these particular default settings is to allow some applications to avoid using the SPI (disabled by pin strapping SEN

high), thereby reducing implementation costs. For example, setting MODE low and CONFIG high configures the AD9868 to be backward compatible with the AD9975, while setting MODE high and CONFIG low makes it backward compatible with the AD9875. Other applications must use the SPI to configure the device.

Rev. 0 | Page 33 of 36

AD9868

A hardware reset ( Register 0x00) can be used to place the AD9868 into a known state of operation as determined by the state of the MODE and CONFIG pins. A dc offset calibration and filter tuning routine is also initiated upon a hardware reset, but not with a software reset. Neither reset method flushes the digital interpolation filters in the Tx path. Refer to the Half-Duplex Mode and Full-Duplex Mode sections for information on flushing the digital filters.

A hardware reset can be triggered by pulsing the for a minimum of 50 ns. The SPI registers are instantly reset to their default settings upon calibration and filter-tuning routine is initiated upon returning high. To ensure sufficient power-on time of the various functional blocks, than 10 ms upon power-up. If a digital reset signal from a microprocessor reset circuit (such as ADM1818) is not available, a simple R-C network referenced to DVDD can be used to hold RESET

low for approximately 10 ms upon power-up.

RESET

pin) or software reset (Bit 5 of

RESET

going low, whereas the dc offset

RESET

returning high should occur no less

RESET

pin low

ANALOG AND DIGITAL LOOPBACK TEST MODES

The AD9868 features analog and digital loopback capabilities that can assist in system debug and final test. Analog loopback routes the digital output of the ADC back into the Tx data path prior to the interpolation filters such that the Rx input signal can be monitored at the output of the TxDAC or IAMP.

As a result, the analog loopback feature can be used for a halfduplex or full-duplex interface to allow testing of the functionality of the entire IC (excluding the digital data interface).

For example, the user can configure the AD9868 with similar settings as the target system, inject an input signal (sinusoidal waveform) into the Rx input, and monitor the quality of the reconstructed output from the TxDAC or IAMP to ensure a minimum level of performance. In this test, the user can exercise the RxPGA as well as validate the attenuation characteristics of the RxLPF. Note that the RxPGA gain setting should be selected such that the input does not result in clipping of the ADC.

Digital loopback can be used to test the full-duplex digital interface of the AD9868. In this test, data appearing on the Tx[5:0] port is routed back to the Rx[5:0] port, thereby confirming proper bus operation. The Rx port can also be three-stated for half-duplex and full-duplex interfaces.

Table 26. SPI Registers for Test Modes

Address (Hex) Bit Description

0x0D 7 Analog loopback. 6 Digital loopback.

5 Rx port three-state.

Rev. 0 | Page 34 of 36

AD9868

OUTLINE DIMENSIONS

7.50 REF

0.30

0.25

0.18 PIN 1

INDICATOR

7.25

7.10 SQ

6.95

0.25 MIN

1.00

0.85

0.80

SEATING

PLANE

12° MAX

9.00

BSC SQ

PIN 1 INDICATOR

VIEW

TOP

0.80 MAX

0.65 TYP

0.50 BSC

8.75

BSC SQ

0.20 REF

0.60 MAX

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

COMPLIANT TO JEDEC S TANDARDS MO-220- VMMD-4

063006-B

Figure 40. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm x 9 mm Body, Very Thin Quad

(CP-64-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9868BCPZ AD9868BCPZRL

Z = RoHS Compliant Part.

−40°C to +85°C 64-Lead LFCSP_VQ CP-64-3

Rev. 0 | Page 35 of 36

AD9868

NOTES

Rev. 0 | Page 36 of 36

Datasheet AD9868 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

Tx PATH SPECIFICATIONS

Rx PATH SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL SPECIFICATIONS

SERIAL PORT TIMING SPECIFICATIONS

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SERIAL PORT

REGISTER MAP DESCRIPTION

SERIAL PORT INTERFACE (SPI)

DIGITAL INTERFACE

HALF-DUPLEX MODE

FULL-DUPLEX MODE

RxPGA CONTROL

TxPGA CONTROL

TRANSMIT PATH

DIGITAL INTERPOLATION FILTERS

TxDAC AND IAMP ARCHITECTURE

Tx PROGRAMMABLE GAIN CONTROL

TxDAC OUTPUT OPERATION

IAMP CURRENT-MODE OPERATION

RECEIVE PATH

Rx PROGRAMMABLE GAIN AMPLIFIER

LOW-PASS FILTER

ANALOG-TO-DIGITAL CONVERTER (ADC)

AGC TIMING CONSIDERATIONS

CLOCK SYNTHESIZER

POWER CONTROL AND DISSIPATION

POWER-DOWN

HALF-DUPLEX POWER SAVINGS

POWER REDUCTION OPTIONS

POWER DISSIPATION

MODE SELECT UPON POWER-UP AND RESET

ANALOG AND DIGITAL LOOPBACK TEST MODES

OUTLINE DIMENSIONS

ORDERING GUIDE