Datasheet AD9850BRS Datasheet (Analog Devices)

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
a
CMOS, 125 MHz
Complete DDS Synthesizer
FUNCTIONAL BLOCK DIAGRAM
CLOCK OUT
CLOCK OUT
ANALOG IN
ANALOG OUT
DAC R
SET
+V
S
GND
COMPARATOR
PHASE
AND
CONTROL
WORDS
SERIAL
LOAD
32-BIT
TUNING
WORD
HIGH SPEED
DDS
FREQUENCY/PHASE
DATA REGISTER
PARALLEL
LOAD
DATA INPUT REGISTER
AD9850
10-BIT
DAC
REF
CLOCK IN
MASTER
RESET
WORD LOAD
CLOCK
FREQUENCY
UPDATE/
DATA REGISTER
RESET
1-BIT
40 LOADS
8-BITS 5 LOADS
FREQUENCY, PHASE, AND CONTROL
DATA INPUT
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced DDS technology coupled with an internal high speed, high performance, D/A converter and comparator, to form a com­plete digitally programmable frequency synthesizer and clock generator function. When referenced to an accurate clock source, the AD9850 generates a spectrally pure, frequency/ phase-programmable, analog output sine wave. This sine wave can be used directly as a frequency source or converted to a square wave for agile-clock generator applications. The AD9850’s innovative high speed DDS core provides a 32-bit frequency tuning word, which results in an output tuning resolution of
0.0291 Hz, for a 125 MHz reference clock input. The AD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or
62.5 MHz), and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second. The device also provides five bits of digitally controlled phase modulation, which enables phase shifting of its output in increments of 180°, 90°, 45°, 22.5°, 11.25° and any
combination thereof. The AD9850 also contains a high speed comparator that can be configured to accept the (externally) filtered output of the DAC to generate a low jitter square wave output. This facilitates the device’s use as an agile clock gen­erator function.
The frequency tuning, control, and phase modulation words are loaded into the AD9850 via a parallel byte or serial loading format. The parallel load format consists of five iterative loads of an 8-bit control word (byte). The first byte controls phase modulation, power-down enable, and loading format; bytes 2–5 comprise the 32-bit frequency tuning word. Serial loading is accomplished via a 40-bit serial data stream on a single pin. The AD9850 Complete-DDS uses advanced CMOS technology to provide this breakthrough level of functionality and performance on just 155 mW of power dissipation (+3.3 V supply).
The AD9850 is available in a space saving 28-lead SSOP, sur­face mount package. It is specified to operate over the extended industrial temperature range of –40°C to +85°C.
FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40 MHz A
OUT
32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial
Loading Format Phase Modulation Capability +3.3 V or +5 V Single Supply Operation Low Power: 380 mW @ 125 MHz (+5 V)
Low Power: 155 mW @ 110 MHz (+3.3 V)
Power-Down Function Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS Frequency/Phase–Agile Sine-Wave Synthesis Clock Recovery and Locking Circuitry for Digital
Communications Digitally Controlled ADC Encode Generator Agile Local Oscillator Applications
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
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AD9850BRS
Parameter Temp Test Level Min Typ Max Units
CLOCK INPUT CHARACTERISTICS
Frequency Range
+5 V Supply Full IV 1 125 MHz +3.3 V Supply Full IV 1 110 MHz
Pulsewidth High/Low
+5 V Supply +25°C IV 3.2 ns +3.3 V Supply +25°C IV 4.1 ns
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
R
SET
= 3.9 k +25°C V 10.24 mA
R
SET
= 1.95 k +25°C V 20.48 mA Gain Error +25°C I –10 +10 % FS Gain Temperature Coefficient Full V 150 ppm/°C Output Offset +25°CI 10 µA Output Offset Temperature Coefficient Full V 50 nA/°C Differential Nonlinearity +25°C I 0.5 0.75 LSB Integral Nonlinearity +25°C I 0.5 1 LSB Output Slew Rate (50 , 2 pF Load) +25°C V 400 V/µs Output Impedance +25°C IV 50 120 kΩ Output Capacitance +25°CIV 8 pF Voltage Compliance +25°C I 1.5 V Spurious-Free Dynamic Range (SFDR):
Wideband (Nyquist Bandwidth)
1 MHz Analog Out +25°C IV 63 72 dBc 20 MHz Analog Out +25°C IV 50 58 dBc 40 MHz Analog Out +25°C IV 46 54 dBc
Narrowband
40.13579 MHz ± 50 kHz +25°C IV 80 dBc
40.13579 MHz ± 200 kHz +25°C IV 77 dBc
4.513579 MHz ± 50 kHz/20.5 MHz CLK +25°C IV 84 dBc
4.513579 MHz ± 200 kHz/20.5 MHz CLK +25°C IV 84 dBc
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance +25°CV 3 pF Input Resistance +25°C IV 500 kΩ Input Current +25°C I –12 +12 µA Input Voltage Range +25°CIV 0 V
DD
V
Comparator Offset* Full VI 30 30 mV
COMPARATOR OUTPUT CHARACTERISTICS
Logic “1” Voltage +5 V Supply Full VI +4.8 V Logic “1” Voltage +3.3 V Supply Full VI +3.1 V Logic “0” Voltage Full VI +0.4 V Propagation Delay, +5 V Supply (15 pF Load) +25°C V 5.5 ns Propagation Delay, +3.3 V Supply (15 pF Load) +25°CV 7 ns Rise/Fall Time, +5 V Supply (15 pF Load) +25°CV 3 ns Rise/Fall Time, +3.3 V Supply (15 pF Load) +25°C V 3.5 ns Output Jitter (p-p) +25°CV 80 ps
CLOCK OUTPUT CHARACTERISTICS
Clock Output Duty Cycle (Clk Gen. Config.) +25°C IV 50 ± 10 %
REV. E
–2–
(VS = +5 V 5% except as noted, R
SET
= 3.9 k⍀)
AD9850–SPECIFICATIONS
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AD9850BRS
Parameter Temp Test Level Min Typ Max Units
CMOS LOGIC INPUTS (Including CLKIN)
Logic “1” Voltage, +5 V Supply +25°C I 3.5 V Logic “1” Voltage, +3.3 V Supply +25°C I 3.0 V Logic “0” Voltage +25°C I 0.4 V Logic “1” Current +25°CI 12 µA Logic “0” Current +25°CI 12 µA Input Capacitance +25°CV 3 pF
POWER SUPPLY (A
OUT
= 1/3 CLKIN)
+V
S
Current @:
62.5 MHz Clock, +3.3 V Supply Full VI 30 48 mA 110 MHz Clock, +3.3 V Supply Full VI 47 60 mA
62.5 MHz Clock, +5 V Supply Full VI 44 64 mA 125 MHz Clock, +5 V Supply Full VI 76 96 mA
P
DISS
@:
62.5 MHz Clock, +3.3 V Supply Full VI 100 160 mW 110 MHz Clock, +3.3 V Supply Full VI 155 200 mW
62.5 MHz Clock, +5 V Supply Full VI 220 320 mW 125 MHz Clock, +5 V Supply Full VI 380 480 mW
P
DISS
Power-Down Mode +5 V Supply Full V 30 mW +3.3 V Supply Full V 10 mW
NOTES *Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
TIMING CHARACTERISTICS*
AD9850BRS
Parameter Temp Test Level Min Typ Max Units
t
DS
(Data Setup Time) Full IV 3.5 ns
t
DH
(Data Hold Time) Full IV 3.5 ns
t
WH
(W_CLK min. Pulsewidth High) Full IV 3.5 ns
t
WL
(W_CLK min. Pulsewidth Low) Full IV 3.5 ns
t
WD
(W_CLK Delay After FQ_UD) Full IV 7.0 ns
t
CD
(CLKIN Delay After FQ_UD) Full IV 3.5 ns
t
FH
(FQ_UD High) Full IV 7.0 ns
t
FL
(FQ_UD Low) Full IV 7.0 ns
t
CF
(Output Latency from FQ_UD) Frequency Change Full IV 18 CLKIN Cycles Phase Change Full IV 13 CLKIN Cycles
t
FD
(FQ_UD Min. Delay After W_CLK) Full IV 7.0 ns
t
RH
(CLKIN Delay After RESET Rising Edge) Full IV 3.5 ns
t
RL
(RESET Falling Edge After CLKIN) Full IV 3.5 ns
t
RS
(Minimum RESET Width) Full IV 5 CLKIN Cycles
t
OL
(RESET Output Latency) Full IV 13 CLKIN Cycles
t
RR
(Recovery from RESET) Full IV 2 CLKIN Cycles Wake-Up Time from Power-Down Mode +25°CV 5 µs
NOTES *Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
(VS = +5 V 5% except as noted, R
SET
= 3.9 k⍀)
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AD9850
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AD9850
–4–
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ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . +165°C
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V
S
Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA
DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300°C
SSOP θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I 100% Production Tested. III – Sample Tested Only. IV – Parameter is guaranteed by design and characterization
testing. V Parameter is a typical value only. VI – All devices are 100% production tested at +25°C.
100% production tested at temperature extremes for
military temperature devices; guaranteed by design and
characterization testing for industrial devices.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9850 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Application Note: Users are cautioned not to apply digital input signals prior to power-up of this device. Doing so may r
esult in a latch-up condition.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9850BRS –40°C to +85°C Shrink Small Outline (SSOP) RS-28
WARNING!
ESD SENSITIVE DEVICE
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AD9850
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Table I. Lead Function Descriptions
Pin No. Mnemonic Function
4–1, D0–D7 8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/ 28–25 control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word.
5, 24 DGND Digital Ground. These are the ground return leads for the digital circuitry.
6, 23 DVDD Supply Voltage Leads for digital circuitry.
7 W_CLK Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
8 FQ_UD Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase)
loaded in the data input register, it then resets the pointer to Word 0.
9 CLKIN Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
10, 19 AGND Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
11, 18 AVDD Supply Voltage for the analog circuitry (DAC and comparator).
12 R
SET
This is the DAC’s external R
SET
connection. This resistor value sets the DAC full-scale output current. For
normal applications (F
S IOUT
= 10 mA), the value for R
SET
is 3.9 k connected to ground. The R
SET/IOUT
relationship is: I
OUT
= 32 (1.248 V/R
SET
).
13 QOUTB Output Complement. This is the comparator’s complement output.
14 QOUT Output True. This is the comparator’s true output.
15 VINN Inverting Voltage Input. This is the comparator’s negative input.
16 VINP Noninverting Voltage Input. This is the comparator’s positive input.
17 DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a “no connect” for optimum performance.
20 IOUTB The Complementary Analog Output of the DAC.
21 IOUT Analog Current Output of the DAC.
22 RESET Reset. This is the master reset function; when set high it clears all registers (except the input register) and
the DAC output will go to Cosine 0 after additional clock cycles—see Figure 19.
PIN CONFIGURATIONS
17
16
15
20
19
18
28
27
26
25
24
23
22
21
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD9850
D3
D7 MSB/SERIAL LOAD
D6
D5
D4
D2
D1
LSB D0
RESET
DVDD
DGND
DGND
DVDD
W
CLK
FQ
UD
CLKIN
AGND AGND
IOUTB
IOUT
AVDD
R
SET
QOUTB
QOUT
AVDD
VINN
VINP
DACBL (NC)
NC = NO CONNECT
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CH1 S
Spectrum
10dB/REF
–8.6dBm
76.642 dB
Fxd
AD9850
CLOCK 125MHz
RBW # 100Hz START 0Hz
VBW 100Hz ATN # 30dB SWP 762 sec
STOP 62.5MHz
0
Figure 1. SFDR, CLKIN = 125 MHz/f
OUT
= 1 MHz
CH1
S Spectrum
10dB/REF
–10dBm
54.818 dB
Fxd
AD9850
CLOCK 125MHz
RBW # 300Hz START 0Hz
VBW 300Hz ATN # 30dB SWP 182.6 sec
STOP 62.5MHz
0
Figure 2. SFDR, CLKIN = 125 MHz/f
OUT
= 41 MHz
Tek Run: 100GS/s ET Sample
Ch 1 500mV M 20.0ns Ch 1 1.58V
D 500ps Runs After
1
: 300ps @: 25.26ns
Figure 3. Typical Comparator Output Jitter, AD9850 Configured as Clock Generator w/42 MHz LP Filter (40 MHz A
OUT
/125 MHz CLKIN)
AD9850–Typical Performance Characteristics
–6–
REV. E
CH1
S Spectrum
10dB/REF
–10dBm
59.925 dB
Fxd
AD9850
CLOCK 125MHz
RBW # 300Hz START 0Hz
VBW 300Hz ATN # 30dB SWP 182.6 sec
STOP 62.5MHz
0
Figure 4. SFDR, CLKIN = 125 MHz/f
OUT
= 20 MHz
CH1 S
Spectrum
12dB/REF
0dBm –85.401 dB
Mkr
AD9850
RBW # 3Hz CENTER 4.513579MHz
VBW 3Hz ATN # 20dB SWP 399.5 sec
SPAN 400kHz
0
–23 kHz
Figure 5. SFDR, CLKIN = 20.5 MHz/f
OUT
= 4.5 MHz
OFFSET FROM 5MHz CARRIER Hz
105
110
155
115
120
125
130
135
140
145
150
100 100k1k
dBc
10k
PN.3RD
Figure 6. Output Residual Phase Noise (5 MHz A
OUT
/
125 MHz CLKIN)
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AD9850
–7–
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Tek Run: 50.0GS/s ET Average
Ch1 1.00V M 1.00ns Ch 1 1.74V
Ch 1 Rise
2.870ns
1
Figure 7. Comparator Output Rise Time (5 V Supply/15 pF Load)
CLKIN – MHz
0 14020 40 60 80 100 120
68
52
SFDR – dB
66
60
58
56
54
64
62
VCC = 5V
VCC = 3.3V
f
OUT
= 1/3 OF CLKIN
Figure 8. SFDR vs. CLKIN Frequency (A
OUT
= 1/3 of CLKIN)
FREQUENCY OUT – MHz
90
80
30
04010
SUPPLY CURRENT – mA
20 30
70
60
50
40
VCC = 5V
VCC = 3.3V
Figure 9. Supply Current vs. A
OUT
Frequency
(CLKIN = 125/110 MHz for 5 V/3.3 V Plot)
Tek Run: 50.0GS/s ET Average
Ch1 1.00V M 1.00ns Ch 1 1.74V
Ch 1 Fall
3.202ns
1
Figure 10. Comparator Output Fall Time (5 V Supply/15 pF Load)
CLOCK FREQUENCY – MHz
0 14020 40 60 80 100 120
90
10
SUPPLY CURRENT – mA
80
50
40
30
20
70
60
VCC = 5V
VCC = 3.3V
Figure 11. Supply Current vs. CLKIN Frequency (A
OUT
= 1/3 of CLKIN)
DAC I
OUT
– mA
75
70
45
205
SFDR – dB
10 15
65
60
55
50
f
OUT
= 1MHz
f
OUT
= 40MHz
f
OUT
= 20MHz
Figure 12. SFDR vs. DAC I
OUT
(A
OUT
= 1/3 of CLKIN)
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AD9850
–8–
REV. E
+V
S
DATA
BUS
LOW-PASS
FILTER
GND
PROCESSOR
XTAL
OSC
CLK
IOUTB
VINN VINP
QOUT
QOUTB
IOUT
100k
100k
200
100
470pF
200
COMP TRUE
CMOS
CLOCK
OUTPUTS
RSET
AD9850
5-POLE ELLIPTICAL 42MHz LOW-PASS 200 IMPEDANCE
8-b 5 PARALLEL DATA, OR 1-b 40 SERIAL DATA, RESET, AND 2 CLOCK LINES
Figure 13. Basic AD9850 Clock Generator Application with Low-Pass Filter
VCA
Rx
IF IN
ADC ENCODE
I/Q MIXER
AND
LOW-PASS
FILTER
I
Q
8
8
AD9059
DUAL 8-BIT
ADC
DIGITAL
DEMODULATOR
Rx BASEBAND DIGITAL DATA OUT
ADC CLOCK
FREQUENCY
LOCKED TO Tx CHIP/
SYMBOL PN RATE
AD9850
CLOCK
GENERATOR
32
CHIP/SYMBOL/PN
RATE DATA
125MHz
REFERENCE
CLOCK
AGC
Figure 14. AD9850 Clock Generator Application in a Spread-Spectrum Receiver
IF
FREQUENCY
IN
TUNING WORD
AD9850
COMPLETE-DDS
125MHz
REFERENCE
FILTER
RF FREQUENCY OUT
FILTER
a. Frequency/Phase–Agile Local Oscillator
TUNING
WORD
AD9850
COMPLETE-
DDS
125MHz
REFERENCE
CLOCK
FILTER
RF
FREQUENCY
OUT
PHASE
COMPARATOR
LOOP
FILTER
VCO
DIVIDE-BY-N
b. Frequency/Phase–Agile Reference for PLL
TUNING WORD
REF
FREQUENCY
RF
FREQUENCY
OUT
PHASE
COMPARATOR
LOOP
FILTER
VCO
FILTER
PROGRAMMABLE
DIVIDE-BY-N
FUNCTION
AD9850
COMPLETE-
DDS
c. Digitally-Programmable Divide-by-N Function in PLL
Figure 15. AD9850 Complete-DDS Synthesizer in
Frequency Up-Conversion Applications
THEORY OF OPERATION AND APPLICATION
The AD9850 uses direct digital synthesis (DDS) technology, in the form of a numerically controlled oscillator, to generate a frequency/phase-agile sine wave. The digital sine wave is con­verted to analog form via an internal 10-bit high speed D/A converter, and an onboard high speed comparator is provided to translate the analog sine wave into a low jitter TTL/CMOS­compatible output square wave. DDS technology is an innova­tive circuit architecture that allows fast and precise manipulation of its output frequency under full digital control. DDS also enables very high resolution in the incremental selection of output frequency; the AD9850 allows an output frequency resolution of 0.0291 Hz with a 125 MHz reference clock ap­plied. The AD9850’s output waveform is phase-continuous when changed.
The basic functional block diagram and signal flow of the AD9850 configured as a clock generator is shown in Figure 16.
The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2
N
number of bits in the tuning word. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it
receives a clock pulse. When the counter overflows it wraps around, making the phase accumulator’s output contiguous. The frequency tuning word sets the modulus of the counter that effectively determines the size of the increment ( Phase) that gets added to the value in the phase accumulator on the next clock pulse. The larger the added increment, the faster the ac­cumulator overflows, which results in a higher output fre­quency. The AD9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value. This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function, which contributes to the small size and low power dissipation of the AD9850. The relationship of the output frequency, reference clock, and tuning word of the AD9850 is determined by the formula:
f
OUT
= (Phase × CLKIN)/2
32
where: Phase = value of 32-bit tuning word
CLKIN = input reference clock frequency in MHz f
OUT
= frequency of the output signal in MHz
The digital sine wave output of the DDS block drives the inter­nal high speed 10-bit D/A converter that reconstructs the sine
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AD9850
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CLK OUT
PHASE
ACCUMULATOR
TUNING WORD SPECIFIES
OUTPUT FREQUENCY
AS A FRACTION OF REF
CLOCK FREQUENCY
N
AMPLITUDE/COS
CONV.
ALGORITHM
DDS CIRCUITRY
D/A
CONVERTER
LP
COMPARATOR
REF
CLOCK
IN DIGITAL DOMAIN
COS (x)
Figure 16. Basic DDS Block Diagram and Signal Flow of AD9850
The reference clock frequency of the AD9850 has a minimum limitation of 1 MHz. The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded and automatically places itself in the power-down mode. When in this state, if the clock frequency again exceeds the threshold, the device resumes normal operation. This shutdown mode prevents excessive current leakage in the dynamic registers of the device.
The D/A converter output and comparator inputs are available as differential signals that can be flexibly configured in any manner desired to achieve the objectives of the end-system. The typical application of the AD9850 is with single-ended output/ input analog signals, a single low-pass filter, and generating the comparator reference midpoint from the differential DAC out­put as shown in Figure 13.
Programming the AD9850
The AD9850 contains a 40-bit register that is used to program the 32-bit frequency control word, the 5-bit phase modulation word and the power-down function. This register can be loaded in a parallel or serial mode.
In the parallel load mode, the register is loaded via an 8-bit bus; the full 40-bit word requires five iterations of the 8-bit word. The W_CLK and FQ_UD signals are used to address and load the registers. The rising edge of FQ_UD loads the (up to) 40-bit control data word into the device and resets the address pointer to the first register. Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to the next register. After five loads, W_CLK edges are ignored until either a reset or an FQ_UD rising edge resets the address pointer to the first register.
In serial load mode, subsequent rising edges of W_CLK shift the 1-bit data on Lead 25 (D7) through the 40 bits of program­ming information. After 40 bits are shifted through, an FQ_UD pulse is required to update the output frequency (or phase).
The function assignments of the data and control words are shown in Table III; the detailed timing sequence for updating the output frequency and/or phase, resetting the device, and powering-up/down, are shown in the timing diagrams of Figures 18–24.
Note: There are specific control codes, used for factory test purposes, that render the AD9850 temporarily inoperable. The user must take deliberate precaution to avoid inputting the codes listed in Table II.
wave in analog form. This DAC has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the AD9850. Since the output of the AD9850 is a sampled signal, its output spectrum follows the Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the Reference Clock Frequency ± the selected output frequency. A graphical representation of the sampled spectrum, with aliased images, is shown in Figure 17.
20MHz
FUNDAMENTAL
80MHz
1ST IMAGE
120MHz
2ND IMAGE
180MHz
3RD IMAGE
220MHz
4TH IMAGE
280MHz
5TH IMAGE
100MHz
REFERENCE CLOCK
FREQUENCY
fc
fc+fo
fc–fo
2fc–fo
2fc+fo 3fc–fo
f
OUT
si n(x )/ x ENVELOPE x= (pi)fo/fc
SIGNAL AMPLITUDE
Figure 17. Output Spectrum of a Sampled Signal
In this example, the reference clock is 100 MHz and the output frequency is set to 20 MHz. As can be seen, the aliased images are very prominent and of a relatively high energy level as deter­mined by the sin(x)/x roll-off of the quantized D/A converter output. In fact, depending on the fo/Ref Clk relationship, the first aliased image can be on the order of –3 dB below the fun­damental. A low-pass filter is generally placed between the out­put of the D/A converter and the input of the comparator to further suppress the effects of aliased images. Obviously, con­sideration must be given to the relationship of the selected output frequency and the Reference Clock frequency to avoid unwanted (and unexpected) output anomalies.
A good rule-of-thumb for applying the AD9850 as a clock generator is to limit the selected output frequency to <33% of Reference Clock frequency, thereby avoiding generating aliased signals that fall within, or close to, the output band of interest (generally dc-selected output frequency). This practice will ease the complexity (and cost) of the external filter requirement for the clock generator application.
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AD9850
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Table II. Factory-Reserved Internal Test Control Codes
Loading Format Factory-Reserved Codes
Parallel 1) W0 = XXXXXX10
2) W0 = XXXXXX01
Serial 1) W32 = 1; W33 = 0
2) W32 = 0; W33 = 1
3) W32 = 1; W33 = 1
Table III. 8-Bit Parallel-Load Data/Control Word Functional Assignment
Word data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0]
W0 Phase-b4 Phase-b3 Phase-b2 Phase-b1 Phase-b0 Power-Down Control Control
(MSB) (LSB)
W1 Freq-b31 Freq-b30 Freq-b29 Freq-b28 Freq-b27 Freq-b26 Freq-b25 Freq-b24
(MSB)
W2 Freq-b23 Freq-b22 Freq-b21 Freq-b20 Freq-b19 Freq-b18 Freq-b17 Freq-b16
W3 Freq-b15 Freq-b14 Freq-b13 Freq-b12 Freq-b11 Freq-b10 Freq-b9 Freq-b8
W4 Freq-b7 Freq-b6 Freq-b5 Freq-b4 Freq-b3 Freq-b2 Freq-b1 Freq-b0
(LSB)
t
DS
W0* W1 W2 W3 W4
t
DH
t
WH
t
WL
t
CF
VALID DATA
OLD FREQ (PHASE) NEW FREQ (PHASE)
*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK
DATA
W
CLK
REF CLK
COS OUT
t
DS
DATA SETUP TIME 3.5ns
t
DH
DATA HOLD TIME 3.5ns
t
WH
W CLK HIGH 3.5ns
t
WL
W CLK LOW 3.5ns
t
CD
CLK DELAY AFTER FQ_UD 3.5ns
t
FH
FQ UD HIGH 7.0ns
t
FL
FQ UD LOW 7.0ns
t
FD
FQ UD DELAY AFTER W CLK 7.0ns
t
CF
OUTPUT LATENCY FROM FQ UD
FREQUENCY CHANGE 18 CLOCK CYCLES
PHASE CHANGE 13 CLOCK CYCLES
SYMBOL DEFINITION MIN
t
CD
t
FD
t
FH
t
FL
FQ UD
Figure 18. Parallel-Load Frequency/Phase Update Timing Sequence
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AD9850
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REV. E
t
RH
t
RL
t
RR
t
RS
t
OL
COS (0)
REF CLK
COS OUT
RESET
t
RH
CLK DELAY AFTER RESET RISING EDGE 3.5ns
t
RL
RESET FALLING EDGE AFTER CLK 3.5ns
t
RR
RECOVERY FROM RESET 2 CLK CYCLES
t
RS
MINIMUM RESET WIDTH 5 CLK CYCLES
t
OL
RESET OUTPUT LATENCY 13 CLK CYCLES
SYMBOL DEFINITION MIN SPEC
RESULTS OF RESET:
FREQUENCY/PHASE REGISTER SET TO 0 ADDRESS POINTER RESET TO W0 POWER-DOWN BIT RESET TO 0” – DATA INPUT REGISTER UNEFFECTED
Figure 19. Master Reset Timing Sequence
XXXXX100
DATA (W0)
W
CLK
FQ
UD
REF CLK
INTERNAL CLOCKS DISABLED
DAC STROBE
Figure 20. Parallel-Load Power-Down Sequence/Internal Operation
XXXXX000
DATA (W0)
W CLK
FQ
UD
REF CLK
INTERNAL CLOCKS ENABLED
Figure 21. Parallel-Load Power-Up Sequence/Internal Operation
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AD9850
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XXXXX011
DATA (W0)
(PARALLEL)
W
CLK
FQ
UD
NOTE: AT LEAST FIRST 8 BITS OF 40-BIT SERIAL LOAD WORD ARE REQUIRED TO SHIFT IN REQUIRED W32–W34 DATA
DATA (SERIAL)
REQUIRED TO RESET CONTROL REGISTERS
NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARD-WIRE LEAD 2 AT “0”, LEAD 3 AT “1”, AND LEAD 4 AT “1” (SEE FIGURE 23).
W32 = 0 W33 = 0 W34 = 0
ENABLE SERIAL MODE RESET CONTROL WORDS
Figure 22. Serial-Load Enable Sequence
+V
SUPPLY
3
4
2
AD9850BRS
Figure 23. Leads 2–4 Connection for Default Serial-Mode Operation
DATA –
W
CLK
FQ
UD
W0 W1 W2 W3 W39
40 W CLK CYCLES
Figure 24. Serial-Load Frequency/Phase Update Sequence
Table IV. 40-Bit Serial-Load Word Function Assignment
W0 Freq-b0 (LSB) W1 Freq-b1 W2 Freq-b2 W3 Freq-b3 W4 Freq-b4 W5 Freq-b5 W6 Freq-b6 W7 Freq-b7 W8 Freq-b8 W9 Freq-b9 W10 Freq-b10 W11 Freq-b11 W12 Freq-b12 W13 Freq-b13
W28 Freq-b28 W29 Freq-b29 W30 Freq-b30 W31 Freq-b31 (MSB) W32 Control W33 Control W34 Power-Down W35 Phase-b0 (LSB) W36 Phase-b1 W37 Phase-b2 W38 Phase-b3 W39 Phase-b4 (MSB)
W14 Freq-b14 W15 Freq-b15 W16 Freq-b16 W17 Freq-b17 W18 Freq-b18 W19 Freq-b19 W20 Freq-b20 W21 Freq-b21 W22 Freq-b22 W23 Freq-b23 W24 Freq-b24 W25 Freq-b25 W26 Freq-b26 W27 Freq-b27
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AD9850
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DATA (7) –
W CLK
FQ
UD
W32=0 W33=0 W34=1 W35=X W36=X W37=X W38=X W39=X
Figure 25. Serial-Load Power-Down Sequence
V
CC
QOUT/ QOUTB
V
CC
IOUT IOUTB
VINP/
VINN
V
CC
DIGITAL
IN
V
CC
DAC Output Comparator Output Comparator Input Digital Inputs
Figure 26. AD9850 I/O Equivalent Circuits
PCB LAYOUT INFORMATION
The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 27–30) represent typical implementations of the AD9850 and exemplify the use of high frequency/high resolu­tion design and layout practices. The printed circuit board that contains the AD9850 should be a multilayer board that allows dedicated power and ground planes. The power and ground planes should be free of etched traces that cause discontinuities in the planes. It is recommended that the top layer of the multi­layer board also contain interspatial ground plane, which makes ground available for surface-mount devices. If separate analog and digital system ground planes exist, they should be con­nected together at the AD9850 for optimum results.
Avoid running digital lines under the device as these will couple noise onto the die. The power supply lines to the AD9850 should use as large a track as possible to provide a low-impedance path and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signal paths. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the circuit board. Use microstrip techniques where possible.
Good decoupling is also an important consideration. The analog (AVDD) and digital (DVDD) supplies to the AD9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with high quality ceramic capacitors. To achieve best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD supplies of the AD9850, it is recommended that the system’s AVDD supply be used.
Analog Devices, Inc., applications engineering support is avail­able to answer additional questions on grounding and PCB layout. Call 1-800-ANALOGD.
Evaluation Boards
Two versions of evaluation boards are available for the AD9850, which facilitate the implementation of the device for bench­top analysis, and serve as a reference for PCB layout. The AD9850/FSPCB is intended for applications where the device will primarily be used as frequency synthesizer. This version facilitates connection of the AD9850’s internal D/A converter output to a 50 spectrum analyzer input; the internal com­parator on the AD9850 DUT is not enabled (see Figure 28 for electrical schematic of AD9850/FSPCB). The AD9850/CGPCB is intended for applications using the device in the clock genera­tor mode. It connects the AD9850’s DAC output to the internal comparator input via a single-ended, 42 MHz low-pass, 5­pole Elliptical filter. This model facilitates the access of the AD9850’s comparator output for evaluation of the device as a frequency- and phase-agile clock source (see Figure 29 for electrical schematic of AD9850/CGPCB).
Both versions of the AD9850 evaluation boards are designed to interface to the parallel printer port of a PC. The operating software runs under Microsoft
®
Windows and provides a user­friendly and intuitive format for controlling the functionality and observing the performance of the device. The 3.5" floppy provided with the evaluation board contains an executable file that loads and displays the AD9850 function-selection screen. The evaluation board may be operated with +3.3 V or +5 V supplies. The evaluation boards are configured at the factory for an external reference clock input; if the onboard crystal clock source is used, remove R2.
All trademarks are the property of their respective holders.
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AD9850
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AD9850 Evaluation Board Instructions
Required hardware/software:
IBM compatible computer operating in a Windows environment Printer port, 3.5" floppy drive and Centronics compatible
printer cable.
XTAL clock or signal generator—if using a signal generator, dc
offset the signal to one-half the supply voltage and apply at least 3 V p-p signal across the 50 (R2) input resistor. Remove R2 for high Z clock input.
AD9850 evaluation board software disk and AD9850/FSPCB or
AD9850/CGPCB evaluation board.
+5 V voltage supply
Setup:
Copy the contents of the AD9850 disk onto your hard drive
(there are three files).
Connect the printer cable from computer to the AD9850
evaluation board.
Apply power to AD9850 evaluation board. The AD9850 is
powered separately from the connector marked “DUT +V.” The AD9850 may be powered with 3.3 V to +5 V. Connect external 50 ohm clock or remove R2 and apply a high
Z input clock such as a crystal “can” oscillator. Locate the file called 9850REV2.EXE and execute that program. Monitor should display a “control panel” to allow operation of
the AD9850 evaluation board.
Operation:
On the control panel, locate the box called “COMPUTER I/O.” Point to and click the selection marked LPT1 and then point to the “TEST” box and click. A message will appear telling you if your choice of output ports is correct. Choose other ports as necessary to achieve a correct setting. If you have trouble getting your computer to recognize any printer port, try the following: connect three 2K pull-up resistors from Pins 9, 8 and 7 of U3 to +5 V. This will assist “weak” printer port outputs in driving the heavy capacitance load of the printer cable. If troubles persist, try a different printer cable.
Locate the “MASTER RESET” button with the mouse and click it. This will reset the AD9850 to 0 Hz, 0 degrees phase. The output should be a dc voltage equal to the full-scale output of the AD9850.
Locate the “CLOCK” box and place the cursor in the frequency box. Type in the clock frequency (in MHz) that you will be applying to the AD9850. Click the LOAD button or press enter on the keyboard.
Move the cursor to the OUTPUT FREQUENCY box and type in the desired output frequency (in MHz). Click the “LOAD” button or press the enter key. The BUS MONITOR section of the control panel will show the 32-bit word that was loaded into the AD9850. Upon completion of this step, the AD9850 output should be active and outputting your frequency information.
Changing the output phase is accomplished by clicking on the “down arrow” in the OUTPUT PHASE DELAY box to make a selection and then clicking the LOAD button.
Other operational modes (Frequency Sweeping, Sleep, Serial Input) are available to the user via keyboard/mouse control.
The AD9850/FSPCB provides access into and out of the on-chip comparator via test point pairs (each pair has an active input and a ground connection). The two active inputs are labeled TP1 and TP2. The unmarked hole next to each labeled test point is a ground connection. The two active outputs are labeled TP5 and TP6. Unmarked ground connections are adjacent to each of these test points.
The AD9850/CGPCB provides BNC inputs and outputs associ­ated with the on-chip comparator and the onboard, 5th order, 200 ohm input/output Z, elliptic 45 MHz low-pass filter. Jumper­ing (soldering a wire) E1 to E2, E3 to E4, and E5 to E6 connects the onboard filter and the midpoint switching voltage to the comparator. Users may elect to insert their own filter and com­parator threshold voltage by removing the jumpers and inserting a filter between J7 and J6 and then providing a threshold voltage at E1.
If you choose to use the XTAL socket to supply the clock to the AD9850, you must remove R2 (a 50 ohm chip resistor). The crystal oscillator must be either TTL or CMOS (preferably) compatible.
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AD9850
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J6
R1
3.9k
R5
25
17
16
15
20
19
18
28
27
26
25
24
23
22
21
14
13
12
11
10
9
8
1
2
3
4
7
6
5
U1
AD9850
D3
D2
D1
DGND
DVDD
W
CLK
FQ
UD
CLKIN
AGND
AVDD
R
SET
QOUT
QOUTB
D0 D7
D6
D5
D4
RESET
DVDD
DGND
AGND
IOUTB
IOUT
AVDD
VINN
VINP
DACBL
D3
D2
D1
D0
GND
+V
D7
D6
D5
D4
+V
GND
RESET
GND
WCLK
CLKIN
GND
+V
FQUD
+V
10mA
R
SET
TP5
TP6
TP7
TP8
GND
GND
GND
GND
TP1
TP2
TP3
TP4
R4 50
DAC OUT TO 50
COMPARATOR INPUTS
R6
1k
R7
1k
GND
+V
COMPARATOR
OUTPUTS
14
VCC
+5V
R2
50
J5
CLKIN
REMOVE
WHEN
USING Y1
8
OUT
XTAL
OSC
GND
Y1
7
RESET
WCLK
FQUD
CHECK
RRESET
WWCLK
FFQUD
RRESET
12
13
14
15
16
17
18
19
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
8D
7D
6D
5D
4D
3D
2D
1D
9
8
7
6
5
4
3
2
U3
74HCT574
CLK
OE
11 1
STROBE
C36CRPX
J1
D0
D1
D2
D3
D4
D5
D6
D7
12
13
14
15
16
17
18
19
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
8D
7D
6D
5D
4D
3D
2D
1D
9
8
7
6
5
4
3
2
U2
74HCT574
CLK
OE
11 1
STROBE
RRESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
FFQUD
WWCLK
STROBE
CHECK
P O R T
1
+V
+5V
C2
0.1␮FC30.1␮F
C4
0.1␮F
C5
0.1␮F
C8
0.1␮F
C9
0.1␮F
C10
0.1␮F
C6 10FC710F
+V
+5V
J2
J3
J4
BANANA
JACKS
+V
+5V
GND
H1#6H2#6H3#6H4
#6
MOUNTING HOLES
R10
2.2k
+5V
RRESET
R9
2.2k
FFQUD
R8
2.2k
WWCLK
R3
2.2k
STROBE
Figure 27. AD9850/FSPCB Electrical Schematic
COMPONENT LIST Integrated Circuits
U1 AD9850BRS (28-Lead SSOP) U2, U3 74HCT574 H-CMOS Octal Flip-Flop
Capacitors
C2–C5, C8–C10 0.1 µF Ceramic Chip Capacitor C6, C7 10 µF Tantalum Chip Capacitor
Resistors
R1 3.9 k Resistor R2, R4 50 Resistor R3, R8, R9, R10 2.2 k Resistor R5 25 Resistor R6, R7 1 k Resistor
Connectors
J1 36-Pin D Connector J2, J3, J4 Banana Jack J5, J6 BNC Connector
Page 16
AD9850
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a. AD9850/FSPCB Top Layer
b. AD9850/FSPCB Ground Plane
c. AD9850/FSPCB Power Plane
d. AD9850/FSPCB Bottom Layer
Figure 28. AD9850/FSPCB Evaluation Board Layout
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AD9850
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REV. E
C36CRPX
J1
D0
D1
D2
D3
D4
D5
D6
D7
12
13
14
15
16
17
18
19
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
8D
7D
6D
5D
4D
3D
2D
1D
9
8
7
6
5
4
3
2
U2
74HCT574
CLK
OE
11
1
STROBE
RRESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
FFQUD
WWCLK
STROBE
CHECK
P O R
T
1
+V
+5V
C2
0.1␮F
C3
0.1␮F
C4
0.1␮F
C5
0.1␮F
C8
0.1␮FC90.1␮F
C10
0.1␮F
C6 10FC710F
+V +5V
BNC
R1
3.9k
R8 100
17
16
15
19
18
20
28
27
26
25
24
23
22
21
14
13
12
11
10
9
8
1
2
3
4
7
6
5
U1
AD9850
D3
D2
D1
DGND
DVDD
W
CLK
FQ
UD
CLKIN
AGND
AVDD
R
SET
QOUT
QOUTB
D0
D7
D6
D5
D4
RESET
DVDD
DGND
AGND
IOUTB
IOUT
AVDD
VINN
VINP
DACBL
D3
D2
D1
D0
GND
+V
WCLK
CLKIN
GND
+V
FQUD
D7
D6
D5
D4
+V
GND
RESET
GND
+V
E3E4E2E1
R6 200
BNC
BNC
C1 470pF
J6
R5 100k
R4 100k
E5
E6
C11 22pF
C12
3.3pF
1
2
L1
1008CS
910nH
C13 33pF
C14
8.2pF
1
2
L2
1008CS
680nH
C15
22pF
R7
200
J9
J7
200 Z
42MHz ELLIPTIC
LOW PASS FILTER
10mA
R
SET
J8
H1#6H2#6H3#6H4
#6
MOUNTING HOLES
RESET
WCLK
FQUD
CHECK
RRESET
WWCLK
FFQUD
RRESET
12
13
14
15
16
17
18
19
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
8D
7D
6D
5D
4D
3D
2D
1D
9
8
7
6
5
4
3
2
U3
74HCT574
CLK OE
11 1
STROBE
J2
J3
J4
BANANA
JACKS
+V
+5V
GND
14
VCC
+5V
R2
50
J5
CLKIN
REMOVE
WHEN
USING Y1
8
OUT
XTAL
OSC
GND
Y1
7
R9
2.2k
+5V
RRESET
R10
2.2k
FFQUD
R11
2.2k
WWCLK
R3
2.2k
STROBE
Figure 29. AD9850/CGPCB Electrical Schematic
COMPONENT LIST Integrated Circuits
U1 AD9850BRS (28-Lead SSOP) U2, U3 74HCT574 H-CMOS Octal Flip-Flop
Capacitors
C1 470 pF Ceramic Chip Capacitor C2–C5, C8–C10 0.1 µF Ceramic Chip Capacitor C6, C7 10 µF Tantalum Chip Capacitor C11 22 pF Ceramic Chip Capacitor C12 3.3 pF Ceramic Chip Capacitor C13 33 pF Ceramic Chip Capacitor C14 8.2 pF Ceramic Chip Capacitor C15 22 pF Ceramic Chip Capacitor
Resistors
R1 3.9 k Resistor R2 50 Resistor R3, R9, R10, R11 2.2 k Resistor R4, R5 100 k Resistor R6, R7 200 Resistor R8 100 Resistor
Connectors
J2, J3, J4 Banana Jack J5–J9 BNC Connector
Inductors
L1 910 nH Surface Mount L2 680 nH Surface Mount
Page 18
AD9850
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a. AD9850/CGPCB Top Layer
b. AD9850/CGPCB Ground Plane
c. AD9850/CGPCB Power Plane
d. AD9850/CGPCB Bottom Layer
Figure 30. AD9850/CGPCB Evaluation Board Layout
Page 19
AD9850
–19–
REV. E
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package
(RS-28)
0.009 (0.229)
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
8 0
0.212 (5.38)
0.205 (5.21)
28 15
14
1
0.407 (10.34)
0.397 (10.08)
0.311 (7.9)
0.301 (7.64)
PIN 1
SEATING
PLANE
0.008 (0.203)
0.002 (0.050)
0.07 (1.79)
0.066 (1.67)
0.0256 (0.65)
BSC
0.078 (1.98)
0.068 (1.73)
0.015 (0.38)
0.010 (0.25)
C2155e–0–5/99
PRINTED IN U.S.A.
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