FEATURES
30 MSPS Correlated Double Sampler (CDS)
4 dB 6 dB 6-Bit Pixel Gain Amplifier (
PxGA
®
)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 30 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 100 mW @ 2.7 V
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
FUNCTIONAL BLOCK DIAGRAM
PBLK
CCDIN
CLPDM
AUX1IN
AUX2IN
CLP
AVDD
4dB6 dB
CDS
CLP
2:1
MUX
AD9846A
AVSS
PxGA
6
BUF
HDVD
COLOR
STEERING
2:1
MUX
CONTROL
REGISTERS
DIGITAL
INTERFACE
PRODUCT DESCRIPTION
The AD9846A is a complete analog signal processor for CCD
applications. It features a 30 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9846A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
Pixel Gain Amplifier (PxGA), digitally controlled variable gain
amplifier (VGA), black level clamp, and a 10-bit A/D converter. Additional input modes are provided for processing
analog video signals.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input configuration, and
power-down modes.
The AD9846A operates from a single 3 V power supply, typically dissipates 117 mW, and is packaged in a 48-lead LQFP.
CLPOB
DRVDD
DRVSS
DOUT
10
VRT
VRB
CML
DVDD
DVSS
2dB~36dB
VGA
10
OFFSET
DAC
8
CLP
ADC
BANDGAP
REFERENCE
INTERNAL
INTERNAL
TIMING
BIAS
SL
PxGA is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
Gain0dB
Allowable CCD Reset Transient
Max Input Range Before Saturation
Max CCD Black Pixel Amplitude
1
1
1
1.0V p-pPxGA Gain at 4 dB
500mVSee Input Waveform in Footnote 1
200mV
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range1.0V p-p
Max Output Range1.6V p-p
Gain Control Resolution64Steps
Gain Monotonicity Guaranteed
Gain Range (Two’s Complement Coding)See Figure 28 for PxGA
Min Gain (PxGA Gain Code 32)–2dB
Max Gain (PxGA Gain Code 31)10dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range1.6V p-p
Max Output Range2.0V p-p
Gain Control Resolution1024Steps
Gain Monotonicity Guaranteed
Gain RangeSee Figure 29 for VGA Gain Curve
Low Gain (VGA Gain Code 91)2dB
Max Gain (VGA Gain Code 1023)36dB
BLACK LEVEL CLAMP
Clamp Level Resolution256Steps
Clamp LevelMeasured at ADC Output
Min Clamp Level0LSB
Max Clamp Level63.75LSB
SYSTEM PERFORMANCESpecifications Include Entire Signal Chain
Gain Accuracy (VGA Code 91 to 1023)
PxGA
Gain Accuracy
Min Gain (PxGA Register Code 32)–10+1dBVGA Gain Fixed at 2 dB (Code 91)
Max Gain (PxGA
Code 31)111212dBVGA Gain Fixed at 2 dB (Code 91)
2
–0.5+0.5Use Equations on Page 18 to Calculate Gain
Peak Nonlinearity, 500 mV Input Signal0.1%12 dB Gain Applied
Total Output Noise0.2LSB rmsAC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR)40dBMeasured with Step Change on Supply
Maximum SCK Frequencyf
SL to SCK Setup Timet
SCK to SL Hold Timet
SDATA Valid to SCK Rising Edge Setupt
SCK Falling Edge to SDATA Valid Holdt
SCK Falling Edge to SDATA Valid Readt
NOTES
1
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
BYP1-4, CCDINAVSS–0.3AVDD + 0.3V
Junction Temperature150°C
Lead Temperature300°C
(10 sec)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9846A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Quad Flatpack
(LQFP)
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
Page 6
AD9846A
PIN CONFIGURATIONS
SCK
SDATASLNC
STBYNCTHREE-STATE
DVSS
DVDD2
VRB
VRT
SHP
SHD
CML
VD
CLPDM
36
35
34
33
32
31
30
29
28
27
26
25
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
BYP2
BYP1
AVDD1
AVSS
AVSS
48 47 46 45 4439 38 3743 42 41 40
1
NC
NC
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
(MSB) D9
NC = NO CONNECT
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
DRVDD
DVSS
DRVSS
AD9846A
TOP VIEW
(Not to Scale)
HD
PBLK
DVDD1
ATACLK
CLPOB
PIN FUNCTION DESCRIPTIONS
Pin NumberNameTypeDescription
1, 2NCInternally not Connected
3–12D0–D9DODigital Data Outputs
13DRVDDPDigital Output Driver Supply
14DRVSSPDigital Output Driver Ground
15, 41DVSSPDigital Ground
16DATACLKDIDigital Data Output Latch Clock
17DVDD1PDigital Supply
18HDDIHorizontal Drive. Used with VD for Color Steering Control
19PBLKDIPreblanking Clock Input
20CLPOBDIBlack Level Clamp Clock Input
21SHPDICDS Sampling Clock for CCD’s Reference Level
22SHDDICDS Sampling Clock for CCD’s Data Level
23CLPDMDIInput Clamp Clock Input
24VDDIVertical Drive. Used with HD for Color Steering Control
25, 26, 35AVSSPAnalog Ground
27AVDD1PAnalog Supply
28BYP1AOInternal Bias Level Decoupling
29BYP2AOInternal Bias Level Decoupling
30CCDINAIAnalog Input for CCD Signal
31NCNCInternally Not Connected
32BYP4AOInternal Bias Level Decoupling
33AVDD2PAnalog Supply
34AUX2INAIAnalog Input
36AUX1INAIAnalog Input
37CMLAOInternal Bias Level Decoupling
38VRTAOA/D Converter Top Reference Voltage Decoupling
39VRBAOA/D Converter Bottom Reference Voltage Decoupling
40DVDD2PDigital Supply
42THREE-STATEDIDigital Output Disable. Active High
43NCNCMay be tied high or low. Do not leave floating.
44STBYDIStandby Mode, Active High. Same as Serial Interface
45NCNCInternally Not Connected. May be Tied High or Low
46SLDISerial Digital Interface Load Pulse
47SDATADISerial Digital Interface Data
48SCKDISerial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
–6–
REV. 0
Page 7
AD9846A
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9846A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
EQUIVALENT INPUT CIRCUITS
DVDD
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2
N
codes) when N is the bit resolution of the
ADC. For the AD9846A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9846A’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9846A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000)
MSBLSB
D10D9D8D7D6D5D4D3D2D1D0Gain (dB)*
XXXXX0 1 1111+10.0
••
••
••
000000+4.3
111111+4.0
••
••
••
100000–2.0
*Control Register Bit D3 must be set High (PxGA Enable) to use the PxGA Gain Registers.
–16–
REV. 0
Page 17
AD9846A
CIRCUIT DESCRIPTION AND OPERATION
The AD9846A signal processing chain is shown in Figure 25.
Each processing step is essential in achieving a high-quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dcrestore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V single supply of
the AD9846A.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal respectively. The CCD signal is sampled on
the rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (t
) of 3 ns is caused by internal
ID
propagation delays.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded black
reference pixels. Unlike some AFE architectures, the AD9846A
removes this offset in the input stage to minimize the effect of a
gain change on the system black level, usually called the “gain
step.” Another advantage of removing this offset at the input
stage is to maximize system headroom. Some area CCDs have
large black level offset voltages, which, if not corrected at the
input stage, can significantly reduce the available headroom in
the internal circuitry when higher VGA gain settings are used.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
together with CLPOB or separately. The CLPDM pulse should
be a minimum of 4 pixels wide.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA
has the capability to “multiplex” its gain value
on a pixel-to-pixel basis. This allows lower output color pixels to
be gained up to match higher output color pixels. Also, the PxGA
may be used to adjust the colors for white balance, reducing the
amount of digital processing that is needed. The four different gain
values are switched according to the “Color Steering” circuitry.
Seven different color steering modes for different types of CCD
color filter arrays are programmed in the AD9846A’s Control
Register. For example, Mosaic Separate steering mode accommodates the popular “Bayer” arrangement of Red, Green, and
Blue filters (see Figure 26).
0.1F
HD
CCDIN
CLPDM
VD
DC RESTORE
CDS
INPUT OFFSET
CLAMP
3
PxGA MODE
SELECTION
PxGA GAIN
REGISTERS
8-BIT
10
DAC
FILTERING
6
PxGA
–2dB TO +10dB
COLOR
STEERING
2
4:1
MUX
VGA GAIN
REGISTER
GAIN0
GAIN1
GAIN2
GAIN3
2dB TO 36dB
VGA
Figure 25. CCD-Mode Block Diagram
INTERNAL
V
REF
10-BIT
ADC
OPTICAL BLACK
CLAMP
DIGITAL
2V FULL SCALE
CLAMP LEVEL
REGISTER
10
DOUT
CLPOB
8
REV. 0
–17–
Page 18
AD9846A
CCD: PROGRESSIVE BAYER
RR
Gr
GbGb
BB
RR
Gr
GbGbBB
Gr
Gr
MOSAIC SEPARATE COLOR
STEERING MODE
LINE0GAIN0, GAIN1, GAIN0, GAIN1 ...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
Figure 26. CCD Color Filter Example: Progressive Scan
CCD: INTERLACED BAYER
EVEN FIELD
RR
Gr
RR
Gr
RR
Gr
RR
Gr
ODD FIELD
GbGbBB
GbGbBB
GbGbBB
GbGbBB
Gr
Gr
Gr
Gr
VD SELECTED COLOR
STEERING MODE
LINE0GAIN0, GAIN1, GAIN0, GAIN1 ...
LINE1
LINE2
LINE0GAIN2, GAIN3, GAIN2, GAIN3 ...
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
Figure 27. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
Selected mode should be used with this type of CCD (see Figure 27). The Color Steering performs the proper multiplexing of
the R, G, and B gain values (loaded into the PxGA
gain registers), and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA
channels is variable from –2 dB to +10 dB, controlled in 64 steps
through the serial interface. The PxGA
Timing section. The PxGA gain for each of the four
gain curve is shown in
Figure 28.
10
8
6
4
PxGA GAIN – dB
2
0
–2
40485608162431
32
(100000)
PxGA GAIN REGISTER CODE
(011111)
Figure 28. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface.
Combined with 4 dB from the PxGA
stage, the total gain range
for the AD9846A is 6 dB to 40 dB. The minimum gain of 6 dB
is needed to match a 1 V input signal with the ADC full-scale
range of 2 V. When compared to 1 V full-scale systems (such as
ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “linear-indB” characteristic. From code 512 to code 1023, the curve follows
a “linear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
Code RangeGain Equation (dB)
0–511Gain = 20 log
([658 + code]/[658 – code]) – 0.4
10
512 –1023Gain = (0.0354)(code) – 0.4
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 91 to 1023. The
Gain Accuracy Specifications also include the PxGA
gain of 4 dB,
for a total gain range of 6 dB to 40 dB.
36
30
24
18
VGA GAIN – dB
12
6
0
0
1272553835116397678951023
VGA GAIN REGISTER CODE
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 64 LSB may be programmed, with 8-bit resolution. The resulting error signal is
filtered to reduce noise, and the correction value is applied to
the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line,
but this loop can be updated more slowly to suit a particular
application. If external digital clamping is used during the post
processing, the AD9846A’s optical black clamping may be disabled
using Bit D5 in the Operation Register (see Serial Interface
Timing and Internal Register Description section). When the
loop is disabled, the Clamp Level Register may still be used
to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the ability to track
low-frequency variations in the black level will be reduced.
–18–
REV. 0
Page 19
AD9846A
A/D Converter
The AD9846A uses high-performance ADC architecture, optimized for high speed and low power. Differential Nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown in
TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9846A ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range (see TPC 3).
AUX1 Mode
For applications that do not require CDS, the AD9846A can be
configured to sample ac-coupled waveforms. Figure 30 shows
the circuit configuration for using the AUX1 channel input
(Pin 36). A single 0.1 µF ac-coupling capacitor is needed between
the input signal driver and the AUX1IN pin. An on-chip dc-bias
circuit sets the average value of the input signal to approximately
0.4 V, which is referenced to the midscale code of the ADC.
The VGA Gain register provides a gain range of 0 dB to 3 6 dB in
this mode of operation (see VGA Gain Curve, Figure 29).
The VGA gains up the signal level with respect to the 0.4 V bias
0.8V
INPUT SIGNAL
??V
0.1F
AUX1IN
0.4V
5k
0dB TO 36dB
level. Signal levels above the bias level will be further increased
to a higher ADC code, while signal levels below the bias level
will be further decreased to a lower ADC code.
AUX2 Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 31 shows the circuit
configuration for using the AUX2 channel input (Pin 34). A
external 0.1 µF blocking capacitor is used with the on-chip video
clamp circuit, to level-shift the input signal to a desired reference level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the
input signal to be equal to the value programmed into the Clamp
Level register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VII.)
ADCVGA
MIDSCALE
0.4V
0.4V
10
VGA GAIN
REGISTER
Figure 30. AUX1 Circuit Configuration
VGA GAIN
REGISTER
9
0dB TO 18dB
VGA
8
ADC
CLAMP LEVEL
REGISTER
CLAMP LEVEL
VIDEO
SIGNAL
0.1F
AUX2IN
BUFFER
VIDEO CLAMP
CIRCUIT
LPF
Figure 31. AUX2 Circuit Configuration
Table VII. VGA Gain Register Used for AUX2-Mode
MSBLSB
D10D9D8D7D6D5D4D3D2D1D0Gain (dB)
X0 XXXXXXXXX0.0
10000000000.0
••
••
••
111111111118.0
REV. 0
–19–
Page 20
AD9846A
APPLICATIONS INFORMATION
The AD9846A is a complete Analog Front End (AFE) product
for digital still camera and camcorder applications. As shown in
Figure 32, the CCD image (pixel) data is buffered and sent to
the AD9846A analog input through a series input capacitor. The
AD9846A performs the dc restoration, CDS, gain adjustment,
black level correction, and analog-to-digital conversion. The
AD9846A’s digital output data is then processed by the image
CCD
V-DRIVE
V
OUT
BUFFER
0.1F
CCD
TIMING
AD9846A
CCDIN
GENERATOR
TIMING
Figure 32. System Applications Diagram
processing ASIC. The internal registers of the AD9846A—used
to control gain, offset level, and other functions—are programmed
by the ASIC or microprocessor through a 3-wire serial digital
interface. A system timing generator provides the clock signals
for both the CCD and the AFE.
DIGITAL
OUT
OUTPUTS
SERIAL
INTERFACE
DIGITAL IMAGE
PROCESSING
ASIC
ADC
REGISTER
DATA
CDS/CLAMP
TIMING
–20–
REV. 0
Page 21
DATA
OUTPUTS
12
SERIAL
INTERFACE
(MSB) D9
3V
DRIVER
SUPPLY
ANALOG SUPPLY
3
SCK
SDATASLNC
STBYNCTHREE-STATE
NC
1
NC
PIN 1
2
IDENTIFIER
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
D8
11
12
13 14 15 16 17 18 19 20 21 22 23 24
DRVDD
0.1F
DVSS
DRVSS
AD9846A
TOP VIEW
(Not to Scale)
HD
DVDD1
DATACLK
PBLK
3V
DVSS
DVDD2
SHP
CLPOB
VRB
SHD
VRT
CML
3748 47 46 45 4439 3843 42 41 40
VD
CLPDM
0.1F
1.0F
1.0F
0.1F
36
35
34
33
32
31
30
29
28
27
26
25
8
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
BYP2
BYP1
AVDD1
AVSS
AVSS
NC = NO CONNECT
CLOCK
INPUTS
0.1F
0.1F
0.1F
0.1F
0.1F
3V
ANALOG SUPPLY
CCD SIGNAL
0.1F
3V
ANALOG SUPPLY
AD9846A
0.1F
3V
ANALOG SUPPLY
Figure 33. Recommended Circuit Configuration for CCD-Mode
Internal Power-On Reset Circuitry
After power-on, the AD9846A will automatically reset all internal registers and perform internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes will be ignored until the internal reset
operation is completed. Pin 43 (formerly RSTB on the AD984x
non-A products) is no longer used for the reset operation.
Toggling Pin 43 in the AD9846A will have no effect.
Grounding and Decoupling Recommendations
As shown in Figure 33, a single ground plane is recommended
for the AD9846A. This ground plane should be as continuous
as possible, particularly around Pins 25 through 39. This will
ensure that all analog decoupling capacitors provide the lowest
possible impedance path between the power and bypass pins
and their respective ground pins. All decoupling capacitors
should be located as close as possible to the package pins.
A single clean power supply is recommended for the AD9846A, but
a separate digital driver supply may be used for DRVDD (Pin
13). DRVDD should always be decoupled to DRVSS (Pin 14),
which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing digital
power dissipation, and reducing potential noise coupling. If the
digital outputs (Pins 3–12) must drive a load larger than 20 pF,
buffering is recommended to reduce digital code transition noise.
Alternatively, placing series resistors close to the digital output pins may also help reduce noise.
REV. 0
–21–
Page 22
AD9846A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP
(ST-48)
0.063 (1.60)
0.030 (0.75)
0.018 (0.45)
MAX
0.354 (9.00) BSC SQ
48
1
37
36
COPLANARITY
0.003 (0.08)
0.004 (0.09)
0.008 (0.2)
0
MIN
7
0
TOP VIEW
(PINS DOWN)
12
13
0.019 (0.5)
BSC
0.006 (0.15)
0.002 (0.05)
0.011 (0.27)
0.006 (0.17)
SEATING
PLANE
24
25
0.276
(7.00)
BSC
SQ
0.057 (1.45)
0.053 (1.35)
–22–
REV. 0
Page 23
–23–
Page 24
C02409–2.5–4/01(0)
–24–
PRINTED IN U.S.A.
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.