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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9845A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Complete 12-Bit 30 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHP
BANDGAP
REFERENCE
2:1
MUX
DOUT
AUX2IN
CLPDM
CCDIN
OFFSET
DAC
PBLK
AUX1IN
VRT
VRB
INTERNAL
TIMING
INTERNAL
BIAS
2dB~36dB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
10
8
CML
DIGITAL
INTERFACE
SDATASCK
SL
CLPOB
12
CDS
VGA
CLP
BUF
2:1
MUX
CLP
AD9845A
CONTROL
REGISTERS
CLP
ADC
4dB 6dB
COLOR
STEERING
HD VD
PxGA
6
FEATURES
30 MSPS Correlated Double Sampler (CDS)
4 dB 6 dB 6-Bit Pixel Gain Amplifier (
PxGA
®
)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
12-Bit 30 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 140 mW @ 3 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
PRODUCT DESCRIPTION
The AD9845A is a complete analog signal processor for CCD
applications. It features a 30 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9845A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
Pixel Gain Amplifier (PxGA), digitally controlled variable gain
amplifier (VGA), black level clamp, and a 12-bit A/D converter.
Additional input modes are provided for processing analog
video signals.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input configuration, and
power-down modes.
The AD9845A operates from a single 3 V power supply, typically dissipates 140 mW, and is packaged in a 48-lead LQFP.
PxGA is a registered trademark of Analog Devices, Inc.
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AD9845A–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating –20 +85 °C
Storage –65 +150 °C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver 2.7 3.6 V
POWER CONSUMPTION
Normal Operation (Specified Under Each Mode of Operation)
Power-Down Modes
Fast Recovery Mode 90 mW
Standby 5 mW
Total Power-Down 1 mW
MAXIMUM CLOCK RATE 30 MHz
A/D CONVERTER
Resolution 12 Bits
Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB
No Missing Codes 12 Bits Guaranteed
Full-Scale Input Voltage 2.0 V
Data Output Coding Straight Binary
VOLTAGE REFERENCE
Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.1 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current I
IH
10 µA
Low Level Input Current I
IL
10 µA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA V
OH
2.2 V
Low Level Output Voltage, IOL = 2 mA V
OL
0.5 V
Specifications subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
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AD9845A
Parameter Min Typ Max Unit Notes
P
OWER CONSUMPTION 140 mW See TPC 1 for Power Curves
MAXIMUM CLOCK RATE 30 MHz
CDS
Gain 0 dB
Allowable CCD Reset Transient
1
500 mV See Input Waveform in Footnote 1
Max Input Range Before Saturation
1
1.0 V p-p PxGA Gain at 4 dB
Max CCD Black Pixel Amplitude
1
200 mV
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range 1.0 V p-p
Max Output Range 1.6 V p-p
Gain Control Resolution 64 Steps
Gain Monotonicity Guaranteed
Gain Range (Two’s Complement Coding) See Figure 28 for PxGA
Gain Curve
Min Gain (PxGA Gain Code 32) –2 dB
Max Gain (PxGA Gain Code 31) 10 dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range See Figure 29 for VGA Gain Curve
Low Gain (VGA Gain Code 91) 2 dB
Max Gain (VGA Gain Code 1023) 36 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output
Min Clamp Level 0 LSB
Max Clamp Level 255 LSB
SYSTEM PERFORMANCE Specifications Include Entire Signal Chain
Gain Accuracy (VGA Code 91 to 1023)
2
–0.5 +0.5 Use Equations on Page 18 to Calculate Gain
PxGA
Gain Accuracy
Min Gain (PxGA Register Code 32) –1 0 +1 dB VGA Gain Fixed at 2 dB (Code 91)
Max Gain (PxGA
Code 31) 11 12 13 dB VGA Gain Fixed at 2 dB (Code 91)
Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied
Total Output Noise 0.6 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply
POWER-UP RECOVERY TIME Normal Clock Signals Applied
Fast Recovery Mode 0.1 ms
Reference Standby Mode 1 ms
Total Shutdown Mode 3 ms
Power-Off Condition 15 ms
NOTES
1
Input Signal Characteristics defined as follows:
200mV MAX
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V MAX
INPUT SIGNAL RANGE
2
PxGA gain fixed at 4 dB (Code 63).
Specifications subject to change without notice.
CCD-MODE SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= f
SHP
= f
SHD
= 30 MHz, unless otherwise noted.)
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AD9845A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 100 mW
MAXIMUM CLOCK RATE 30 MHz
INPUT BUFFER
Gain 0dB
Max Input Range 1.0 V p-p
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 1023 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 36 dB
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 100 mW
MAXIMUM CLOCK RATE 30 MHz
INPUT BUFFER (Same as AUX1-MODE)
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 512 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 18 dB
ACTIVE CLAMP
Clamp Level Resolution 256 Steps
Clamp Level (Measured at ADC Output)
Min Clamp Level 0 LSB
Max Clamp Level 255 LSB
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
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AD9845A
–5–
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CONV
32 33 ns
DATACLK Hi/Low Pulsewidth t
ADC
13 16.7 ns
SHP Pulsewidth t
SHP
5 8.3 ns
SHD Pulsewidth t
SHD
5 8.3 ns
CLPDM Pulsewidth t
CDM
4 10 Pixels
CLPOB Pulsewidth
1
t
COB
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S1
0 8.3 ns
SHP Rising Edge to SHD Rising Edge t
S2
13 16.7 ns
Internal Clock Delay t
ID
3.0 ns
Inhibited Clock Period t
INH
10 ns
DATA OUTPUTS
Output Delay t
OD
14.5 16 ns
Output Hold Time t
H
7.0 7.6 ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
NOTES
1
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9845A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
(CL = 20 pF, f
SAMP
= 30 MHz, CCD-Mode Timing in Figures 10 and 11, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 26–29.)
ABSOLUTE MAXIMUM RATINGS
With
Respect
Parameter To Min Max Unit
AVDD1, AVDD2 AVSS –0.3 +3.9 V
DVDD1, DVDD2 DVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V
CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V
VRT, VRB, CMLEVEL AVSS –0.3 AVDD + 0.3 V
BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature 300 °C
(10 sec)
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9845AJST –20°C to +85°C Thin Plastic ST-48
Quad Flatpack
(LQFP)
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA
= 92°C
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AD9845A
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PIN FUNCTION DESCRIPTIONS
Pin Number Name Type Description
1–12 D0–D11 DO Digital Data Outputs
13 DRVDD P Digital Output Driver Supply
14 DRVSS P Digital Output Driver Ground
15, 41 DVSS P Digital Ground
16 DATACLK DI Digital Data Output Latch Clock
17 DVDD1 P Digital Supply
18 HD DI Horizontal Drive. Used with VD for Color Steering Control
19 PBLK DI Preblanking Clock Input
20 CLPOB DI Black Level Clamp Clock Input
21 SHP DI CDS Sampling Clock for CCD’s Reference Level
22 SHD DI CDS Sampling Clock for CCD’s Data Level
23 CLPDM DI Input Clamp Clock Input
24 VD DI Vertical Drive. Used with HD for Color Steering Control
25, 26, 35 AVSS P Analog Ground
27 AVDD1 P Analog Supply
28 BYP1 AO Internal Bias Level Decoupling
29 BYP2 AO Internal Bias Level Decoupling
30 CCDIN AI Analog Input for CCD Signal
31 NC NC Internally Not Connected
32 BYP4 AO Internal Bias Level Decoupling
33 AVDD2 P Analog Supply
34 AUX2IN AI Analog Input
36 AUX1IN AI Analog Input
37 CML AO Internal Bias Level Decoupling
38 VRT AO A/D Converter Top Reference Voltage Decoupling
39 VRB AO A/D Converter Bottom Reference Voltage Decoupling
40 DVDD2 P Digital Supply
42 THREE-STATE DI Digital Output Disable. Active High
43 NC NC May be tied high or low. Do not leave floating.
44 STBY DI Standby Mode, Active High. Same as Serial Interface
45 NC NC Internally Not Connected. May be Tied High or Low
46 SL DI Serial Digital Interface Load Pulse
47 SDATA DI Serial Digital Interface Data
48 SCK DI Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
PIN CONFIGURATIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
(LSB) D0
D1
D2
D3
D4
D5
D6
NC = NO CONNECT
D7
D8
D9
D10
BYP2
BYP1
AVDD1
AVSS
AD9845A
(MSB) D11
AVSS
SCK
SDATASLNC
STBYNCTHREE-STATE
DVSS
DVDD2
VRB
VRT
CML
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
HD
PBLK
CLPOB
SHP
SHD
CLPDM
VD
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AD9845A
–7–
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 12-bit
resolution indicates that all 4096 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD984x from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2
N
codes) when N is the bit resolution of the
ADC. For the AD9845A, 1 LSB is 500 µV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD984x’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD984x
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
330
DVDD
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DVSS
DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Figure 2. Data Outputs—D0–D11
60
ACVDD
ACVSS
ACVSS
Figure 3. CCDIN (Pin 30)
330
DVDD
DVSS
DVDD
DVSS
DVSS
DATA IN
RNW
DATA OUT
Figure 4. SDATA (Pin 47)
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AD9845A
–8–
–Typical Performance Characteristics
SAMPLE RATE – MHz
160
130
100
10 30
20
POWER DISSIPATION – mW
110
120
140
150
VDD = 3.3V
VDD = 3.0V
VDD = 2.7V
TPC 1. Power vs. Sample Rate
0 1000500 1500 2000 2500 3000 3500 4000
0
–0.5
0.5
–0.25
0.25
TPC 2. Typical DNL Performance
VGA GAIN CODE – LSB
15
0
0 1000400
OUTPUT NOISE – LSB
200
5
600
10
800
TPC 3. Output Noise vs. VGA Gain
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AD9845A
–9–
CCD-MODE AND AUX MODE TIMING
N N+1 N+2 N+9 N+10
t
ID
t
ID
t
S1
t
S2
t
CP
t
INH
t
OD
t
H
N–10 N–9N–8N–1N
NOTES:
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
Figure 5. CCD-Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
CLPDM
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
DUMMY PIXELS EFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
Figure 6. Typical CCD-Mode Line Clamp Timing
DATACLK
OUTPUT
DATA
VIDEO
SIGNAL
N
N+1
N+2
N+8
N+9
N–10 N–9N–8N–1N
t
ID
t
CP
t
OD
t
H
Figure 7. AUX-Mode Timing
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AD9845A
–10–
PIXEL GAIN AMPLIFIER (PxGA) TIMING
FRAME n
LINE 0 LINE 1 LINE 2 LINE m
0101... 2323... 0101...
LINE m–1 LINE 0 LINE 1 LINE 2 LINE m
0101... 2323...
0101...
LINE m–1
NOTE: 0 = GAIN0
,
1 = GAIN1, 2 = GAIN2, 3 = GAIN3
FRAME n+1
VD
HD
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
SHP
HD
3ns MIN
3ns MIN
PxGA GAIN
GAIN0 GAIN1 GAIN0
GAIN3
GAIN2
GAINXGAINX
VD
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
5 PIXEL MIN
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
0101... 2323... 0101...
0101... 2323...
0101...
HD
LINE 0 LINE 1 LINE 2 LINE mLINE m–1 LINE 0 LINE 1 LINE 2 LINE mLINE m–1
EVEN FIELD ODD FIELD
NOTE: 0 = GAIN0
,
1 = GAIN1, 2 = GAIN2, 3 = GAIN3
VD
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
SHP
HD
PxGA
GAIN
GAIN0 GAIN1 GAIN0
GAIN3GAIN2
GAINX
GAINX
3ns MIN
3ns MIN
5 PIXEL MIN
VD
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
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AD9845A
–11–
HD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
012012012... 012012012......01201
VD
LINE n LINE n+1
Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA GAIN
GAIN1
VD
GAIN2 GAIN0
GAIN1GAIN0
GAINXGAIN0GAINX
3ns MIN
5 PIXEL MIN
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.
Figure 13. PxGA Mode 3 (3-Color) Detailed Timing
VD
HD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
LINE n LINE n+1
012301230123......0123001230123012...
Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA GAIN
GAIN1
VD
GAIN2 GAIN0
GAIN1GAIN0
GAINXGAIN0
GAINX
3ns MIN
5 PIXEL MIN
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.
Figure 15. PxGA Mode 4 (4-Color) Detailed Timing
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AD9845A
–12–
0101...
0101...
0101...
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
2323...
2323...
2323...
HD
LINE 0 LINE 1 LINE 2 LINE m
LINE m–1
LINE 0 LINE 1 LINE 2 LINE m
LINE m–1
EVEN FIELD
ODD FIELD
VD
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA GAIN
GAIN0 GAIN1 GAIN0
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101...
(
EVEN) OR 2323 ... (ODD).
GAIN3
GAIN2GAINXGAINX
3ns MIN
VD
3ns MIN
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
FRAME n
VD
HD
LINE 0 LINE 1 LINE 2 LINE m
0101...
1212...
0101...
LINE m–1 LINE 0 LINE 1 LINE 2 LINE m
0101...
1212...
0101...
LINE m–1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
FRAME n+1
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
SHP
HD
PxGA GAIN
GAIN0 GAIN1 GAIN0
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
GAIN2GAINXGAINX GAIN1
3ns MIN
VD
3ns MIN
5 PIXEL MIN
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
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AD9845A
–13–
SHP
HD
3ns MIN
GAIN1
VD
GAIN0
GAIN2
GAIN3
3ns MIN
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. VD = 0 AND HD = 0 SELECTS GAIN0.
3. VD = 0 AND HD = 1 SELECTS GAIN1.
4. VD = 1 AND HD = 0 SELECTS GAIN2.
5. VD = 1 AND HD = 1 SELECTS GAIN3.
GAIN0
PxGA GAIN
NOTES:
Figure 20. PxGA Mode 7 (User-Specified) Detailed Timing
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AD9845A
–14–
SDATA
SCK
SL
RNW TEST BIT
0
A2 0A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 21. Serial Write Operation
SDATA
SCK
SL
RNW TEST BIT
10
0
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON
SCK FALLING EDGES.
t
DV
Figure 22. Serial Readback Operation
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register Address Data Bits
Name A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Operation 0 0 0 Channel Select Power-Down Software OB Clamp 0* 1** 0* 0* 0*
CCD/AUX1/2 Modes Reset On/Off
VGA Gain 1 0 0 LSB MSB X
Clamp Level 0 1 0 LSB MSB X X X
Control 1 1 0 Color Steering Mode PxGA Clock Polarity Select for 0* 0* Three- X
Selection On/Off SHP/SHD/CLP/DATA State
PxGA Gain0 0 0 1 LSB MSB X X X X X
PxGA Gain1 1 0 1 LSB MSB X X X X X
PxGA Gain2 0 1 1 LSB MSB X X X X X
PxGA Gain3 1 1 1 LSB MSB X X X X X
*Internal use only. Must be set to zero.
**
Must be set to one.
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AD9845A
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SDATA
SCK
SL
A0
A1 A2
D0
D10 D0 D9
D0
D0D7
RNW
00 D9000 D0
1
21735342726166543 44 45 51 6362575650 68
...
...
...
...
...
...
...
...
10 BITS
ACG GAIN
D5
D0 D5 D0 D0
D5
D5
...
...
...
... ...
...
... ...
...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
8 BITS
CLAMP LEVEL
10 BITS
CONTROL
11 BITS
OPERATION
6 BITS
PxGA GAIN0
6 BITS
PxGA GAIN1
6 BITS
PxGA GAIN2
6 BITS
PxGA GAIN3
Figure 23. Continuous Serial Write Operation to All Registers
SDATA
A0 A1
A2
D1D0 D1 D2 D3 D4 D5 D0
D3D2D4
0
0
23 2412 17161514131211109876543 2918
...
...
D5001 D5D5D0
D0
RNW
SCK
SL
PxGA GAIN0
PxGA GAIN1
PxGA GAIN3
PxGA GAIN2
...
...
...
Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers
Table II. Operation Register Contents (Default Value x000)
Optical Black Clamp Reset Power-Down Modes Channel Selection
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
*
0*0*1** 0
*
0 Enable Clamping 0 Normal 0 0 Normal Power 0 0 CCD Mode
1 Disable Clamping 1 Reset All Registers 0 1 Fast Recovery 0 1 AUX1 Mode
to Default 1 0 Standby 1 0 AUX2 Mode
1 1 Total Power-Down 11Test Only
*Must be set to zero.
**Set to one.
Table III. VGA Gain Register Contents (Default Value x096)
MSB LSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB)
X00 010111112.0
••
••
••
11 1111111035.965
11 1111111136.0
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AD9845A
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Table IV. Clamp Level Register Contents (Default Value x080)
MSB LSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp Level (LSB)
XXX0000 0000 0
0000 0001 1
0000 0010 2
• •
• •
• •
11111110 254
11111111 255
Table V. Control Register Contents (Default Value x000)
Data Out DATACLK CLP/PBLK SHP/SHD PxGA Color Steering Modes
D10 D9 D8 D7 D6 D5 D4 D3
**
D2 D1 D0
X 0 Enable 0* 0* 0 Rising Edge Trigger 0 Active Low 0 Active Low 0 Disable 0 0 0 Steering Disabled
1 Three-State 1 Falling Edge Trigger 1 Active High 1 Active High 1 Enable 0 0 1 Mosaic Separate
0 1 0 Interlace
0 1 1 3-Color
1 0 0 4-Color
1 0 1 VD Selected
1 1 0 Mosaic Repeat
1 1 1 User Specified
*Must be set to zero.
**When D3 = 0 (PxGA disabled) the PxGA gain is fixed to 4 dB.
Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000)
MSB LSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB)*
XXXXX0 1 1111+10.0
••
••
••
000000+4.3
111111+4.0
••
••
••
100000–2.0
*Control Register Bit D3 must be set High (PxGA Enable) to use the PxGA Gain Registers.
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CIRCUIT DESCRIPTION AND OPERATION
The AD9845A signal processing chain is shown in Figure 25.
Each processing step is essential in achieving a high-quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dcrestore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V single supply of
the AD9845A.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal respectively. The CCD signal is sampled on
the rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (t
ID
) of 3 ns is caused by internal
propagation delays.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded black
reference pixels. Unlike some AFE architectures, the AD9845A
removes this offset in the input stage to minimize the effect of a
gain change on the system black level, usually called the “gain
step.” Another advantage of removing this offset at the input
stage is to maximize system headroom. Some area CCDs have
large black level offset voltages, which, if not corrected at the
input stage, can significantly reduce the available headroom in
the internal circuitry when higher VGA gain settings are used.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
together with CLPOB or separately. The CLPDM pulse should
be a minimum of 4 pixels wide.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA
has the capability to “multiplex” its gain value
on a pixel-to-pixel basis. This allows lower output color pixels to
be gained up to match higher output color pixels. Also, the PxGA
may be used to adjust the colors for white balance, reducing the
amount of digital processing that is needed. The four different gain
values are switched according to the “Color Steering” circuitry.
Seven different color steering modes for different types of CCD
color filter arrays are programmed in the AD984x’s Control Register. For example, Mosaic Separate steering mode accommodates
the popular “Bayer” arrangement of Red, Green, and Blue filters
(see Figure 26).
2dB TO 36dB
CLPDM
CCDIN
DIGITAL
FILTERING
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
0.1F
DOUT
12-BIT
ADC
VGA
8-BIT
DAC
CLAMP LEVEL
REGISTER
8
VGA GAIN
REGISTER
10
CDS
INPUT OFFSET
CLAMP
INTERNAL
V
REF
2V FULL SCALE
COLOR
STEERING
4:1
MUX
3
GAIN0
GAIN1
GAIN2
GAIN3
PxGA
–2dB TO +10dB
PxGA
MODE
SELECTION
2
6
VD
HD
PxGA
GAIN
REGISTERS
12
Figure 25. CCD-Mode Block Diagram
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AD9845A
–18–
RR
Gb Gb
Gr
Gr
BB
CCD: PROGRESSIVE BAYER
LINE0 GAIN0, GAIN1, GAIN0, GAIN1 ...
RR
Gr
Gr
Gb GbBB
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 26. CCD Color Filter Example: Progressive Scan
LINE0 GAIN0, GAIN1, GAIN0, GAIN1 ...
RR
Gr
Gr
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
Gb GbBB
LINE0 GAIN2, GAIN3, GAIN2, GAIN3 ...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
ODD FIELD
Gb GbBB
Gb GbBB
Gb GbBB
RR
Gr
Gr
RR
Gr
Gr
RR
Gr
Gr
Figure 27. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
Selected mode should be used with this type of CCD (see Figure 27). The Color Steering performs the proper multiplexing of
the R, G, and B gain values (loaded into the PxGA
gain registers), and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA
Timing section. The PxGA gain for each of the four
channels is variable from –2 dB to +10 dB, controlled in 64 steps
through the serial interface. The PxGA
gain curve is shown in
Figure 28.
PxGA GAIN REGISTER CODE
10
32
PxGA GAIN – dB
40 48 56 0 8 16 24 31
8
6
4
2
0
–2
(100000)
(011111)
Figure 28. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface.
Combined with 4 dB from the PxGA
stage, the total gain range
for the AD9845A is 6 dB to 40 dB. The minimum gain of 6 dB
is needed to match a 1 V input signal with the ADC full-scale
range of 2 V. When compared to 1 V full-scale systems (such as
ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “linear-indB” characteristic. From code 512 to code 1023, the curve follows
a “linear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
Code Range Gain Equation (dB)
0–511 Gain = 20 log
10
([658 + code]/[658 – code]) – 0.4
512 –1023 Gain = (0.0354)(code) – 0.4
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 91 to 1023. The
Gain Accuracy Specifications also include the PxGA
gain of 4 dB,
for a total gain range of 6 dB to 40 dB.
VGA GAIN REGISTER CODE
36
0
VGA GAIN – dB
127 255 383 511 639 767 895 1023
30
24
18
12
6
0
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 255 LSB may be programmed, with 8-bit resolution. The resulting error signal is
filtered to reduce noise, and the correction value is applied to
the ADC input through a D/A converter. Normally, the optical
black clamp loop is turned on once per horizontal line, but this
loop can be updated more slowly to suit a particular application.
If external digital clamping is used during the post processing,
the AD9845A optical black clamping may be disabled using Bit
D5 in the Operation Register (see Serial Interface Timing and
Internal Register Description section). When the loop is disabled,
the Clamp Level Register may still be used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the ability to track
low-frequency variations in the black level will be reduced.
Page 19
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AD9845A
–19–
A/D Converter
The AD9845A uses high-performance ADC architecture, optimized for high speed and low power. Differential Nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown in
TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9845A’s ADC uses a 2 V input range. Better noise performance results from using a larger ADC full-scale range (see
TPC 3).
AUX1 Mode
For applications that do not require CDS, the AD9845A can be
configured to sample ac-coupled waveforms. Figure 30 shows
the circuit configuration for using the AUX1 channel input
(Pin 36). A single 0.1 µF ac-coupling capacitor is needed between
the input signal driver and the AUX1IN pin. An on-chip dc-bias
circuit sets the average value of the input signal to approximately
0.4 V, which is referenced to the midscale code of the ADC.
The VGA Gain register provides a gain range of 0 dB to 3 6 dB in
this mode of operation (see VGA Gain Curve, Figure 29).
The VGA gains up the signal level with respect to the 0.4 V bias
level. Signal levels above the bias level will be further increased
to a higher ADC code, while signal levels below the bias level
will be further decreased to a lower ADC code.
AUX2 Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 31 shows the circuit
configuration for using the AUX2 channel input (Pin 34). A
external 0.1 µF blocking capacitor is used with the on-chip video
clamp circuit, to level-shift the input signal to a desired reference level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the
input signal to be equal to the value programmed into the Clamp
Level register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VII.)
AUX1IN
0.1F
VGA GAIN
REGISTER
ADCVGA
10
5k
0.4V
0.4V
INPUT SIGNAL
??V
0.8V
0.4V
MIDSCALE
0dB TO 36dB
Figure 30. AUX1 Circuit Configuration
0dB TO 18dB
8
AUX2IN
BUFFER
0.1F
VIDEO
SIGNAL
9
CLAMP LEVEL
LPF
VGA GAIN
REGISTER
ADC
VGA
VIDEO CLAMP
CIRCUIT
CLAMP LEVEL
REGISTER
Figure 31. AUX2 Circuit Configuration
Table VII. VGA Gain Register Used for AUX2-Mode
MSB LSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB)
X0 XXXXXXXXX0.0
10000000000.0
••
••
••
111111111118.0
Page 20
REV. 0
AD9845A
–20–
CCD
CCDIN
BUFFER
V
OUT
0.1F
AD9845A
ADC
OUT
REGISTER
DATA
SERIAL
INTERFACE
DIGITAL
OUTPUTS
DIGITAL IMAGE
PROCESSING
ASIC
TIMING
GENERATOR
V-DRIVE
CCD
TIMING
CDS/CLAMP
TIMING
Figure 32. System Applications Diagram
APPLICATIONS INFORMATION
The AD9845A is a complete Analog Front End (AFE) product
for digital still camera and camcorder applications. As shown in
Figure 32, the CCD image (pixel) data is buffered and sent to
the AD9845A analog input through a series input capacitor.
The AD9845A performs the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion.
The AD9845A’s digital output data is then processed by the
image processing ASIC. The internal registers of the AD984x—
used to control gain, offset level, and other functions—are
programmed by the ASIC or microprocessor through a 3-wire
serial digital interface. A system timing generator provides the
clock signals for both the CCD and the AFE.
Page 21
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AD9845A
–21–
Internal Power-On Reset Circuitry
After power-on, the AD9845A will automatically reset all internal registers and perform internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes will be ignored until the internal reset operation is completed. Pin 43 (formerly RSTB on the AD984x non-A
products) is no longer used for the reset operation. Toggling Pin
43 in the AD9845A will have no effect.
Grounding and Decoupling Recommendations
As shown in Figure 33, a single ground plane is recommended
for the AD9845A. This ground plane should be as continuous
as possible, particularly around Pins 25 through 39. This will
ensure that all analog decoupling capacitors provide the lowest
possible impedance path between the power and bypass pins and
their respective ground pins. All decoupling capacitors should
be located as close as possible to the package pins. A single clean
power supply is recommended for the AD9845A, bu t a separate
digital driver supply may be used for DRVDD (Pin 13). DRVDD
should always be decoupled to DRVSS (Pin 14), which should
be connected to the analog ground plane. Advantages of using
a separate digital driver supply include using a lower voltage
(2.7 V) to match levels with a 2.7 V ASIC, reducing digital power
dissipation, and reducing potential noise coupling. If the digital
outputs (Pins 3–12) must drive a load larger than 20 pF, buffering is recommended to reduce digital code transition noise.
Alternatively, placing series resistors close to the digital output pins may also help reduce noise.
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
3748 47 46 45 44 39 3843 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
BYP2
BYP1
AVDD1
AVSS
AVSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
(MSB) D11
AD9845A
SCK
SDATASLNC
STBY
RSTB
THREE-STATE
DVSS
DVDD2
VRB
VRT
CML
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
HD
PBLK
CLPOB
SHP
SHD
CLPDM
VD
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
3V
ANALOG SUPPLY
CCD SIGNAL
3V
ANALOG SUPPLY
12
DATA
OUTPUTS
3
SERIAL
INTERFACE
0.1F
1.0F
1.0F
0.1F
3V
ANALOG SUPPLY
8
CLOCK
INPUTS
0.1F
0.1F
3V
ANALOG SUPPLY
3V
DRIVER
SUPPLY
NC = NO CONNECT
D9
D10
Figure 33. Recommended Circuit Configuration for CCD-Mode
Page 22
REV. 0
AD9845A
–22–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP
(ST-48)
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.019 (0.5)
BSC
0.276
(7.00)
BSC
SQ
0.011 (0.27)
0.006 (0.17)
0.354 (9.00) BSC SQ
0.063 (1.60)
MAX
0.030 (0.75)
0.018 (0.45)
0.008 (0.2)
0.004 (0.09)
0
MIN
COPLANARITY
0.003 (0.08)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
7
0
0.057 (1.45)
0.053 (1.35)
C02385–2.5–1/01 (rev. 0)
PRINTED IN U.S.A.
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