Page 1
Complete 16-Bit Imaging
a
FEATURES
16-Bit 15 MSPS A/D Converter
3-Channel 16-Bit Operation up to 15 MSPS
1-Channel 16-Bit Operation up to 12.5 MSPS
2-Channel Mode for Mono Sensors with Odd/Even Outputs
Correlated Double Sampling
1~6ⴛ Programmable Gain
ⴞ300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output
Optional Single Byte Output Mode
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
28-Lead SSOP Package
Low Power CMOS: 400 mW (Typ)
Power-Down Mode Available
APPLICATIONS
Flatbed Document Scanners
Digital Copier
Multifunction Peripherals
Infrared Imaging Applications
Machine Vision
Signal Processor
AD9826
PRODUCT DESCRIPTION
The AD9826 is a complete analog signal processor for imaging
applications. It features a 3-channel architecture designed to
sample and condition the outputs of trilinear color CCD arrays.
Each channel consists of an input clamp, Correlated Double
Sampler (CDS), offset DAC, and Programmable Gain Amplifier
(PGA), multiplexed to a high-performance 16-bit A/D converter.
The AD9826 can operate at speeds greater than 15 MSPS with
reduced performance.
The CDS amplifiers may be disabled for use with sensors that
do not require CDS, such as Contact Image Sensors (CIS),
CMOS active pixel sensors, and Focal Plane Arrays.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single byte output mode. The internal registers are programmed
through a 3-wire serial interface, and provide adjustment of
the gain, offset, and operating mode.
The AD9826 operates from a single 5 V power supply, typically
consumes 400 mW of power, and is packaged in a 28-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
VINR
VING
VINB
OFFSET
AVDD AVSS
CDS
CDS
CDS
INPUT
CLAMP
BIAS
CML
9-BIT
9-BIT
9-BIT
DAC
DAC
DAC
CAPT
PGA
PGA
PGA
CAPB
6
RED
9
GREEN
BLUE
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
AVSS
AVDD
BANDGAP
REFERENCE
3:1
MUX
CONFIGURATION
REGISTER
MUX
REGISTER
RED
GREEN
GAIN
BLUE
REGISTERS
OFFSET
REGISTERS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
16-BIT
ADC
ADCCLKCDSCLK2CDSCLK1
DRVDD DRVSS
AD9826
16
16:8
MUX
DIGITAL
CONTROL
INTERFACE
OEB
8
DOUT
SCLK
SLOAD
SDATA
Page 2
AD9826–SPECIFICA TIONS
(T
to T
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
MAX
ANALOG SPECIFICATIONS
MIN
Gain = 1, Input range = 4 V p-p, unless otherwise noted.)
Parameter Min Typ Max Unit
MAXIMUM CONVERSION RATE
3-Channel Mode with CDS 30 MSPS
2-Channel Mode with CDS 30 MSPS
1-Channel Mode with CDS 18 MSPS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution 16 Bits
Integral Nonlinearity (INL) ±16 LSB
Differential Nonlinearity (DNL) ±0.5 LSB
No Missing Codes Guaranteed
ANALOG INPUTS
Input Signal Range (Programmable)
Allowable Reset Transient
Input Limits
2
1
1
2.0/4.0 V p-p
1.0 V
AVSS – 0.3 AVDD + 0.3 V
Input Capacitance 10 pF
Input Bias Current 10 nA
AMPLIFIERS
PGA Gain 1 6 V/V
PGA Gain Resolution
2
64 Steps
PGA Gain Monotonicity Guaranteed
Programmable Offset –300 +300 mV
Programmable Offset Resolution 512 Steps
Programmable Offset Monotonicity Guaranteed
NOISE AND CROSSTALK
Total Output Noise @ PGA Minimum 3.0 LSB rms
Total Output Noise @ PGA Maximum 9.0 LSB rms
Channel-to-Channel Crosstalk
@ 15 MSPS 70 dB
@ 6 MSPS 90 dB
POWER SUPPLY REJECTION
AVDD = 5 V 0.25 V 0.1 % FSR
DIFFERENTIAL VREF (at 25°C)
CAPT–CAPB 2.0 V
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –65 +150 °C
POWER SUPPLIES
AVDD 4.75 5.0 5.25 V
DRVDD 3.0 5.0 5.25 V
OPERATING CURRENT
AVDD 75 mA
DRVDD 5 mA
Power-Down Mode 200 µA
POWER DISSIPATION
3-Channel Mode 400 mW
1-Channel Mode 300 mW
NOTES
1
Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.
4V SET BY INPUT CLAMP
1V TYP
RESET TRANSIENT
2
The PGA Gain is approximately “linear in dB” and follows the equation:
Specifications subject to change without notice.
(3V OPTION ALSO AVAILABLE)
4V p-p MAX INPUT SIGNAL RANGE
GND
ain=
1+5.0
6.0
where G is the register value.
63 – G
63
G
ADCCLK
= 15 MHz, f
CDSCLK1
= f
= 5 MHz, PGA
CDSCLK2
–2–
REV. A
Page 3
AD9826
(T
to T
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
MAX
DIGITAL SPECIFICATIONS
MIN
CL = 10 pF, unless otherwise noted.)
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
Input Capacitance C
IH
IL
IH
IL
IN
2.0 V
LOGIC OUTPUTS
High Level Output Voltage V
Low Level Output Voltage V
High Level Output Current I
Low Level Output Current I
OH
OL
OH
OL
4.5 V
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage, (I
= 50 µA) V
OH
Low Level Output Voltage (IOL = 50 µA) V
Specifications subject to change without notice.
(T
to T
TIMING SPECIFICATIONS
MIN
, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
MAX
OH
OL
2.95 V
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
3-Channel Pixel Rate t
1-Channel Pixel Rate t
ADCCLK Pulsewidth t
CDSCLK1 Pulsewidth t
CDSCLK2 Pulsewidth t
CDSCLK1 Falling to CDSCLK2 Rising t
ADCCLK Falling to CDSCLK2 Rising t
CDSCLK2 Rising to ADCCLK Rising t
CDSCLK2 Falling to ADCCLK Falling t
CDSCLK2 Falling to CDSCLK1 Rising t
Aperture Delay for CDS Clocks t
PRA
PRB
ADCLK
C1
C2
C1C2
ADC2
C2ADR
C2ADF
C2C1
AD
200 ns
80 ns
30 ns
8ns
8ns
0ns
0ns
5ns
30 ns
5ns
SERIAL INTERFACE
Maximum SCLK Frequency f
SLOAD to SCLK Set-Up Time t
SCLK to SLOAD Hold Time t
SDATA to SCLK Rising Set-Up Time t
SCLK Rising to SDATA Hold Time t
SCLK Falling to SDATA Valid t
SCLK
LS
LH
DS
DH
RDV
10 MHz
10 ns
10 ns
10 ns
10 ns
10 ns
DATA OUTPUTS
Output Delay t
3-State to Data Valid t
Output Enable High to 3-State t
OD
DV
HZ
Latency (Pipeline Delay) 3 (Fixed) Cycles
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz,
0.8 V
10 µA
10 µA
10 pF
0.1 V
50 µA
50 µA
0.05 V
2ns
6ns
10 ns
10 ns
REV. A
–3–
Page 4
AD9826
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter To Min Max Unit
VIN, CAPT, CAPB AVSS –0.3 AVDD + 0.3 V
Digital Inputs AVSS –0.3 AVDD + 0.3 V
AVDD AVSS –0.5 +6.5 V
DRVDD DRVSS –0.5 +6.5 V
AVSS DRVSS –0.3 +0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature –65 +150 °C
Lead Temperature 300 °C
(10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Model Range Description Option
AD9826KRS –40°C to +85°C 5.3 mm SSOP RS-28
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 5.3 mm SSOP
θ
= 109°C/W
JA
θ
= 39°C/W
JC
ORDERING GUIDE
Temperature Package Package
–4–
REV. A
Page 5
PIN CONFIGURATION
AD9826
OEB
DRVDD
DRVSS
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
AD9826
7
TOP VIEW
8
(Not to Scale)
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVD D
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVD D
SLOAD
SCLK
SDATA
CDSCLK1
CDSCLK2
ADCCLK
(MSB) D7
(LSB) D0
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Type Description
1 CDSCLK1 DI CDS Reference Level Sampling Clock
2 CDSCLK2 DI CDS Data Level Sampling Clock
3 ADCCLK DI A/D Converter Sampling Clock
4 OEB DI Output Enable, Active Low
5 DRVDD P Digital Output Driver Supply
6 DRVSS P Digital Output Driver Ground
7 D7 DO Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte
8 D6 DO Data Output. ADC DB14 High Byte, ADC DB6 Low Byte
9 D5 DO Data Output. ADC DB13 High Byte, ADC DB5 Low Byte
10 D4 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
11 D3 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
12 D2 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
13 D1 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
14 D0 DO Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte
15 SDATA DI/DO Serial Interface Data Input/Output
16 SCLK DI Serial Interface Clock Input
17 SLOAD DI Serial Interface Load Pulse
18, 28 AVDD P 5 V Analog Supply
19, 27 AVSS P Analog Ground
20 CAPB AO ADC Bottom Reference Voltage Decoupling
21 CAPT AO ADC Top Reference Voltage Decoupling
22 VINB AI Analog Input, Blue Channel
23 CML AO Internal Bias Level Decoupling
24 VING AI Analog Input, Green Channel
25 OFFSET AO Clamp Bias Level Decoupling
26 VINR AI Analog Input, Red Channel
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. A
–5–
Page 6
AD9826
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from “zero scale” through “positive full
scale.” The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a level
1 1/ 2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed
to 16-bit resolution indicates that all 65536 codes, respectively, must be present over all operating ranges.
OFFSET ERROR
The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the
ideal level.
GAIN ERROR
The last code transition should occur for an analog value
1 1/2 LSB below the nominal full scale voltage. Gain error is
the deviation o f the actual difference between first and last
code transitions and the ideal difference between the first and
last code transitions.
INPUT REFERRED NOISE
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in
LSB, and can be converted to an equivalent voltage, using the
relationship 1 LSB = 4 V/65536 = 61 µV. The noise may then
be referred to the input of the AD9826 by dividing by the
PGA gain.
CHANNEL-TO-CHANNEL CROSSTALK
In an ideal 3-channel system, the signal in one channel will not
influence the signal level of another channel. The channel-tochannel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9826, one channel is grounded and the other two channels are exercised with full scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAY
The aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9826 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTION
Power supply rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
–6–
REV. A
Page 7
Typical Performance Characteristics–
AD9826
20
10
0
–10
–20
0
12000
24000 36000 48000 64000
TPC 1. Typical INL Performance at 15 MSPS
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
0
200
400 600 800 1000
TPC 4. Typical INL Performance at 30 MSPS
1.0
0.5
0
–0.5
–1.0
0 12000
24000 36000 48000
64000
TPC 2. Typical DNL Performance at 15 MSPS
10
5
NOISE – LSB RMS
0
0
15
30 45 63
GAIN SETTING
TPC 3. Output Noise vs. Gain
–0.5
–1.0
0
200
400 600 800 1000
TPC 5. Typical DNL Performance at 30 MSPS
10
5
NOISE – LSB RMS
0
0
15
30 45 63
GAIN SETTING
TPC 6. Input Referred Noise vs. Gain
REV. A
–7–
Page 8
AD9826
TIMING DIAGRAMS
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
t
ADCLK
t
AD
t
C1
HIGH
BYTE
LOW
BYTE
t
C1C2
PIXEL n (R,G,B)
t
AD
t
C2C1
t
C2
t
C2ADF
t
ADC2
t
ADCLK
HB LB HB LB HB LB HB LB HB HBLB LB
t
C2ADR
PIXEL
(n+1)
t
PRA
t
OD
PIXEL
(n+2)
G(n)G(n)R(n)R(n)B(n–1)B(n–1)G(n–1)G(n–1)R(n–1)R(n–1)B(n–2)B(n–2)G(n–2)G(n–2)R(n–2)
Figure 1. 3-Channel CDS Mode Timing
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
ANALOG
INPUTS
t
AD
t
C1
PIXEL n PIXEL
t
AD
t
C2C1
(n+1)
t
PRB
PIXEL
(n+2)
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
t
C1C2
t
ADCLK
PIXEL (n–4) PIXEL (n–4) PIXEL (n–3) PIXEL (n–3) PIXEL (n–2) PIXEL (n–2)
HIGH BYTE LOW BYTE
NOTE
IN 1-CHANNEL CDS MODE, THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”
t
C2ADR
t
C2
t
C2ADF
t
ADCLK
t
OD
LOW BYTE LOW BYTEHIGH BYTE HIGH BYTE
Figure 2. 1-Channel CDS Mode Timing
–8–
REV. A
Page 9
AD9826
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
ANALOG
INPUTS
t
AD
CH1(n–2)
t
ADC2
HIGH
BYTE
t
C1
t
C1C2
t
ADCLK
BYTE
PIXEL n
t
AD
t
C2C1
t
C2
t
C2ADR
t
C2ADF
t
ADCLK
CH2(n–2) CH1(n–1) CH2(n–1)
LOW
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
Figure 3. 2-Channel CDS Mode Timing
PIXEL n
t
AD
t
C2
PIXEL (n+1)
LOW
BYTE
PIXEL
(n+1)
t
PRA
HIGH
BYTE
LOW
BYTE
CH1(n)
HIGH
BYTE
PIXEL (n+2)
LOW
BYTE
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
t
ADC2
CH1(n–2)
HIGH
BYTE
t
ADCLK
t
C2ADR
t
C2ADF
t
ADCLK
CH1(n–1) CH2(n–1)
HIGH
BYTE
LOW
BYTE
CH2(n–2)
HIGH
BYTE
LOW
BYTE
Figure 4. 2-Channel SHA Mode Timing
LOW
BYTE
HIGH
BYTE
LOW
BYTE
CH1(n)
HIGH
BYTE
LOW
BYTE
REV. A
–9–
Page 10
AD9826
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
t
ADCLK
R (n–2)
G (n–2)
HIGH
BYTE
PIXEL n (R,G,B)
t
ADC2
t
ADCLK
G (n–2)
B (n–2) B (n–2) R (n–1)
LOW
BYTE
HB LB HB HB HB HB HBLB LB
t
C2
t
C2AD
t
C2ADR
t
AD
R (n–1)
t
PRA
t
G (n–1)
OD
PIXEL (n+1)
G (n–1) B (n–1)
B (n–1) R (n) R (n) G (n)
LB
LB LB
Figure 5. 3-Channel SHA Mode Timing
PIXEL n
t
AD
t
PRB
t
C2
t
C2ADR
t
t
ADCLK
ADCLK
PIXEL (n–4) PIXEL (n–4) PIXEL (n–3) PIXEL (n–3) PIXEL (n–2) PIXEL (n–2)
HIGH BYTE LOW BYTE LOW BYTE LOW BYTEHIGH BYTE HIGH BYTE
NOTE
IN 1-CHANNEL SHA MODE, THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”
t
ADCLK
t
C2ADF
t
OD
Figure 6. 1-Channel SHA Mode Timing
G (n)
–10–
REV. A
Page 11
ADCCLK
AD9826
t
t
OD
OD
OUTPUT
DAT A
<D7:D0>
OEB
ADCCLK
OUTPUT
DAT A
<D7:D0>
OEB
SDATA
R/Wb
HIGH BYTE
DB15–DB8
t
OD
t
DH
LOW BYTE
DB7–DB0
PIXEL n PIXEL n
HB
n+1
LB
n+1
t
HZ
Figure 7. Digital Output Data Timing
HIGH BYTE
DB15–DB8
PIXEL n
HIGH BYTE
DB15–DB8
PIXEL n+1
Figure 8. Single Byte Mode Digital Output Data Timing
A0A2
A1
t
DS
D8
D7
D5
D6
HB
n+3
HB
n+3
LB
n+2
t
DV
HB
n+2
t
HZ
D3 D2
D4
t
DV
D0
D1
SCLK
SLOAD
SDATA
SCLK
SLOAD
R/Wb
t
LS
t
LH
Figure 9. Serial Write Operation Timing
A0A2 A1
t
LS
D8
D7
t
RDV
D5
D6
D3 D2
D4
D0
D1
t
LH
Figure 10. Serial Read Operation Timing
REV. A
–11–
Page 12
AD9826
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
RED
PGA
OUT
GREEN
PGA
OUT
BLUE
PGA
OUT
MUX
OUT
RED (n–1)
GREEN (n–1)
BLUE (n–1)
PIXEL n (R,G,B)
RED (n)
GREEN (n)
BLUE (n)
BLUE (n–1)GREEN (n–1) GREEN (n)
RED (n)
PIXEL (n+1)
RED (n+1)
GREEN (n+1)
BLUE (n+1)
BLUE (n) GREEN (n+1)
RED (n+1)
OUTPUT
DATA
D<7:0>
R(n–2) G(n–2) G(n–2) B(n–2)
HIGH
LOW
BYTE
BYTE
NOTES
1. THE MUX STATE MACHINE IS INTERNALLY RESET AT THE CDSCLK2 RISING EDGE.
2. EACH PIXEL IS SAMPLED AND AMPLIFIED BY THE PGAs AT CDSCLK2 FALLING EDGE.
3. AFTER CDSCLK2 RISING EDGE, THE NEXT ADCCLK RISING EDGE WILL ALWAYS SELECT RED PGA OUTPUT.
4. THE ADC SAMPLES THE MUX OUTPUT ON ADCCLK FALLING EDGES.
5. THE MUX SWITCHES TO THE NEXT PGA OUTPUT AT ADCCLK RISING EDGES.
B(n–2) R(n–1)
HB LB LB LBLB LB LBHB HB HB HB HB
R(n–1)
G(n–1) G(n–1)
Figure 11. Internal Timing Diagram for 3-Channel CDS Mode
B(n–1) B(n–1) R(n)
R(n)
G(n) G(n)
–12–
REV. A
Page 13
AD9826
FUNCTIONAL DESCRIPTION
The AD9826 can be operated in six different modes: 3-Channel
CDS Mode, 3-Channel SHA Mode, 2-Channel CDS Mode,
2-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel
SHA Mode. Each mode is selected by programming the Configuration Registers through the serial interface. For more detail on
CDS or SHA mode operation, see the Circuit Operation section.
3-Channel CDS Mode
In 3-Channel CDS Mode, the AD9826 simultaneously samples
the Red, Green, and Blue input voltages from the CCD outputs.
The sampling points for each Correlated Double Sampler (CDS)
are controlled by CDSCLK1 and CDSCLK2 (see Figures 11
and 13). CDSCLK1’s falling edge samples the reference level of
the CCD waveform. CDSCLK2’s falling edge samples the data
level of the CCD waveform. Each CDS amplifier outputs the
difference between the CCD’s reference and data levels. Next,
the output voltage of each CDS amplifier is level-shifted by an
Offset DAC. The voltages are then scaled by the three Programmable Gain Amplifiers before being multiplexed through the
16-Bit ADC. The ADC sequentially samples the PGA outputs
on the falling edges of ADCCLK.
The offset and gain values for the Red, Green, and Blue channels are programmed using the serial interface. The order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration register.
Timing for this mode is shown in Figure 1. It is recommended
that the falling edge of CDSCLK2 occur before the rising edge
of ADCCLK, although this is not required to satisfy the minimum timing constraints. The rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as
shown by t
3-Channel SHA Mode
. The output data latency is three clock cycles.
ADC2
In 3-Channel SHA Mode, the AD9826 simultaneously samples
the Red, Green, and Blue input voltages. The sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. The output voltages from the
three SHAs are modified by the offset DACs and then scaled by
the three PGAs. The outputs of the PGAs are then multiplexed
through the 16-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 14). With the OFFSET pin
grounded, a zero volt input corresponds to the ADC’s zero scale
output. The OFFSET pin may also be used as a coarse offset
adjust pin. A voltage applied to this pin will be subtracted from
the voltages applied to the Red, Green, and Blue inputs in the first
amplifier stage of the AD9826. The input clamp is disabled in this
mode. For more information, see the Circuit Operation section.
Timing for this mode is shown in Figure 5. CDSCLK1 should
be grounded in this mode. Although it is not required, it is recommended that the falling edge of CDSCLK2 occur before the
rising edge of ADCCLK. The rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as shown
by t
. The output data latency is three ADCCLK cycles.
ADC2
The offset and gain values for the Red, Green, and Blue channels are programmed using the serial interface. The order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration register.
2-Channel CDS Mode
The 2-Channel Mode is selected by writing a “1” into two of the
channel select bits of the MUX register (D4–D6). Bit D5 of the
configuration register also needs to be set low to take the part out
of 3-Channel Mode. The channels that will be used is determined
by the contents of Bits D4–D6 of the MUX Configuration Register (see Table III). The combination of inputs that can be
selected are; RG, RB, or GB by writing a “1” into the appropriate bit. The sample order is selected by Bit D7. If D7 is high,
the MUX will sample in the following order: RG or RB or GB
depending on which channels are turned on. If Bit D7 is set low
the mux will sample in the following order: GR or BR or BG
depending on which channels are turned on.
The AD9826 simultaneously samples the selected channels’
input voltages from the CCD outputs. The sampling points
for each Correlated Double Sampler (CDS) are controlled by
CDSCLK1 and CDSCLK2 (see Figure 11). CDSCLK1’s falling edge samples the reference level of the CCD waveform.
CDSCLK2’s falling edge samples the data level of the CCD
waveform. Each CDS amplifier outputs the difference between
the CCD’s reference and data levels. Next, the output voltage of
each CDS amplifier is level-shifted by an Offset DAC. The voltages are then scaled by the two Programmable Gain Amplifiers
before being multiplexed through the 16-bit ADC. The ADC
sequentially samples the PGA outputs on the falling edges of
ADCCLK.
The offset and gain values for the Red, Green, and Blue channels are programmed using the serial interface. The order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration Register.
Timing for this mode is shown in Figure 3. The rising edge of
CDSCLK2 should not occur before the previous falling edge of
ADCCLK, as shown by t
. The output data latency is three
ADC2
clock cycles.
2-Channel SHA Mode
The 2-Channel Mode is selected by writing a “1” into two of the
channel select bits of the MUX Register (D4–D6). Bit D5 of the
configuration register also needs to be set low to take the part
out of 3-Channel Mode. The channels that will be used is determined by the contents of Bits D4–D6 of the MUX Configuration
Register (see Table III ). The combination of inputs that can be
selected are; RG, RB, or GB by writing a “1” into the appropriate bit. The sample order is selected by Bit D7. If D7 is high,
the mux will sample in the following order: RG or RB or GB,
depending on which channels are turned on. If Bit D7 is set low,
the mux will sample in the following order: GR or BR or BG,
depending on which channels are turned on.
In 2-Channel SHA Mode, the AD9826 simultaneously samples
the selected channels’ input voltages. The sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. The output voltages from the
two SHAs are modified by the offset DACs and then scaled by
the two PGAs. The outputs of the PGAs are then multiplexed
through the 16-bit ADC. The ADC sequentially samples the PGA
outputs on the falling edges of ADCCLK.
The input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 14). With the OFFSET pin
grounded, a zero volt input corresponds to the ADC’s zero scale
output. The OFFSET pin may also be used as a coarse offset
REV. A
–13–
Page 14
AD9826
adjust pin. A voltage applied to this pin will be subtracted from
the voltages applied to the Red, Green, and Blue inputs in the first
amplifier stage of the AD9826. The input clamp is disabled in this
mode. For more information, see the Circuit Operation section.
Timing for this mode is shown in Figure 4. CDSCLK1 should
be grounded in this mode. The rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as shown
by t
. The output data latency is three ADCCLK cycles. The
ADC2
offset and gain values for the Red, Green, and Blue channels are
programmed using the serial interface. The order in which the
channels are switched through the multiplexer is selected by
programming the MUX Configuration Register.
1-Channel CDS Mode
This mode operates the same way as the 3-Channel CDS mode.
The difference is that the multiplexer remains fixed in this mode,
so only the channel specified in the MUX Configuration Register is processed.
Timing for this mode is shown in Figure 2.
1-Channel SHA Mode
This mode operates the same way as 3-Channel SHA mode,
except that the multiplexer remains stationary. Only the channel
specified in the MUX Configuration Register is processed.
Timing for this mode is shown in Figure 6. CDSCLK1 should
be grounded in this mode of operation.
Configuration Register
The Configuration Register controls the AD9826’s operating
mode and bias levels. Bits D8 and D1 should always be set low.
Bit D7 controls the input range of the AD9826. Setting D7 high
sets the input range to 4 V while setting Bit D7 low sets the
input range to 2 V. Bit D6 controls the internal voltage reference. If the AD9826’s internal voltage reference is used, then
this bit is set high. Setting Bit D6 low will disable the internal
voltage reference, allowing an external voltage reference to be
used. Setting Bit D5 high will configure the AD9826 for 3channel operation. If D5 is set low, the part will be in either
2CH or 1CH mode based on the settings in the MUX Configuration Register (See Table III and the MUX Configuration
Register description). Setting Bit D4 high will enable the CDS
mode of operation, and setting this bit low will enable the SHA
mode of operation. Bit D3 sets the dc bias level of the AD9826’s
input clamp.
This bit should always be set high for the 4 V clamp bias, unless
a CCD with a reset feedthrough transient exceeding 2 V is used.
If the 3 V clamp bias level is used, then the peak-to-peak i nput
signal range to the AD9826 is reduced to 3 V maximum. Bit D2
controls the power-down mode. Setting Bit D2 high will place
the AD9826 into a very low-power “sleep” mode. All register
contents are retained while the AD9826 is in the powered-down
state. Bit D0 controls the output mode of the AD9826. Setting
Bit D0 high will enable a single byte output mode where only
the 8 MSBs of the 16 b ADC will be output on each rising edge
of ADCCLK (see Figure 8). If Bit D0 is set low, then the 16b
ADC output is multiplexed into two bytes. The MSByte is
output on ADCCLK rising edge and the LSByte is output on
ADCCLK falling edge.
Table I. Internal Register Map
Register Address Data Bits
Name A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Configuration 0 0 0 0 Input Rng VREF 3CH Mode CDS On Clamp Pwr Dn 0 1 Byte Out
MUX Config 0 0 1 0 RGB/BGR Red Green Blue 0 0 0 0
Red PGA 0 1 0 0 0 0 MSB LSB
Green PGA 0 1 1 0 0 0 MSB LSB
Blue PGA 1 0 0 0 0 0 MSB LSB
Red Offset 1 0 1 MSB LSB
Green Offset 1 1 0 MSB LSB
Blue Offset 1 1 1 MSB LSB
Table II. Configuration Register Settings
D
8D7 D6 D5 D4 D3 D2 D1 D0
Set Input Range Internal VREF 3CH Mode CDS Operation Input Clamp Bias Power-Down Set Output Mode
to
1 = 4 V* 1 = Enabled* 1 = On* 1 = CDS Mode* 1 = 4 V* 1 = On
0
0 = 2 V 0 = Disabled 0 = Off 0 = SHA Mode 0 = 3 V 0 = Off (Normal)*
*Power-on default value.
to
0
0 = 2 Byte*
1 = 1 Byte
–14–
REV. A
Page 15
AD9826
MUX Configuration Register
The MUX Configuration Register controls the sampling channel order and the 2-Channel Mode configuration in the AD9826.
Bits D8 and D3–D0 should always be set low. Bit D7 is used
when operating in 3-Channel or 2-Channel Mode. Setting Bit
D7 high will sequence the MUX to sample the Red channel
first, then the Green channel, and then the Blue channel. When
in 3-channel mode, the CDSCLK2 pulse always resets the MUX
to sample the Red channel first (see Figure 11). When Bit D7 is
set low, the channel order is reversed to Blue first, Green second, and Red third. The CDSCLK2 pulse will always reset the
MUX to sample the Blue channel first. Bits D6, D5, and D4 are
used when operating in 1 or 2-Channel Mode. Bit D6 is set high
to sample the Red channel. Bit D5 is set high to sample the
Green channel. Bit D4 is set high to sample the Blue channel.
The MUX will remain stationary during 1-channel mode. TwoChannel Mode is selected by setting two of the channel select
Bits (D4–D6) high. The MUX samples the channels in the
PGA Gain Registers
There are three PGA registers for individually programming the
gain in the Red, Green, and Blue channels. Bits D8, D7, and
D6 in each register must be set low, and Bits D5 through D0
control the gain range from 1× to 6× in 64 increments. See
Figure 17 for a graph of the PGA gain versus PGA register
code. The coding for the PGA registers is straight binary, with
an all “zeros” word corresponding to the minimum gain setting
(1×) and an all “ones” word corresponding to the maximum
gain setting (6×).
Offset Registers
There are three Offset Registers for individually programming
the offset in the Red, Green, and Blue channels. Bits D8 through
D0 control the offset range from –300 mV to +300 mV in 512
increments. The coding for the Offset Registers is Sign Magnitude, with D8 as the sign bit. Table V shows the offset range
as a function of the Bits D8 through D0.
order selected by Bit D7.
Table III. MUX Configuration Register Settings
D
8 D7 D6 D5 D4 D3 D2 D1 D0
Set MUX Order Channel Select Channel Select Channel Select Set Set Set Set
to
0
*Power-on default value.
1 = R-G-B* 1 = RED* 1 = GREEN 1 = BLUE
0 = B-G-R 0 = Off 0 = Off* 0 = Off*
to to to to
00 00
Table IV. PGA Gain Register Settings
D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (V/V) Gain (dB)
Set to 0 Set to 0 Set to 0 MSB LSB
000000000* 1.0 0.0
000000001 1.013 0.12
• • •
• • •
• • •
000111111 5.56 14.9
000111111 6.0 15.56
*Power-on default value.
Table V. Offset Register Settings
D8 D7 D6 D5 D4 D3 D2 D1 D0 Offset (mV)
MSB LSB
000000000* 0
000000001 +1.2
• •
• •
• •
011111111 +300
100000000 0
100000001 –1.2
• •
• •
• •
111111111 –300
*Power-on default value.
REV. A
–15–
Page 16
AD9826
CIRCUIT OPERATION
Analog Inputs—CDS Mode Operation
Figure 12 shows the analog input configuration for the CDS
mode of operation. Figure 13 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage representing the difference between the two
sampled levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1 µF
input capacitor, level-shifting the CCD signal into the AD9826’s
input common-mode range. The time constant of the input
clamp is determined by the internal 5 kΩ resistance and the
external 0.1 µF input capacitance.
AD9826
SIGNAL
1F
CCD
+
0.1F
OFFSET
0.1F
VINR
S1
5K
S2
S4
1.7k⍀
4V
2.2k⍀
3V
6.9k⍀
4pF
CML
S3
CML
4pF
INPUT CLAMP LEVEL
IS SELECTED IN THE
CONFIGURATION
REGISTER
External Input Coupling Capacitors
The recommended value for the input coupling capacitors is
0.1 µF. While it is possible to use a smaller capacitor, this larger
value is chosen for several reasons:
Crosstalk
The input coupling capacitor creates a capacitive divider with
any parasitic capacitance between PCB traces and on chip traces.
C
should be large relative to these parasitic capacitances in
IN
order to minimize this effect. For example, with a 100 pF input
capacitance and just a few hundred f F of parasitic capacitance
on the PCB and/or the IC the imaging system could expect
to have hundreds of LSBs of crosstalk at the 16 b level. Using
a large capacitor value = 0.1 µF will minimize any errors due
to crosstalk.
Signal Attenuation
The input coupling capacitor creates a capacitive divider with a
CMOS integrated circuit’s input capacitance, attenuating the
CCD signal level. C
should be large relative to the IC’s 10 pF
IN
input capacitance in order to minimize this effect.
Linearity
Some of the input capacitance of a CMOS IC is junction capacitance, which varies nonlinearly with applied voltage. If the input
coupling capacitor is too small, then the attenuation of the CCD
signal will vary nonlinearly with signal level. This will degrade
the system linearity performance.
Sampling Errors
The internal 4 pF sample capacitors have a “memory” of the
previously sampled pixel. There is a charge redistribution error
between C
to-pixel voltage swings. As the value of C
resulting error in the sampled voltage will increase. With a C
and the internal sample capacitors for larger pixel-
IN
is reduced, the
IN
IN
value of 0.1 µF, the charge redistribution error will be less than
1 LSB for a full-scale pixel-to-pixel voltage swing.
Figure 12. CDS-Mode Input Configuration (All Three
Channels Are Identical)
S1, S4 CLOSED
CDSCLK1
CDSCLK2
(INTERNAL)
Q3
S1, S4 OPEN
S2 CLOSED
S2 OPEN
S3 CLOSED
S3 OPEN
Figure 13. CDS-Mode Internal Switch Timing
–16–
S1, S4 CLOSED
S2 CLOSED
S3 CLOSED
REV. A
Page 17
AD9826
SHA
SHA
SHA
VINR
VING
VINB
OFFSET
RED
GREEN
BLUE
VRED FROM
CIS MODULE
AVDD
R1
R2
DC OFFSET
REDOFFSET
GREENOFFSET
BLUEOFFSET
AD9826
0.1F
Analog Inputs—
SHA Mode Operation
Figure 14 shows the analog input configuration for the SHA
mode of operation. Figure 15 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential output voltage representing the difference between the sampled
input voltage and the OFFSET voltage. The input clamp is
disabled during SHA mode operation.
AD9826
4pF
CML
4pF
CML
INPUT
SIGNAL
OPTIONAL DC
OFFSET (OR
CONNECT
TO GND)
VINR
OFFSET
VING
S1
S3
S2
Figure 16 shows how the OFFSET pin may be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET
pin, the CIS signal will be restored to “zero.” After the large dc
offset is removed, the signal can be scaled using the PGA to
maximize the ADC’s dynamic range.
VINB
Figure 14. SHA-Mode Input Configuration (All Three
Channels Are Identical)
S1, S2 CLOSED S1, S2 CLOSED
CDSCLK2
(INTERNAL)
S1, S2 OPEN
S3 CLOSED
Q3
Figure 15. SHA-Mode Internal Switch Timing
S3 OPEN
S3 CLOSED
Figure 16. SHA-Mode Used with External DC Offset
REV. A
–17–
Page 18
AD9826
Programmable Gain Amplifiers
The AD9826 uses one Programmable Gain Amplifier (PGA) for
each channel. Each PGA has a gain range from 1× (0 dB) to
6.0× (15.56 dB), adjustable in 64 steps. Figure 17 shows the
PGA gain as a function of the PGA register code. Although the
gain curve is approximately “linear in dB,” the gain in V/V varies nonlinearly with register code, following the equation:
.
GainG=
60
.
150
+
63
63
–
where G is the decimal value of the gain register contents, and
varies from 0 to 63.
6.00
4.75
3.50
GAIN – V/V
2.25
1.00
GAIN – dB
16
12
8
4
0
0
12
GAIN – dB
GAIN – V/V
24 36 63
PGA REGISTER VALUE – Decimal
48 60
APPLICATIONS INFORMATION
Circuit and Layout Recommendations
The recommended circuit configuration for 3-Channel CDS
Mode operation is shown in Figure 18. The recommended
input coupling capacitor value is 0.1 µF (see Circuit Operation
section for more details). A single ground plane is recommended
for the AD9826. A separate power supply may be used for
DRVDD, the digital driver supply, but this supply pin should
still be decoupled to the same ground plane as the rest of the
AD9826. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by
using external digital buffers. To minimize the effect of digital
transients during major output code transitions, the falling edge
of CDSCLK2 should occur coincident with or before the
rising edge of ADCCLK (see Figures 1 through 6 for timing).
All 0.1 µF decoupling capacitors should be located as close as
possible to the AD9826 pins. When operating in 1CH or 2CH
Mode, the unused analog inputs should be grounded.
For 3-Channel SHA Mode, all of the above considerations also
apply, except that the analog input signals are directly connected
to the AD9826 without the use of coupling capacitors. The analog
input signals must already be dc-biased between 0 V and 4 V.
Also, the OFFSET pin should be grounded if the inputs to the
AD9826 are to be referenced to ground, or a dc offset voltage
should be applied to the OFFSET pin in the case where a coarse
offset needs to be removed from the inputs. (See Figure 16 and
the Circuit Operation section for more details.)
Figure 17. PGA Gain Transfer Function
CLOCK
INPUTS
0.1F
DAT A
INPUTS
5V/3V
CDSCLK1
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
(MSB) D7
D6
D5
D4
D3
D2
(LSB)D0
1
2
3
4
5
6
7
8
9
10
11
12
D1
13
14
Figure 18. Recommended Circuit Configuration, 3-Channel CDS Mode
AD9826
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVD D
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVD D
SLOAD
SCLK
SDATA
5V
0.1F
0.1F
0.1F
0.1F
5V
0.1F
0.1F
0.1F
0.1F
0.1F
10F
0.1F
SERIAL
INTERFACE
RED INPUT
GREEN INPUT
BLUE INPUT
1.0F
–18–
REV. A
Page 19
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead 5.3 mm SSOP
0.407 (10.34)
0.397 (10.08)
28 15
0.311 (7.9)
0.301 (7.64)
(RS-28)
141
0.212 (5.38)
0.205 (5.21)
AD9826
0.078 (1.98)
0.068 (1.73)
0.008 (0.203)
0.002 (0.050)
PIN 1
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.066 (1.67)
SEATING
PLANE
0.07 (1.79)
0.009 (0.229)
0.005 (0.127)
8°
0°
0.03 (0.762)
0.022 (0.558)
Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
REV. A
–19–
Page 20
C02367–0–10/01(A)
–20–
PRINTED IN U.S.A.
Loading...