Datasheet AD9802 Datasheet (Analog Devices)

CCD Signal Processor

a

FEATURES
10-Bit, 18 MSPS A/D Converter
18 MSPS Full Speed Correlated Double Sampler (CDS)
Low Noise, Wideband PGA
Internal Voltage Reference
No Missing Codes Guaranteed
+3 V Single Supply Operation
Low Power CMOS: 185 mW
48-Terminal TQFP Package

PRODUCT DESCRIPTION

The AD9802 is a complete CCD signal processor developed
for electronic cameras. It is suitable for both camcorder and
consumer-level still camera applications.

The signal processing chain is comprised of a high speed CDS,
variable gain PGA and 10-bit ADC. Required clamping cir­cuitry and an onboard voltage reference are provided as well as a
direct ADC input. The AD9802 operates from a single +3 V
supply with a typical power consumption of 185 mW.

The AD9802 is packaged in a space saving 48-terminal thin
quad flatpack (TQFP) and is specified over an operating tem­perature range of 0°C to +70°C.

For Electronic Cameras

AD9802

FUNCTIONAL BLOCK DIAGRAM

SHP

S/H

AD9802

ACVDD

SHD ADCCLK

TIMING

GENERATOR

A/D

ADVDD

10

DOUT

DRVDD

DVDD

PBLK

CLPDM

PGACONT1 PGACONT2

CLAMP

PIN
DIN

ADCIN

CMLEVEL VRT VRB STBY

PRODUCT HIGHLIGHTS

CDS

REFERENCE

PGA

CLAMP

CLPOB

MUX

ADCMODE

1. On-Chip Input Clamp and CDS
Clamp circuitry and high speed correlated double sampler
allow for simple ac-coupling to interface a CCD sensor at full
18 MSPS conversion rate.

2. On-Chip PGA
The AD9802 includes a low-noise, wideband amplifier with
analog variable gain from 0 dB to 31.5 dB (linear in dB).

3. Direct ADC Input
A direct input to the 10-bit A/D converter is provided for
digitizing video signals.

4. 10-Bit, High Speed A/D Converter
A linear 10-bit ADC is capable of digitizing CCD signals at
the full 18 MSPS conversion rate. Typical DNL is ± 0.5 LSB
and no missing code performance is guaranteed.

5. Low Power
At 185 mW, and 15 mW in power-down, the AD9802 con­sumes a fraction of the power of presently available multichip
solutions.

6. Digital I/O Functionality
The AD9802 offers three-state digital output control.

7. Small Package
Packaged in a 48-terminal, surface-mount thin quad flatpack,
the AD9802 is well suited to very compact, low headroom
designs.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

(T

to T

with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V

MAX

AD9802–SPECIFICA TIONS

MIN

unless otherwise noted)

Parameter Min Typ Max Units

TEMPERATURE RANGE

Operating 0 70 °C
Storage –65 150 °C

POWER SUPPLY VOLTAGE (For Functional Operation)

ACVDD 3.00 3.15 3.50 V
ADVDD 3.00 3.15 3.50 V
DVDD 3.00 3.15 3.50 V
DRVDD 3.00 3.15 3.50 V

POWER SUPPLY CURRENT

ACVDD 39.5 mA
ADVDD 14.6 mA
DVDD 4.7 mA
DRVDD 0.07 mA

POWER CONSUMPTION

Normal Operation 185 mW

Power-Down Mode 15 mW
MAXIMUM SHP, SHD, ADCCLK RATE 18 MHz
ADC

Resolution 10 Bits

Differential Nonlinearity ±0.5 LSBs

No Missing Codes GUARANTEED

ADCCLK Rate 18 MHz

Reference Top Voltage 1.75 V

Reference Bottom Voltage 1.25 V

Input Range 1.0 V p-p
CDS

Maximum Input Signal 500 mV p-p

Pixel Rate 18 MHz

1

PGA

Maximum Gain 31.5 dB

High Gain 14.5 19 23.5 dB

Medium Gain 1.0 4.0 7.0 dB

Minimum Gain –4.0 0 +4 dB
CLAMP (During CLPOB. Only Stable over PGA Range 0.3 V to 2.7 V)

Average Black Level 32 LSBs

Pixel-to-Pixel Offset (See Black Level Clamping for Description) 2 8 LSBs

NOTES

1

PGA test conditions: maximum gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain

0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V.

Specifications subject to change without notice.

PGACONT1 =

(T

to T

with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise

MAX

DIGITAL SPECIFICATIONS

MIN

noted)

Parameter Symbol Min Typ Max Units

LOGIC INPUTS

High Level Input Voltage V

Low Level Input Voltage V

High Level Input Current I

Low Level Input Current I

Input Capacitance C

IH

IL
IH
IL

IN

2.4 V

0.6 V
10 µA
10 µA
10 pF

LOGIC OUTPUTS

High Level Output Voltage V
Low Level Output Voltage V

OH
OL

I

OH

I

OL

2.4 V

0.6 V
50 µA
50 µA

–2–

REV. 0

AD9802

WARNING!

ESD SENSITIVE DEVICE

(T

to T

TIMING SPECIFICATIONS

Parameter Min Typ Max Units

ADCCLK Clock Period 55.6 ns
ADCCLK Hi-Level Period 24.8 27.8 ns
ADCCLK Lo-Level Period 24.8 27.8 ns
SHP, SHD Clock Period 55.6 ns
SHP, SHD Minimum Pulse Width 12.5 ns
SHP Rising Edge to SHD Rising Edge 28 ns
Digital Output Delay 20 ns

PBLK MODE1 MODE2 Digital Output Data (D9–D0)

0 0 0 0000000000
1 0 0 Normal Operation
1 0 1 1010101010
1 1 0 0101010101
1 1 1 High Impedance

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect To Min Max Units

ADVDD ADVSS, SUBST –0.3 6.5 V
ACVDD ACVSS, SUBST –0.3 6.5 V
DVDD DVSS, DSUBT –0.3 6.5 V
DRVDD DRVSS, DSUBST –0.3 6.5 V
SHP, SHD DSUBST –0.3 DVDD + 2.0 V
ADCCLK, CLPOB, CLPDM DSUBST –0.3 DVDD + 0.3 V
PGACONT1, PGACONT2 SUBST –0.3 ACVDD + 0.3 V
PIN, DIN SUBST –0.3 ACVDD + 0.3 V
DOUT DSUBST –0.3 DRVDD + 0.3 V
VRT, VRB SUBST –0.3 ADVDD + 0.3 V
CLAMP_BIAS SUBST –0.3 ACVDD + 0.3 V
CCDBYP1, CCDBYP2 SUBST –0.3 ACVDD + 0.3 V
STBY DSUBST –0.3 DVDD + 0.3 V
MODE1, MODE2 SUBST –0.3 ADVDD + 0.3 V
DRVSS, DVSS, ACVSS, ADVSS SUBST, DSUBST –0.3 +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device

at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.

MIN

noted)

with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise

MAX

Digital Output Data Control

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9802JST 0°C to +70°C 48-Terminal Plastic Thin Quad Flatpack ST-48

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9802 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. 0

AD9802

PIN CONFIGURATION

ADVSS

ADVDD

ADVSS

AD9802

TOP VIEW

(Not to Scale)

STBY

DVDD

ADCCLK

NC

ADCMODE

PBLK

CLPOB

MODE2

MODE1

SHP

SHD

CMLEVEL

SHABYP

DVSS

CLPDM

36

ADCIN

35

TEST2

34

TEST1

33

ACVDD

32

CLAMP_BIAS

31

ACVSS

30

PGACONT2

29

PGACONT1

28

CCDBYP1

27

PIN

26

DIN

25

CCDBYP2

ADVSS

(LSB) D0

D1
D2
D3
D4
D5
D6
D7
D8

(MSB) D9

DRVDD

NC = NO CONNECT

SUBST

VRB

VRT

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER
3
4
5
6
7
8
9

10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

DVSS

DRVSS

DSUBST

PIN FUNCTION DESCRIPTIONS

Pin # Pin Name Type Description

1 ADVSS P Analog Ground
2–11 D0–D9 DO Digital Data Outputs: D0 = LSB, D9 = MSB
12 DRVDD P +3 V Digital Driver Supply
13 DRVSS P Digital Driver Ground
14 DSUBST P Digital Substrate
15 DVSS P Digital Ground
16 ADCCLK DI ADC Sample Clock Input
17 DVDD P +3 V Digital Supply
18 STBY DI Power-Down (Active High)
19 PBLK DI Pixel Blanking (Active Low)
20 CLPOB DI Black Level Restore Clamp (Active Low)
21 SHP DI Reference Sample Clock Input
22 SHD DI Data Sample Clock Input
23 CLPDM DI Input Clamp (Active Low)
24 DVSS P Digital Ground
25 CCDBYP2 AO CCD Bypass. Decouple to analog ground through 0.1 µF.
26 DIN AI CDS Input. Tie to Pin 27 and AC-Couple to CCD output through 0.1µF.
27 PIN AI CDS Input. See above.
28 CCDBYP1 AO CCD Bypass. Decouple to analog ground through 0.1 µF.
29 PGACONT1 AI Coarse PGA Gain Control (0.3V–2.7 V). Decoupled to analog ground through 0.1 µF.
30 PGACONT2 AI Fine PGA Gain Control
31 ACVSS P Analog Ground
32 CLAMP_BIAS AO Clamp Bias Level. Decouple to analog ground through 0.1 µF.
33 ACVDD P +3 V Analog Supply
34, 35 TEST1, TEST2 AI Reserved Test Pins. Should be left NC or pulled high to ACVDD.
36 ADCIN AI Direct ADC Analog Input (See Driving the Direct ADC Input)
37 CMLEVEL AO Common-Mode Level. Decouple to analog ground through 0.1 µF.
38 SHABYP AO Internal Bias Level. Decouple to analog ground through 0.1µF.
39 MODE2 DI ADC Test Mode Control (See Digital Output Data Control.)
40 MODE1 DI ADC Test Mode Control (See Digital Output Data Control.)
41 ADCMODE DI ADC Input Control. Logic low for CDS/PGA, high for direct input.
42 NC No Connect
43 ADVDD P +3 V Analog Supply
44, 45 ADVSS P Analog Ground
46 SUBST P Substrate. Connect to analog ground.
47 VRB AO Bottom Reference Bypass. Decouple to analog ground through 0.1µF.
48 VRT AO Top Reference Bypass

NOTE
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

–4–

REV. 0

AD9802

EQUIVALENT INPUT CIRCUITS

DVDD DRVDD

DVSS DRVSS

Figure 1. Pins 2–11 (DB0–DB9)

DVDD

200V

DSUBST

Figure 2. Pin 21 (SHP) and Pin 22 (SHD)

DVSS

ACVDD

50V

10pF

SUBST

ACVSS

Figure 6. Pin 26 (DIN) and Pin 27 (PIN)

ACVDD

PGACONT1

PGACONT2

SUBST

8kV 8kV

ACVDD

10kV

1kV

Figure 7. Pin 29 (PGACONT1) and Pin 30 (PGACONT2)

ACVDD

10kV

200V

DVDD

200V

DSUBST

DVSS

Figure 3. Pin 16 (ADCCLK)

ADVDD

9.3kV

ADVSS

Figure 4. Pin 37 (CMLEVEL)

ACVDD

50V

30kV

SUBST ACVSS

Figure 8. Pin 32 (CLAMP BIAS)

SUBST

3kV

ADVDD

200V

ADVSS

1.1kV

Figure 9. Pin 48 (VRT) and Pin 47 (VRB)

ACVDD

50V

1pF

SUBST

SUBST

ACVSS

Figure 5. Pin 25 (CCDBYP2) and Pin 28 (CCDBYP1)

REV. 0

Figure 10. Pin 36 (ADCIN) and Pin 38 (SHABYP)

–5–

AD9802

CCD

SHP

SHD

CLPOB

PBLK

CLPDM

ADCCLK

EFFECTIVE

PIXEL

INTERVAL

BLACK

LEVEL

INTERVAL

BLANKING

INTERVAL

DUMMY

BLACK

INTERVAL

EFFECTIVE

PIXEL

INTERVAL

ADC DATA

NOTES:
CLPDM AND CLPOB OVERWRITE PBLK
CLAMP TIMING NEEDS TO BE ADJUSTED RELATIVE TO CCD'S BLACK PIXELS
RECOMMENDED PULSE WIDTH CLPDM = 1.5

s MIN

Figure 11. Typical Horizontal Interval Timing

–6–

REV. 0

CCD SIGNAL

(DELAYED TO MATCH

ACTUAL SAMPLING

EDGE)

SHD

SHP

ACTUAL

SAMPLING

EDGE

ADCCLK

DIGITAL OUT

AD9802

1234567

N N+4

35ns35ns

N+1

t

ID

t

OD

N+2

N+3

t

H

DATA N–1 DATA N

OUTPUT LOAD C

SHP

SHD

PRE-ADC

OUTPUT LATCH

PRE-ADC

OUTPUT LATCH

DATA TRANSITION

ADCCLK

= 20pF OUTPUT DELAY

L

INTERNAL CLOCK DELAY

HOLD TIME

Figure 12. Timing Diagram

5ns

10ns

5ns

20ns

INHIBITED PERIOD

FOR ADCCLK

RISING EDGE

RISING EDGE

ANYWHERE IN

THIS PERIOD OK

t

= 15ns

OD

t

= 2ns

H

t

= 3ns

ID

LATENCY = 5 CYCLES

Figure 13. ADCCLK Timing Edge

–7–REV. 0

AD9802

THEORY OF OPERATION
Introduction

The AD9802 is a 10-bit analog-to-digital interface for CCD
cameras. The block level diagram of the system is shown in
Figure 14. The device includes a correlated double sampler
(CDS), 0 dB–31 dB variable gain amplifier (PGA), black level
correction loop, input clamp and voltage reference. The only
external analog circuitry required at the system level is an emit­ter follower buffer between the CCD output and AD9802
inputs.

CDS

BLACK

LEVEL

PGA

GAIN

10-BIT

ADC

REF

OUT

CLAMP

IN

Figure 14.

Correlated Double Sampling (CDS)

CDS is important in high performance CCD systems as a method
for removing several types of noise. Basically, two samples of the
CCD output are taken: one with the signal present (data) and one
without (reference). Subtracting these two samples removes
any noise that is common to—or correlates with—both.

Figure 15 shows the block diagram of the AD9802’s CDS. The
S/H blocks are directly driven by the input and the sampling
function is performed passively, without the use of amplifiers.
This implementation relies on the off-chip emitter follower
buffer to drive the two 10 pF sampling capacitors. Only one
capacitor at a time is seen at the input pin.

The AD9802 actually uses two CDS circuits in a “ping-pong”
fashion to allow the system more acquisition time. In this way,
the output from one of the two CDS blocks will be valid for an
entire clock cycle. Thus, the bandwidth requirement of the
subsequent gain stage is reduced as compared to that for a
single CDS channel system. This lower bandwidth translates to
lower power and noise.

S/H

FROM

CCD

Q1

S/H

Q2

S

10pF

OUT

Figure 15.

Programmable Gain Amplifier (PGA)

The on-chip PGA provides a (linear in dB) gain range of 0dB–

31.5 dB. A typical gain characteristic plot is shown in Figure 16.
Only the range from 0.3 V to 2.7 V is intended for actual use.

35

30

25

20

15

10

GAIN – dB

5

0

–5

–10
–15

030.5 1 1.5 2 2.5
PGACONT1 – Volts

Figure 16.

As shown in Figure 17, PGA control is provided through the
PGACONT1 and PGACONT2 inputs. PGACONT1 provides
coarse, and PGACONT2 fine (1/16), gain control.

PGACONT1

PGACONT1 = COARSE CONTROL
PGACONT2 = FINE (1/16) CONTROL

PGACONT2

A

Figure 17.

Black Level Clamping

For correct processing, the CCD signal must be referenced to a
well established “black level” by the AD9802. At the edge of the
CCD, there is a collection of pixels covered with metal to pre­vent any light penetration. As the CCD is read out, these “black
pixels” provide a calibration signal that is used to establish the
black level.

The feedback loop shown in Figure 18 is closed around the
PGA during the calibration interval (CLPOB = LOW) to set the
black level. As the black pixels are being processed, an integra­tor block measures the difference between the input level and
the desired reference level. This difference, or error, signal is
amplified and passed to the CDS block where it is added to the
incoming pixel data. As a result of this process, the black pixels
are digitized at one end of the ADC range, taking maximum
advantage of the available linear range of the system.

–8–

CDS

IN

INTEGRATOR

PGA

ADC
CLPOB

NEG REF

Figure 18.

REV. 0

AD9802

The actual implementation of this loop is slightly more compli­cated as shown in Figure 19. Because there are two separate
CDS blocks, two black level feedback loops are required and
two offset voltages are developed. Figure 19 also shows an addi­tional PGA block in the feedback loop labeled “RPGA.” The
RPGA uses the same control inputs as the PGA, but has the
inverse gain. The RPGA functions to attenuate by the same
factor as the PGA amplifies, keeping the gain and bandwidth of
the loop constant.

There exists an unavoidable mismatch in the two offset voltages
used to correct both CDS blocks. This mismatch causes a slight
difference in the offset level for odd and even pixels, called
“pixel-to-pixel offset” (see Specifications). The pixel-to-pixel
offset is an output referred specification, because the black level
correction is done using the output of the PGA.

CDS1

IN

CDS2

PGA

RPGA2

RPGA1

CONTROL

INT2

INT1

ADC
CLPOB

NEG REF

Figure 19.

Input Bias Level Clamping

The buffered CCD output is connected to the AD9802 through
an external coupling capacitor. The dc bias point for this cou­pling capacitor is established during the clamping (CLPDM =
LOW) period using the “dummy clamp” loop shown in Figure

20. When closed around the CDS, this loop establishes the
desired dc bias point on the coupling capacitor.

CLPDM

INPUT

CLAMP

CCD

CDS

PGA

BLACK

LEVEL CLP

TO ADC

Figure 20.

Input Blanking

In some applications, the AD9802’s input may be exposed to
large signals from the CCD. These signals can be very large,
relative to the AD9802’s input range, and could thus saturate
on-chip circuit blocks. Recovery time from such saturation
conditions could be substantial.

To avoid problems associated with processing these transients,
the AD9802 includes an input blanking function. When active
(PBLK = LOW) this function stops the CDS operation and
allows the user to disconnect the CDS inputs from the CCD
buffer.

If the input voltage exceeds the supply rail by more than 0.3V,
then protection diodes will be turned on, increasing current flow
into the AD9802 (see Equivalent Input Circuits). Such voltage
levels should be externally clamped to prevent device damage or
reliability degradation.

10-Bit Analog-to-Digital Converter (ADC)

The ADC employs a multibit pipelined architecture that is
well suited for high throughput rates while being both area and
power efficient. The multistep pipeline presents a low input
capacitance resulting in lower on-chip drive requirements. A
fully differential implementation was used to overcome head­room constraints of the single +3 V power supply.

Direct ADC Input

The analog processing circuitry may be bypassed in the
AD9802. When ADCMODE (Pin 41) is taken high, the
ADCIN pin provides a direct input to the SHA. This feature
allows digitization of signals that do not require CDS and
gain adjustment. The PGA output is disconnected from the
SHA when ADCMODE is taken high.

Differential Reference

The AD9802 includes a 0.5 V reference based on a differential,
continuous-time bandgap cell. Use of an external bypass capaci­tor reduces the reference drive requirements, thus lowering the
power dissipation. The differential architecture was chosen for
its ability to reject supply and substrate noise. Recommended
decoupling shown in Figure 21.

0.1mF

1mF

0.1mF

REF

VRT

VRB

Figure 21.

Internal Timing

The AD9802’s on-chip timing circuitry generates all clocks
necessary for operation of the CDS and ADC blocks. The user
needs only to synchronize the SHP and SHD clocks with the
CCD waveform, as all other timing is handled internally. The
ADCCLK signal is used to strobe the output data, and can be
adjusted to accommodate desired timing.

–9–REV. 0

AD9802

APPLICATIONS INFORMATION
Generating Clock Signals

For best performance, the AD9802 should be driven by 3 V
logic levels. As shown in the Equivalent Input Circuits, the use
of 5 V logic for ADCCLK will turn on the protection diode to
DVDD, increasing the current flow into this pin. As a result,
noise and power dissipation will increase. The CDS clock in­puts, SHP and SHD, have a additional protection and can with­stand direct 5 V levels.

External clamping diodes or resistor dividers can be used to
translate 5 V levels to 3 V levels, but the lowest power dissi­pation is achieved with a logic transceiver chip. National
Semiconductor’s 74LVX4245 provides a 5 V to 3 V level shift
for up to eight clock signals, has a three-state option, and
features low power consumption. Philips Semiconductor and
Quality also manufacture similar devices.

Driving the Direct ADC Input

The AD9802 can be used in a “direct ADC input” mode, in
which the input signal bypasses the input clamp, CDS and
PGA, and is sent directly to the sample and hold amplifier (SHA)
of the ADC. There are several methods that may be used to
drive the direct ADC input.

To enable the direct input mode of operation, ADCMODE (Pin

41) is taken to logic high. This will internally disconnect the
PGA output from the SHA input, and connect ADCIN (Pin 36)
to the SHA input.

The SHA has a differential input, consisting of ADCIN (Pin 36)
as the positive input, and SHABYP (Pin 38) as the negative
input. Both pins must be properly dc biased.

Figures 22 through 25 show four circuits for driving the direct
ADC input. Decoupling capacitors are not shown for CML,
VRT, VRB and SHABYP pins.

1V p-p

CML

+3V

ADCIN

CML

SHABYP

ADCMODE

SHA

1.5V

AD9802

Figure 22. DC-Coupled Input

Figure 22 is a single-ended, dc-coupled circuit. SHABYP is
connected to CML (1.5 V) to establish a midpoint bias. The
input signal of 1 V p-p should be centered around CML.

Figure 23 shows an ac-coupled configuration, where both inputs
are biased to CML. The input capacitor C

and bias resistors

IN

should be sized to set the appropriate high pass cutoff frequency
for the application. To minimize the differential offset voltage
due to the input bias currents, both resistors should be equal.

–10–

1V p-p

C

IN

+3V

ADCIN

R

BIAS

CML

R

BIAS

SHABYP

ADCMODE

SHA

1.5V

AD9802

Figure 23. AC-Coupled Input

Figure 24 shows an alternative ac-coupled configuration. By
connecting SHABYP to CML, the dc bias at Pin 36 (ADCIN)
will internally track to the same voltage, automatically setting
the input bias level. With a given input capacitor value, C

IN

, the
time constant in this configuration will be dependent on the
sampling frequency F

1V p-p

. Specifically:

S

τ = (C

IN/FS

C

IN

+3V

) × 2E +12

ADCIN

CML

SHABYP

ADCMODE

SHA

1.5V

AD9802

Figure 24. “Auto Bias” AC-Coupled Input

Figure 25 shows a true differential drive circuit. Each input
would be 500 mV p-p, to achieve the 1 V full-scale input to the
ADC. The common-mode input range for this configuration
extends from about 500 mV to 2.5 V. This circuit could also be
implemented with ac coupling, similar to Figure 23.

500mV p-p

500mV p-p

+3V

ADCIN

SHA

CML
SHABYP

AD9802

ADCMODE

Figure 25. Differential Input

Figure 26 shows a video clamp circuit which may be used with
the direct ADC mode of the AD9802 (supplies and decoupling
not shown). The circuit will clamp the reference black level of
an incoming video signal to 1.25 V dc. With SHABYP con­nected to 1.75 V (VRT), the ADCIN range spans from 1.25V
to 2.25 V. To accomplish this, the CLAMP pulse should be
asserted during the horizontal sync interval, when the video is at
its reference black level. A 5 V logic high applied to the gate of
the SD210 will turn on the device, and the input capacitor C

IN

will charge up to provide 1.25 V at the ADCIN pin of the
AD9802. Other appropriate NMOS devices may be substituted
for the SD210. The AD8047 op amp requires ± 5 V supplies;
appropriate single supply op amps may be substituted. The size
of capacitor C

should be set to meet the acquisition time and

IN

REV. 0

AD9802

droop specifications needed. A capacitor value of 0.01µF will
result in a droop of less than 10 LSB across one video line, and
requires only a CLAMP pulse of 1 µs to charge up. A larger
capacitor may be used to reduce droop, but then a longer
CLAMP pulse may be necessary.

1V p-p

CLAMP

500V

C

IN

SD210

AD8047

500V

+3V

ADCIN

CML
SHABYP

VRT

VRB

ADCMODE

SHA

AD9802

Figure 26. Video Clamp Circuit

1.0

0.5

0

20.5

21.0

0 600100 200 300 400 500

700 800 900

1023

Figure 27. Direct ADC-Mode Typical INL

1.0

0.5

0

20.5

0

AMPLITUDE – dB

–100

0 9.0

FREQUENCY – MHz

Figure 29. Direct ADC Mode Typical FFT; FIN = 3.58 MHz,

= 18 MHz

F

S

Figures 27–29 show the typical linearity and distortion perfor­mance of the AD9802 in direct ADC mode.

Digitally Programmable Gain Control

The AD9802’s PGA is controlled by an analog input voltage of

0.3 V to 2.7 V. In some applications, digital gain control is
preferable. Figure 30 shows a circuit using Analog Devices’
AD8402 Digital Potentiometer to generate the PGA control
voltage. The AD8402 functions as two individual potentiom­eters, with a serial digital interface to program the position of
each wiper over 256 positions. The device will operate with 3V
or 5 V supplies, and features a power-down mode and a reset
function.

To keep external components to a minimum, the ends of the
“potentiometers” can be tied to ground and +3 V. One pot is
used for the coarse gain adjust, PGACONT1, with steps of
about 0.2 dB/LSB. The other pot is used for fine gain control,
PGACONT2, and is capable of around 0.01dB steps if all
eight bits are used. The two outputs should be filtered with
1 µF or larger capacitors to minimize noise into the PGACONT
pins of the AD9802.

PGACONT2

+3V

1mF

1

2

3

AD8402-10

4

5

6

7

14

13

12

11

10

9

8

+3V

PGACONT1

+3V

0.1mF1mF

21.0
0 600100 200 300 400 500

700 800 900

Figure 28. Direct ADC-Mode Typical DNL

1023

SHDN CS

SDI

RS

CLK

Figure 30. Digital Control of PGA

–11–REV. 0

AD9802

The disadvantage of this circuit is that the control voltage will
be supply dependent. If additional precision is required, an
external op amp can be used to amplify the VREFT (1.75 V) or
VREFB (1.25 V) pins on the AD9802 to the desired voltage
level. These reference voltages are stable over the operating
supply range of the AD9802. Low power, low cost, rail-to-rail
output amplifiers like the AD820, OP150 and OP196 are speci­fied for 3 V operation. Alternatively, a precision voltage refer­ence may be used. The REF193 from Analog Devices features
low power, low dropout performance, maintaining a 3 V output
with a minimum 3.1 V supply when lightly loaded.

Power and Grounding Recommendations

The AD9802 should be treated as an analog component when
used in a system. The same power supply and ground plane
should be used for all of the pins. In a two-ground system, this
requires that the digital supply pins be decoupled to the analog
ground plane and the digital ground pins be connected to ana­log ground for best noise performance. If any pins on the
AD9802 are connected to the system digital ground, then noise
can capacitively couple inside the AD9802 (through package
and die parasitics) from the digital circuitry to the analog
circuitry. Separate digital supplies can be used, particularly if
slightly different driver supplies are needed, but the digital
power pins should still be decoupled to the same point as the
digital ground pins (analog ground plane). If the AD9802 digi­tal outputs need to drive a bus or substantial load, a buffer
should be used at the AD9802’s outputs, with the buffer refer­enced to system digital ground. In some cases, when system
digital noise is not substantial, it is acceptable to split the
ground pins on the AD9802 to separate analog and digital
ground planes. If this is done, be sure to connect the ground
pins together at the AD9802.

To further improve performance, isolating the driver supply
DRVDD from DVDD with a ferrite bead can help reduce kick­back effects during major code transitions. Alternatively, the use
of damping resistors on the digital outputs will reduce the out­put rise times, reducing the kickback effect.

Evaluation Board

An evaluation board for the AD9802 is available. The board
includes circuitry for manual PGA gain adjustment, input signal
buffering, and logic level translation for 3 V or 5 V digital signals.

Documentation for the AD9802-EB is included, consisting of a
board description, schematic and layout information.

AD9801/AD9802 EVALUATION BOARD DESCRIPTION
Power Supply Connectors

J1 VDD: +3 V supply for the AD9801/AD9802. Data

sheet specifications are given for +3.15 V. Operational
range is from +3 V to +3.5 V.

J2 AVCC: +5 V supply for the AD8047 buffer, and for the

PGACONT and PIN potentiometers. If the buffer am­plifier is not needed, AVCC may be connected to the
VDD supply.

J3 AVSS: –5 V supply for the AD8047 buffer. If the buffer

amplifier is not needed, AVSS may be connected to J4.

J4 AGND: This is the analog ground plane for the

AD9801/AD9802 and the buffer amplifier. The two
ground planes are already connected together in one
place on the evaluation board.

J5 DGND: This is the digital ground plane for the

LVXC3245 transceivers. The two ground planes are
already connected together in one place on the evalua-

tion board.
J6 +3D: +3 V digital supply for the LVXC3245 transceivers.
J7 +3/5D: +3 V or +5 V digital supply for the LVXC3245

transceivers. This voltage determines the logic compat-

ibility of the evaluation board. If 3 V clock levels and

3 V digital output levels are to be used, connect +3 V to

J7. If +5 V clock levels and +5 digital output levels are

to be used, connect +5 V to J7.

Input Connectors

J8 DIN: Unbuffered input to the AD9801/AD9802. This

input is 50 Ω terminated by R4, which may be removed

if no termination is required. See Input Configurations

for more information.
J9 VIN: Input to the AD8047 buffer amplifier. This

input is 50 Ω terminated by R5, which may be re-

moved if no termination is required. This op amp

can be used as a buffer to drive the DIN pin on the

AD9801/AD9802, or as a buffer for driving the direct

ADC input on the AD9802. See Input Configurations

and the AD9802 data sheet for more information.

Clock Connectors

J10 CLPDM
J11 SHD
J12 SHP
J13 CLPOB
J14 PBLK
J15 ADCCLK

All of the clock inputs are 50 Ω terminated and buffered by an
LVXC3245 transceiver. The supply level at J7 determines the
input clock level compatibility. The outputs of the LVXC3245
always send +3 V clock levels to the AD9801/AD9802.

–12–

REV. 0

AD9802

Jumper Descriptions

JP1 Connect to bypass the input coupling capacitor C18.
JP2 Connect to short PIN and DIN (Pins 26 and 27 of the

AD9801) together.
JP3 Connects PIN to the dc level set by the wiper of R1.
JP4 Connect to short the input coupling capacitor to ground,

for test purposes.
JP5 Connects the output of the buffer amplifier to the

AD9801/AD9802 input.
JP6 Connects the AD9801/AD9802’s DRVDD pin to the

VDD supply through ferrite bead FB6.
JP7 Connects the AD9801/AD9802’s DRVDD pin to the

+3D supply.
JP8 Connects the output of the AD8047 op amp to the

direct ADC input of the AD9802. This jumper should

never be connected on the AD9801-EB.
JP9 Selects the regular camera mode of operation on the

AD9802. This jumper should always be in place on the

AD9801-EB.
JP10 Selects the direct ADC input mode on the AD9802.

This jumper should never be connected on the

AD9801-EB.

Input Configurations

Input JP1 JP2 JP3 JP4 JP5 JP8 JP9 JP10

Standard CCD Input J8 open short open open open open short open
Grounded Input Test none open short open short open open short open
Buffered Input* J9 open short open open short open short open
Direct ADC Input J9 [ ... don’t care... ] short open short

(9802 only)

*When using the buffer amplifier, ±5 V must be connected to AVCC and AVSS, and R4 should be removed.

Test Point Descriptions

TP1 Input signal at J8.
TP2 Input signal at PIN/DIN of AD9801/AD9802.
TP3 PGACONT1 voltage.
TP4 PGACONT2 voltage.
TP5 STANDBY pin, pull high to enable power-down mode.
TP6 CLPDM at AD9801/AD9802.
TP7 SHD at AD9801/AD9802.
TP8 SHP at AD9801/AD9802.
TP9 CLPOB at AD9801/AD9802.
TP10 PBLK at AD9801/AD9802.
TP11 ADCCLK at AD9801/AD9802.
TP12 VDD
TP13 AVCC
TP14 AVSS
TP15 AGND
TP16 DGND
TP17 +3D
TP18 +3/5D

Prototype Area

The top left hole in the prototyping area is connected to
AGND. The bottom right hole is connected to AVCC.

–13–REV. 0

AD9802

VDD

+3D

FB6

C55

0.01mF

JP6

JP7

C17

0.01mF

VDD

D0

D1
D2
D3
D4

D5
D6
D7
D8
D9

C4

0.1mF

0.1mF

0.1mF

C16

0.1mF

JP10

VDD

JP9

C5

MODE1

MODE2

SHABYP

CLAMP_BIAS

PGACONT2

PGACONT1

CCDBYP1

CCDBYP2

SHD

CLPDM

SHP

0.1mF

C6

0.1mF

ADCIN

CMLEVEL

TEST2

TEST1

ACVDD

ACVSS

PIN
DIN

DVSS

TP5
TP6
TP7
TP8
TP9
TP10
TP11

36
35
34
33

32
31
30
29

28
27
26
25

0.1mF

0.1mF
TP1

C13

C18

JP1

JP2

R4

50V

C19

0.1mF

C56

0.1mF

C8

0.1mF

C9

0.1mF

C10

0.1mF

C11

0.1mF

C12

0.1mF

J8

DIN

JP3

CW

PGACONT2
PGACONT1

R1

1kV

JP5

TP2

AVCC

JP8

AMP_OUT

C2

1
2
3
4
5
6
7
8

9

10

11
12

C1
1mF

48 47 46 45 44 39 38 3743 42 41 40

VRT

VRB

SUBST

ADVSS

ADVSS

ADVSS

ADVDD

D0 (LSB)
D1
D2
D3
D4
D5
D6

U1

AD9802

D7
D8
D9 (MSB)
DRVDD

DRVSS

ADCCLK

DVDD

DVSS

STBY

DSUBST

13 14 15 16 17 18 19 20 21 22 23 24

ADVDD

ADCMODE

PBLK

CLPOB

C3

VDD

C15

0.01mF

C14

0.1mF

JP4

SHP

SHD

PBLK

CLPOB

ADCCLK

CLPDM

Figure 31. Evaluation Board

–14–

REV. 0

AD9802

J1

J2

J3

J4

J5

J6

J7

+3V

+5V

–5V

GND

DGND

+3D

+3/5D

C34

0.1mF

C37

0.1mF

C40

0.1mF

C43

0.1mF

C46

0.1mF

FB1

FB2

FB3

FB4

FB5

TP15

TP16

TP12

TP13

TP14

TP17

TP18

C35
22mF

C38
22mF

C41
22mF

C44
22mF

C47
22mF

C36

0.1mF

C39

0.1mF

C42

0.1mF

C45

0.1mF

C48

0.1mF

VDD

AVCC

AVSS

+3D

+3/5D

AVCC

CW

R2

10kV

AVCC

CW

R3

10kV

AVCC

VIN

J9

R5
50V

R13
500V

U2

AD8047

AVSS

C31

0.1mF

C33

0.1mF

TP3

TP4

C21

0.01mF

C23

0.01mF

C30
10mF
16V

C32
10mF
16V

PGACONT1

PGACONT2

C20

1.0mF

C22

1.0mF

R6

20V

AMP_OUT

Figure 32. Evaluation Board

–15–REV. 0

AD9802

C26

0.01mF

C28

0.01mF

C53

0.1mF

C52

0.1mF

ADCCLK

R7

50V

R9

50V

R11

50V

J10

J12

J14

CLPDM

R8

50V

SHP

R10

50V

PBLK

R12

50V

J11

SHD

J13

CLPOB

J15

ADCCLK

+3D

74LVXC3245

1

VCCA

2

T/R

B

3

D9
D8
D7
D6
D5
D4
D3
D2

D1
D0

+3D

A0

4

A1

5

A2

6

A3

7

A4

8

A5

9

A6

10

A6

11

GND

12

GND

1

VCCA

2

T/R

3

A0

4

A1

5

A2

6

A3

7

A4

8

A5

9

A6

10

A6

11

GND

12

GND

U4

74LVXC3245

B

U5

V

OE

GND

V

OE

GND

+3/5D

C27

C50

0.01mF

0.1mF

24

B

CC

23

NC

22

B

21

B0
B1
B2
B3
B4
B5
B6
B7

CC

NC

B0
B1
B2
B3
B4
B5
B6
B7

DB9

20

DB8

19

DB7

18

DB6

17

DB5

16

DB4

15

DB3

14

DB2

13

+3/5D

C29

C51

0.01mF

0.1mF

24

B

23
22

B

21

DB1

20

DB0

19
18
17
16
15
14

CLKOUT

13

C24

0.01mF

C54

0.1mF

CLPDM

SHD
SHP

CLPOB

PBLK

ADCCLK

+3D

1

VCCA

2

T/R

3

A0

4

A1

5

A2

6

A3

7

A4

8

A5

9

A6

10

A6

11

GND

12

GND

74LVXC3245

B

U3

40-PIN HEADER

+3/5D

C25

C49

24

V

B

CC

23

NC

22

OE

B

21

B0

20

B1

19

B2

18

B3

17

B4

16

B5

15

B6

14

B7

13

GND

2

1
3
5
7

10

9
11
13
15

J16

17

20

19
21
23

30

33

40

0.1mF

DB9 (MSB)
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)

CLKOUT

0.01mF

Figure 33. Evaluation Board

–16–

REV. 0

AD9802

Figure 34. Primary Side (Layer 1)

Figure 35. Ground Plane (Layer 2)

–17–REV. 0

AD9802

Figure 36. Power Plane (Layer 3)

Figure 37. Secondary Layer (Layer 4)

–18–

REV. 0

AD9802

Figure 38. Primary Side Assembly

Figure 39. Secondary Side Assembly

–19–REV. 0

AD9802

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

48-Terminal Plastic Thin Quad Flatpack (TQFP)

(ST-48)

0.030 (0.75)

0.018 (0.45)

SEATING

PLANE

0.076 MAX

0° – 7°

0.063 (1.60) MAX

0.030 (0.75)

0.057 (1.45)

0.018 (0.45)

0.053 (1.35)

0° MIN

0.007 (0.18)

0.004 (0.09)

0.354 (9.00) BSC

0.276 (7.0) BSC

48

1

TOP VIEW

(PINS DOWN)

12

13

0.019 (0.5)
BSC

37

36

25

24

0.011 (0.27)

0.006 (0.17)

0.276 (7.0) BSC

0.354 (9.00) BSC

C3102–3–10/97

–20–

PRINTED IN U.S.A.

REV. 0