Datasheet AD9786 Datasheet (ANALOG DEVICES)

16-Bit, 200 MSPS/500 MSPS TxDAC+® with

2×/4×/8× Interpolation and Signal Processing

FEATURES

16-bit resolution, 200 MSPS input data rate
IMD 90 dBc @10 MHz
Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.3 LSB
INL = ±0.6 LSB
Selectable 2×/4×/8× interpolation filters

/2, f

/4, f

Selectable f

DAC

DAC

Single- or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface

3.3 V-compatible digital interface
On-chip 1.2 V reference
80-lead, thermally enhanced, TQFP_EP package

APPLICATIONS

Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA,

IS136, TETRA

Instrumentation

RF signal generators, arbitrary waveform generators
HDTV transmitters
Broadband wireless systems
Digital radio links
Satellite systems

/8 modulation modes

DAC

FUNCTIONAL BLOCK DIAGRAM

AD9786

PRODUCT HIGHLIGHTS

1. 16-bit, high speed, interpolating TxDAC+.

2. 2×/4×/8× user-selectable interpolating filter. The filter

eases data rate and output signal reconstruction filter
requirements.

3. 200 MSPS input data rate.

4. Ultra high speed, 500 MSPS DAC conversion rate.

5. Flexible clock with single-ended or differential input.

CMOS, 1 V p-p sine wave, and LVPECL capability.

6. Complete CMOS DAC function. It operates from a 3.1 V

to 3.5 V single analog (AVDD) supply, 2.5 V digital supply,
and a 3.3 V digital (DRVDD) supply. The DAC full-scale
current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.

7. On-chip voltage reference. The AD9786 includes a

1.20 V temperature-compensated band gap voltage
reference.

8. Multichip synchronization. Multiple AD9786 DACs can
be synchronized to a single master AD9786 to ease timing
design requirements and optimize image reject transmit
performance.

LATCH

P1B[15:0]

P2B[15:0]

DATACLK

CLK+

CLK–

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

DATA

ASSEMBLER

DATA PORT

SYNCHRONIZER

×1

LATCH

2×2×2×

f

/2

DAC

/4

f

DAC

f

/8

DAC

2×2×2×

CLOCK DISTRIBUTION AND CONTROL

CIRCUITS

REFERENCE

SPI

FSADJ

REFIO

IOUTA
IOUTB

SDIO
SDO
CSB
SCLK
RESET

I

0

90

0

90

0

90

Q

Δt

HILBERT

Re()/Im()

ZERO

STUFF

CALIBRATION

16-BIT DAC

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

03152-001

AD9786

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

Dynamic Specifications ............................................................... 6

Digital Specifications ................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Clock .............................................................................................. 9

General Operation of the Serial Interface............................... 20

Serial Interface Port Pin Descriptions..................................... 20

MSB/LSB Transfers .................................................................... 21

Notes on Serial Port Operation ................................................ 21

Mode Control (via Serial Port)..................................................... 22

Digital Filter Specifications........................................................... 26

Digital Interpolation Filter Coefficients.................................. 26

Clock/Data Timing .................................................................... 27

Real and Complex Signals......................................................... 32

Modulation Modes..................................................................... 33

Power Dissipation....................................................................... 38

Hilbert Transform Implementation......................................... 40

Operating the AD9786 Rev. F Evaluation Board ....................... 44

Power Supplies............................................................................ 44

PECL Clock Driver .................................................................... 44

Analog.......................................................................................... 10

Data ..............................................................................................10

Serial Interface ............................................................................ 11

Terminology .................................................................................... 12

Typical Performance Characteristics ........................................... 14

Serial Control Interface.................................................................. 20

Data Inputs.................................................................................. 45

Serial Port.................................................................................... 45

Analog Output............................................................................ 45

Outline Dimensions....................................................................... 55

Ordering Guide .......................................................................... 55

Rev. B | Page 2 of 56

AD9786

REVISION HISTORY

10/05—Rev. A to Rev. B

Updated Format.................................................................. Universal

Changes to Figure 1...........................................................................1

Changes to Table 2 ............................................................................6

Changes to Table 3 ............................................................................7

Changes to External Sync Mode Section .....................................31

Updated Outline Dimensions........................................................58

Changes to Ordering Guide...........................................................58

2/05—Rev. 0 to Rev. A

Changed DRVDD Supply Range......................................Universal

Changes to DC Specifications .........................................................4

Changes to Dynamic Specifications ...............................................5

Changes to Digital Specifications....................................................6

Changes to Absolute Maximum Ratings........................................7

Change to Figure 2............................................................................8

Replaced Figure 13..........................................................................14

Replaced Figure 14..........................................................................14

Replaced Figure 16..........................................................................15

Replaced Figure 21..........................................................................16

Replaced Figure 22..........................................................................16

Replaced Figure 26..........................................................................16

Replaced Figure 27..........................................................................17

Changes to Table 15........................................................................22

Change to Figure 44........................................................................26

Replaced Figure 45..........................................................................26

Change to Figure 47........................................................................27

Change to Figure 48........................................................................27

Change to Figure 51........................................................................29

Change to Figure 52........................................................................29

Change to Figure 53........................................................................30

Change to DATAADJUST Synchronization Section..................31

Changes to Power Dissipation Section.........................................40

Changes to Table 37........................................................................42

Changes to Data Inputs Section ....................................................46

Change to Figure 88........................................................................49

Replaced Figure 95..........................................................................55

Updated Outline Dimensions........................................................60

Changes to Ordering Guide...........................................................60

7/04—Revision 0: Initial Version

Rev. B | Page 3 of 56

AD9786

GENERAL DESCRIPTION

The AD9786 is a 16-bit, high speed, CMOS DAC with
2×/4×/8× interpolation and signal processing features tuned
for communications applications. It offers state-of-the-art
distortion and noise performance. The AD9786 was developed
to meet the demanding performance requirements of multicarrier
and third-generation base stations. The selectable interpolation
filters simplify interfacing to a variety of input data rates while
also taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.

The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or
differential mode. Internal dividers generate the required data
rate interface clocks.

The AD9786 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9786 is
manufactured on an advanced, low cost, 0.25 μm CMOS process.

Rev. B | Page 4 of 56

AD9786

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; I

MAX

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 16 Bits

DC Accuracy1

Integral Nonlinearity ±0.6 LSB
Differential Nonlinearity ±0.3 LSB

ANALOG OUTPUT

Offset Error ±0.015 ±0.0175 % of FSR

Gain Error (with Internal Reference) ±1.5 % of FSR
Full-Scale Output Current2 10 20 mA
Output Compliance Range –1.0 +1.0 V
Output Resistance 10 MΩ

REFERENCE OUTPUT

Reference Voltage 1.15 1.23 1.30 V
Reference Output Current3 1 μA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference Mode) 10 MΩ
Small Signal Bandwith 200 kHz

TEMPERATURE COEFFICIENTS

Unipolar Offset Drift 0 ppm of FSR/°C
Gain Drift (with Internal Reference) ±4 ppm of FSR/°C
Reference Voltage Drift ±30 ppm/°C

POWER SUPPLY

AVDD1, AVDD2

Voltage Range 3.1 3.3 3.5 V
Analog Supply Current (I
I

+ I

AVDD1

in Sleep Mode 18 mA

AVDD2

AVDD1

+ I

) 50 mA

AVDD2

ACVDD, ADVDD

Voltage Range 2.35 2.5 2.65 V
Analog Supply Current (I

ACVDD

+ I

) 2.5 mA

ADVDD

CLKVDD

Voltage Range 2.35 2.5 2.65 V
Clock Supply Current (I

) 12 mA

CLKVDD

DVDD

Voltage Range 2.35 2.5 2.65 V
Digital Supply Current (I

) 52.5 mA

DVDD

DRVDD

Voltage Range 3.1 3.3 3.5 V
Digital Supply Current (I

) 5.3 μA

DRVDD

Nominal Power Dissipation4 1.25 W

OPERATING RANGE –40 +85 °C

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

4

Measured under the following conditions: f

driving a virtual ground.

OUTA

, is 32× the I

OUTFS

current.

REF

= 125 MSPS, f

DATA

= 500 MSPS, 4× interpolation, f

DAC

/4 modulation, Hilbert off.

DAC

= 20 mA, unless otherwise noted.

OUTFS

Rev. B | Page 5 of 56

AD9786

DYNAMIC SPECIFICATIONS

T

to T

MIN

coupled output; 50 Ω doubly terminated, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Minimum DAC Output Update Rate 20 MHz

Maximum DAC Output Update Rate (f
AC LINEARITY/BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

Two-Tone Intermodulation (IMD) to Nyquist (f

Noise Power Spectral Density (NPSD)

Adjacent Channel Power Ratio (ACLR)

; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; I

MAX

) 500 MSPS

DAC

= 0 dBFS)

OUT

f

= 100 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 200 MSPS; f

DATA

f

= 156 MSPS; f

DATA

f

= 156 MSPS; f

DATA

= 5 MHz, 4×, 2× Interpolation 93 dBc

OUT

= 10 MHz 85 dBc

OUT

= 25 MHz 78 dBc

OUT

= 50 MHz 78 dBc

OUT

= f

OUT1

= 5 MHz; f

OUT1

= 15 MHz; f

OUT1

= 25 MHz; f

OUT1

= 45 MHz; f

OUT1

= 65 MHz; f

OUT1

= 85 MHz; f

OUT1

= 10 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz −164 dBm/Hz

OUT

= 50 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz −161 dBm/Hz

OUT

= 6 MHz 85 dBc

OUT2

= 16 MHz 85 dBc

OUT2

= 26 MHz 84 dBc

OUT2

= 46 MHz 80 dBc

OUT2

= 66 MHz 78 dBc

OUT2

= 86 MHz 75 dBc

OUT2

= –6 dBFS)

OUT2

= 20 mA; differential transformer

OUTFS

WCDMA ACLR with 3.84 MHz BW, Single Carrier

IF = 21 MHz, f
IF = 224.76 MHz, f

= 122.88 MSPS, 4× Interpolation 80 dB

DATA

= 122.88 MSPS, 4× Interpolation, High-Pass Interpolation Filter Mode 72 dB

DATA

Rev. B | Page 6 of 56

AD9786

DIGITAL SPECIFICATIONS

T

to T

MIN

; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; I

MAX

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 1.6 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current –10 +10 μA
Logic 0 Current –10 +10 μA
Input Capacitance 5 pF

CLOCK INPUTS1

Input Voltage Range 0 2.65 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
Latch Pulse Width (t

) 5 ns

LPW

Data Setup Time to DACCLK Out in Master Mode (tS) −0.5 ns
Data Hold Time to DACCLK Out in Master Mode (tH) 2.9 ns

1

See the Clock/Data Timing section for setup and hold times in various timing modes.

= 20 mA, unless otherwise noted.

OUTFS

Rev. B | Page 7 of 56

AD9786

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter With Respect to Rating

AVDD1, AVDD2,
DRVDD

AGND1, AGND2,
ACGND, ADGND,

−0.3 V to +3.6 V

CLKGND, DGND

ACVDD, ADVDD,
CLKVDD, DVDD

AGND1, AGND2,
ACGND, ADGND,

−0.3 V to +2.8 V

CLKGND, DGND

AGND1, AGND2,
ACGND, ADGND,
CLKGND, DGND

AGND1, AGND2,
ACGND, ADGND,
CLKGND, DGND

−0.3 V to +0.3 V

REFIO, FSADJ AGND1 −0.3 to AVDD1 + 0.3
IOUTA, IOUTB AGND1 −1.0 to AVDD1 +0.3
P1B15 to P1B0,

DGND −0.3 to DRVDD + 0.3

P2B15 to P2B0, RESET
DATACLK DGND −0.3 to DRVDD + 0.3
CLK+, CLK− CLKGND −0.3 to CLKVDD + 0.3
CSB, SCLK,

DGND −0.3 to DRVDD + 0.3

SDIO, SDO
Junction

−65°C to +125°C

Temperature Range
Storage

150°C

Temperature
Lead Temperature

300°C

(10 sec)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type1 θ

80-lead TQFP_EP (Thermally Enhanced) 23.5 °C/W

`

1

With thermal pad soldered to PCB.

Unit

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.

Rev. B | Page 8 of 56

AD9786

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DNC

ADVDD

ADGND

ACVDD

ACGND

AVDD2

AGND2

AVDD1

AGND1

IOUTA

IOUTB

AGND1

AVDD1

AGND2

AVDD2

ACGND

ACVDD

ADGND

ADVDD

DNC

FSADJ

60

REFIO

59

RESET

58

CSB

57

SCLK

56

SDIO

55

SDO

54

DGND

53

DVDD

52

P2B0

51

P2B1

50

P2B2

49

P2B3

48

P2B4

47

P2B5

46

DGND

45

DVDD

44

P2B6

43

P2B7

42

P2B8

41

P2B9

P2B11

P2B12

P2B10

CLKVDD

DNC
CLKVDD
CLKGND

CLK+
CLK–

CLKGND

DGND

DVDD
P1B15
P1B14
P1B13
P1B12
P1B11
P1B10

DGND

DVDD

P1B9
P1B8
P1B7

DNC = DO NOT CONNECT

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1

PIN 1

2

IDENTIFIER

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P1B6

P1B5

P1B4

P1B3

DGND

DVDD

P1B2

AD9786

TOP VIEW

(Not to Scale)

P1B1

P1B0

DRVDD

DATACLK

DGND

P2B13

IQSEL/P2B15

DVDD

Figure 2. Pin Configuration

CLOCK

Table 6. Clock Pin Function Descriptions

Pin
No. Mnemonic Direction Description

5, 6 CLK+, CLK– I Differential Clock Input.
2 DNC Do Not Connect.
31 DATACLK I/O

1, 3 CLKVDD Clock Domain 2.5 V.
4, 7 CLKGND Clock Domain 0 V.

DCLKEXT
0x02[3]

0

Mode

Pin configured for input of channel data rate or synchronizer clock. Internal clock
synchronizer can be turned on or off with DCLKCRC (0x02[2]).

1 Pin configured for output of channel data rate or synchronizer clock.

ONEPORTCLOCK/P2B14

03152-002

Rev. B | Page 9 of 56

AD9786

ANALOG

Table 7. Analog Pin Function Descriptions

Pin No. Mnemonic Direction Description

59 REFIO A Reference.
60 FSADJ A Full-Scale Adjust.
70, 71 IOUTB, IOUTA A Differential DAC Output Currents.
61 DNC Do Not Connect.
62, 79 ADVDD Analog Domain Digital Content 2.5 V.
63, 78 ADGND Analog Domain Digital Content 0 V.
64, 77 ACVDD Analog Domain Clock Content 2.5 V.
65, 76 ACGND Analog Domain Clock Content 0 V.
66, 75 AVDD2 Analog Domain Clock Switching 3.3 V.
67, 74 AGND2 Analog Domain Switching 0 V.
68, 73 AVDD1 Analog Domain Quiet 3.3 V.
69, 72 AGND1 Analog Domain Quiet 0 V.
80 DNC Do Not Connect.

DATA

Table 8. Data Pin Function Descriptions

Pin No. Mnemonic Direction Description

10 to 15, 18 to
24, 27 to 29

32 IQSEL/P2B15 I

33 ONEPORTCLOCK/P2B14 I/O

34, 37 to 43,
46 to 51

30 DRVDD Digital Output Pin Supply, 3.3 V.
9, 17, 26,

36, 44, 52
8, 16, 25,

35, 45, 53

P1B15 to P1B0 I

P2B13 to P2B0 I Input Data Port 2, Bit 13 to Bit 0.

DVDD Digital Domain, 2.5 V.

DGND Digital Domain, 0 V.

Input Data Port 1.

ONEPORT
0x02[6] Mode

0 Latched data routed for I channel processing.
1

ONEPORT
0x02[6]

0 X X

1 0 0

1 0 1

1 1 0

1 1 1

ONEPORT
0x02[6]

0 Latched data routed for Q channel Bit 14 processing.
1

Latched data demultiplexed by IQSEL and routed for
interleaved I/Q processing.

IQPOL
0x02[1]

Pin configured for output of clock at twice the channel
data route.

IQSEL/
P2B15 Mode (IQPOL = 0)

Latched data routed to Q channel Bit 15
(MSB) processing.

Latched data on Data Port 1 routed to Q
channel processing.

Latched data on Data Port 1 routed to I
channel processing.

Latched data on Data Port 1 routed to I
channel processing.

Latched data on Data Port 1 routed to Q
channel processing.

Rev. B | Page 10 of 56

AD9786

SERIAL INTERFACE

Table 9. Serial Interface Pin Function Descriptions

Pin No. Mnemonic Direction Description

54 SDO O

55 SDIO I/O

56 SCLK I Serial Interface Clock.
57 CSB I Serial Interface Chip Select.
58 RESET I Resets entire chip to default state.

SDIODIR
0x00[7]

CSB

1 X High impedance.
0 0 Serial data output.
0 1 High impedance.

SDIODIR

CSB

0x00[7] Mode

1 X High impedance.
0 0 Serial data output.
0 1 Serial data input/output depending on Bit 7 of the serial instruction byte.

Mode

Rev. B | Page 11 of 56

AD9786

TERMINOLOGY

Linearity Error (Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normal­ized to full scale, associated with a 1 LSB change in digital
input code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to 1.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1, minus the output when all inputs are set to 0.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Tem p er at u re Dr if t

Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-sec.

Spurious-Free Dynamic Range (SFDR)

The difference between the rms amplitude of the output signal
and the amplitude of the peak spurious signal over the specified
bandwidth. The units are often in dBc (dB with respect to the
carrier).

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

(interpolation rate), a digital filter can be constructed that has

f

DATA

a sharp transition band near f
appear around f

(output data rate) can be greatly suppressed.

DAC

/2. Images that would typically

DATA

Pass Band

Frequency band in which any input applied therein passes
unattenuated to the DAC output.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.

Rev. B | Page 12 of 56

AD9786

Group Delay

Number of input clocks between an impulse applied at the
device input and peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range

Impulse Response

Response of the device to an impulse applied to the input.

Hilbert Transform

A function with unity gain over all frequencies, but with a phase
shift of 90° for negative frequencies and a phase shift of –90° for
positive frequencies. Although this function cannot be imple­mented ideally, it can be approximated with a short FIR filter
with enough accuracy to be very useful in single sideband radio
architectures.

Adjacent Channel Leakage Ratio (ACLR)

A ratio in dBc between the measured power within a channel
relative to its adjacent channel.

Complex Modulation

The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = e
coswt + jsinwt) and realizing real and imaginary components
on the modulator output.

jwt

=

Complex Image Rejection

In a traditional two-part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex modulator
in series with the first complex modulator, either the upper or
lower frequency image near the second IF can be rejected.

Rev. B | Page 13 of 56

AD9786

TYPICAL PERFORMANCE CHARACTERISTICS

T

to T

MIN

coupled output; 50 Ω doubly terminated, unless otherwise noted.

; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; I

MAX

120

120

= 20 mA; differential transformer

OUTFS

100

80

60

SFDR (dBc)

40

20

0

Figure 3. SFDR vs. Frequency, f

120

100

80

60

SFDR (dBc)

40

–3dBFS

–6dBFS

0dBFS

FREQUENCY (MHz)

= 200 MSPS, 1× Interpolation

DATA

–3dBFS

–6dBFS

0dBFS

100

80

60

SFDR (dBc)

40

20

800 10203040506070

03152-003

0

Figure 6. SFDR vs. Frequency, f

120

100

80

60

SFDR (dBc)

40

–6dBFS

FREQUENCY (MHz)

= 200 MSPS, 2× Interpolation

DATA

–3dBFS

–6dBFS

0dBFS

0dBFS

–3dBFS

800 10203040506070

03152-006

20

0

Figure 4. SFDR vs. Frequency, f

120

100

80

60

SFDR (dBc)

40

20

0

Figure 5. SFDR vs. Frequency, f

FREQUENCY (MHz)

= 100 MSPS, 4× Interpolation

DATA

0dBFS

FREQUENCY (MHz)

= 50 MSPS, 8× Interpolation

DATA

–6dBFS

–3dBFS

450 5 10 15 20 25 30 35 40

03152-004

250 5 10 15 20

03152-005

Rev. B | Page 14 of 56

20

0

Figure 7. SFDR vs. Frequency, f

120

100

80

60

SFDR (dBc)

40

20

0

–6dBFS

0dBFS

–3dBFS

Figure 8. SFDR vs. Frequency, f

FREQUENCY (MHz)

= 125 MSPS, 4× Interpolation

DATA

FREQUENCY (MHz)

= 62.5 MSPS, 8× Interpolation

DATA

600 1020304050

03152-007

300 5 10 15 20 25

03152-008

AD9786

90

90

85

80

75

70

65

SFDR (dBc)

60

55

50

0dBFS

Figure 9. Out-of-Band SFDR, f

100

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

0dBFS

Figure 10. Out-of-Band SFDR, f

–3dBFS

F

(MHz)

OUT

= 200 MSPS, 2× Interpolation

DATA

–6dBFS

–3dBFS

F

(MHz)

OUT

= 125 MSPS, 4× Interpolation

DATA

–6dBFS

85

80

75

70

65

60

OUT OF BAND SFDR (dBc)

55

50

800 102030 607040 50

03152-009

010 304020

–6dBFS

ANALOG OUTPUT FREQUENCY (MHz)

Figure 12. Out-of-Band SFDR, f

90

85

80

75

–3dBFS

70

65

60

OUT OF BAND SFDR (dBc)

55

260200 220 2400 20 40 60 120 140 160 18080 100

03152-010

50

0dBFS

ANALOG OUTPUT FREQUENCY (MHz)

Figure 13. Out-of-Band SFDR, f

0dBFS

–3dBFS

= 100 MSPS, 4× Interpolation

DATA

–6dBFS

= 50 MSPS, 8× Interpolation

DATA

03152-012

250 5 10 15 20

03152-013

100

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

–3dBFS

0dBFS

Figure 11. Out-of-Band SFDR, f

–6dBFS

F

(MHz)

OUT

= 62.5 MSPS, 8× Interpolation

DATA

2600 20 40 60 120 140 160 180 200 220 24080 100

03152-011

Rev. B | Page 15 of 56

100

–6dBFS

–3dBFS

F

(MHz)

OUT

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

Figure 14. Third-Order IMD vs. Frequency, f

0dBFS

800 204060

= 160 MSPS, 1× Interpolation

DATA

03152-014

AD9786

100

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

–3dBFS

0dBFS

F

OUT

(MHz)

Figure 15. Third-Order IMD vs. Frequency, f

–6dBFS

1600 20 40 60 120 14080 100

= 160 MSPS, 2× Interpolation

DATA

03152-015

100

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

–3dBFS

0dBFS

F

(MHz)

OUT

Figure 18. Third-Order IMD vs. Frequency, f

–6dBFS

10002040 8060

= 200 MSPS,1x Interpolation

DATA

03152-018

100

–3dBFS

0dBFS

F

OUT

(MHz)

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

Figure 16. Third-Order IMD vs. Frequency, f

100

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

0dBFS

F

OUT

–3dBFS

(MHz)

Figure 17. Third-Order IMD vs. Frequency, f

–6dBFS

2000 20 40 60 120 140 160 18080 100

= 200 MSPS, 2× Interpolation

DATA

–6dBFS

260200 220 2400 20 40 60 120 140 160 18080 100

= 125 MSPS, 4× Interpolation

DATA

03152-016

03152-017

100

–3dBFS

F

0dBFS

OUT

–6dBFS

(MHz)

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

Figure 19. Third-Order IMD vs. Frequency, f

100

IMD (dBc)

95

90

85

80

75

70

65

60

55

50

–3dBFS

0dBFS

F

(MHz)

OUT

Figure 20. Third-Order IMD vs. Frequency, f

2000 20 40 60 120 140 160 18080 100

= 100 MSPS, 4× Interpolation

DATA

–6dBFS

2000 20 40 60 120 140 160 18080 100

= 50 MSPS, 8× Interpolation

DATA

03152-019

03152-020

Rev. B | Page 16 of 56

AD9786

100

95

90

85

80

75

70

IMD (dBc)

65

60

55

50

–3dBFS

0dBFS

F

(MHz)

OUT

Figure 21. Third-Order IMD vs. Frequency, f

–6dBFS

2600 204060 12010080 160140 180 200 220 240

= 62.5 MSPS, 8× Interpolation

DATA

03152-021

0.3

0.2

0.1

0

–0.1

DNL (LSBs)

–0.2

–0.3

–0.4

CODE

655360 8192 16384 24576 49152 5734432768 40960

03152-024

Figure 24. Typical DNL

1.25

1.00

0.75

0.50

0.25

INL (LSBs)

–0.25

–0.50

–140

–145

–150

–155

–160

–165

–170

–175

NOISE SPECTRAL DENSITY(dBm/Hz)

–180

0

CODE

Figure 22. Typical INL

F

= 156MSPS, 1× INTERPOLATION

DATA

F

= 156MSPS, 2× INTERPOLATION

DATA

ANALOG OUTPUT FREQUENCY (MHz)

Figure 23. Noise Spectral Density vs. Analog

Input Frequency, f

DATA

= 156 MSPS

–140

–145

–150

F

= 78MSPS, 1× INTERPOLATION

–155

–160

–165

–170

–175

NOISE SPECTRAL DENSITY(dBm/Hz)

655360 8192 16384 24576 49152 5734432768 40960

03152-022

–180

DATA

F

= 78MSPS, 2× INTERPOLATION

DATA

ANALOG OUTPUT FREQUENCY (MHz)

800 102030 607040 50

03152-025

Figure 25. Noise Spectral Density vs. Analog

Input Frequency, f

–150

–152

–154

–156

–158

–160

AIN = 0DBFS

–162

–164

–166

NOISE SPECTRAL DENSITY (dBm/Hz)

–168

1600 20 40 60 120 14080 100

03152-023

–170

A

= –3DBFS

IN

ANALOG OUTPUT FREQUENCY (MHz)

= –6DBFS

A

IN

= 78 MSPS

DATA

800 10203040506070

03152-026

Figure 26. Noise Spectral Density vs. Analog Input Frequency,

f

= 78 MSPS, 2x Interpolation

DATA

Rev. B | Page 17 of 56

AD9786

–

–150

–152

–154

A

= –3dBFS

–156

–158

–160

AIN = 0dBFS

IN

–162

= –6dBFS

A

–164

IN

–166

NOISE SPECTRAL DENSITY (dBm/Hz)

–168

–170

ANALOG OUTPUT FREQUENCY (MHz)

Figure 27. Noise Spectral Density vs. Analog Input Frequency,

f

= 156 MSPS, 2x Interpolation

DATA

–60

–10
–20
–30
–40
–50
–60
–70
–80
–90
100

1600 20 40 60 80 100 120 140

03152-027

–110

Figure 30. Two Tones Around 23 MHz, f

10

Ref Lv1
10 dBm

Marker 1 [T1]

–87.73 dBm

9.71442886 MHz

RBW
VBW
SWT

10 kHz
10 kHz
5 s

RF Att

Unit

0

1AVG

1

START 100 kHz STOP 200 MHz19.9 MHz/

= 200 MSPS,

DATA

2× Interpolation, Low-Pass Digital Filter Mode

20 dB

dBm

A

1MA

–65

–70

–75

ACLR (dBc)

–80

0dBFS

–3dBFS

–6dBFS

–85

–90

F

(MHz)

OUT

Figure 28. ACLR for First Adjacent Band vs. Frequency,

f

= 61.44 MSPS, 4× Interpolation

DATA

–60

–65

–70

0dBFS

–75

ACLR (dBc)

–80

–85

–90

F

(MHz)

OUT

Figure 29. ACLR for First Adjacent Band vs. Frequency,

f

= 76.8 MSPS, 4× Interpolation

DATA

–6dBFS

–3dBFS

10

0

Ref Lv1
10 dBm

Marker 1 [T1]

–87.95 dBm

11.71743487 MHz

RBW
VBW
SWT

10 kHz
10 kHz
5 s

RF Att

Unit

20 dB

dBm

A

–10
–20
–30

1AVG

1MA
–40
–50
–60
–70
–80

1

–90

1500 25 50 75 100 125

03152-028

–100
–110

START 100 kHz STOP 200 MHz19.9 MHz/

Figure 31. Two Tones Around 177 MHz, f

= 200 MSPS,

DATA

03152-031

2× Interpolation, High-Pass Digital Filter Mode

REF –29.82dBm
*AVG

Log
10dB/

AVERAGE
103

PAVG
22
W1 S2

CENTER 51.44MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER

2000 20 40 60 80 100 120 140 160 180

03152-029

–17.41dBm/

3.84MHz

*ATTEN 6dB

FREQ OFFSET

5.000MHz

10.000MHz

15.000MHz

20.000MHz

REF BW

3.840MHz

3.840MHz

3.840MHz

3.840MHz

dBc

0.15
–74.24
–75.73
–75.67

SWEEP 142.2ms (601 pts)VBW 300kHz

LOWER

dBm
–17.26
–91.65
–93.14
–93.08

SPAN 43.84MHz

UPPER

dBc

dBm

–74.63

–92.05

–75.67

–93.08

–76.38

–93.79

–75.75

–93.17

03152-032

Figure 32. ACLR for Two WCDMA Carriers @ 51.44 MHz,

f

= 61.44 MSPS, 4× Interpolation

DATA

Rev. B | Page 18 of 56

AD9786

REF –22.76dBm
*AVG

Log
10dB/

AVERAGE
22

PAVG
22
W1 S2

CENTER 20.00MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER
–10.38dBm/

3.84 MHz

*ATTEN 8dB

FREQ OFFSET

5.000MHz

10.000MHz

15.000MHz

REF BW

3.840MHz

3.840MHz

3.840MHz

dBc
–79.00
–80.78
–79.71

SWEEP 109.8ms (601 pts)VBW 300kHz

LOWER

dBm
–89.38
–91.16
–90.09

Figure 33. ACLR for Single WCDMA Carrier @ 20 MHz,

f

= 61.44 MSPS, 4× Interpolation

DATA

AC-COUPLED

SPAN 33.84MHz

UPPER

dBc

dBm

–79.63

–90.01

–81.77

–92.15

–81.45

–91.83

03152-033

REF –33.3dBm
*AVG

Log
10dB/

AVERAGE
104

PAVG
104
W1 S2

CENTER 46.40MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER
–20.32dBm/

3.84MHz

Figure 35. ACLR for Four WCDMA Carriers Near 50 MHz,

*ATTEN 6dB

FREQ OFFSET

5.000MHz

10.000MHz

15.000MHz

20.000MHz

25.000MHz

f

REF BW

dBc

3.840MHz

0.22

3.840MHz

–0.60

3.840MHz

–72.68

3.840MHz

–72.74

3.840MHz

–73.05

= 61.44 MSPS, 4× Interpolation

DATA

SWEEP 174.6ms (601 pts)VBW 300kHz

LOWER

dBm
–20.11
–20.92
–93.00
–93.06
–93.37

AC-COUPLED

SPAN 53.84MHz

UPPER

dBc

dBm

–0.16

–20.48

–72.05

–92.37

–72.85

–93.18

–72.55

–92.88

–72.02

–92.35

03152-035

REF –28.2dBm
*AVG

Log
10dB/

AVERAGE
22

PAVG
22
W1 S2

CENTER 142.88MHz
*RES BW 30kHz

RMS RESULTS

CARRIER POWER
–15.30dBm/

3.84MHz

*ATTEN 6dB

FREQ OFFSET

5.000MHz

10.000MHz

15.000MHz

REF BW

3.840MHz

3.840MHz

3.840MHz

dBc
–72.33
–72.41
–72.67

SWEEP 109.8ms (601 pts)VBW 300kHz

LOWER

dBm
–87.64
–87.71
–87.97

dBc
–72.13
–73.02
–73.50

Figure 34. ACLR for Single WCDMA Carrier @ 142.88 MHz,

f

= 61.44 MSPS, 4× Interpolation

DATA

SPAN 33.84MHz

UPPER

dBm
–87.43
–88.32
–88.88

03152-034

Rev. B | Page 19 of 56

AD9786

S

SERIAL CONTROL INTERFACE

SDO (PIN 54)

SDIO (PIN 55)

CLK (PIN 56)
CSB (PIN 57)

Figure 36. AD9786 SPI Port Interface

AD9786 SPI
PORT INTERFACE

03152-036

The AD9786 serial port is a flexible, synchronous serial commu­nications port, allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI® and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9786. Single­or multiple-byte transfers are supported, as well as MSB-first or
LSB-first transfer formats. The AD9786 serial interface port can
be configured as a single pin I/O (SDIO), or as two unidirectional
pins for input/output (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9786.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9786, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9786
serial port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines whether the upcoming data transfer is a
read or a write, the number of bytes in the data transfer, and the
starting register address for the first byte of the data transfer. The
first eight SCLK rising edges of each communication cycle are
used to write the instruction byte into the AD9786.

A logic high on the CSB pin, followed by a logic low, resets the
SPI port timing to the initial state of the instruction cycle. This
is true regardless of the present state of the internal registers or
the other signal levels present at the inputs to the SPI port. If the
SPI port is in the midst of an instruction cycle or a data transfer
cycle, none of the present data is written.

The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9786
and the system controller. Phase 2 of the communication cycle
is a transfer of 1, 2, 3, or 4 data bytes, as determined by the instruc­tion byte. Using one multibyte transfer is the preferred method.
Single-byte data transfers are useful to reduce CPU overhead
when register access requires one byte only. Registers change
immediately upon writing to the last bit of each transfer byte.

Instruction Byte

R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.

Logic high indicates a read operation; Logic 0 indicates a write
operation. N1 and N0, Bit 6 and Bit 5 of the instruction byte,
determine the number of bytes to be transferred during the data
transfer cycle (see Table 10).

Table 10. Bytes Transferred During Data Transfer Cycle

N1 N2 Description

0 0 Transfer 1 byte
0 1 Transfer 2 bytes
1 0 Transfer 3 bytes
1 1 Transfer 4 bytes

The bit decodes are shown as follows:

MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0

R/W

N1 N0 A4 A3 A2 A1 A0

A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0) of
the instruction byte determine which register is accessed during
the data transfer portion of the communication cycle. For multibyte
transfers, this address is the starting byte address. The remaining
register addresses are generated by the AD9786.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK—Serial Clock. The serial clock pin is used to
synchronize data to and from the AD9786 and to run the
internal state machines. The maximum frequency of SCLK
is 20 MHz. All data input to the AD9786 is registered on the
rising edge of SCLK. All data is driven out of the AD9786
on the falling edge of SCLK.

CSB—Chip Select. Active low input starts and gates a communi­cation cycle. It allows more than one device to be used on the
same serial communication lines. The SDO and SDIO pins go
to a high impedance state when this input is high. Chip select
should stay low during the entire communication cycle.

SDIO—Serial Data I/O. Data is always written into the
AD9786 on this pin. However, this pin can be used as a
bidirectional data line. The configuration of this pin is
controlled by Bit 7 of Register Address 0x00. The default is
Logic 0, which configures the SDIO pin as unidirectional.

SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9786 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.

Rev. B | Page 20 of 56

AD9786

MSB/LSB TRANSFERS

The AD9786 serial port can support both MSB-first or LSB-first
data formats. This functionality is controlled by register address
DATADIR (0x00[6]). The default is MSB first. When this bit is
set active high, the AD9786 serial port is in LSB-first format.
That is, if the AD9786 is in LSB-first mode, the instruction byte
must be written from least significant bit to most significant bit.
Multibyte data transfers in MSB-first format can be completed
by writing an instruction byte that includes the register address
of the most significant byte. In MSB-first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB-first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB-first mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.

The AD9786 serial port controller address increments from 0x1F
to 0x00 for multibyte I/O operations if the MSB-first mode is
active. The serial port controller address decrements from 0x00 to
0x1F for multibyte I/O operations if the LSB-first mode is active.

NOTES ON SERIAL PORT OPERATION

The AD9786 serial port configuration bits reside in Bit 6 and
Bit 7 of Register Address 0x00. Note that the configuration
changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register might occur
during the middle of a communication cycle. Care must be
taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.

The same considerations apply to setting the software reset
SWRST (0x00[5]) bit. All other registers are set to their default
values, but the software reset does not affect the bits in Register
Address 0x00 and Register Address 0x04.

It is recommended to use only single-byte transfers when
changing serial port configurations or initiating a software
reset.

CSB

SCLK

SDIO

SDO

CSB

SCLK

SDIO

SDO

CSB

SCLK

SDIO

CSB

SCLK

SDIO

SDO

INSTRUCTION CYCLE DATA TRANSFER CYCLE

R/W N1 N0 A4 A3 A2 A1 A0 D7 D6ND5

D7 D6ND5

N

0

N

0

Figure 37. Serial Register Interface Timing MSB First

INSTRUCTION CYCLE DATA TRANSFER CYCLE

A0 A1 A2 A3 A4 N0 N1 R/W D00D10D2

D00D10D2

0

N

0

N

Figure 38. Serial Register Interface Timing LSB First

t

DS

t

DS

t

PWH

t

t

SCLK

t

PWL

DH

INSTRUCTION BIT 6INSTRUCTION BIT 7

Figure 39. Timing Diagram for Register Write

t

DV

DATA BIT n–1DATA BIT n

Figure 40. Timing Diagram for Register Read

D00D10D20D3

D00D10D20D3

03152-037

D7ND6ND5ND4

D7ND6ND5ND4

03152-038

03152-039

03152-040

Rev. B | Page 21 of 56

AD9786

MODE CONTROL (VIA SERIAL PORT)

Table 11.

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

COMMS 00 SDIODIR DATADIR SWRST SLEEP PDN EXREF
FILTER 01 INTERP[1] INTERP[0] ZSTUFF HPFX8 HPFX4 HPFX2
DATA 02 DATAFMT ONEPORT DCLKSTR DCLKPOL DCLKEXT DCLKCRC IQPOL CRAYDIN
MODULATE 03 CHANNEL HILBERT MODDUAL SIDEBAND MOD[1] MOD[0]
RESERVED 04 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
DCLKCRC 05 DATAADJ[3] DATAADJ[2] DATAADJ[1] DATAADJ[0] MODSYNC MODADJ[2] MODADJ[1] MODADJ[0]
06 Reserved
07 Reserved
08 Reserved
09 Reserved
0A Reserved
0B Reserved
0C Reserved
0D Reserved
CALMEMCK 0E CALMEM[1] CALMEN[0] CALCKDIV[2] CALCKDIV[2] CALCKDIV[2]
MEMRDWR 0F CALSTAT CALEN XFERSTAT XFEREN SMEMWR SMEMRD FMEMRD UNCAL
MEMADDR 10 MEMADDR[7] MEMADDR[6] MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]
MEMDATA 11 MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]
DCRCSTAT 12 DCRCSTAT[2] DCRCSTAT[1] DCRCSTAT[0]

Table 12.

COMMS(00) Bit Direction Default Description

SDIODIR 7 I 0 0: SDIO pin configured for input only during data transfer

1: SDIO configured for input or output during data transfer

DATADIR 6 I 0 0: Serial data uses MSB-first format

1: Serial data uses LSB-first format
SWRST 5 I 0 1: Default all serial register bits, except Address 0x00 and Address 0x04
SLEEP 4 I 0 1: DAC output current off
PDN 3 I 0 1: All analog and digital circuitry, except serial interface, off
EXREF 0 I 0 0: Internal band gap reference

1: External reference

Table 13.

FILTER(01) Bit Direction Default Description

INTERP[1:0] [7:6] I 00 00: No interpolation

01: Interpolation 2×
10: Interpolation 4×

11: Interpolation 8×
ZSTUFF 3 I 0 1: Zero stuffing on
HPFX8 2 I 0 0: ×8 interpolation filter configured for low-pass

1: ×8 interpolation filter configured for high-pass
HPFX4 1 I 0 0: ×4 interpolation filter configured for low-pass

1: ×4 interpolation filter configured for high-pass
HPFX2 0 I 0 0: ×2 interpolation filter configured for low-pass

1: ×2 interpolation filter configured for high-pass

Rev. B | Page 22 of 56

AD9786

Table 14.

DATA(02) Bit Direction Default Description

DATAFMT 7 I 0 0: Twos complement data format

1: Unsigned binary input data format

ONEPORT 6 I 0 0: I and Q input data onto Port 1 and Port 2, respectively

1: I and Q input data interleaved onto Port 1

DCLKSTR 5 I 0 0: DATACLK pin, 12 mA drive strength

1: DATACLK pin, 24 mA drive strength

DCLKPOL 4 I 0 0: Input data latched on DATACLK/DACCLK rising edge (dependent on mode)

1: Input data latched on DATACLK/DACCLK falling edge (dependent on mode)

DCLKEXT 3 I 0 0: DATACLK pin inputs channel data rate or modulator synchronizer clock

1: DATACLK pin outputs channel data rate or modulator synchronizer clock

DCLKCRC 2 I 0 0: With DATACLK pin as input, DATACLK clock recovery off

1: With DATACLK pin as input, DATACLK clock recovery on

IQPOL 1 I 0

GRAYDIN 0 I 0 0: Gray decoder off

Table 15.

MODULATE(03) Bit Direction Default Description

CHANNEL 7 I 0

HILBERT 6 I 0 1: With MODDUAL on, Hilbert transform on
MODDUAL 5 I 0 0: Modulator uses a single channel

SIDEBAND 4 I 0 0: With MODDUAL on, upper sideband rejected

MOD[1:0] [3:2] I 00 00: No modulation

0: In one-port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data

into Q channel

1: In one-port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data

into Q channel

1: Gray decoder on

MODDUAL
0x03[5]

CHANNEL
0x03[7]

0 0 I channel processing routed to DAC
0 1 Q channel processing routed to DAC
1 0 Modulator real output routed to DAC
1 1 Modulator imaginary output routed to DAC

1: Modulator uses both I and Q channels

1: With MODDUAL on, lower sideband rejected

01: f

/2 modulation

S

10: f

/4 modulation

S

11: f

/8 modulation

S

Rev. B | Page 23 of 56

AD9786

Table 16.

DCLKCRC(05) Bit Direction Default Description

DATAADJ[3:0] [7:4] I 0000

MODSYNC 3 I 00 0: Channel data rate clock synchronizer mode

MODADJ[2:0] [2:0] I 000

Table 17.

VERSION(0D) Bit Direction Default Description

VERSION[3:0] [3:0] O Hardware version identifier

Table 18.

CALMEMCK(OE) Bit Direction Default Description

CALMEM [5:4] O 00 Calibration memory

CALCKDIV[2:0] [2:0] I 00 Calibration clock divide ratio from channel data rate

Table 19.

MEMRDWR(OF) Bit Direction Default Description

CALSTAT 7 O 0 0: Self-calibration cycle not complete

CALEN 6 I 0 1: Self-calibration in progress
XFERSTAT 5 O 0 0: Factory memory transfer not complete

XFEREN 4 I 0 1: Factory memory transfer in progress
SMEMWR 3 I 0 1: Write static memory data from external port
SMEMRD 2 I 0 1: Read static memory to external port
FMEMRD 1 I 0 1: Read factory memory data to external port
UNCAL 0 I 0 1: Use uncalibrated

DATACLK offset (twos complement representation)

0111: +7

:

0000: 0

:

1000: −8

1: State machine clock synchronizer mode

fS/8 fS/4 fS/2

000 1 1 1

001 +1/√2 0 –1

010 0 –1 1

011 –1/√2 0 –1

100 –1 +1 +1

101 –1/√2 0 –1

110 0 –1 +1

111 +1/√2 0 –1

00: Uncalibrated

01: Self-calibration

10: Factory calibration

11: User input

000: /32

001: /64

:

110: /2048

111: /4096

1: Self-calibration cycle complete

1: Factory memory transfer complete

Modulator coefficient offset

Rev. B | Page 24 of 56

AD9786

Table 20.

MEMADDR(10) Bit Direction Default Description

MEMADDR [7:0] [7:0] I/O 00000000 Address of factory or static memory to be accessed

Table 21.

MEMDATA(11) Bit Direction Default Description

MEMDATA [5:0] [5:0] I/O 000000 Data or factory or static memory access

Table 22.

DCRCSTAT(12) Bit Direction Default Description

DCRCSTAT (2) 2 O 0 0: With DATACLK CRC on, lock has never been achieved

1: With DATACLK CRC on, lock has been achieved at least once

DCRCSTAT(1) 1 O 0 0: With DATACLK CRC on, system is currently not locked

1: With DATACLK CRC on, system is currently locked

DCRCSTAT(0) 0 O 0 0: With DATACLK CRC on, system is currently locked

1: With DATACLK CRC on, system lost lock due to jitter

Rev. B | Page 25 of 56

AD9786

–

–

–

–

–

–

–

–

–

DIGITAL FILTER SPECIFICATIONS

DIGITAL INTERPOLATION FILTER COEFFICIENTS

Table 23. Stage 1 Interpolation Filter Coefficients

Lower Coefficient Upper Coefficient Integer Value

H(1) H(43) 9
H(2) H(42) 0
H(3) H(41) –27
H(4) H(40) 0
H(5) H(39) 65
H(6) H(38) 0
H(7) H(37) –131
H(8) H(36) 0
H(9) H(35) 239
H(10) H(34) 0
H(11) H(33) –407
H(12) H(32) 0
H(13) H(31) 665
H(14) H(30) 0
H(15) H(29) –1070
H(16) H(28) 0
H(17) H(27) 1764
H(18) H(26) 0
H(19) H(25) –3273
H(20) H(24) 0
H(21) H(23) 10358
H(22) 16384

Table 24. Stage 2 Interpolation Filter Coefficients

Lower Coefficient Upper Coefficient Integer Value

H(1) H(19) 19
H(2) H(18) 0
H(3) H(17) –120
H(4) H(16) 0
H(5) H(15) 436
H(6) H(14) 0
H(7) H(13) –1284
H(8) H(12) 0
H(9) H(11) 5045
H(10) 8192

Table 25. Stage 3 Interpolation Filter Coefficients

Lower Coefficient Upper Coefficient Integer Value

H(1) H(11) 7
H(2) H(10) 0
H(3) H(9) –53
H(4) H(8) 0
H(5) H(7) 302
H(6) 512

0

–20

–40

–60

–80

100

120

140

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

03152-041

Figure 41. 2× Interpolation Filter Response

0

–20

–40

–60

–80

100

120

140

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

03152-042

Figure 42. 4× Interpolation Filter Response

0

–20

–40

–60

–80

100

120

140

03152-043

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

Figure 43. 8× Interpolation Filter Response

Rev. B | Page 26 of 56

AD9786

CLOCK/DATA TIMING

Table 26. Data Port Synchronization

DCLKEXT
0x02, Bit 3

1 0 X DATACLK Master Channel data rate clock output
1 1 X Modulator Master

0 0 0 External Sync Mode

0 0 1 DATACLK Slave

0 1 0 Low Setup/Hold

0 1 1 Modulator Slave

MODSYNC
0x05, Bit 3

DCLKCRC
0x02, Bit 2 Mode Function

Modulator synchronization
DATACLK output

DATACLK inactive, DACCLK
synchronous with external data

DATACLK input, data rate clock,
data recovery on

DATACLK input, input data
synchronous with DATACLK

Input modulator synchronizer
DATACLK input

Two-Port Data Input Mode (DATACLK Master)

With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same frequency.
Note that DACCLK refers to the differential clock inputs applied
at Pin 5 and Pin 6. As Figure 44 and Figure 45 show, there is a
constant delay between the edges of DACCLK and DATACLK.

The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be
latched into the AD9786 upon either the rising or falling edge
of DACCLK. With DCLKPOL = 0, the data is latched in upon
the falling edge of DACCLK, as shown in Figure 44. With
DCLKPOL = 1, as shown in Figure 45, data is latched in upon
the rising edge of DACCLK. The setup and hold times are
always with respect to the latching edge of DACCLK.

DACCLK

IN

DATACLK

OUT

t

= 6ns TYP

D

Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0

t

Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1

= 5.5ns TYP

D

t

= –0.5ns MIN

S

t

= –0.5ns MIN

S

t

t

H

= 2.9ns MIN

H

t

12

= 2.9ns MIN

DATA

DACCLK

DATACLK

DATA

IN

OUT

03152-044

03152-045

With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the digital
inputs of the AD9786 upon every other rising edge of DACCLK,
as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as
shown in Figure 47, the latching edge of DACCLK is the rising
edge that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is
the rising edge of DACCLK that occurs just before the rising edge
of DATACLK. The setup and hold time values are identical to
those in Figure 44 and Figure 45.

Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 46 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.

With the interpolation set to 4× or 8×, the DACCLK input
runs at 4× or 8× the speed of the DATACLK output. The data
is latched in upon a rising edge of DACCLK, similar to the
2× interpolation mode.

However, the latching edge is every fourth edge in 4× inter­polation mode and every eighth edge in the 8× interpolation
mode. Similar to operation in the 2× interpolation mode, with
DCLKPOL = 0, the latching edge of DACCLK is the rising edge
that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, the latching edge of DACCLK is the rising
edge that occurs just before the rising edge of DATACLK.
The setup and hold time values are identical to those in 1×
and 2× interpolation.

Rev. B | Page 27 of 56

AD9786

t

Note that DCLKPOL (Register 0x02, Bit 4) can be used to select
the edge of DACCLK upon which the input data is latched.

There is a defined setup-and-hold window with respect to input
data and the latching edge of DACCLK. There is also a required
timing relationship between DATACLK and DACCLK. This is

and tHT (setup and

ST

DACCLK

DATACLK

DATA

IN

IN

03152-049

Figure 46. DATACLK Duty Cycle

= 6ns TYP

D

t

= –0.5ns MIN

S

t

= 2.9ns MIN

H

Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0

DACCLK

DATACLK

DATA

DACCLK

DATACLK

IN

OUT

03152-046

IN

03152-047

OUT

referred to in Figure 49 and Figure 50 as t
hold for transition). For example, with DCLKPOL set to Logic 0,
the input data latches upon the first rising edge of DACCLK
that occurs more than 1.5 ns before the falling edge of DATACLK.
DACCLK should not be given a rising edge in the window of
500 ps to 1.5 ns before the latching edge (falling edge when
DCLKPOL = 0, rising edge when DCLKPOL = 1) of DATACLK.
Failure to account for this timing relationship could result in
corrupt data.

There are three status bits available for a read that allow the user
to verify DLL lock. These are Bit 0, Bit 1, and Bit 2 (DCRCSTAT) in
Register 0x12.

t

= 1.5ns MIN

HT

t

= –500ps MIN

ST

t

= 0.0ns MIN

S

Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0

t

= 3.2ns MIN

H

t

= 5ns TYP

D

t

= –0.5ns MIN

S

t

= 2.9ns MIN

H

DATA

Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1

DATACLK Slave Mode (Data Recovery On)

DATACLK (Pin 31) can be used as an input to synchronize
multiple AD9786s. A clock generated by an AD9786 operating
in master mode, or a clock from an external source, can be used
to drive DATACLK.

In this mode, two clocks are required to be applied to the
AD9786. A clock running at the DAC sample rate, referred to as
DACCLK, must be applied to the differential inputs (Pin 5 and
Pin 6) of the AD9786. As described previously, a clock at the
input sample rate must also be applied to Pin 31 (DATACLK).
An internal DLL synchronizes the two applied clocks. The
timing relationships between the input data, DATACLK, and
DACCLK are given in Figure 49 and Figure 50.

Rev. B | Page 28 of 56

03152-048

t

= –1.0ns MIN

ST

t

= 2.0ns MIN

HT

t

= 0.0ns MIN

S

t

= 3.2ns MIN

H

Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1

DACCLK

DATACLK

DATA

IN

IN

03152-050

AD9786

Low Setup/Hold Mode
(DATACLK Input, Data Recovery Off)

Some applications might require that digital input data be
synchronized with the DATACLK input, rather than DACCLK.
For these applications, the AD9786 can be programmed for low
setup/hold mode by entering the values in Table 26 into the SPI
registers. With data recovery off and the MODSYNC bit set to
Logic 1, the AD9786 latches data in upon the rising or falling
edge of DATACLK input, depending on the state of DCLKPOL.

DACCLK

IN

DATACLK

IN

t

= 0.0ns MIN

t

= –1.1ns MIN

S

HT

t

= 2.8ns MIN

H

DATA

03152-051

t

= 3.0ns MIN

ST

Figure 51. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 0

DACCLK

IN

DATACLK

IN

t

= 2.0ns MIN

ST

t

= 1.0ns MIN

HT

t

= –1.8ns MIN tH = 3.1ns MIN

S

DATA

03152-052

Figure 52. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 1

External Sync Mode

In the external sync mode, the DATACLK is programmed as an
input but is not used. Applying a DATACLK input while in this
mode has no effect. The digital input data is synchronized solely
to the DACCLK input. With 1× interpolation, the data input is
latched upon every rising edge of DACCLK. The challenge is
that the user has no way of knowing exactly which edge is the
latching edge when the interpolating filters are in use. In 2×, 4×,
and 8× interpolation modes, the latching edge of DACCLK is

nd

every 2

, 4th, or 8th edge, respectively.

With the 2 ns keep-out window, shown in Figure 53, there is a
strong possibility of violating setup and hold times, especially at
high speeds. It is recommended that users sense the DAC output
noise floor for setup and hold violations. If setup and hold is violated,
DCLKPOL can be switched. The effect of switching the state of
DCLKPOL is that the latching edge is moved by one, two, or four
DACCLK cycles if the AD9786 is in 2×, 4×, or 8× interpolation
modes, respectively. Note that in this mode, the DATAADJ bits
have no effect.

t

= –300ps MIN tH = 2.9ns MIN

S

Figure 53. External Sync Mode with 2× Interpolation

Note that when using the AD9786 in external sync mode with
1× interpolation, that functionality is identical to master mode,
except that DATACLK out is not available. That is, with
DATACLKPOL = 0, data is latched on the falling edge of DACCLK,
and with DATACLKPOL = 1, data is latched on the rising edge
of DACCLK.

DATAADJUST Synchronization

When designing the digital interface for high speed DACs, care
must be taken to ensure that the DAC input data meets setup
and hold requirements. Often, compensation must be used in
the clock delay path to the digital engine driving the DAC. The
AD9786 has the on-chip capability to vary the latching edge of
DACCLK. With the interpolation function enabled, this allows
the user the choice of multiple edges upon which to latch the
data. For instance, if the AD9786 is using 8× interpolation, the
user can latch from one of eight edges before the rising edge of
DATACLK, or seven edges after this rising edge. The specific
edge upon which data is latched is controlled by SPI Register
0x05, Bits 7:4. Table 27 shows the relationship of the latching
edge of DACCLK and DATACLK with the various settings of
the DATAADJ bits.

Table 27. DATAADJ Values for Latching Edge Sync

SPI Register 0x05

Bit 7 Bit 6 Bit 5 Bit 4

Latching Edge Write DATACLK

0 0 0 0 0
0 0 0 1 +1
0 0 1 0 +2
0 0 1 1 +3
0 1 0 0 +4
0 1 0 1 +5
0 1 1 0 +6
0 1 1 1 +7
1 0 0 0 –8
1 0 0 1 –7
1 0 1 0 –6
1 0 1 1 –5
1 1 0 0 –4
1 1 0 1 –3
1 1 1 0 –2
1 1 1 1 –1

DACCLK

DATA

IN

03152-053

Rev. B | Page 29 of 56

AD9786

Note that the data in Figure 44 to Figure 53 was taken with the
DATAADJ default of 0000. Changing the DATAADJ values allows
the user to select the specific edge of DACCLK upon which the
input data is latched. This can be done in master mode, but it
is most useful in slave mode. For more information on using
DATAADJ and MODADJ to synchronize multiple AD9786s,
see Analog Devices Application Note 747. Table 27 lists the values
available for 8× interpolation, which, in turn, provides a choice of
16 edges to sync data. With 4× interpolation, there is
a choice of eight edges, and the relevant values from Table 27
are 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These
options allow latching edge placement from +3 cycles to −4 cycles.
In 2× interpolation, four edges are available, and the relevant
values from Table 27 are 0000, 0100, 1000, and 1100. The
choices for DATAADJ are diminished to +1 cycle to –2 cycles.

Figure 54, Figure 55, and Figure 56 show the alignment for the
latching edge of DACCLK with 4× interpolation and different
settings for DATAADJ. In Figure 54, the AD9786 is in
DATACLK master mode. DATAADJ is set to 0000, with
DCLKPOL set to 0 so that the latching edge of DACCLK is
immediately before the rising edge of DATACLK. The data
transitions shown in Figure 54 are synchronous with the
DACCLK, so that DACCLK and input data are constant with
respect to each other.

The only visible change when DATAADJ is altered is that
DATACLK moves, indicating the latching edge has moved as
well. Note that in DATACLK master mode, when DATAADJ is
altered, the latching edge with respect to DATACLK remains
the same.

Figure 55 shows the same conditions, but with DATAADJ set to

1111. This moves DATACLK to the left in the plot, indicating that
it occurs one DACCLK cycle before it did in Figure 54; therefore,
the latching edge of DACCLK also occurs one cycle earlier.

RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK

DACCLK

LATCHING EDGE

DATA TRANSITION

03152-055

Figure 55. DATAADJ = 1111

Figure 56 shows the same conditions, with DATAADJ set
to 0001; therefore, DATACLK moves to the right in the plot.
This indicates that it occurs one DACCLK cycle after it did in
Figure 54; therefore, the latching edge of DACCLK also occurs
one cycle later.

RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK

DATA TRANSITION

Figure 54. DATAADJ = 0000

RISING EDGE OF DATACLK
CONCURRENT WITH
LATCHING EDGE OF DACCLK

DACCLK
LATCHING EDGE

03152-054

DATA TRANSITION

Figure 56. DATAADJ = 0001

DACCLK

LATCHING EDGE

03152-056

Rev. B | Page 30 of 56

AD9786

–

–

–

–

–

–

–

–

Interpolation Modes

Table 28. Interpolation Modes

INTERP[1] INTERP[0] Mode

0 0 No interpolation
0 1 ×2 interpolation
1 0 ×4 interpolation
1 1 ×8 interpolation

Interpolation is the process of increasing the number of points
in a time domain waveform by approximating points between
the input data points on a uniform time grid. This produces
a higher output data rate. Applied to an interpolation DAC,
a digital interpolation filter is used to approximate the interpolated
points, having an output data rate increased by the interpolation
factor. Interpolation filter responses are achieved by cascading
individual digital filter banks, whose filter coefficients are given in
Table 23, Table 24, and Table 25. Filter responses are shown in
Figure 57, which shows the interpolation filters of the AD9786
under different interpolation rates, normalized to the input data

SIN

.

rate, f

The digital filter’s frequency domain response exhibits symmetry
about half the output data rate and dc. It causes images of the
input data to be shaped by the interpolation filter’s frequency
response. This has the advantage of causing input data images
that fall in the stop band of the digital filter to be rejected by
the stop-band attenuation of the interpolation filter, while input

0

–50

100

150

–8 –6 –4 –2 –0 2 4 6 8

0

–50

100

150

–8 –6 –4 –2 0 2 4 6 8

0

–50

100

150

–8 –6 –4 –2 0 2

0

–50

100

150

–8 –6 –4 –2 0 2 4 68

Figure 57. Interpolation Modes

data images falling in the interpolation filter pass band are passed.
In band-limited applications, the images at the output |of the
DAC must be limited by an analog reconstruction filter. The
complexity of the analog reconstruction filter is determined by
the proximity of the closest image to the required signal band.
Higher interpolation rates yield larger stop-band regions,
suppressing more input images and resulting in a much relaxed
analog reconstruction filter.

A DAC shapes its output with a sinc function, having a null at
the sampling frequency of the DAC. The higher the DAC sam­pling rate compared to the input signal bandwidth, the less the
DAC sinc function shapes the output. The higher the
interpolation rate, the more input data images fall in the
interpolation filter stop band and are rejected; the bandwidth
between passed images is larger with higher interpolation
factors. The sinc function shaping is also reduced with a higher
interpolation factor.

Table 29. Sinc Shaping at Band Edge of Interpolation Filters

Sinc Shaping

Mode

No interpolation –2.8241 f
×2 interpolation –0.6708 2 f
×4 interpolation –0.1657 4 f
×8 interpolation –0.0413 8 f

SINCRESPONSE

4 68

@ 0.43 f

NO INTERPOLATION

×2INTERPOLATION

×4INTERPOLATION

×8INTERPOLATION

SIN

(dB) Bandwidth to First Image

SIN

SIN

SIN

SIN

INTERP[1] = 0
INTERP[0] = 0

f

SIN

INTERP[1] = 0
INTERP[0] = 1

f

SIN

INTERP[1] = 1
INTERP[0] = 0

f

SIN

INTERP[1] = 1
INTERP[0] = 1

f

SIN

03152-057

Rev. B | Page 31 of 56

AD9786

REAL AND COMPLEX SIGNALS

A complex signal contains both magnitude and phase
information. Given two signals at the same frequency, if the
leading signal in phase is cosinusoidal and the lagging signal is
sinusoidal, information pertaining to the magnitude and phase of
a combination of the two signals can be derived; the combination
of the two signals can be considered a complex signal. The cosine
and sine can be represented as a series of exponentials, recalling
that a multiplication by j is a counterclockwise rotation about
the Re/Im plane. The phasor representation of a complex signal
with Frequency f is shown in Figure 58.

Im

C

2πft

Acos(2πft) = A =

Asin(2πft) = A =[je

A

C = Ae

Re

Figure 58. Complex Phasor Representation

Im

A/2

–f

2πft

= Acos(2πft) + jAsin(2πft)

+j2πft

–j2πft

e

+j2πft

e

+ e

2

+ e
2j

–j2πft

A

2

A

2

Re

A/2

A/2

0

+f

FREQUENCY

A/2

+j2πft

–j2πft

[

e

+ e

]

+j2πft

–j2πft

+ e

]

03152-058

The cosine term—referred to as the real in-phase, or I component,
of a complex signal—represents a signal on the real plane with
mirror symmetry about dc. The sine term—referred to as the
imaginary quadrature, or Q complex signal component—
represents a signal on the imaginary plane with mirror
asymmetry about dc.

The AD9786 has two channels of interpolation filters, allowing
both I and Q components to be shaped by the same filter transfer
function. The interpolation filter’s frequency response is a real
transfer function. Two DACs are required to represent a complex
signal. A single DAC can only synthesize a real signal. When a
DAC synthesizes a real signal, negative frequency components
fold onto the positive frequency axis. If the input to the DAC is
mirrored symmetrically about dc, the negative frequency
components fold directly onto the positive frequency compo­nents in phase-producing, constructive signal summation. If
the input to the DAC is not mirrored symmetrically about dc,
negative frequency components might not be in phase with
positive frequency components, causing destructive signal
summation. Different applications might benefit from either
type of signal summation.

Rev. B | Page 32 of 56

AD9786

MODULATION MODES

Table 30. Single-Channel Modulation

MODDUAL CHANNEL MOD[1] MOD[0] Mode

0 0 0 0 I channel, no modulation
0 0 0 1 I channel, modulation by f
0 0 1 0 I channel, modulation by f
0 0 1 1 I channel, modulation by f
0 1 0 0 Q channel, no modulation
0 1 0 1 Q channel, modulation by f
0 1 1 0 Q channel, modulation by f
0 1 1 1 Q channel, modulation by f

Either channel of the AD9786 interpolation filter channels can
be routed to the DAC and modulated. In single-channel
operation, the input data can be modulated by a real sinusoid;
the input data and the modulating sinusoid contain both
positive and negative frequency components. A double side­band output results when modulating two real signals. At the
DAC output, the positive and negative frequency components
add in phase, resulting in constructive signal summation.

As the modulating sinusoidal frequency becomes a larger
fraction of the DAC update rate, f

the sinc function of the

DAC,

DAC shapes the modulated signal bandwidth more, and the
first image moves closer.

Because the AD9786 interpolation filter pass band represents a
large portion of the input data Nyquist band, it is possible for
modulated signal bands to touch or overlap images if sufficient
interpolation is not used under certain modulation and
interpolation modes.

Figure 59 shows the effects of f

/8 modulation when using 8×

DAC

interpolation. Figure 60 to Figure 62 show the effects of real

Table 31. Synthesis Bandwidth vs. Interpolation Modes

Interpolation
Modulation None ×2 ×4 ×8

None f
f

/2 f

DAC

f

/4 Overlap Touching 2 f

DAC

f

/8 Overlap Overlap Touching 6 f

DAC

2 f

SIN

2 f

SIN

Table 32. Modulated Pass-Band Edges Sinc Shaping
(Lower/Upper)

Interpolation
Modulation None ×2 ×4 ×8

None 0 0 0 0
–2.8241 –0.6708 –0.1657 –0.0413
f

/2 –0.0701 –1.1932 –2.3248 –3.0590

DAC

–22.5378 –9.1824 –6.1190 –4.9337
f

/4 Overlap Touching –0.2921 –0.5974

DAC

–1.9096 –1.3607
f

/8 Overlap Overlap Touching –0.0727

DAC

–0.4614

modulation under all interpolation modes. The sinc shaping at
the corners of the modulated signal band and the bandwidth to
the first image for those cases whose pass bands do not touch or
overlap are tabulated.

/2

DAC

/4

DAC

/8

DAC

/2

DAC

/4

DAC

/8

DAC

4 f

SIN

4 f

SIN

8 f

SIN

8 f

SIN

4 f

SIN

SIN

SIN

SIN

SIN

Rev. B | Page 33 of 56

AD9786

–

–

–

–

–

–

–

–

FILTERED INTERPOLATION IMAGES

0

DAC/8

f

–

f

/8 MODULATION

S

DAC/8

f

–

DAC/8fDAC/43fDAC/8fDAC/25fDAC/83fDAC/47fDAC/8

f

DAC/8fDAC/43fDAC/8fDAC/25fDAC/83fDAC/47fDAC/8

f

f

–

–f

DAC

DAC

/8

DAC

–7f

/8

DAC

–7f

/4

f

–3

/4

f

–3

DAC

DAC

/8

f

–5

/8

f

–5

DAC

DAC

/2

f

–

/2

f

–

DAC

DAC

/8

f

–3

/8

f

–3

DAC

DAC

/4

f

–

/4

f

–

DAC

DAC

Figure 59. Double Sideband Modulation

0

–50

100

150

–8 –6 –4 –2 0 2 4 68

0

–50

100

150

–8–6–4–202468

0

–50

100

150

–8–6–4–202468

0

–50

100

150

–8 –6 –4

Figure 60. Real Modulation by f

–202468

/2 Under All Interpolation Modes

DAC

NO INTERPOLATION

×2INTERPOLATION

×4 INTERPOLATION

×8 INTERPOLATION

DAC

f

DAC

f

03152-059

INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1

f

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

f

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1

f

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

f

SIN

03152-060

Rev. B | Page 34 of 56

AD9786

0

–50

–100

–150

–8 –6 –4 –2 0 2 4 68

0

–50

–100

–150

–8 –6 –4 –2 0 2

0



–50

–100

–150

–8 –6 –4 –2 0 2 4 6 8

0

–50

–100

–150

–8 –6 –4 –2 0 2 4 6 8

Figure 61. Real Modulation by f

/4 Under All Interpolation Modes

DAC

468

NO INTERPOLATION

×2 INTERPOLATION

×4 INTERPOLATION

×8 INTERPOLATION

INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

f

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

f

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

f

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

f

SIN

03215-061

0

–50

–100

–150

–8

0

–50

–100

–150

–8 –6

0

–50

–100

–150

–8 –6

0

–50

–100

–150

8– –6

–6 –4 –2

–4 –2 0

–4 –2 0

–4 –2

Figure 62. Real Modulation by f

0 2

246

246

024

/8 Under All Interpolation Modes

DAC

4 6 8

NO INTERPOLATION

×2 INTERPOLATION

×4 INTERPOLATION

×8 INTERPOLATION

68

INTERP[1] = 0
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

f

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

8

f

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

8

f

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

f

SIN

03152-062

Rev. B | Page 35 of 56

AD9786

Table 33. Dual-Channel Complex Modulation

MODDUAL CHANNEL MOD[1] MOD[0] Mode

0 0 0 0 Real output, no modulation
0 0 0 1 Real output, modulation by f
0 0 1 0 Real output, modulation f
0 0 1 1 Real output, modulation f
0 1 0 0 Image output, no modulation
0 1 0 1 Image output, modulation by f
0 1 1 0 Image output, modulation by f
0 1 1 1 Image output, modulation by f

In dual-channel mode, the two channels can be modulated by
a complex signal, with either the real or imaginary modulation
result directed to the DAC. Assume initially, as in Figure 63,
that the complex modulating signal is defined for a positive
frequency only. This causes the output spectrum to be trans­lated in frequency by the modulation factor only. No additional
sidebands are created as a result of the modulation process;
therefore, the bandwidth to the first image from the baseband
bandwidth is the same as the output of the interpolation filters.
Furthermore, pass bands do not overlap or touch. The sinc
shaping at the corners of the modulated signal band is tabulated
in Table 34. Figure 64, Figure 65, and Figure 66 show the effects

Table 34. Complex Modulated Pass-Band Edges Sinc Shaping
(Lower/Upper)

Interpolation
Modulation None ×2 ×4 ×8

None 0 0 0 0
–2.8241 –0.6708 –0.1657 –0.0413
f

/2 –0.0701 –1.1932 –2.3248 –3.0590

DAC

–22.5378 –9.1824 –6.1190 –4.9337
f

/4 –0.4680 –0.0175 –0.2921 –0.5974

DAC

–6.0630 –3.3447 –1.9096 –1.3607
f

/8 –1.3723 –0.1160 –0.0044 –0.0727

DAC

–4.9592 –1.7195 –0.7866 –0.4614

of complex modulation with varying interpolation rates.

FILTERED INTERPOLATION IMAGES

DAC

DAC

DAC

/4
/8

/2

DAC

DAC

DAC

/2
/4
/8

f

–

f

–

DAC

DAC

/8

DAC

f

–7

/8

DAC

f

–7

/4

f

–3

/4

f

–3

DAC

DAC

/8

f

–5

/8

f

–5

DAC

DAC

/2

f

–

/2

f

–

DAC

DAC

/8

f

–3

/8

f

–3

DAC

DAC

/4

DAC

f

–

/4

DAC

f

–

0

/8

DAC

f

–

f

/8 MODULATION

S

0

/8

DAC

f

–

/8

DAC

f

NO NEGATIVE
SIDEBAND

/8

DAC

f

/4

DAC

f

/4

DAC

f

/8

3f

/8

3f

DAC

DAC

/2

DAC

f

/2

DAC

f

/8

5f

/8

5f

DAC

DAC

/4

3f

/4

3f

DAC

DAC

/8

DAC

7f

/8

DAC

7f

f

f

DAC

DAC

03152-063

Figure 63. Complex Modulation

Rev. B | Page 36 of 56

AD9786

–

–

–

–

–

–

–

–

–

–

–

–

0

–50

100

150

–8 –6 –4 –2 0 2 4 68

0

–50

100

150

–8 –6 –4 –2 0 2

0

–50

100

150

–8 –6 –4 –2 0 2 4 6 8

Figure 64. Complex Modulation by f

/2 Under All Interpolation Modes

DAC

468

×2INTERPOLATION

×4INTERPOLATION

×8INTERPOLATION

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

f

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 0
MOD[0] = 1

f

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 0
MOD[0] = 1

f

SIN

03152-064

0

–50

100

150

–8 –6 –4 –2 0

0

–50

100

150

–8

0

–50

100

150

–8 –6 –4 –2 0 2 4 6 8

–6 –4 –2 0 2 4 6 8

Figure 65. Complex Modulation by f

0

–50

–100

–150

–8 –6 –4 –2 0 2 4 68

0

–50

–100

–150

–8 –6 –4 –2 0 2 4 68

0

–50

–100

–150

–8 –6 –4 –2 0 2 4 68

Figure 66. Complex Modulation by f

2 4 68

/4 Under All Interpolation Modes

DAC

/8 Under All Interpolation Modes

DAC

×2INTERPOLATION

×4INTERPOLATION

×8INTERPOLATION

×2INTERPOLATION

×4INTERPOLATION

×8INTERPOLATION

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

f

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 0

f

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 0

f

SIN

INTERP[1] = 0
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 1

f

SIN

INTERP[1] = 1
INTERP[0] = 0
MOD[1] = 1
MOD[0] = 1

f

SIN

INTERP[1] = 1
INTERP[0] = 1
MOD[1] = 1
MOD[0] = 1

f

SIN

03152-065

03152-066

Rev. B | Page 37 of 56

AD9786

POWER DISSIPATION

The AD9786 has seven power-supply domains: two 3.3 V
analog domains (AVDD1 and AVDD2), two 2.5 V analog
domains (ADVDD and ACVDD), one 2.5 V clock domain
(CLKVDD), and two digital domains (DVDD, which runs
from 2.5 V; and DRVDD, which runs from 3.3 V).

The current needed for the 3.3 V analog supplies, AVDD1 and
AVDD2, is consistent across speed and varying modes of the
AD9786. Nominally, the current for AVDD1 is 29 mA across all
speeds and modes, whereas the current for AVDD2 is 20 mA.

60

50

40

30

ICLKVDD (mA)

20

10

4×8×

2×

1×

The current for the 2.5 V analog supplies and the digital
supplies varies depending on speed and mode of operation.
Figure 67, Figure 68, and Figure 69 show this variation. Note
that CLKVDD, ADVDD, and ACVDD vary with clock speed
and interpolation rate, but not with modulation rate.

425
400
375
350
325
300
275
250
225
200
175

IDVDD (mA)

150
125
100

75
50
25

0

F

DATA

4× fs/8
4× fs/4

4×

(MSPS)

8× fs/8

8× fs/4

8×

Figure 67. DVDD Supply Current vs. Clock Speed,

Interpolation, and Modulation Rates

2× fs/8

2× fs/4

2×

1×

2500 25 50 75 100 125 150 175 200 225

03152-067

0

F

(MSPS)

DATA

2500 25 50 75 100 125 150 175 200 225

03152-068

Figure 68. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates

30

25

20

15

10

IADVDD AND IACVDD (mA)

5

0

8×

F

DATA

4×

(MSPS)

2×

1×

2500 25 50 75 100 125 150 175 200 225

03152-069

Figure 69. ADVDD and ACVDD Supply Current vs. Clock Speed

and Interpolation Rates

Rev. B | Page 38 of 56

AD9786

FILTERED INTERPOLATION IMAGES

/8

/4

/8

/2

f

–

f

–

f

–

DAC

DAC

DAC

f

–7

/8

f

–7

/8

f

–7

DAC

DAC

DAC

DAC

f

–3

/4

DAC

f

–3

/4

DAC

f

–3

DAC

f

–5

/8

DAC

f

–5

/8

DAC

f

–5

DAC

f

–

/2

DAC

f

–

/2

DAC

f

–

/8

f

–3

/8

f

–3

/8

f

–3

DAC

DAC

DAC

/4

DAC

f

–

/4

DAC

f

–

/4

DAC

f

–

/8

DAC

f

–

f

/8 MODULATION

S

/8

DAC

f

–

f

/4 MODULATION

S

/8

DAC

f

–

Figure 70. Complex Modulation with Negative Frequency Aliasing

Table 35. Dual Channel Complex Modulation with Hilbert

Hilbert Mode

0 Hilbert transform off
1 Hilbert transform on

When complex modulation is performed, the entire spectrum is
translated by the modulation factor. If the resulting modulated
spectrum is not mirrored symmetrically about dc when the
DAC synthesizes the modulated signal, negative frequency
components fall on the positive frequency axis and can cause
destructive summation of the signals, as shown in Figure 70. For
some applications, this can distort the modulated output signal.

X = Ae
Im

j2π(f + fm)t

Re

Y = Ae
Im

j2π(f + fm)t – π/2

Re

Z = HILBERT(Y) C = X – Z

Im

Re

Im

Re

000

/8

/4

/8

/2

/8

/4

/8

DAC

DAC

f

/8

DAC

f

/8

DAC

f

DAC

f

/4

DAC

f

/4

DAC

f

3f

/8

3f

DAC

/8

DAC

3f

DAC

f

/2

f

/2

f

DAC

DAC

DAC

5f

/8

5f

/8

5f

DAC

DAC

DAC

DAC

3f

/4

DAC

3f

/4

DAC

3f

7f

/8

7f

/8

7f

DAC

DAC

DAC

f

f

f

DAC

DAC

The operation of the Hilbert transform (Figure Z) rotates the
negative frequency components of Figure Y by +π/2, and the
positive frequency components of Figure Y by −π/2. The result
of the Hilbert transform output is then summed with the complex
signal in the main signal path. The result is that negative frequen­cies are cancelled and, therefore, do not fold back into the
positive side of the frequency spectrum. The Δt block in the main
signal path offsets the delay inherent in the Hilbert transform
(nine DAC clock cycle delay). When the DAC synthesizes the
modulated output, there are no negative frequency components to
fold onto the positive frequency axis out of phase; consequently,
no distortion is produced as a result of the modulation process.

0

ALIASED NEGATIVE FREQUENCY INTERPOLATION IMAGES

03152-070

A/2

A/2

f

A/2 A/2

A/2 A/2

A/2

A/2

A/2A/2

A/2

f

A/2

f

A

0000

f

A

Figure 71. Negative Frequency Image Rejection

In Figure 71, Figure X represents a complex signal typically
found in the AD9786 signal path. Figure Y is identical to Figure X,
but it is shifted by π/2. The phase shifting in the AD9786 occurs
because the digital LO driving the digital quadrature modulator
in the Hilbert transform path is phase shifted by π/2.

Rev. B | Page 39 of 56

03152-071

–50

dBFS

–100

–150

Figure 72. Negative Frequency Aliasing Distortion

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

03152-072

AD9786

–

–

–

–

–

Figure 72 shows this effect at the DAC output for a signal
mirrored asymmetrically about dc that is produced by complex
modulation without a Hilbert transform. The signal bandwidth
was narrowed to show the aliased negative frequency
interpolation images.

The transfer function of an ideal Hilbert transform has a +90°
phase shift for negative frequencies, and a –90° phase shift for
positive frequencies. Because of the discontinuities that occur at
0 Hz and at 0.5 × the sample rate, any real implementation of
the Hilbert transform trades off bandwidth vs. ripple.

In contrast, Figure 73 shows the same waveform with the
Hilbert transform applied. Clearly, the aliased interpolation
images are not present.

0

–50

dBFS

–100

–150

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

03152-073

Figure 73. Effects of Hilbert Transform

If the output of the AD9786 is used with a quadrature modulator,
negative frequency images are cancelled without the need for
a Hilbert transform.

HILBERT TRANSFORM IMPLEMENTATION

The Hilbert transform on the AD9786 is implemented as a
19-coefficient FIR. The coefficients are given in Table 36.

Table 36.

Coefficient Integer Value

H(1) –6
H(2) 0
H(3) –17
H(4) 0
H(5) –40
H(6) 0
H(7) –91
H(8) 0
H(9) –318
H(10) 0
H(11) +318
H(12) 0
H(13) +91
H(14) 0
H(15) +40
H(16) 0
H(17) +17
H(18) 0
H(19) +6

Figure 74 and Figure 75 show the gain of the Hilbert transform
vs. frequency. Gain is essentially flat, with a pass-band ripple of

0.1 dB over the frequency range of 0.07 × the sample rate to

0.43 × the sample rate.

Figure 76 shows the phase response of the Hilbert transform
implemented in the AD9786. The phase response for positive
frequencies begins at –90° at 0 Hz, followed by a linear phase
response (pure time delay) equal to nine filter taps (nine
DACCLK cycles). For negative frequencies, the phase response
at 0 Hz is +90°, followed by a linear phase delay of nine filter
taps. To compensate for the unwanted 9-cycle delay, an equal
delay of nine taps is used in the AD9786 digital signal path
opposite the Hilbert transform. This delay block is shown as Δt
in the Functional Block Diagram (Figure 1).

10

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100

1000100 200 300 400 500 600 700 800 900

03152-074

Figure 74. Hilbert Transform Gain

1.0

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1.0
1000100 200 300 400 500 600 700 800 900

03152-075

Figure 75. Hilbert Transform Ripple

Rev. B | Page 40 of 56

AD9786

4

3

2

1

0

–1

–2

–3

A baseband double sideband signal modulated to IF increases
IF filter complexity and reduces power efficiency. If the base­band signal is complex, a single sideband IF modulation can be
used, relaxing IF filter complexity and increasing power
efficiency.

The AD9786 has the ability to place the baseband single side­band complex signal either above or below the IF frequency.
Figure 78, Figure 79, and Figure 80 illustrate this.

0

–4

1200100 200 400 600 800 1000

03152-076

Figure 76. Phase Response of Hilbert Transform

Table 37. Dual Channel Complex Modulation Sideband Selection

Sideband Mode

0 Upper IF sideband rejected
1 Lower IF sideband rejected

LO

Re()

Im()

0

90

03152-077

I

AD9786

Q

AD9786

Figure 77. AD9786 Driving Quadrature Modulator

The AD9786 can be configured to drive a quadrature modulator,
as in Figure 77. When two AD9786s are used with one AD9786
producing the real output, the second AD9786 produces the
imaginary output. By configuring the AD9786 as a complex
modulator coupled to a quadrature modulator, IF image
rejection is possible. The quadrature modulator acts as the real
part of a complex modulation, producing a double sideband
spectrum at the local oscillator (LO) frequency with mirror
symmetry about dc.

dBFS

–100

–150

dBFS

–100

–150

BASEBAND IF

–50

–50

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

03152-078

Figure 78. Upper IF Sideband Rejected

0

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

03152-079

Figure 79. Lower IF Sideband Rejected

IF

–f

IF

f

–

IF

f

–

00

0

IF

f

SIDEBAND = 1

IF

f

SIDEBAND = 0

IF

f

03152-080

Figure 80. IF Quadrature Modulation of Real and Complex Baseband Signals

Rev. B | Page 41 of 56

AD9786

Master/Slave, Modulator/DATACLK Master Modes

In applications where two or more AD9786s are used to synthe­size several digital data paths, it might be necessary to ensure
that the digital inputs to each device are latched synchronously.
In complex data processing applications, digital modulator phase
alignment might be required between two AD9786s. To allow
data synchronization and phase alignment, only one AD9786
should be configured as a master device, providing a reference
clock for another slave-configured AD9786.

With synchronization enabled, a reference clock signal is
generated on the DATACLK pin of the master. The DATACLK
pins on the slave devices act as inputs for the reference clock
generated by the master. The DATACLK pin on the master and
all slaves must be directly connected. All master and slave devices
must have the same clock source connected to their respective
CLK+/CLK– pins.

When configured as a master, the reference clock generated can
take one of two forms. In modulator master mode, the reference
clock is a square wave with a period equal to 16 cycles of the
DAC update clock. Internal to the AD9786 is a 16-state, finite
state machine, running at the DAC update rate. This state machine
generates all internal and external synchronization clocks and
modulator phasings. The rising edge of the master reference clock
is time aligned to state zero of the internal state machine. Slave
devices use the master reference clock to synchronize data latching
and align modulator phase by aligning state zero of the local
state machine to the master.

DAC

CLOCK

The second master mode, DATACLK master mode, generates a
reference clock that is at the channel data rate. In this mode, the
slave devices align their internal channel data rate clock to the
master. If modulator phase alignment is needed, a concurrent
serial write to all slave devices is necessary. To achieve this, the
CSB pin on all slaves must be connected together, and a group
serial write to the MODADJ register bits must be performed.
Following a successful serial write, the modulator coefficient
alignment is updated upon the next rising edge of the internal
state machine (see Figure 81). Modulator master mode does not
need a concurrent serial write, because slaves lock to the master
phase automatically.

In a slave device, the local channel data rate clock and the
digital modulator clock are created from the internal state
machine. The local channel data rate clock is used by the slave
to latch digital input data. At high data rates, the delay inherent
in the signal path from master to slave can cause the slave to lag
the master when acquiring synchronization. To accommodate
for this, an integer number of the DAC update clock cycles can
be programmed into the slave device as an offset. The value in
DATAADJ allows the local channel data rate clock in the slave
device to advance by up to eight cycles of the DAC clock, or to
be delayed by up to seven cycles (see Figure 82).

The digital modulator coefficients are updated at the DAC clock
rate and decoded in sequential order from the state machine
according to Figure 83. The MODADJ bits can be used to align
a different coefficient to the finite state machine’s zero state, as
shown in Figure 84.

STATE

MACHINE

MODULATOR

COEFFICIENT

MODADJ

STATE MACHINE

CYCLE CLOCK

CHANNEL DATA

RATE CLOCK

01234567891011121314150123456789101112131415

10–1010–1010–1010–10–1010–1010–1010–1010

000 000

Figure 81. Synchronous Serial Modulator Phase Alignment

Rev. B | Page 42 of 56

03152-081

AD9786

RECEIVED CHANNEL

DATADJ[3:0]

DAC CLOCK

DATA RATE CLOCK

LOCAL CHANNEL

DATA RATE CLOCK

0000 00011111

–1 +1

Figure 82. Local Channel Data Rate Clock Synchronized with Offset

03152-082

STATE 2 3 4 5 6 7 8 9 10 11 12 13 4 1510

DECODE 0 0 0 0 0 –1 0 0 0 0 01 1/ 2 –1/ 2 –1/ 2 –1/ 2

fs/8 12345670
fs/4 1 2 30
fs/2

0 1

Figure 83. Digital Modulator State Machine Decode

MODADJ[2:0]

DAC CLOCK

STATE

MACHINE

MODULATOR

COEFFICIENT

STATE MACHINE

CYCLE CLOCK

14150123 1501 15012

–1 0 1 0 –1 0 0 –1 0 1 0 –1 0

000 101010

Figure 84. Local Modulator Coefficient Synchronized with Offset

1

03152-083

03152-084

Rev. B | Page 43 of 56

AD9786

A

X

OPERATING THE AD9786 REV. F EVALUATION BOARD

This section provides information to power up the board and
verify correct operation; a description of more advanced modes
of operation has been omitted.

POWER SUPPLIES

The AD9786 Rev. F evaluation board has five power supply
connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD,
CLKVDD, and DVDD, whereas the AD9786 has seven power
supply domains. To reconcile the power supply domains on the
chip with the power supply connectors on the evaluation board,
use Table 38.

Additionally, the DRVDD power supply on the AD9786 is used
to supply power for the digital input bus. DRVDD should be
run from 3.3 V. On the evaluation board, DRVDD is jumper­selectable by JP1, which is just to the left of the chip on the
evaluation board. With the jumper set to the 3.3 V position, the
DRVDD chip receives its power from VDD3IN.

CLK

CLKVDDS

C32

0.1μF

R23
115Ω

R4

90.9Ω

7

U2

MC100EPT22

1

2

CLKVDDS;8

PECL CLOCK DRIVER

The AD9786 system clock is driven from an external source via
Connector S1. The AD9786 evaluation board includes an
ON Semiconductor® MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CLKVDD power connector
or 3.3 V from the VDD3IN power connector. This setting is
done via Jumper JP2, situated next to the CLKVDD power
connector, and by setting Input Bias Resistor R23 and Input
Bias Resistor R4 on the evaluation board. The factory default is
for the PECL driver to be powered from CLKVDD at 2.5 V
(R23 = 90.9 Ω, R4 = 115 Ω). To operate the PECL driver with
a 3.3 V supply, R23 must be replaced with a 115 Ω resistor; R4
must be replaced with a 90.9 Ω resistor; and the position of JP2
must be changed. The schematic of the PECL driver section of
the evaluation board is shown in Figure 85. A low jitter sine
wave should be used as the clock source. Care must be taken to
ensure that the clock amplitude does not exceed the power
supply rails for the PECL driver.

COND;5

CLKVDDS

R5
50Ω

R6
50Ω

R7

50Ω

CLK+

CLK–

03152-085

Figure 85. PECL Driver on AD9786 Rev. F Evaluation Board

Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board

Nominal Power

Evaluation Board Label/PS Domain on Chip

Supply Voltage (V) Description

DVDD 2.5 SPI port
CLKVDD 2.5 Clock circuitry
ACVDD/ADVDD 2.5 Analog circuitry containing clock and digital interface circuitry
AVDD2 3.3 Switching analog circuitry
AVDD1 3.3 Analog output circuitry

Rev. B | Page 44 of 56

AD9786

DATA INPUTS

Digital data inputs to the AD9786 are accessed on the evaluation
board through Connector J1 and Connector J2. These are 40-pin,
right-angle connectors that are intended to be used with standard
ribbon cable connectors. The input level should be 3.3 V. The
data format is selectable through Register 0x02, Bit 7 (DATAFMT).
With this bit set to a default 0, the AD9786 assumes that the input
data is in twos complement format. With this bit set to 1, data
should be input in offset binary format.

When the evaluation board is first powered up and the clock
and data are running, it is recommended that the proper operating
current be verified. Press Reset Switch SW1 to ensure that the
AD9786 is in default mode. The default mode for the AD9786 is
for the interpolation set to 1×. The modulator is turned off in
default mode. The nominal operating currents for the evaluation
board in the power-up default mode are shown in Table 39.

Table 39. Nominal Operating Currents in Power-Up Default
Mode

Nominal Current @ Speed (mA)

Evaluation Board
Power Supply

50
MSPS

100
MSPS

150
MSPS

200
MSPS

DVDD 26 49 74 99
CLKVDD 78 83 87 92
ACVDD/ADVDD 1 4 6 8
AVDD1 30 30 30 30
AVDD2 27 27 27 27

Table 40. SPI Registers

Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 0

0x01 INTERP[1] INTERP[0]

SERIAL PORT

SW1 is a hard reset switch that sets the AD9786 to its default
state. It should be used every time the AD9786 power supply is
cycled, the clock is interrupted, or new data is to be written via
the SPI port. Set the SPI software to read back data from the
AD9786, and then verify that the expected values are read back
when the software is run.

ANALOG OUTPUT

The analog output of the AD9786 is accessed via Connector S3.
Once all settings are selected and the current levels and SPI port
functionality are verified, the analog signal at S3 can be viewed.
For most of the AD9786 applications, a spectrum analyzer is the
preferred instrument to verify proper performance. A typical
spectral plot is shown in Figure 86, with the AD9786 synthesizing
a two-tone signal in the default mode with a 200 MSPS sample
rate. A single-tone CW signal should provide output power of
approximately +0.5 dBm to the spectrum analyzer.

If the spectrum does not look correct at this point, the data
input might be violating setup and hold times with respect to
the input clock. To correct this, the user should vary the input
data timing. If this is not possible, SPI Register 0x02, Bit 4
(DCLKPOL), can be inverted. This bit controls the clock edge
upon which the data is latched. If neither of these methods corrects
the spectrum, it is unlikely that the issue is timing related. In this
case, verify that all instructions have been followed correctly and
that the SPI port readback indicates the correct values.

–10
–20
–30
–40
–50
–60
–70
–80

–90
–100
–110
–120

REF LVL

0

1AVG

0dBm

MARKER 1 [T1]

–84.96dBm VBW

193.00170300MHz

Figure 86. Typical Spectral Plot

RBW

SWT

30kHz
30kHz

560ms

RF ATT

UNIT

STOP 200MHzSTART 100MHz 19.9MHz/

20dB

dBm

A

1MA

03152-086

Rev. B | Page 45 of 56

AD9786

CGND; 5

4

CLK+

3

MC100EPT22

CLK–

R7

50Ω

R5

50Ω

R6

50Ω

CLKVDDS; 8

U2

6

6.3V

C28

4.7μF

+

AVD3

JP30

L11

ADVDD

L12

FERRITE

JP33

ACVDD

C76

C75

FERRITE

TP12

CLKVDDS

0.1μF

0.1μF

BLK

R23

DVDD

JP34

CGND; 5

1

MC100EPT22

U2

7

90.9Ω

C32

0.1μF

ACLKX

AVDD2

3

2

JP1

AB

1

DVDD

VDD

CLKVDDS; 8

2

JP36

TP16

R4

BLK

115Ω

DRVDD

DVDDS

CLKVDDS

JP9

AVDD2

C35

0.1μF

L13

L14

VAL

JP7

JP8

JP6

CLKVDDS

C34

0.1μF

L6

FERRITE

+

16V

C29

22μF

A

B

3

1

2

JP2

AVDD

AVD2

TP3

BLK

JP10

TP5

BLK

TP35

BLK BLKBLKBLKBLKBLKBLK

TP36

L7

L10

VAL

VAL

VAL

TP30 TP31 TP32 TP33 TP34

CLKVDD

JP5

TP7

CVD

BLK

AVD1

TP4

SMAEDGE

RED

L2

FERRITE

1

S10

C68

0.1μF

C64

22μF

16V

+

3.3VQ

AGND; 3,4,5

2

CLKVDD_IN

TP6

SMAEDGE

RED

L1

FERRITE

CGND;3,4,5

S11

C69

C63

+

2.5VQ

0.1μF

22μF

POWER INPUT FILTERS

16V

03152-087

C67

RED

S9

FERRITE

C65

22μF

+

3.3V

AGND2; 3,4,5

0.1μF

16V

AVDD_IN

C47

0.1μF

TP1

RED

L8

FERRITE

C45

22μF

16V

+

2.5V

AGND2; 3,4,5

S7

SMAEDGE

ADVDD2_IN

DVDD_IN

TP13

L9

SMAEDGE

RED

S5

C48

FERRITE

C46

+

2.5VN

DGND; 3,4,5

0.1μF

TP18

BLK

TP2

TP17

BLK

22μF

16V

L3

SMAEDGE

ADVDD3_IN

Figure 87. Power Supply Distribution, Rev. F Evaluation Board

Rev. B | Page 46 of 56

AD9786

AVDD2

AVDD

S3

R42

49.9Ω

OUT1

P

IOUTB

T3

C66
+

ACOM1P21

AGND; 3,4,5

S

ADTL1-12

46

10μF

6.3V

ACVDD

AVDD1P1

ACOM2P2

3

1
PS

T2B

NC = 5

C3

10μF

6.3V

+

TP8

C15

0.1μF

C17

0.1μF

AVDD2P2

ACVDDP2

ACCOM2P2

WHT

TP11

WHT

DNC1

FSADJ

ADVDDP2

ADCOMP2

4

TP10

5

WHT

REFIO

R8

+

RESET

RESET

TTWB-1-B

6

2kΩ

0.01%

C16

0.1μF

C30

10V

SPCSB

SPI_CSB

C61

0.001μF

C18

0.001μF

C4

0.1μF

C62

0.1μF

C55

0.001μF

C20

0.001μF

C49

0.1μF

807978777675747372717069686766656463626160595857565554535251504948474645444342

DNC2

ADVDD

ADVDDP1

R10

49.9ΩR949.9Ω

31

C2

10μF

6.3V

+

C14

0.1μF

C19

0.1μF

IOUTA

AVDD1P2

AVDD2P1

ACVDDP1

ACOM2P1

ACCOMP1

ACOM1P11

ACOM2P12

BLK

TP29

AGND; 3,4,5

S8

DVDD

C5

10μF

6.3V

+

C21

0.001μF

C38

0.1μF

10μF

SPCLK

SPSDI

SPSDO

BD00

SP-SDI

SP-CLK

SP-SDO

DVDD6

DCOM6

P2B0LSB

BD03

BD02

BD01

P2B1

P2B2

P2B3

DRVDD

2

1

SW1

4

3

FLOAT; 5

RESET

DVDD

6.3V

C6

10μF

+

C22

0.001μF

C37

0.1μF

BD04

BD05

P2B4

P2B5

DVDD5

DCOM5

BD08

BD07

BD06

41

P2B6

P2B7

P2B8

U1

AD9786BTSP

LPF

123

5

6

CLKCOM1

CLKVDD2

R1

50Ω

T1

4

CLKVDD1

123456789

C27

1pF

C42

0.1μF

C11

0.1μF

C12

0.1μF

C1

10μF

CLKVDD

R3

10kΩ

R2

10kΩ

6.3V

+

CLKVDD

JP22

C13

0.1μF

TP15

WHT

JP23

T1-1T

CLKCOM2

S1

ACLKX

DCOM1

CLK– CLK+

DVDD

CGND; 3,4,5

DVDD1

P1B12

P1B13

P1B14

P1B15MSB

10111213141516171819202122232425262728293031323334353637383940

AD12

AD13

AD14

AD15

C40

0.1μF

C26

0.001μF

C10

10μF

6.3V

+

DCOM2

DVDD2

P1B10

P1B11

AD11

AD10

DRVDD

DVDD

P1B8

P1B9

AD08

AD09

C41

0.1μF

C25

C9

10μF

+

C33

0.1μF

C54

C31

10μF

+

0.001μF

0.001μF

P1B7

AD07

6.3V

6.3V

P1B5

P1B6

AD05

AD06

DCOM3

DVDD3

P1B2

P1B3

P1B4

AD02

AD03

AD04

C39

0.1μF

C24

C8

10μF

+

DVDD

S2

WHT

TP14

DCLK-PLLL

DRVDD1

P1B0LSB

P1B1

AD00

AD01

0.001μF

6.3V

DATACLK

DGND; 3,4,5

P2B15MSB-IQSEL

BD14

3

BD15

P2B14-OPCLK

A

JP28

P2B13

BD13

2

DCOM4

B

DVDD4

DVDD

JP27

1

OPCLK_3

P2B10

P2B11

P2B12

BD12

S6

P2B9

BD11

BD09

BD10

C36

0.1μF

C23

0.001μF

C7

10μF

6.3V

+

S4

OPCLK

OPCLK

IQ

DGND; 3,4,5

03152-088

CLK+

CLK–

Figure 88. AD9786 Local Circuitry, Rev. F Evaluation Board

Rev. B | Page 47 of 56

AD9786

R30

DATA-A

AX15

AX14

AX13

AX12

100

100

100

100

R26

R27

R28

R29

Ω

Ω

100

R31

100

Ω

R32

100

Ω

R33

100

Ω

AX08

Ω

AX09

Ω

AX10

Ω

AX11

JP3

JP12

R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

RP5

DNP

RCOM

21 34567891021 345678910

RP7
DNP

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

RIBBON

AX15

1

AX14

3

AX13

5

AX12

7

AX11

9

AX10

11

AX09

13

AX08

15

AX07

17

AX06

19

AX05

21

AX04

23

AX03

25

AX02

27

AX01

29

AX00

31
33
35
37
39

J1

AX07

AX06

AX05

AX04

100

100

100

100

R38

R39

R40

R34

21 345678910

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

R44

100

Ω

R43

100

Ω

R41

100

Ω

R46

100

AX00

Ω

AX01

Ω

AX02

Ω

AX03

Ω

Ω

RP1 22

116

RP1 22

215

RP1 22

314

RP1 22

413

RP1 22

512

RP1 22

611

RP1 22

710

RP1 22

89

RP2 22

116

RP2 22

215

RP2 22

314

RP2 22

413

RP2 22

512

RP2 22

611

RP2 22

710

RP2 22

89

RP6

DNP

21 345678910

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

JP21

JP19

AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00

RP8
DNP

03152-089

Figure 89. Digital Data Port A Input Terminations, Rev. F Evaluation Board

Rev. B | Page 48 of 56

AD9786

R57

R62

Ω

Ω

100

DATA-B

BX15

BX14

BX13

BX12

100

R61

100

R60

100

R64

100

R58

100

Ω

R59

100

Ω

R63

100

Ω

Ω

Ω

Ω

RCOM

BX08

BX09

BX10

BX11

RP12

DNP

JP26

JP31

R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

21 34567891021 345678910

RP9

DNP

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

RIBBON

BX15

1

BX14

3

BX13

5

BX12

7

BX11

9

BX10

11

BX09

13

BX08

15

BX07

17

BX06

19

BX05

21

BX04

23

BX03

25

BX02

27

BX01

29

BX00

31
33

SDO

35

CLK

37

SDI

39

CSB

J2

BX07

BX06

BX05

BX04

R55

100

R54

100

R53

100

R56

100

21 345678910

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

R51

100

Ω

R49

100

Ω

R47

100

Ω

R52

100

BX00

Ω

BX01

Ω

BX02

Ω

BX03

Ω

Ω

RP3 22

116

RP3 22

215

RP3 22

314

RP3 22

413

RP3 22

512

RP3 22

611

RP3 22

710

RP3 22

89

RP4 22

116

RP4 22

215

RP4 22

314

RP4 22

413

RP4 22

512

RP4 22

611

RP4 22

710

RP4 22

89

RP11

DNP

21 345678910

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

JP25

JP24

BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
BD05
BD04
BD03
BD02
BD01
BD00

RP10

DNP

03152-090

Figure 90. Digital Data Port B Input Terminations, Rev. F Evaluation Board

Rev. B | Page 49 of 56

AD9786

DVDDS

C52

OPCLK

3

J

1

CLK

2

K

74LCX112
U7

11

J

13

CLK

12

K

74LCX112
U7

15

10

14

4
PRE

CLR

PRE

CLR

5

Q

6

Q_

DGND;8
DVDDS;16

9

Q

7

Q_

DGND;8
DVDDS;16

SPCSB

SPCLK

SPSDI

SPSDO

+

4.7μF

OPCLK_3

R21

10kΩ

6.3V

R20
10kΩ

Figure 91. SPI and One-Port Clock Circuitry, Rev. F Evaluation Board

C53

0.1μF

U5

21

74AC14

U5

4

74AC14

U5

6

74AC14

U6

12

U6

3

U6

5

3

5

74AC14

4

74AC14

6

74AC14

12 13

74AC14

10

74AC14

8

74AC14

13 12

11

9

U5

U5

11

U5

9

U6

74AC14

U6

10

74AC14

U6

8

74AC14

R50
9kΩ

R48
9kΩ

R45
9kΩ

DVDDS

++

C43

4.7μF

6.3V

C50

0.1μF

C44

4.7μF

6.3V

C51

0.1μF

SPI PORT

P1

1
2
3
4
5
6

03152-091

Rev. B | Page 50 of 56

AD9786

Figure 92. PCB Assembly, Primary Side, Rev. F Evaluation Board

03152-092

Figure 93. PCB Assembly, Secondary Side, Rev. F Evaluation Board

Rev. B | Page 51 of 56

03152-093

AD9786

03152-094

Figure 94. PCB Assembly, Layer 1 Metal, Rev. F Evaluation Board

Figure 95. PCB Assembly, Layer 6 Metal, Rev. F Evaluation Board

03152-095

Rev. B | Page 52 of 56

AD9786

03152-096

Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane),Rev. F Evaluation Board

Figure 97. PCB Assembly, Layer 3 Metal (Power Plane),Rev. F Evaluation Board

03152-097

Rev. B | Page 53 of 56

AD9786

03152-098

Figure 98. PCB Assembly, Layer 4 Metal (Power Plane), Rev. F Evaluation Board

Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane), Rev. F Evaluation Board

03152-099

Rev. B | Page 54 of 56

AD9786

OUTLINE DIMENSIONS

14.20

0.75

0.60

0.45

1.20
MAX

14.00 SQ

13.80

1

PIN 1

12.20

12.00 SQ

11.80

6180

61 80

60

60

1

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0° MIN

0.08 MAX
COPLANARITY

0.20

0.09
7°

3.5°
0°

TOP VIEW

(PINS DOWN)

20

21

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD

41

41

40 40

LEAD PITCH

0.50 BSC

EXPOSED

PAD

BOTTOM VIEW

(PINS UP)

0.27

0.22

0.17

6.00

BSC SQ

20

21

Figure 100. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-80-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option
AD9786BSV −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786BSVRL −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786BSVZ1 −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786BSVZRL1 −40°C to +85°C 80-Lead TQFP_EP SV-80-1
AD9786-EB Evaluation Board

1

Z = Pb-free part.

Rev. B | Page 55 of 56

AD9786

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03152-0-10/05(B)

Rev. B | Page 56 of 56