Datasheet AD9777EB, AD9777BSV Datasheet (Analog Devices)

16-Bit, 160 MSPS 2/4/8

Interpolating Dual TxDAC+

D/A Converter

FEATURES 16-Bit Resolution, 160/400 MSPS Input/Output Data Rate Selectable 2/4/8 Interpolating Filter Programmable Channel Gain and Offset Adjustment

/4, fS/8 Digital Quadrature Modulation

Capability Direct IF Transmission Mode for 70 MHz + IFs Enables Image Rejection Architecture Fully Compatible SPI Port Excellent AC Performance

SFDR –73 dBc @ 2 MHz–35 MHz

WCDMA ACPR 71 dB @ IF = 71 MHz Internal PLL Clock Multiplier Selectable Internal Clock Divider Versatile Clock Input

Differential/Single-Ended Sine Wave or

TTL/CMOS/LVPECL Compatible Versatile Input Data Interface

Two’s Complement/Straight Binary Data Coding

Dual-Port or Single-Port Interleaved Input Data Single 3.3 V Supply Operation Power Dissipation: Typical 1.2 W @ 3.3 V On-Chip 1.2 V Reference 80-Lead Thermally Enhanced TQFP Package

AD9777

APPLICATIONS Communications

Analog Quadrature Modulation Architectures 3G, Multicarrier GSM, TDMA, CDMA Systems Broadband Wireless, Point-to-Point Microwave Radios Instrumentation/ATE

GENERAL DESCRIPTION

The AD9777 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) providing a high level of programmability, thus allowing for enhanced system level options. These options include: selectable 2×/4×/8× interpolation filters; f

/2, fS/4, or fS/8 digital quadrature

modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or two’s complement data interface; and a single-port or dual-port data interface.

The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression

(continued on page 2)

FUNCTIONAL BLOCK DIAGRAM

AD9777

HALF-

HALFBAND

***

FILTER 2

1616

LATCH

FILTER 1

DATA

ASSEMBLER

I AND Q

NONINTERLEAVED

INTERLEAVED

DATA

WRITE

SELECT

TxDAC+ is a registered trademark of Analog Devices, Inc. *Protected by U.S. Patent Numbers, 5568145, 5689257, and 5703519. Other patents pending.

MUX

CONTROL

CLOCK OUT

SPI INTERFACE AND

CONTROL REGISTERS

HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR "ZERO STUFFING ONLY"

BAND

FILTER 3

HALFBAND

FILTER

BYPASS

MUX

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

COS

SIN

/2, 4, 8

DAC

SIN

COS

(

)

DAC

PRESCALER

PHASE DETECTOR

AND VCO

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

GAIN DAC

VREF

IDAC

GAIN/OFFSET

REGISTERS

IDAC

OFFSET

I/Q DAC

DIFFERENTIAL CLK

DAC

OUT

IOFFSET

AD9777

(continued from page 1)

errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.

The AD9777 features the ability to perform f digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9777 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (i.e., the Direct IF Mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.

The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or two’s complement formats and supports single-port interleaved or dual-port data.

Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9777 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.

Targeted at wide dynamic range, multicarrier and multistandard systems, the superb baseband performance of the AD9777 is ideal for wideband CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high order QAM modulation schemes. The image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.

/2, fS/4, and fS/8

PRODUCT HIGHLIGHTS

1. The AD9777 is the 16-bit member of the AD977x pin-

compatible, high performance, programmable 2× /4×/8× interpolating TxDAC+ family.

2. Direct IF transmission is possible for 70 MHz + IFs through a novel digital mixing process.

3. f

/2, fS/4, and fS/8 digital quadrature modulation and

user-selectable image rejection simplify/remove cascaded SAW filter stages.

4. A 2×/4×/8× user-selectable interpolating filter eases data rate and output signal reconstruction filter requirements.

5. User-selectable two’s complement/straight binary data coding.

6. User programmable channel gain control over 1 dB range in 0.01 dB increments.

7. User-programmable channel offset control ±10% over the FSR.

8. Ultra high speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for easy interfacing.

10. Flexible clock input with single-ended or differential input, CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: Complete CMOS DAC operates on 1.2 W from a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation, and several sleep functions are provided to reduce power during idle periods.

12. On-chip voltage reference: The AD9777 includes a 1.20 V temperature compensated band gap voltage reference.

13. 80-lead thermally enhanced TQFP.

REV. 0–2–

AD9777

AD9777–SPECIFICATIONS

to T

DC SPECIFICATIONS

MIN

otherwise noted.)

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

Parameter Min Typ Max Unit

RESOLUTION 16 Bits DC Accuracy

Integral Nonlinearity ±6 LSB Differential Nonlinearity –6.5 ± 3 +6.5 LSB

ANALOG OUTPUT (for 1R and 2R Gain Setting Modes) Offset Error –0.025 ±0.01 +0.025 % of FSR

Gain Error (with Internal Reference) –1.0 +1.0 % of FSR Gain Matching –1 ±0.1 +1 % of FSR Full-Scale Output Current

220mA

Output Compliance Range –1.0 +1.25 V Output Resistance 200 kΩ Output Resistance 3 pF Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V Reference Output Current

100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V Reference Input Resistance (REFLO = 3 V) 10 MΩ Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C Gain Drift (With Internal Reference) 50 ppm of FSR/°C Reference Voltage Drift ppm/°C

POWER SUPPLY

AVDD

Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I

in SLEEP Mode 23.3 26 mA

AVDD

)

72.5 76 mA

CLKVDD (PLL OFF)

Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

CLKVDD

)

8.5 mA

CLKVDD (PLL ON)

Clock Supply Current (I

)23.5mA

CLKVDD

DVDD

Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I Nominal Power Dissipation

DIS

in PWDN 6.0 mW

DIS

DVDD

)

34 41 mA 380 410 mW

1.75 W

Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

Measured at I

Nominal full-scale current, I

Use an external amplifier to drive any external load.

100 MSPS f

400 MSPS f

Specifications subject to change without notice.

driving a virtual ground.

DAC

OUTA

with f , f

DATA

OUTFS

= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

OUT

= 50 MSPS, fS/2 modulation, PLL enabled.

, is 32× the I

current.

REF

= 20 mA, unless

OUTFS

REV. 0

–3–

AD9777

to T

MIN

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I

MAX

Interpolation = 2, Differential Transformer Coupled Output, 50  Doubly Terminated,

DYNAMIC SPECIFICATIONS

unless otherwise noted.)

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f Output Settling Time (t

) (to 0.025%) 11 ns

) 400 MSPS

DAC

Output Rise Time (10% to 90%)* 0.8 ns Output Fall Time (10% to 90%)* 0.8 ns Output Noise (I

= 20 mA) 50 pA√Hz

OUTFS

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

= 100 MSPS, f

DATA

= 65 MSPS, f

DATA

= 65 MSPS, f

DATA

= 78 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 160 MSPS, f

DATA

= 1 MHz 71 85 dBc

OUT

= 1 MHz 85 dBc

OUT

= 15 MHz 84 dBc

OUT

= 1 MHz 85 dBc

OUT

= 15 MHz 83 dBc

OUT

= 1 MHz 85 dBc

OUT

= 15 MHz 83 dBc

OUT

= 0 dBFS)

OUT

Spurious-Free Dynamic Range within a 1 MHz Window

= 0 dBFS, f

OUT

Two-Tone Intermodulation (IMD) to Nyquist (f

= 65 MSPS, f

DATA

= 65 MSPS, f

DATA

= 78 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 160 MSPS, f

DATA

= 100 MSPS, f

DATA

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 1 MHz) 73 99.1

OUT

= 11 MHz 85 dBc

OUT2

= 21 MHz 78 dBc

OUT2

= 11 MHz 85 dBc

OUT2

= 21 MHz 78 dBc

OUT2

OUT1

= f

= –6 dBFS)

OUT2

= 11 MHz 85 dBc = 21 MHz 84 dBc

Total Harmonic Distortion (THD)

= 100 MSPS, f

DATA

= 1 MHz; 0 dBFS –71 –83 dB

OUT

Signal-to-Noise Ratio (SNR)

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 5 MHz; 0 dBFS 79 dB

OUT

= 5 MHz; 0 dBFS 75 dB

OUT

Adjacent Channel Power Ratio (ACLR)

WCDMA with MHz BW, MHz Channel Spacing IF = Baseband, f IF = 19.2 MHz, f

= 76.8 MSPS 77 dBc

DATA

= 76.8 MSPS 73 dBc

DATA

Four-Tone Intermodulation

21 MHz, 22 MHz, 23 MHz, and 24 MHz at –12 dBFS 76 dBFS (f

= MSPS, Missing Center)

DATA

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

201 MHz, 202 MHz, 203 MHz, and 204 MHz at –12 dBFS 72 dBFS (f

= 160 MSPS, f

DATA

*Measured single ended into 50 Ω load.

Specifications subject to change without notice.

= 320 MHz)

DAC

OUTFS

= 20 mA,

REV. 0–4–

AD9777

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

DIGITAL SPECIFICATIONS

MIN

otherwise noted.)

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic “1” Voltage 2.1 3 V Logic “0” Voltage 0 0.9 V Logic “1” Current –10 +10 µA Logic “0” Current –10 +10 µA Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect to Min Max Unit

AVDD, DVDD, CLKVDD AGND, DGND, CLKGND –0.3 +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD –4.0 +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND –0.3 +0.3 V REFIO, REFLO, FSADJ1/2 AGND –0.3 AVDD + 0.3 V I

OUTA

, I

OUTB

AGND –1.0 AVDD + 0.3 V P1B15–P1B0, P2B15–P2B0 DGND –0.3 DVDD + 0.3 V DATACLK, PLL_LOCK DGND –0.3 DVDD + 0.3 V CLK+, CLK–, RESET CLKGND –0.3 CLKVDD + 0.3 V LPF CLKGND –0.3 CLKVDD + 0.3 V SPI_CSB, SPI_CLK, DGND –0.3 DVDD + 0.3 V SPI_SDIO, SPI_SDO Junction Temperature +125 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) +300 °C

= 20 mA, unless

OUTFS

*Stresses above those listed under the ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9777BSV –40°C to +85°C 80-Lead TQFP SV-80

THERMAL CHARACTERISTICS

Thermal Resistance

80-Lead Thermally Enhanced TQFP Package ␪

*With thermal pad soldered to PCB.

= 23.5 °C/W*

AD9777EB Evaluation Board

*SV = Thin Plastic Quad Flatpack

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9777 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD9777

CLKVDD

LPF

CLKVDD

CLKGND

CLK+

CLK–

CLKGND

DATACLK/PLL_LOCK

DGND

DVDD

P1B15 (MSB)

P1B14

P1B13

P1B12

P1B11

P1B10

DGND

DVDD

P1B9

P1B8

PIN CONFIGURATION

OUTA2

AGND

P1B0 (LSB)

OUTB2

AGND

P2B12

P2B13

AGND

AVDD

DVDD

DGND

AVDD

AGND

AVDD

AGND

AVDD

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

PIN 1

IDENTIFIER

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P1B7

P1B6

P1B5

P1B4

DGND

AGND

P1B3

DVDD

AD9777

TxDAC+

TOP VIEW

(Not to Scale)

P1B2

P1B1

OUTB1

OUTA1

AGND

AVDD

P2B11

P2B10

AGND

P2B9

AVDD

P2B8

FSADJ1

FSADJ2

REFIO

RESET

SPI_CSB

SPI_CLK

SPI_SDIO

SPI_SDO

DGND

DVDD

P2B0 (LSB)

P2B1

P2B2

P2B3

P2B4

P2B5

DGND

DVDD

P2B6

P2B7

IQSEL/P2B15 (MSB)

ONEPORTCLK/P2B14

REV. 0–6–

AD9777

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Description

1, 3 CLKVDD Clock Supply Voltage 2 LPF PLL Loop Filter 4, 7 CLKGND Clock Supply Common 5 CLK+ Differential Clock Input 6 CLK– Differential Clock Input 8 DATACLK/PLL_LOCK With the PLL enabled, this pin indicates the state of the PLL. A read of a

Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at

the input data rate. 9, 17, 25, 35, 44, 52 DGND Digital Common 10, 18, 26, 36, 43, 51 DVDD Digital Supply Voltage 11–16, 19–24, 27–30 P1B15 (MSB) to P1B0 (LSB) Port “1” Data Inputs 31 IQSEL/P2B15 (MSB) In “1” port mode, IQSEL = 1 followed by a rising edge of the differential

input clock will latch the data into the I channel input register. IQSEL = 0

will latch the data into the Q channel input register. In “2” port mode, this

pin becomes the port “2” MSB. 32 ONEPORTCLK/P2B14 With the PLL disabled and the AD9777 in “1” port mode, this pin becomes

a clock output that runs at twice the input data rate of the I and Q channels.

This allows the AD9777 to accept and demux interleaved I and Q data to

the I and Q input registers. 33, 34, 37–42, 45–50 P2B13 to P2B0 (LSB) Port “2” Data Inputs 53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO

becomes an output, SDO enters a High-Z state. 54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register

Address 00h. The default setting for this bit is “0,” which sets SDIO as an input. 55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK.

Data output on the SPI port is registered on the falling edge. 56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets

SPI port logic and initializes instruction cycle. 57 RESET Logic “1” resets all of the SPI port registers, including Address 00h, to their

default values. A software reset can also be done by writing a Logic “1” to

SPI Register 00h, Bit 5. However, the software reset has no effect on the bits

in Address 00h. 58 REFIO Reference Output, 1.2 V Nominal 59 FSADJ2 Full-Scale Current Adjust, Q Channel 60 FSADJ1 Full-Scale Current Adjust, I Channel 61, 63, 65, 76, 78, 80 AVDD Analog Supply Voltage 62, 64, 66, 67, 70, 71, AGND Analog Common

74, 75, 77, 79 68, 69 I 72, 73 I

OUTA2

OUTA1

, I , I

OUTB2

OUTB1

Differential DAC Current Outputs, Q Channel

Differential DAC Current Outputs, I Channel

REV. 0

–7–

AD9777

DIGITAL FILTER SPECIFICATIONS

Half-Band Filter No. 1 (43 Coefficients)

Tap Coefficient

1, 43 8 2, 42 0 3, 41 –29 4, 40 0 5, 39 67 6, 38 0 7, 37 –134 8, 36 0 9, 35 244 10, 34 0 11, 33 –414 12, 32 0 13, 31 673 14, 30 0 15, 29 –1079 16, 28 0 17, 27 1772 18, 26 0 19, 25 –3280 20, 24 0 21, 23 10364 22 16384

–20

–40

–60

–80

ATTENUATION – dBFS

–100

–120

0 0.5

– Normalized to Input Data Rate

OUT

1.0 1.5 2.0

Figure 1a. 2 Interpolating Filter Response

–20

–40

–60

–80

ATTENUATION – dBFS

Half-Band Filter No. 2 (19 Coefficients)

Tap Coefficient

1, 19 19 2, 18 0 3, 17 –120 4, 16 0 5, 15 438 6, 14 0 7, 13 –1288 8, 12 0 9, 11 5047 10 8192

Half-Band Filter No. 3 (11 Coefficients)

Tap Coefficient

1, 11 7 2, 10 0 3, 9 –53 4, 8 0 5, 7 302 6 512

–100

–120

0 0.5

– Normalized to Input Data Rate

OUT

1.0 1.5 2.0

Figure 1b. 4 Interpolating Filter Response

–20

–40

–60

–80

ATTENUATION – dBFS

–100

–120

– Normalized to Input Data Rate

OUT

468

Figure 1c. 8 Interpolating Filter Response

REV. 0–8–

AD9777

DEFINITIONS OF SPECIFICATIONS Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Complex Modulation

The process of passing the real and imaginary components of a signal through a complex modulator (transfer function = e

j␻t

cos␻t + jsin␻t) and realizing real and imaginary components on the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to “1,” minus the output when all inputs are set to “0.”

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV–S.

Group Delay

Number of input clocks between an impulse applied at the device input and peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range.

Impulse Response

Response of the device to an impulse applied to the input.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

(interpolation rate), a digital filter can be constructed that has a

DATA

sharp transition band near f appear around f

Linearity Error (Also Called Integral Nonlinearity or INL)

(output data rate) can be greatly suppressed.

DAC

/2. Images that would typically

DATA

Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.

Monotonicity

A D/A converter is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of “0” is called offset error. For I inputs are all “0.” For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to “1.”

Output Compliance Range

The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Pass Band

Frequency band in which any input applied therein passes unattenuated to the DAC output.

Power Supply Rejection

The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Settling Time

The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.

Temperature Drift

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).

REV. 0

–9–

AD9777

–Typical Performance Characteristics

(T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I Doubly Terminated, unless otherwise noted.)

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

65 130

FREQUENCY – MHz

TPC 1. Single-Tone Spectrum @ f f

= f

OUT

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

= 65 MSPS with

DATA

50 150

FREQUENCY – MHz

100

TPC 4. Single-Tone Spectrum @ f

= f

OUT

= 78 MSPS with

DATA

SFDR – dBc

= 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 

OUTFS

0dBFS

–6dBFS

–12dBFS

FREQUENCY – MHz

15 255

20 30

TPC 2. In-Band SFDR vs. f @ f

DATA

–12dBFS

= 65 MSPS

0dBFS

–6dBFS

FREQUENCY – MHz

15 255

20 30

TPC 5. In-Band SFDR vs. f @ f

= 78 MSPS

DATA

OUT

0dBFS

SFDR – dBc

–6dBFS

–12dBFS

15 255

FREQUENCY – MHz

TPC 3. Out-of-Band SFDR vs. f

OUT

–6dBFS

SFDR – dBc

@ f

0dBFS

= 65 MSPS

DATA

–12dBFS

15 255

FREQUENCY – MHz

TPC 6. Out-of-Band SFDR vs. f

OUT

@ f

= 78 MSPS

DATA

20 30

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

100 300 FREQUENCY – MHz

200

TPC 7. Single-Tone Spectrum @ f with f

OUT

= 160 MSPS

DATA

= f

DATA

–12dBFS

SFDR – dBc

0dBFS

–6dBFS

20 30

FREQUENCY – MHz

TPC 8. In-Band SFDR vs. f @ f

= 160 MSPS

DATA

40 50

OUT

SFDR – dBc

–12dBFS

0dBFS

–6dBFS

20 30

FREQUENCY – MHz

TPC 9. Out-of-Band SFDR vs. f

OUT

@ f

= 160 MSPS

DATA

40 50

REV. 0–10–

AD9777

(T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I Doubly Terminated, unless otherwise noted.)

IMD – dBc

–3dBFS

0dBFS

–6dBFS

15 255

FREQUENCY – MHz

20 30

TPC 10. Third Order IMD Products vs. Two-Tone f

IMD – dBc

@ f

OUT

DATA

4

8

1

2

30 5010

FREQUENCY – MHz

= 65 MSPS

40 60

TPC 13. Third Order IMD Products vs. Two-Tone f

and Interpola-

OUT

tion Rate

⫻

DATA

= 160 MSPS, = 160 MSPS, = 80 MSPS, = 50 MSPS

1 2⫻ f 4⫻ f

⫻

IMD – dBc

TPC 11. Third Order IMD Products vs. Two-Tone f

IMD – dBc

TPC 14. Third Order IMD Products vs. Two-Tone A f

DATA

1⫻ f

DAC

⫻

DAC

4⫻ f

DAC

8⫻ f

DAC

= 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 

OUTFS

IMD – dBc

–3dBFS

–6dBFS

0dBFS

30 5010

FREQUENCY – MHz

–3dBFS

0dBFS

–6dBFS

15 255

FREQUENCY – MHz

20 30

TPC 12. Third Order IMD Products

–15

2

OUT

–10

@ f

OUT

DATA

– dBFS

= 78 MSPS

8

4

1

–5 0

vs. Two-Tone f

SFDR – dBc

OUT

@ f

DATA

0dBFS

–6dBFS

–12dBFS

AVDD – V

TPC 15. SFDR vs. AVDD @

and Interpolation Rate

OUT

= 50 MSPS for All Cases

= 10 MHz, f

OUT

= 160 MSPS

DATA

= 320 MSPS,

DAC

= 50 MSPS, = 100 MSPS, = 200 MSPS, = 400 MSPS

40 60

= 160 MSPS

3.43.33.23.1

3.5

IMD – dBc

0dBFS

–3dBFS

–6dBFS

3.43.33.23.1

AVDD – V

TPC 16. Third Order IMD Products vs. AVDD @ f f

= 320 MSPS, f

DAC

= 10 MHz,

OUT

DATA

= 160 MSPS

REV. 0

3.5

SNR – dB

050 150100

PLL OFF

PLL ON

INPUT DATA RATE – MSPS

TPC 17. SNR vs. Data Rate for

= 5 MHz

OUT

–11–

SFDR – dBc

–50 0 100

78MSPS

FDATA = 65MSPS

TEMPERATURE – C

160MSPS

TPC 18. SFDR vs. Temperature @

= f

DATA

/11

OUT

AD9777

(T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I Doubly Terminated, unless otherwise noted.)

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

050 150100

FREQUENCY – MHz

TPC 19. Single-Tone Spurious Performance, f f

= 150 MSPS, No Interpolation

DATA

–20

–40

–60

AMPLITUDE – dBm

–80

–100

515

010

= 10 MHz,

OUT

25 35

20 30

FREQUENCY – MHz

TPC 22. Two-Tone IMD Performance, f

= 90 MSPS, Interpolation = 4

DATA

⫻

–20

–40

–60

AMPLITUDE – dBm

–80

–100

TPC 20. Two-Tone IMD Performance, f No Interpolation

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

TPC 23. Single-Tone Spurious Performance, f f

DATA

= 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 

OUTFS

050

FREQUENCY – MHz

40302010

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

0 100 250150

FREQUENCY – MHz

TPC 21. Single-Tone Spurious

DATA

50 150

100 300200

FREQUENCY – MHz

= 150 MSPS,

250

Performance, f f

= 150 MSPS, Interpolation = 2

DATA

–20

–40

–60

AMPLITUDE – dBm

–80

–100

01525

= 10 MHz,

OUT

10 20

FREQUENCY – MHz

TPC 24. Two-Tone IMD Performance,

= 10 MHz,

OUT

= 80 MSPS, Interpolation = 4

⫻

= 10 MHz, f

OUT

Interpolation = 8

= 50 MSPS,

DATA

⫻

200

30050



–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

0 100 400200

FREQUENCY – MHz

300

TPC 25. Single-Tone Spurious Performance, f f

= 50 MSPS, Interpolation = 8

DATA

= 10 MHz,

OUT

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE – dBm

–80

–90

–100

020 8040

FREQUENCY – MHz

TPC 26. Eight-Tone IMD Performance, f

= 160 MSPS, Interpolation = 8

DATA

⫻

REV. 0–12–

AD9777

MODE CONTROL (VIA SPI PORT)

Table I. Mode Control via SPI Port

(Default Values Are Highlighted)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h SDIO LSB, MSB First Software Reset on Sleep Mode Power-Down Mode 1R/2R Mode PLL_LOCK

01h Filter Filter Modulation Modulation Mode 0 = No Zero Stuffing 1 = Real Mix Mode 0 = e

02h 0 = Signed Input 0 = Two Port Mode DATACLK Driver DATACLK Invert ONEPORTCLK Invert IQSEL Invert Q First

03h PLL Divide PLL Divide

04h 0 = PLL OFF 0 = Automatic PLL Charge Pump PLL Charge Pump PLL Charge Pump

05h IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain IDAC Fine Gain

06h IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain IDAC Coarse Gain

07h IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset IDAC Offset

08h IDAC I

09h QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain QDAC Fine Gain

0Ah QDAC Coarse QDAC Coarse QDAC Coarse QDAC Coarse

0Bh QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset QDAC Offset

0Ch QDAC I

0Dh Version Register Version Register Version Register Version Register

Bidirectional 0 = MSB Logic “1” Logic “1” shuts down Logic “1” shuts down DAC output current set Indicator 0 = Input 1 = LSB the DAC output all digital and analog by one or two external 1 = I/O currents. functions. resistors.

Interpolation Interpolation Mode (None, f Rate Rate (None, f (1×, 2×, 4×, 8×)(1×, 2×, 4×, 8×)f

Data 1 = One Port Mode Strength 0 = No Invert 0 = No Invert 0 = No Invert 0 = I First 1 = Unsigned 1 = Invert 1 = Invert 1 = Invert 1 = Q First

/2, Filters, Logic “1” Mix Mode Select

/4, fS/8) enables zero stuffing. 0 = PLLLOCK

/2, fS/4, fS/8) on Interpolation 0 = Complex 1 = e

0 = 2R, 1 = 1R

–j

+j␻

DATACLK/ PLL_LOCK

1 = DATACLK

(Prescaler) Ratio (Prescaler) Ratio

1 = PLL ON Charge Pump Control Control Control Control

1 = Programmable

Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment

Adjustment Adjustment Adjustment Adjustment

Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2

OFFSET

Direction Adjustment Bit 1 Adjustment Bit 0

0 = I

OFFSET

on I

OUTA

1 = I

OFFSET

OUTB

IDAC Offset IDAC Offset

Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment Adjustment

Gain Adjustment Gain Adjustment Gain Adjustment Gain Adjustment

Adjustment Bit 9 Adjustment Bit 8 Adjustment Bit 7 Adjustment Bit 6 Adjustment Bit 5 Adjustment Bit 4 Adjustment Bit 3 Adjustment Bit 2

OFFSET

Direction Adjustment Bit 1 Adjustment Bit 0

0 = I

OFFSET

on I

OUTA

1 = I

OFFSET

on I

OUTB

QDAC Offset QDAC Offset

REV. 0

–13–

AD9777

Bit 7 Logic “0” (default) causes the SDIO pin to act as

an input during the data transfer (Phase 2) of the communications cycle. When set to “1,” SDIO can act as an input or output, depending on Bit 7 of the instruction byte.

Bit 6 Logic “0” (default). Determines the direction

(LSB/MSB first) of the communications and data transfer communications cycles. Refer to the section MSB/LSB Transfers for a detailed description.

Bit 5 Writing a “1” to this bit resets the registers to their

default values and restarts the chip. The RESET bit always reads back “0.” Register Address 00h bits are not cleared by this software reset. However, a high level at the RESET pin forces all registers, including those in Address 00h, to their default state.

Bit 4 Sleep mode. A Logic “1” to this bit shuts down the

DAC output currents.

Bit 3 Power-Down. Logic “1” shuts down all analog

and digital functions except for the SPI port.

Bit 2 1R/2R Mode. The default (“0”) places the AD9777

in two resistor mode. In this mode, the I

REF

currents for the I and Q DAC references are set separately by the R

resistors on FSADJ1 and FSADJ2 (Pins

SET

60 and 59). In the 2R mode, assuming the coarse gain setting is full scale and the fine gain setting is “0,” I I

FULLSCALE1

FULLSCALE2

= 32 × V

/FSADJ2. With this bit set

REF

/FSADJ1 and

REF

to “1,” the reference currents for both I and Q DACs are controlled by a single resistor on Pin 60. I

FULLSCALE

in one resistor mode for both the I and Q DACs is half of what it would be in the 2R mode, assuming all other conditions (R

, register settings)

SET

remain unchanged. The full-scale current of each DAC can still be set to 20 mA by choosing a resistor of half the value of the R

value used in the 2R mode.

SET

Bit 1 PLL_LOCK Indicator. When the PLL is enabled,

reading this bit will give the status of the PLL. A Logic “1” indicates the PLL is locked. A Logic “0” indicates an unlocked state.

Address 01h

Bits 7, 6 Filter interpolation rate according to the follow-

ing table: 00 1×

01 2× 10 4× 11 8×

Bits 5, 4 Modulation mode according to the following table:

00 none 01 f

10 f

11 f

Bit 3 Logic “1” enables zero stuffing mode for interpola-

tion filters.

Bit 2 Default (“1”) enables the real mix mode. The I and

Q data channels are individually modulated by f

/4, or fS/8 after the interpolation filters. However,

/2,

no complex modulation is done. In the complex mix mode (Logic “0”), the digital modulators on the I and Q data channels are coupled to create a digital complex modulator. When the AD9777 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second IF frequency (i.e., the second IF frequency is the LO of the analog quadrature modulator external to the AD9777) according to the bit value of Register 01h, Bit 1.

Bit 1 Logic “0” (default) causes the complex modulation to

be of the form e

–j␻t

, resulting in the rejection of the higher frequency image when the AD9777 is used with an external quadrature modulator. A Logic “1” causes the modulation to be of the form e

+j␻t

, which

causes rejection of the lower frequency image.

Bit 0 In two port mode, a Logic “0” (default) causes Pin 8

to act as a lock indicator for the internal PLL. A Logic “1” in this register causes Pin 8 to act as a DATACLK, either generating or acting as an input clock (see Register 02h, Bit 3) at the input data rate of the AD9777.

Address 02h

Bit 7 Logic “0” (default) causes data to be accepted on

the inputs as two’s complement binary. Logic “1” causes data to be accepted as straight binary.

Bit 6 Logic “0” (default) places the AD9777 in two port

mode. I and Q data enters the AD9777 via Ports 1 and 2, respectively. A Logic “1” places the AD9777 in one port mode in which interleaved I and Q data is applied to Port 1. See the Pin Function Descriptions for DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK for detailed information on how to use these modes.

Bit 5 DATACLK Driver Strength. With the internal PLL

disabled and this bit set to Logic “0,” it is recommended that DATACLK be buffered. When this bit is set to Logic “1,” DATACLK acts as a stronger driver capable of driving small capacitive loads.

Bit 4 Default Logic “0.” A value of “1” inverts

DATACLK at Pin 8.

Bit 2 Default Logic “0.” A value of “1” inverts

ONEPORTCLK at Pin 32.

Bit 1 The default of Logic “0” causes IQSEL = 1 to

direct input data to the I channel, while IQSEL = 0 directs input data to the Q channel. A Logic “1” in this register inverts the sense of IQSEL.

Bit 0 The default of Logic “0” defines IQ pairing as IQ,

IQ... while programming a Logic “1” causes the pair ordering to be QI, QI...

REV. 0–14–

AD9777

Address 03h

Bits 1, 0 Setting this divide ratio to a higher number allows

the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run substantially slower. The divider ratio is set according to the following table:

00 ⫼1 01 ⫼2 10 ⫼4 11 ⫼8

Address 04h

Bit 7 Logic “0” (default) disables the internal PLL.

Logic “1” enables the PLL.

Bit 6 Logic “0” (default) sets the charge pump control to

automatic. In this mode, the charge pump bias current is controlled by the divider ratio defined in Address 03h, Bits 1 and 0. Logic “1” allows the user to manually define the charge pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the PLL.

Bits 2, 1, 0 With the charge pump control set to manual, these

bits define the charge pump bias current according to the following table:

000 50 µA 001 100 µA 010 200 µA 011 400 µA 100 800 µA

Address 05h, 09h

Bits 7–0 These bits represent an 8-bit binary number (Bit 7

MSB) that defines the fine gain adjustment of the I (05h) and Q (09h) DAC according to the equation given below.

Address 06h, 0Ah

Bits 3–0 These bits represent a 4-bit binary number (Bit 3

MSB) that defines the coarse gain adjustment of the I (06h) and Q (0Ah) DACs according to the equation below.

Address 07h, 0Bh

Bits 7–0

Address 08h, 0Ch

Bits 1, 0 The 10 bits from these two address pairs (07h, 08h

and 0Bh, 0Ch) represent a 10-bit binary number that defines the offset adjustment of the I and Q DACs according to the equation below (07h, 0Bh–Bit 7 MSB/08h, 0Ch–Bit 0 LSB).

Address 08h, 0Ch

Bit 7 This bit determines the direction of the offset of the

I (08h) and Q (0Ch) DACs. A Logic “0” will apply a positive offset current to I will apply a positive offset current to I

, while a Logic “1”

OUTA

OUTB

. The magnitude of the offset current is defined by the bits in Addresses 07h, 0Bh, 08h, 0Ch according to the formulas given below.





OUTA

OUTB

OFFSET REF

Equation 1 shows I mode, the current I

REF REF







 



REF REF









=×

OUTA

REF





COARSE













COARSE











OFFSET

 

1024

and I

OUTB





–













–









  

as a function of fine gain, coarse gain, and offset adjustment when using the 2R mode. In the 1R



 





32 256





 





32 256



is created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a













FINE DATA

FINE

1024



















































10242421

  

 



––DATA



 













 





scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.

(1)

REV. 0

–15–

AD9777

FUNCTIONAL DESCRIPTION

The AD9777 dual interpolating DAC consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9777 capable of 2×, 4×, or 8× interpolation. High speed input and output data rates can be achieved within the following limitations:

Interpolation Input Data DAC Sample Rate (MSPS) Rate (MSPS) Rate (MSPS)

1× 160 160 2× 160 320 4× 100 400 8× 50 400

Both data channels contain a digital modulator capable of mixing the data stream with an LO of f where f

is the output data rate of the DAC. A zero stuffing

DAC

/2, f

DAC

/4, or f

DAC

/8,

feature is also included and can be used to improve pass-band flatness for signals being attenuated by the SIN(x)/x characteristic of the DAC output. The speed of the AD9777, combined with its digital modulation capability, enables direct IF conversion architectures at 70 MHz and higher.

The digital modulators on the AD9777 can be coupled to form a complex modulator. By using this feature with an external analog quadrature modulator, such as the Analog Devices AD8345, an image rejection architecture can be enabled. To optimize the image rejection capability, as well as LO feedthrough in this architecture, the AD9777 offers programmable (via the SPI port) gain and offset adjust for each DAC.

Also included on the AD9777 are a phase-locked loop (PLL) clock multiplier and a 1.20 V band gap voltage reference. With the PLL enabled, a clock applied to the CLK+/CLK– inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. Each 16-bit DAC provides two complementary current outputs whose full-scale currents can be determined either from a single external resistor, or independently from two separate resistors (see 1R/2R mode). The AD9777 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square wave input. Separate voltage supply inputs are provided for each functional block to ensure optimum noise and distortion performance.

SLEEP and power-down modes can be used to turn off the DAC output current (SLEEP) or the entire digital and analog sections (power-down) of the chip. An SPI-compliant serial port is used to program the many features of the AD9777. Note that in power-down mode, the SPI port is the only section of the chip still active.

SDO (PIN 53)

SDIO (PIN 54)

SCLK (PIN 55)

CSB (PIN 56)

AD9777 SPI PORT

INTERFACE

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9777 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9777. Single- or multiple-byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9777’s serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9777. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9777 coincident with the first eight SCLK rising edges. The instruction byte provides the AD9777 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9777.

A logic high on the CSB pin, followed by a logic low, will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written.

The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9777 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, to 4 data bytes as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.

INSTRUCTION BYTE

The instruction byte contains the information shown below.

N1 N0 Description

00Transfer 1 Byte 01Transfer 2 Bytes 10Transfer 3 Bytes 11Transfer 4 Bytes

R/W

Bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic zero indicates a write operation.

Figure 2. SPI Port Interface

REV. 0–16–

AD9777

N1, N0

Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the following table:

MSB LSB

I7 I6 I5 I4 I3 I2 I1 I0 R/W N1 N0 A4 A3 A2 A1 A0

A4, A3, A2, A1, A0

Bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9777.

SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK (Pin 55)—Serial Clock

The Serial Clock Pin is used to synchronize data to and from the AD9777 and to run the internal state machines. SCLK maximum frequency is 15 MHz. All data input to the AD9777 is registered on the rising edge of SCLK. All data is driven out of the AD9777 on the falling edge of SCLK.

CSB (Pin 56)—Chip Select

Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO Pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.

SDIO (Pin 54)—Serial Data I/O

Data is always written into the AD9777 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 00h. The default is Logic “0,” which configures the SDIO Pin as unidirectional.

SDO (Pin 53)—Serial Data Out

Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9777 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.

MSB/LSB TRANSFERS

The AD9777 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by Register Address 00h, Bit 6. The default is MSB first. When this bit is set active high, the AD9777 serial port is in LSB first format. That is, if the AD9777 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte. In MSB first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. Multibyte data transfers in LSB first format can be completed by writing an instruction byte that includes the register address of the least significant byte. In LSB first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle.

The AD9777 serial port controller address will increment from 1Fh to 00h for multibyte I/O operations if the MSB first mode is active. The serial port controller address will decrement from 00h to 1Fh for multibyte I/O operations if the LSB first mode is active.

SCLK

SDIO

SDO

SCLK

SDIO

SDO

R/W

I6 I5

(N) (N)

INSTRUCTION CYCLE

I4 I3 I2 I1 I0 D6

D7ND6

DATA TRANSFER CYCLE

Figure 3a. Serial Register Interface Timing MSB First

DATA TRANSFER CYCLEINSTRUCTION CYCLE

I5I4I3I2I1I0 D6

R/WI6 D7

(N)(N)

D00D10D2

Figure 3b. Serial Register Interface Timing LSB First

REV. 0

–17–

AD9777

SCLK

SDIO

SCLK

SDIO

SDO

INSTRUCTION BIT 7 INSTRUCTION BIT 6

PWH

SCLK

PWL

Figure 4. Timing Diagram for Register Write to AD9777

DATA BIT N DATA BIT N–1

Figure 5. Timing Diagram for Register Read from AD9777

NOTES ON SERIAL PORT OPERATION

The AD9777 serial port configuration bits reside in Bits 6 and 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle.

The same considerations apply to setting the reset bit in Register Address 00h. All other registers are set to their default values, but the software reset doesn’t affect the bits in Register Address 00h.

It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset.

A write to Bits 1, 2, and 3 of Address 00h with the same logic levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 00h with reset bit low and serial port configuration as specified above (XY) reprograms the OSC IN multiplier setting. A changed f

frequency is stable after a maximum of 200 f

SYSCLK

MCLK

cycles

(equals wake-up time).

DAC OPERATION

The dual 16-bit DAC output of the AD9777, along with the reference circuitry, gain, and offset registers, is shown in Figure 6. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external R

SET

resistor, and the values in the coarse gain register. The fine gain DAC subtracts a small amount from this and the result is input to IDAC and QDAC, where it is scaled by an amount equal to 1024/24. Figures 7a and 7b show the scaling effect of the coarse and fine adjust DACs. IDAC and QDAC are PMOS current source arrays, segmented in a 5-4-7 configuration. The five most significant bits control an array of 31 current sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current source. The seven LSBs are binary weighted fractions of the middle bit’s current sources. All current sources are switched to either I

OUTA

or I

OUTB

, depend-

ing on the input code.

The fine adjustment of the gain of each channel allows for improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. In the Applications section of this data sheet, performance data is included that shows to what degree image rejection can be improved when the AD9777 is used with an AD8345 quadrature modulator from ADI.

REV. 0–18–

AD9777

COARSE GAIN REGISTER CODE – Assuming

RSET1, 2 = 1.9k

0 200

OFFSET CURRENT – mA

400 600 800

2R MODE

1R MODE

1000

The offset control defines a small current that can be added

OUTA

or I

to I selection of which I

(not both) on the IDAC and QDAC. The

OUTB

this offset current is directed toward is

OUT

programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch, Bit 7 (QDAC). Figure 9 shows the scale of the offset current that can be added to one of the complementary outputs on the IDAC and QDAC. Offset control can be used for suppression of LO leakage resulting from modulation of dc signal components. If the AD9777 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9777 as well as the input offset on the modulator. Figure 9 shows a typical example of the effect that the offset control has on LO suppression.

OFFSET

DAC

OFFSET

DAC

OUTA1

OUTB1

OUTA2

OUTB2

GAIN

CONTROL

REGISTERS

1.2VREF

REFIO

0.1F

FSADJ1

RSET1

FINE GAIN DAC

COARSE

GAIN

FSADJ2

RSET2

DAC

COARSE

GAIN

DAC

GAIN

CONTROL

REGISTERS

CONTROL

REGISTERS

IDAC

QDAC

CONTROL

REGISTERS

Figure 6. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust

–0.5

–1.0

–1.5

–2.0

–2.5

FINE REFERENCE CURRENT – mA

–3.0

FINE GAIN REGISTER CODE – Assuming

2R MODE

RSET1, 2 = 1.9k

Figure 7b. Fine Gain Effect on I

1R MODE

10 15 20

FULLSCALE

In Figure 9, the negative scale represents an offset added to I

, while the positive scale represents an offset added to

OUTB

of the respective DAC. Offset Register 1 corresponds

OUTA

to IDAC, while Offset Register 2 corresponds to QDAC. Figure 9 represents the AD9777 synthesizing a complex signal that is then dc-coupled to an AD8345 quadrature modulator with an LO of 800 MHz. The dc-coupling allows the input offset of the AD8345 to be calibrated out as well. The LO suppression at the AD8345 output was optimized first by adjusting Offset Register 1, in the AD9777. When an optimal point was found (roughly Code 54), this code was held in Offset Register 1, and Offset Register 2 was adjusted. The resulting LO suppression is 70 dBFS. These are typical numbers, and the specific code for optimization will vary from part to part.

COARSE REFERENCE CURRENT – mA

COARSE GAIN REGISTER CODE – Assuming

2R MODE

1R MODE

10 15 20

RSET1, 2 = 1.9k

Figure 7a. Coarse Gain Effect on I

FULLSCALE

Figure 8. DAC Output Offset Current

REV. 0

–19–

AD9777

–10

–20

–30

–40

–50

–60

LO SUPPRESSION – dBFS

–70

–80

–1024 –768

DAC1, DAC2 – Offset Register Codes

OFFSET REGISTER 1 ADJUSTED

OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE

1024–512 –256 0 256 512 768

Figure 9. Offset Adjust Control, Effect on LO Suppression

1R/2R MODE

In the 2R mode, the reference current for each channel is set independently by the FSADJ resistor on that channel. The AD9777 can be programmed to derive its reference current from a single resistor on Pin 60 by placing the part in the 1R mode. The transfer functions in Equation 1 are valid for the 2R mode. In the 1R mode, the current developed in the single FSADJ resistor is split equally between the two channels. The result is that in the 1R mode, a scale factor of one-half must be applied to the formulas in Equation 1. The full-scale DAC current in the 1R mode can still be set to as high as 20 mA by using the internal 1.2 V reference and a 950 Ω resistor, instead of the 1.9 kΩ resistor typically used in the 2R mode.

CLOCK INPUT CONFIGURATIONS

The clock inputs to the AD9777 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources.

Figure 10 shows the AD9777 driven from a single-ended clock source. The CLK+/CLK– Pins form a differential input (CLKIN), so that the statically terminated input must be dc-biased to the midswing voltage level of the clock driven input.

AD9777

THRESHOLD

SERIES

0.1F

CLK+

CLKVDD

CLK–

CLKGND

Figure 10. Single-Ended Clock Driving Clock Inputs

A configuration for differentially driving the clock inputs is given in Figure 11. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed CLKVDD or CLKGND. If the driver voltage swings are within the supply range of the AD9777, the dc-blocking capacitors and bias resistors are not necessary.

AD9777



CLK+



CLKVDD



CLK–



CLKGND

ECL/PECL

0.1F

0.1



Figure 11. Differential Clock Driving Clock Inputs

A transformer, such as the T1-1T from Mini-Circuits, can also be used to convert a single-ended clock to differential. This method is used on the AD9777 evaluation board so that an external sine wave with no dc offset can be used as a differential clock.

PECL/ECL drivers require varying termination networks, the details of which are left out of Figures 10 and 11 but can be found in application notes such as AND8020/D from On Semiconductor. These networks depend on the assumed transmission line impedance and power supply voltage of the clock driver. Optimum performance of the AD9777 is achieved when the driver is placed very close to the AD9777 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch.

The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry should provide the AD9777 with a low jitter clock input that meets the min/max logic levels while providing fast edges. Although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain bandwidth product of the AD9777’s differential comparator can tolerate sine wave inputs as low as 0.5 V p-p, with minimal degradation of the output noise floor.

PROGRAMMABLE PLL

CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled) according to the state of Address 02h, Bit 7 in the SPI port register. The internal operation of the AD9777 clock circuitry in these two modes is illustrated in Figures 12 and 13.

The PLL clock multiplier and distribution circuitry produce the necessary internal synchronized 1×, 2×, 4×, and 8× clocks for the rising edge triggered latches, interpolation filters, modulators, and DACs. This circuitry consists of a phase detector, charge pump, voltage controlled oscillator (VCO), prescaler, clock distribution, and SPI port control. The charge pump and VCO are powered from PLLVDD while the differential clock input buffer, phase detector, prescaler, and clock distribution are powered from CLKVDD. PLL lock status is indicated by the logic signal at the PLL_LOCK Pin, as well as by the status of Bit 1, Register 00h. To ensure optimum phase noise performance from the PLL clock multiplier, and distribution, PLLVDD and CLKVDD should originate from the same clean analog supply. The speed of the VCO with the PLL enabled also has an effect on phase noise. Optimal phase noise with respect to VCO speed is achieved by running the VCO in the range of 450 MHz to 550 MHz. The VCO speed is a function of the input data rate, the interpolation rate, and the VCO prescaler, according to the following function:

VCO Speed MHz

Input Data Rate MHz InterpolationRate escaler

()

××Pr

REV. 0–20–

PLL_LOCK

FREQUENCY OFFSET – MHz

PHASE NOISE – dBFS

–80

–70

–60

–50

–40

–30

–20

–10

–90

–110

–100

12345

DATA

– MHz

050

DVDD

– mA

100 150 200

100

150

200

250

300

350

400

(MOD. ON),

4 (MOD. ON),

(MOD. ON),



1 = LOCK

0 = NO LOCK

CLK+

AD9777

CLK–

PLLVDD

AD9777

INPUT

DATA

LATCHES

INTERPOLATION

RATE

CONTROL

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

CLOCK

DISTRIBUTION

CIRCUITRY

INTERNAL SPI

CONTROL

REGISTERS

SPI PORT

MODULATION

DETECTOR

PRESCALER

RATE

CONTROL

PHASE

CHARGE

PUMP

VCO

PLL DIVIDER

(PRE SCALER)

CONTROL

PLL

CONTROL

(PLL ON)

Figure 12. PLL and Clock Circuitry with PLL Enabled

CLK–

CLK+

PLL_LOCK

INPUT

DATA

LATCHES

INTERPOLATION

RATE

CONTROL

1 = LOCK

0 = NO LOCK

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

CLOCK

DISTRIBUTION

CIRCUITRY

INTERNAL SPI

CONTROL

REGISTERS

SPI PORT

PHASE

DETECTOR

PRESCALER

MODULATION

RATE

CONTROL

AD9777

CHARGE

PUMP

VCO

PLL DIVIDER

(PRE SCALER)

CONTROL

PLL

CONTROL

(PLL ON)

LPF

Figure 14. Phase Noise Performance

It is important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9777. This will suffice unless the input data rate is below 10 MHz, in which case an external series RC is required between the LPF and PLLVDD Pins.

POWER DISSIPATION

The AD9777 has three voltage supplies: AVDD, DVDD, and CLKVDD. Figures 15, 16, and 17 show the current required from each of these supplies when each is set to the 3.3 V nominal specified for the AD9777. Power dissipation (P

) can easily

be extracted by multiplying the given curves by 3.3. As Figure 15 shows, I

is very dependent on the input data rate, the

DVDD

interpolation rate, and the activation of the internal digital modulator. I modulation rate by itself. In Figure 16, I

, however, is relatively insensitive to the

DVDD

shows the same

AVDD

type of sensitivity to data, interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 17, I

varies over a wide range yet is responsible for only a small

CLKVDD

percentage of the overall AD9777 supply current requirements.

Figure 13. PLL and Clock Circuitry with PLL Disabled

In addition, if the zero stuffing option is enabled, the VCO will double its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 14 illustrates typical phase noise performance of the AD9777 with 2× interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of f The repetitive nature of this signal eliminated quantization noise and distortion spurs as a factor in the measurement. Although the curves blend together in Figure 14, the different conditions are called out here for clarity.

REV. 0

DATA

125 MSPS Disabled

PLL Prescaler Ratio

125 MSPS Enabled div1 100 MSPS Enabled div2 75 MSPS Enabled div2 50 MSPS Enabled div4

DATA

/4.

–21–

Figure 15. I PLL Disabled

DVDD

vs. f

vs. Interpolation Rate,

DATA

AD9777

76.0

75.5

75.0

74.5

– mA

74.0

AVDD

73.5

73.0

72.5

72.0 050

Figure 16. I

AVDD

8 (MOD. ON),



vs. f



4 (MOD. ON),



100 150 200

– MHz

DATA

vs. Interpolation Rate,

DATA

2 (MOD. ON),



PLL Disabled

– mA

CLKVDD

050

Figure 17. I



CLKVDD

vs. f



100 150 200

– MHz

DATA

vs. Interpolation Rate,

DATA



PLL Disabled

SLEEP/POWER-DOWN MODES (Control Register 00h, Bits 3 and 4)

The AD9777 provides two methods for programmable reduction in power savings. The sleep mode, when activated, turns off the DAC output currents but the rest of the chip remains functioning. When coming out of sleep mode, the AD9777 will immediately return to full operation. Power-down mode, on the other hand, turns off all analog and digital circuitry in the AD9777 except for the SPI port. When returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. Note that optimal performance with the PLL enabled is achieved with the UCO in the PLL control loop running at 450 MHz – 550 MHz.

ONE/TWO PORT INPUT MODES

The digital data input ports can be configured as two independent ports or as a single (one port mode) port. In two port mode, the AD9777 can be programmed to generate an externally available data rate clock (DATACLK) for the purpose of data synchronization. Data at the two input ports can be latched into the AD9777 on every rising clock edge of DATACLK. In one port mode, P2B14 and P2B15 from input data Port 2 are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9777 in this mode for the purpose of external data synchronization. ONEPORTCLK runs at the input interleaved data rate, which is 2× the data rate at the internal input to either channel.

Test configurations showing the various clocks that are required and produced by the AD9777 in the PLL and one/two port modes are given in Figures 55 through 58. Jumper positions needed to operate the AD9777 evaluation board in these modes are given as well.

PLL ENABLED, TWO PORT MODE (Control Register 02h, Bits 6–0 and 04h, Bits 7–1)

With the phase-locked loop (PLL) enabled and the AD9777 in two port mode, the speed of CLKIN is inherently that of the input data rate. In two port mode, Pin 8 (DATACLK/PLL_ LOCK) can be programmed (Control Register 01h, Bit 0) to function as either a lock indicator for the internal PLL or as a clock running at the input data rate. When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of CLKIN. Data at the input ports is latched into the AD9777 on the rising edge of the CLKIN. Figure 18 shows the delay, t

, inherent between the

rising edge of CLKIN and the rising edge of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2. Note that the setup and hold times given in Figure 18 are the input data transitions with respect to CLKIN. t

can vary with

CLKIN speed, PLL divider setting, and interpolation rate. It is therefore highly recommended that the input data be synchronized to CLKIN rather than DATACLK when the PLL is enabled. Note that in two port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at Ports 1 and 2.

The DAC output sample rate in two port mode is equal to the clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of two must be included to calculate the DAC sample rate.

DATACLK Inversion (Control Register 02h, Bit 4)

By programming this bit, the DATACLK signal shown in Figure 18 can be inverted. With inversion enabled, t

will refer to the time between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing will occur.

REV. 0–22–

AD9777

CLKIN

I AND Q INTERLEAVED

INPU T DATA AT PORT 1

ONEPORTCLK

IQSEL

IQH

IQS

= 4.7ns

= 3.0ns

= –0.5ns

IQS

= 3.5ns

IQH

= –1.5ns

CLKIN

DATACLK

DATA AT PORTS

1 AND 2

= 0.0ns

= 2.5ns

(TYP SPECS)

Figure 18. Timing Requirements in Two Port Input Mode with PLL Enabled

DATACLK DRIVER STRENGTH (Control Register 02h, Bit 5)

The DATACLK output driver strength is capable of driving >10 mA into a 330 Ω load while providing a rise time of 3 ns. Figure 19 shows DATACLK driving a 330 Ω resistive load at a frequency of 50 MHz. By enabling the drive strength option (Control Register 02h, Bit 5), the amplitude of DATACLK under these conditions will be increased by approximately 200 mV.

3.0

the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9777 is in one port mode) on the rising edge of ONEPORTCLK. IQSEL = 1 under these conditions will latch the data into the I channel on the clock rising edge, while IQSEL = 0 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic “1”). Figure 20 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in one port mode.

The DAC output sample rate in one port mode is equal to CLKIN multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.

ONEPORTCLK INVERSION (Control Register 02h, Bit 2)

By programming this bit, the ONEPORTCLK signal shown in Figure 20 can be inverted. With inversion enabled, t

refers to

the delay between the rising edge of the external clock and the falling edge of ONEPORTCLK. The setup and hold times, t

and tH, will be with respect to the falling edge of ONEPORTCLK. There will be no other effect on timing.

ONEPORTCLK DRIVER STRENGTH

The drive capability of ONEPORTCLK is identical to that of DATACLK in the two port mode. Refer to Figure 19 for performance under load conditions.

PLL ENABLED, ONE PORT MODE (Control Register 02h, Bits 6–1 and 04h, Bits 7–1)

In one port mode, the I and Q channels receive their data from an interleaved stream at digital input Port 1. The function of Pin 32 is defined as an output (ONEPORTCLK) that generates a clock at the interleaved data rate, which is 2⫻ the internal input data rate of the I and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. The selection of

2.5

2.0

1.5

1.0

FREQUENCY – V

0.5

–0.5

010

Figure 19. DATACLK Driver Capability into 330 at 50 MHz

DELTA APPROX. 2.8ns

20 30 40

TIME – ns

⍀

Figure 20. Timing Requirements in One Port Input Mode, with the PLL Enabled

REV. 0

–23–

AD9777

IQ PAIRING (Control Register 02h, Bit 0)

In one port mode, the interleaved data is latched into the AD9777 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. The following is an example of the effect this has on incoming interleaved data.

Given the following interleaved data stream, where the data indicates the value with respect to full scale:

IQIQIQIQIQ

0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5

With the control register set to “0” (I first), the data will appear at the internal channel inputs in the following order in time:

I channel 0.5 1 0.5 0 0.5 Q channel 0.5 1 0.5 0 0.5

With the control register set to “1” (Q first), the data will appear at the internal channel inputs in the following order in time:

I channel 0.5 1 0.5 0 0.5 x Q channel y 0.5 1 0.5 0 0.5

The values x and y represent the next I value and the previous Q value in the series.

PLL DISABLED, TWO PORT MODE

With the PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal clock dividers in the AD9777 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Ports 1 and 2 of the AD9777 on the rising edge of DATACLK. DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate. With zero stuffing enabled, this division increases by a factor of 2. Figure 21 illustrates the delay between the rising edge of CLKIN and the rising edge of DATACLK, as well as t

and tH in this mode.

The programmable modes DATACLK inversion and DATACLK driver strength described in the previous section (PLL Enabled, Two Port Mode) have identical functionality with the PLL disabled.

As described earlier in the PLL-Enabled Mode section, t

can vary depending on CLKIN frequency and interpolation rate. However, with the PLL disabled, the input data latches are closely synchronized to DATACLK so that it is recommended in this mode that the input data be timed from DATACLK, not CLKIN.

CLKIN

DATACLK

DATA AT PORTS

1 AND 2

= 5.0ns

= –3.2ns

tHt

(TYP SPECS)

Figure 21. Timing Requirements in Two Port Input Mode, with PLL Disabled

PLL DISABLED, ONE PORT MODE

In one port mode, data is received into the AD9777 as an interleaved stream on Port 1. A clock signal (ONEPORTCLK),

running at the interleaved data rate, which is 2

the input data rate of the internal I and Q channels is available for data synchronization at Pin 32.

With PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal dividers synthesize the ONEPORTCLK signal at Pin 32. The selection of the data for the I or Q channel is determined by the state of the logic level applied to Pin 31 (IQSEL when the AD9777 is in one port mode) on the rising edge of ONEPORTCLK. IQSEL = 1 under these conditions will latch the data into the I channel on the clock rising edge, while IQSEL = 0 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic “1”). Figure 22 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one port mode.

One port mode is very useful when interfacing with devices such as Analog Devices’ AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed).

REV. 0–24–

AD9777

The programmable modes’ ONEPORTCLK inversion, ONEPORTCLK driver strength, and IQ pairing described in the previous section (PLL Enabled, One Port Mode) have identical functionality with the PLL disabled.

CLKIN

ONEPORTCLK

I AND Q INTERLEAVED

INPU T DATA AT PORT 1

= 4.7ns

= 3.0ns

= –1.0ns

= 3.5ns

IQS

= –1.5ns

IQH

(TYP SPECS)

IQSEL

IQS

IQH

Figure 22. Timing Requirements in One Port Input Mode, with PLL Disabled

DIGITAL FILTER MODES

The I and Q data paths of the AD9777 have their own independent half-band FIR filters. Each data path consists of three FIR filters, providing up to 8× interpolation for each channel. The rate of interpolation is determined by the state of Control Register 01h, Bits 7 and 6. Figures 1a–1c show the response of the digital filters when the AD9777 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs have been normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than 75 dB of out-of-band rejection.

An online tool is available for quick and easy analysis of the AD9777 interpolation filters in the various modes. The link can be accessed at: www.analog.com/techSupport/designTools/

interactiveTools/dac/ad9777image.html.

AMPLITUDE MODULATION

Given two sine waves at the same frequency, but with a 90 phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative frequency images. This is shown graphically in the frequency domain in Figure 23.

–jt

/2j

SINE

–jt

/2j

–jt

COSINE

Figure 23. Real and Imaginary Components of Sinusoidal and Cosinusoidal Waveforms

Amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of two. This scaling will be very important in the discussion of the various modulation modes. The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. Examples of sine and cosine modulation are given in Figure 24.

–jt

/2j

SINUSOIDAL MODULATION

–jt

/2j

–jt

/2 Ae

–jt

COSINUSOIDAL

MODULATION

Figure 24. Baseband Signal, Amplitude Modulated with Sine and Cosine Carriers

REV. 0

–25–

AD9777

MODULATION, NO INTERPOLATION

With Control Register 01h, Bits 7 and 6 set to “00,” the interpolation function on the AD9777 is disabled. Figures 25a–25d show the DAC output spectral characteristics of the AD9777 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4. The tall rectangles represent the digital domain spectrum of a baseband signal of

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

0 0.2

0.4 0.6 0.8 1.0

(

DATA

)

OUT

Figure 25a. No Interpolation, Modulation Disabled

narrow bandwidth. By comparing the digital domain spectrum to the DAC SIN(x)/x roll-off, an estimate can be made for the characteristics required for the DAC reconstruction filter. Note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to f

/4 or fS/8)

are scaled by a factor of 2. In the situation where the modulation is f

/2, the modulated spectral components add constructively

and there is no scaling effect.

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

0 0.2

Figure 25c. No Interpolation, Modulation = f

0.4 0.6 0.8 1.0

(

DATA

)

DAC

OUT

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

0 0.2

0.4 0.6 0.8 1.0

(f

DATA

)

OUT

Figure 25b. No Interpolation, Modulation = f

Figure 25. Effects of Digital Modulation on DAC Output Spectrum, Interpolation Disabled

DAC

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

0 0.2

Figure 25d. No Interpolation, Modulation = f

0.4 0.6 0.8 1.0

(

DATA

)

DAC

OUT

REV. 0–26–

AD9777

OUT

(f

DATA

)

0 0.5

AMPLITUDE – dBFS

–100

–80

–60

–40

–20

1.0 1.5 2.0

OUT

(f

DATA

)

0 0.5

AMPLITUDE – dBFS

–100

–80

–60

–40

–20

1.0 1.5 2.0

MODULATION, INTERPOLATION = 2×

With Control Register 01h, Bits 7 and 6 set to “01,” the interpolation rate of the AD9777 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (1, –1). Figures 26a–26d represent the spectral response of the AD9777 DAC output with 2× interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic). The advantage of interpolation becomes clear in Figures 26a–26d, where it can be seen that the images that would normally appear in the spectrum around the

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

0 0.5

1.0 1.5 2.0

(

DATA

)

OUT

Figure 26a. 2 × Interpolation, Modulation = Disabled

input data rate frequency are suppressed by >70 dB. Another significant point is that the interpolation filtering is done previous to the digital modulator. For this reason, as Figures 26a–26d show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high-pass digital filter.

Note that when using the f stop band as the band edges coincide with each other. In the f

/4 modulation mode, there is no true

modulation mode, amplitude scaling occurs over only a portion of the digital filter pass band due to constructive addition over just that section of the band.

Figure 26c. 2 × Interpolation, Modulation = f

DAC

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

0 0.5

Figure 26b. 2 × Interpolation, Modulation = f

Figure 26. Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 2

1.0 1.5 2.0

(

DATA

)

OUT

DAC

Figure 26d. 2 × Interpolation, Modulation = f

DAC

REV. 0

–27–

AD9777

MODULATION, INTERPOLATION = 4×

With Control Register 01h, Bits 7 and 6 set to “10,” the interpolation rate of the AD9777 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

234

(

DATA

)

OUT

Figure 27a. 4 × Interpolation, Modulation Disabled

–20

by the sequence (0, 1, 0, –1). Figures 27a–27d represent the spectral response of the AD9777 DAC output with 4× interpo- lation in the various modulation modes to a narrow band baseband signal.

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

Figure 27c. 4 × Interpolation, Modulation = f

–20

234

(

DATA

)

DAC

OUT

–40

–60

AMPLITUDE – dBFS

–80

–100

234

(

DATA

)

OUT

Figure 27b. 4 × Interpolation, Modulation = f

Figure 27. Effect of Digital Modulation on DAC Output Spectrum, Interpolation = 4

DAC

–40

–60

AMPLITUDE – dBFS

–80

–100

Figure 27d. 4 × Interpolation, Modulation = f

234

(

DATA

)

DAC

OUT

REV. 0–28–

AD9777

OUT

(f

DATA

)

AMPLITUDE – dBFS

–100

–80

–60

–40

–20

234 5678

OUT

(

DATA

)

AMPLITUDE – dBFS

–100

–80

–60

–40

–20

234 5678

MODULATION, INTERPOLATION = 8×

With Control Register 01h, Bits 7 and 6, set to “11,” the interpolation rate of the AD9777 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, 0.707, 1, 0.707, 0, –0.707, –1, 0.707). Figures 28a–28d represent the spectral response of the AD9777 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal.

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

234

(

DATA

)

OUT

Figure 28a. 8 × Interpolation, Modulation Disabled

Looking at Figures 26 through 29, the user can see how higher interpolation rates reduce the complexity of the reconstruction filter needed at the DAC output. It also becomes apparent that the ability to modulate by f

/2, fS/4, or fS/8 adds a degree of

flexibility in frequency planning.

Figure 28c. 8 × Interpolation, Modulation = f

DAC

ZERO STUFFING (Control Register 01h, Bit 3)

As shown in Figure 29, a “0” or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f This is due to the inherent SIN(x)/x roll-off response in the digitalto-analog conversion. In applications where the desired frequency content is below f f tions, this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced amplitude of the desired signal.

–20

–40

–60

AMPLITUDE – dBFS

–80

–100

Figure 28b. 8 × Interpolation, Modulation = f

234

(

DATA

)

DAC

OUT

Figure 28. Effect of Digital Modulation on DAC Output Spectrum, Interpolation = 8

/2, this may not be a problem. Note that at

/2 the loss due to SIN(x)/x is 4 dB. In direct RF applica-

DAC

Figure 28d. 8 × Interpolation, Modulation = f

DAC

Consider an application where the digital data into the AD9777 represents a baseband signal around f

/10. The reconstructed signal out of the AD9777 would

DAC

/4 with a pass band of

DAC

experience only a 0.75 dB amplitude variation over its passband.

However, the image of the same signal occurring at 3 × f

DAC

/4 will suffer from a pass-band flatness variation of 3.93 dB. This image may be the desired signal in an IF application using one of the various modulation modes in the AD9777. This roll-off of image frequencies can be seen in Figures 25 through 28, where the effect of the interpolation and modulation rate is apparent as well.

REV. 0

–29–

AD9777

–10

–20

OUT

ZERO STUFFING

DISABLED

, NORMALIZED TO f

–30

SIN (X)/ X ROLL-OFF – dBFS

–40

–50

0.5

DISABLED – Hz

ZERO STUFFING

ENABLED

1.0 1.5 2.0

WITH ZERO STUFFING

DATA

Figure 29. Effect of Zero Stuffing on DAC’s SIN(x)/x Response

To improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to a Logic “1.” This option increases the ratio of f

DAC/fDATA

by a factor of 2 by doubling the DAC sample rate and inserting a midscale sample (i.e., 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This is important as it will affect the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the DAC.

The net effect is to increase the DAC output sample rate by a factor of 2× with the “0” in the SIN(x)/x DAC transfer function occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident, as can be seen in Figure 30.

It is important to realize that the zero stuffing option by itself does not change the location of the images but rather their amplitude, pass-band flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the image at 3 × f

/4 is now improved to 0.59 dB while the signal level

DATA

has increased slightly from –10.5 dBFS to –8.1 dBFS.

INTERPOLATING (COMPLEX MIX MODE) (Control Register 01h, Bit 2)

In the complex mix mode, the two digital modulators on the AD9777 are coupled to provide a complex modulation function. In conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. The complex modulation function can be programmed for e

+j␻t

–j␻t

or e

to give upper or lower image rejec-

tion. As in the real modulation mode, the modulation frequency ␻ can be programmed via the SPI port for f

/8, where f

DAC

represents the DAC output rate.

DAC

/2, f

DAC

/4, and

OPERATIONS ON COMPLEX SIGNALS

Truly complex signals cannot be realized outside of a computer simulation. However, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. I (real) and Q (imaginary) data paths are often defined this way. By using the architecture defined in Figure 30, a system that operates on complex signals can be realized, giving a complex (real and imaginary) output.

+j␻t

If a complex modulation function (e imaginary components of the system correspond to the real and imaginary components of e

+j␻t

, or cos␻t and sin␻t. As Figure 31

) is desired, the real and

shows, the complex modulation function can be realized by applying these components to the structure of the complex system defined in Figure 30.

c(t) b(t) + d b(t)

a(t)

b(t)

INPUT

OUTPUT

COMPLEX FILTER

= (c + jd)

IMAGINARY

OUTPUT

INPUT



b(t) a(t) + c b(t)



Figure 30. Realization of a Complex System

INPUT

(REAL)

INPUT

(IMAGINARY)



90



–jt

= COSt + jSINt

OUTPUT (REAL)

OUTPUT (IMAGINARY)

Figure 31. Implementation of a Complex Modulator

COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS

In traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an IF (intermediate frequency) and then modulated a second time to the transmit frequency. Although this approach has several benefits, a major drawback is that two images are created near the transmit frequency. Only one image is needed, the other being an exact duplicate. Unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced.

A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. Figure 32 is a block diagram of a quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal.

INPUT

(REAL)

INPUT

(IMAGINARY)

SINt



90

OUTPUT

COSt

Figure 32. Quadrature Modulator

REV. 0–30–

AD9777

The entire upconversion from baseband to transmit frequency is represented graphically in Figure 33. The resulting spectrum shown in Figure 33 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. It is important to remember that in this application (two baseband data channels), the image rejection is not dependent on the data at either of the AD9777 input channels.

–F

REAL CHANNEL (IN)

–F

IMAGINARY CHANNEL (OUT)

–F

IMAGINARY CHANNEL (IN)

COMPLEX

MODULATOR

In fact, image rejection will still occur with either one or both of the AD9777 input channels active. Note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. This is easily done in the AD9777 by selecting the e

+j␻t

bit (Register 01h, Bit 1). In purely complex terms, Figure 31 represents the two-stage upconversion from complex baseband to carrier.

REAL CHANNEL (OUT)

A/2A/2

B/2J–B/2J

A/2J–A/2J

–F

B/2B/2

TO QUADRATURE MODULATOR

REAL

IMAGINARY

–F

*FC = COMPLEX MODULATION FREQUENCY

*FQ = QUADRATURE MODULATION FREQUENCY

A/4 + B/4J A/4 – B/4J

– F

–F

OUT

QUADRATURE

MODULATOR

A/2 + B/2J A/2 – B/2J

–F

+ F

REJECTED IMAGES

FQ – F

A/4 + B/4JA/4 – B/4J

A/4 + B/4JA/4 – B/4J–A/4 – B/4J –A/4 + B/4J

Figure 33. Two-Stage Upconversion and Resulting Image Rejection

FQ + F

REV. 0

–31–

AD9777

COMPLEX BASEBAND

SIGNAL



j(1 + 2)t

FREQUENCY

OUTPUT = REAL

= REAL

1/2 1/2

–1 – 2 1 + 2

Figure 34. Two-Stage Complex Upconversion

IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS

As shown in Figure 33, image rejection can be achieved by applying baseband data to the AD9777 and following the AD9777 with a quadrature modulator. To process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. As Figure 34 shows, single- or multiple-complex modulators can be used to synthesize complex carriers. These

BASEBAND CHANNEL 1

BASEBAND CHANNEL 2

REAL INPUT

IMAGINARY INPUT

REAL INPUT

IMAGINARY INPUT

COMPLEX

MODULATOR 1

COMPLEX

MODULATOR 2

R(1)

R(2)

complex carriers are then summed and applied to the real and imaginary inputs of the AD9777. A system in which multiple baseband signals are complex modulated and then applied to the AD9777 real and imaginary inputs, followed by a quadrature modulator is shown in Figure 36, which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in Figure 36 and Figure 34. Figure 36 adds an additional complex modulator stage for the purpose of summing multiple carriers at the AD9777 inputs. Also, as in Figure 33, the image rejection is not dependent on the real or imaginary baseband data on any channel. Image rejection on a channel will occur if either the real or imaginary data, or both, is present on the baseband channel.

It is important to remember that the magnitude of a complex signal can be 1.414× the magnitude of its real or imaginary components. Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9777 must be kept at least 3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator will result in severe distortion at the DAC output.

MULTICARRIER REAL OUTPUT = R(1) + R(2) +...R(N) (TO REAL INPUT OF AD9777)

MULTICARRIER IMAGINARY OUTPUT = I(1) + I(2) +...I(N) (TO IMAGINARY INPUT OF AD9777)

MULTIPLE BASEBAND CHANNELS

REAL

IMAGINARY

BASEBAND CHANNEL N

REAL INPUT

IMAGINARY INPUT

Figure 35. Synthesis of Multicarrier Complex Signal

MULTIPLE COMPLEX

MODULATORS

FREQUENCY = 

–1 – C – 

, 2...N

Figure 36. Image Rejection with Multicarrier Signals

COMPLEX

MODULATOR N

REAL

IMAGINARY

COMPLEX BASEBAND

SIGNAL

OUTPUT = REAL

REJECTED IMAGES

R(N)

MODULATOR

FREQUENCY = 

R(N) = REAL OUTPUT OF N I(N) = IMAGINARY OUTPUT OF N

AD9777

COMPLEX

j(



IMAGINARY

1 + C + 

REAL

QUADRATURE

MODULATOR

FREQUENCY = 

REAL

REV. 0–32–

AD9777

The complex carrier synthesized in the AD9777 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at f tions with modulation rates of f

/2. As a result, complex modulation only func-

DAC

/4 and f

DAC

/8.

Regions A and B of Figures 37 through 42 are the result of the complex signal described above, when complex modulated in the AD9777 by +e signal described above, again with positive frequency components only, modulated in the AD9777 by –e modulator after the AD9777 inherently modulates by +e

Region A

j␻t

. Regions C and D are the result of the complex

j␻t

. The analog quadrature

j␻t

Region A is a direct result of the upconversion of the complex signal near baseband. If viewed as a complex signal, only the images in Region A will remain. The complex Signal A, consisting of positive frequency components only in the digital domain, has images in the positive odd Nyquist zones (1, 3, 5...) as well as images in the negative even Nyquist zones. The appearance and rejection of images in every other Nyquist zone will become more apparent at the output of the quadrature modulator. The A images will appear on the real and the imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale now represents the frequency offset from this LO.

Region B

Region B is the image (complex conjugate) of Region A. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region B will appear in the spectrum. However, on the output of the quadrature modulator, Region B will be rejected.

Region C

Region C is most accurately described as a down conversion, as the modulating carrier is –e

j␻t

. If viewed as a complex signal, only the images in Region C will remain. This image will appear on the real and imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale will represent the frequency offset from this LO.

Region D

Region D is the image (complex conjugate) of Region C. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region D will appear in the spectrum. However, on the output of the quadrature modulator, Region D will be rejected.

Figures 43 through 50 show the measured response of the AD9777 and AD8345 given the complex input signal to the AD9777 in Figure 43. The data in these graphs was taken with a data rate of

12.5 MSPS at the AD9777 inputs. The interpolation rate of 4× or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result, the high end of the DAC output spectrum in these graphs is the first null point for the SIN(x)/x roll-off, and the asymmetry of the DAC output images is representative of the SIN(x)/x roll-off over the spectrum. The internal PLL was enabled for these results. In addition, a 35 MHz third order low-pass filter was used at the AD9777/AD8345 interface to suppress DAC images.

An important point can be made by looking at Figures 45 and 47. Figure 45 represents a group of positive frequencies modulated by complex +f tive frequencies modulated by complex –f

/4, while Figure 47 represents a group of nega-

DAC

/4. When looking at

DAC

the real or imaginary outputs of the AD9777, as shown in Figures 45 and 47, the results look identical. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figures 46 and 48.

REV. 0

–33–

AD9777

–20

DABCDABC

–40

–60

–80

–100

–2.0

–1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

OUT

(LO) (

DATA

)

Figure 37. 2 × Interpolation, Complex f

–20

DABC DA BC

–40

–60

/4 Modulation

DAC

–20

–40

–60

–80

–100

–2.0

ABCDAB

–1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

OUT

(LO)

(

DATA

)

Figure 40. 2 × Interpolation, Complex f

–20

–40

ABCDAB

–60

/8 Modulation

DAC

–80

–100

–4.0

–3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0

OUT

(LO)

(f

DATA

)

Figure 38. 4 × Interpolation, Complex f

–20

DA BC DA BC

–40

–60

–80

–100

–6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0

–8.0

OUT

(LO) (

DATA

)

Figure 39. 8 × Interpolation, Complex f

/4 Modulation

DAC

/4 Modulation

DAC

–80

–100

–3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0

–4.0

OUT

(LO)

(f

DATA

)

Figure 41. 4 × Interpolation, Complex f

–20

AD CB AD CB

–40

–60

–80

–100

–6.0 –4.0 –2.0 0 2.0 4.0 6.0 8.0

–8.0

OUT

(LO)

(f

DATA

)

Figure 42. 8 × Interpolation, Complex f

/8 Modulation

DAC

/8 Modulation

DAC

REV. 0–34–

AMPLITUDE – dBm

–30

–100

02040

–60

–70

–90

–80

–40

–50

–20

FREQUENCY – MHz

–10

5010

AMPLITUDE – dBm

–30

–100

–60

–70

–90

–80

–40

–50

–20

–10

750

FREQUENCY – MHz

760 770 780 790 800 810 820 830 840 850

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

–100

010 5020

FREQUENCY – MHz

30 40

Figure 43. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies



Only), Interpolation = 4

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

–100

750

760 770 780 790 800 810 820 830 840 850

, No Modulation in AD9777

FREQUENCY – MHz

Figure 44. AD9777 Complex Output from Figure 43, Now Quadrature Modulated by AD8345 (LO = 800 MHz)

AD9777

Figure 45. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies



Only), Interpolation = 4 AD9777 = +f

DAC

Figure 46. AD9777 Complex Output from Figure Figure 45, Now Quadrature Modulated by AD8345 (LO = 800 MHz)

, Complex Modulation in

REV. 0

–35–

AD9777

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

–100

02040

FREQUENCY – MHz

5010

Figure 47. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Negative Frequencies



Only), Interpolation = 4 AD9777 = –f

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

–100

750

DAC

760 770 780 790 800 810 820 830 840 850

, Complex Modulation in

FREQUENCY – MHz

Figure 48. AD9777 Complex Output from Figure 47, Now Quadrature Modulated by AD8345 (LO = 800 MHz)

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

–100

020 8040

FREQUENCY – MHz

100

Figure 49. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies



Only), Interpolation = 8 AD9777 = +f

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

–100

700

DAC

720 740 760 780 800 820 840 860 880 900

, Complex Modulation in

FREQUENCY – MHz

Figure 50. AD9777 Complex Output from Figure 49, Now Quadrature Modulated by AD8345 (LO = 800 MHz)

REV. 0–36–

AD9777

APPLYING THE AD9777 OUTPUT CONFIGURATIONS

The following sections illustrate typical output configurations for the AD9777. Unless otherwise noted, it is assumed that I

OUTFS

is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configuration is suggested. A simple differential output may be achieved by converting I

OUTA

and I

to a voltage output by terminating

OUTB

them to AGND via equal value resistors. This type of configuration may be useful when driving a differential voltage input device such as a modulator. If a conversion to a single-ended signal is desired and the application allows for ac-coupling, an RF transformer may be useful; if power gain is required, an op amp may be used. The transformer configuration provides optimum high frequency noise and distortion performance. The differential op amp configuration is suitable for applications requiring dccoupling, signal gain, and/or level shifting within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if I

, referred to AGND. This configuration is most suitable

LOAD

OUTA

and/or I

is connected to a load resistor,

OUTB

for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting I

OUTA

or I

OUTB

into a negative unipolar voltage. This configuration provides the best DAC dc linearity as I

OUTA

or I

are maintained at

OUTB

ground or virtual ground.

UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT

In many applications, it may be necessary to understand the equivalent DAC output circuit. This is especially useful when designing output filters or when driving inputs with finite input impedances. Figure 51 illustrates the output of the AD9777 and the equivalent circuit. A typical application where this informatWn may be useful is when designing an interface filter between the AD9777 and Analog Devices’ AD8345 quadrature modulator.

OUTFS

SOURCE

 (RA + RB)

p-p

OUTA

OUTB

RA + R

OUT

–

OUT

(DIFFERENTIAL)

Figure 51. DAC Output Equivalent Circuit

For the typical situation, where I

= 20 mA and RA and R

OUTFS

both equal 50 Ω, the equivalent circuit values become:

V R

SOURCE

= 100 Ω

OUT

= 2 V p-p

Note that the output impedance of the AD9777 DAC itself is greater than 100 kΩ and typically has no effect on the impedance of the equivalent output circuit.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 52. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes.

MINI-CIRCUITS

OUTA

DAC I

OUTB

T1-T2

LOAD

Figure 52. Transformer-Coupled Output Circuit

The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path for both I at I

OUTA

and I

OUTB

. The complementary voltages appearing

OUTB

(i.e., V

OUTA

and V

) swing symmetrically

OUTB

around AGND and should be maintained within the specified output compliance range of the AD9777. A differential resistor,

, may be inserted in applications where the output of the

DIFF

transformer is connected to the load, R struction filter or cable. R

is determined by the transformer’s

DIFF

, via a passive recon-

LOAD

impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across R

DIFF

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 53. This has the added benefit of providing signal gain as well. In Figure 53, the AD9777 is configured with two equal load resistors, R differential voltage developed across I

OUTA

and I

, of 25 Ω. The

LOAD

is converted

OUTB

to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across I

OUTA

and I

OUTB

, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp’s distortion performance by preventing the DAC’s fast slewing output from overloading the input of the op amp.

500

OUTA

DAC

OUTB

25

225

AD8021

225

OPT

25

500

R 225

OPT

AVDD

Figure 53. Op Amp-Coupled Output Circuit

The common-mode (and second order distortion) rejection of this configuration is typically determined by the resistor matching. The op amp used must operate from a dual supply since its output is approximately ± 1.0 V. A high speed amplifier, such as the AD8021, capable of preserving the differential performance of the

REV. 0

–37–

AD9777

AD9777 while meeting other system level objectives (i.e., cost, power) is recommended. The op amp’s differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. R

OPT

is only necessary if level shifting is required on the op amp output. In Figure 53, AVDD, which is the positive analog supply for both the AD9777 and the op amp, is also used to level shift the differential output of the AD9777 to midsupply (i.e., AVDD/2).

INTERFACING THE AD9777 WITH THE AD8345 QUADRATURE MODULATOR

The AD9777 architecture was defined to operate in a transmit signal chain using an image reject architecture. A quadrature modulator is also required in this application and should be designed to meet the output characteristics of the DAC as much as possible. The AD8345 from Analog Devices meets many of the requirements for interfacing with the AD9777. As with any DAC output interface, there are a number of issues that have to be resolved. Among the major issues are the following.

DAC Compliance Voltage/Input Common-Mode Range

The dynamic range of the AD9777 is optimal when the DAC outputs swing between ±1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components.

Gain/Offset Adjust

The matching of the DAC output to the common-mode input of the AD8345 allows the two components to be dc-coupled, with no level shifting necessary. The combined voltage offset of the two parts can therefore be compensated for via the AD9777 programmable offset adjust. This allows excellent LO cancellation at the AD8345 output. The programmable gain adjust allows for optimal image rejection as well.

The AD9777 evaluation board includes an AD8345 and recommended interface (Figures 59 and 60). On the output of the AD9777, R9 and R10 convert the DAC output current to a voltage. R16 may be used to do a slight common-mode shift if necessary. The (now voltage) signal is applied to a low pass reconstruction filter to reject DAC images. The components installed on the AD9777 provide a 35 MHz cutoff, but may be changed to fit the application. A balun (Mini-Circuits ADTL1-12) is used to cross the ground plane boundary to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, so a single connection between the AD9777 and AD8345 ground planes is recommended.

The performance of the AD9777 and AD8345 in an image reject transmitter, reconstructing three WCDMA carriers, can be seen in Figure 54. The LO of the AD8345 in this application is 800 MHz. Image rejection (50 dB) and LO feedthrough (–78 dBFS) have been optimized with the programmable features of the AD9777. The average output power of the digital waveform for this test was set to –15 dBFS to account for the peak-to-average ratio of the WCDMA signal.

–10

–20

–30

–40

–50

–60

AMPLITUDE – dBm

–70

–80

–90

–100

762.5

782.5 802.5 822.5 842.5 FREQUENCY – MHz

Figure 54. AD9777/AD8345 Synthesizing a Three Carrier WCDMA Signal at an LO of 800 MHz

EVALUATION BOARD

The AD9777 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from either Win95

or Win98®. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9777 in an image reject transmit signal chain.

Figures 55 through 58 describe how to configure the evaluation board in the one and two port input modes with the PLL enabled and disabled. Refer to Figures 59 through 68, the schematics, and the layout for the AD9777 evaluation board for the jumper locations described below. The AD9777 outputs can be configured for various applications by referring to the following instructions.

DAC Single-Ended Outputs

Remove transformers T2 and T3. Solder jumper link JP4 or JP28 to look at the DAC1 outputs. Solder jumper link JP29 or JP30 to look at the DAC2 outputs. Jumpers 8 and 13–17 should remain unsoldered. The jumpers JP35–JP38 may be used to ground one of the DAC outputs while the other is measured single-ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4.

DAC Differential Outputs

Transformers T2 and T3 should be in place. Note that the lower band of operation for these transformers is 300 kHz to 500 kHz. Jumpers 4, 8, 13–17, and 28–30 should remain unsoldered. The outputs are taken from S3 and S4.

Using the AD8345

Remove transformers T2 and T3. Jumpers JP4 and 28–30 should remain unsoldered. Jumpers 13–16 should be soldered. The desired components for the low pass interface filters L6, L7, C55, and C81 should be in place. The LO drive is connected to the AD8345 via J10 and the balun T4, and the AD8345 output is taken from J9.

Win95 and Win98 are a registered trademarks of Microsoft Corporation.

REV. 0–38–

AD9777

INPU T CLOCK

AWG2021

DG2020

LECROY PULSE GENE RATOR

40-PIN RIBBON CABLE

TRIG

INP

DAC1, DB11–DB0

DAC2, DB11–DB0

SIGNAL GENERATOR

CLK+/CLK–DATACLK

AD9777

JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON

SOLDERED/IN UNSOLDERED/OUT JP1 -  JP2 –  JP3 –  JP5 –  JP6 –  JP12 –  JP24 –  JP25 –  JP26 –  JP27 –  JP31 –  JP32 –  JP33 – 

Figure 55. Test Configuration for AD9777 in Two Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency  Interpolation Rate

LECROY PULSE GENE RATOR

INPU T CLOCK

AWG2021

DG2020

JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON

SOLDERED/IN UNSOLDERED/OUT JP1 –  JP2 –  JP3 –  JP5 –  JP6 –  JP12 –  JP24 –  JP25 –  JP26 –  JP27 –  JP31 –  JP32 –  JP33 – 

TRIG

INP

DAC1, DB11–DB0

DAC2, DB11–DB0

SIGNAL GENERATOR

CLK+/CLK–ONEPORTCLK

AD9777

Figure 56. Test Configuration for AD9777 in One Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output



Data Rate = Signal Generator Frequency

Interpolation Rate

REV. 0

–39–

AD9777

INPU T CLOCK

AWG2021

DG2020

LECROY PULSE GENE RATOR

40-PIN RIBBON CABLE

TRIG

INP

DAC1, DB11–DB0

DAC2, DB11–DB0

SIGNAL GENERATOR

CLK+/CLK–DATACLK

AD9777

JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF

SOLDERED/IN UNSOLDERED/OUT JP1 –  JP2 –  JP3 –  JP5 –  JP6 –  JP12 –  JP24 –  JP25 –  JP26 –  JP27 –  JP31 –  JP32 –  JP33 – 

Figure 57. Test Configuration for AD9777 in Two Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate

LECROY PULSE GENE RATOR

INPU T CLOCK

AWG2021

DG2020

JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON

SOLDERED/IN UNSOLDERED/OUT JP1 –  JP2 –  JP3 –  JP5 –  JP6 –  JP12 –  JP24 –  JP25 –  JP26 –  JP27 –  JP31 –  JP32 –  JP33 – 

TRIG

INP

DAC1, DB11–DB0

DAC2, DB11–DB0

SIGNAL GENERATOR

CLK+/CLK–ONEPORTCLK

AD9777

Figure 58. Test Configuration for AD9777 in One Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2 Signal Generator Frequency/Interpolation Rate

REV. 0–40–

AD9777

R36 51

R37

DNP

O1P

L5 DNP

C54

DNP

C73

DNP

J20

O1N

L4 DNP

ADTL1-12

R35

51

C77

100pF

C80

DNP

ETC1-1-13

W11

W12

J7J21

VDDMIN

R30

DNP

C72

10F

VDDM

10V

C35

10F

C75

C32

0.1F

ADTL1-12

C74 100pF

R23 0

J10

VDDM

C78

0.1F

C78

0.1F

R28 0

J10

R26

JP18

1k

LOCAL OSC INPUT

DGND; 3, 4, 5

POWER INPUT FILTERS

L8 FERRITE

C28 22F 16V

VDDMIN

O2P

MODULATED OUTPUT

DGND; 3, 4, 5

L7 DNP

R33 51

R34 DNP

C55

DNP

C81

DNP

J19

O2N

L6 DNP

R32 51

C79 DNP

TP2

C66 22F 16V

C61 22F 16V

C62 22F 16V

RED

TP3

BLK

TP4

RED

TP5

BLK

TP6

RED

TP7

BLK

DVDD_IN

AGND

AVDD_IN

AGND

CLKVDD_IN

AGND

L3 FERRITE

C65 22F 16V

L2 FERRITE

C64 22F 16V

L1 FERRITE

C63 22F 16V

C67

0.1F

C68

0.1F

C69

0.1F

J10

J11

Figure 59. AD8345 Circuitry on AD9777 Evaluation Board

DVDD

AVDD

CLKVDD

REV. 0

–41–

AD9777

O1N

O1P

O2N

O2P

AGND;3,4,5

OUT1

R42

456

321

6.3V

49.9

J35

C58, DNP

T1-1T

J15

J13

C58, DNP

J14

J16

C57, DNP

J36

AVDD

C59, DNP

J29

J38

C70, 0.1F

R16, 10

J28

R9, 51

R10, 51

J37

C41

C40

C39

C38

C37

AVDD

0.1F

10F

C14

0.1F

C19

0.1F

C20

0.1F

J30

10F

C15

C17

C18

6.3V

0.1F

AGND;3,4,5

OUT2

456

321

TP8

WHT

TP9

WHT

TP10

WHT

TP11

WHT

R43

49.9 J17

T1-1T

R12, 51

2k

10F

C16

SPCSP

C70, 0.1F

R11, 51

6.3V

0.1F

1k

SPCLK

SPSDI

R17, 10

SPSDO

DVDD

BD00

C21

BD01

10F

6.3V

0.001F

BD02

BD03

BD04

BD05

DVDD

BD06

C22

BD07

10F

6.3V

0.001F

DVDD

CLKVDD

1k

807978777675747372717069686766656463626160595857565554535251504948474645444342

C36

0.1F

VDDA6VDDC1

VSSA10

123456789

C42

0.1F

C11

0.1F

C12

0.1F

10F

6.3V

J22

C13

0.1F

WHT

TP15

VSSA9VSSC1

VDDA5

VDDC2

200

J23

VDDA4

CLKP

VSSA7

VSSA8

CLKN

VSSC2

R38, 10k

J33

T1-1T

ADCLK

VSSA6

IOUT1P

DCLK-PLLL

IOUT2P

IOUT1N

P1D14

P1D15

VDDD1

VSSD1

10111213141516171819202122232425262728293031323334353637383940

AD15

AD14

C26

0.001F

C10

10F

DVDD

AGND;3,4,5

CLKIN

49.9

IOUT2N

P1D12

P1D13

AD13

6.3V

J24

P1D11

AD11

AD12

J25

CX3

74VCX86

VDDA3

P1D10

AD10

CX2

VSSD2

DVDD; 14

CX1

VDDA2

P1D9

VDDD2

AD09

DVDD

AGND; 7

WHT

TP14

R40

J12

VDDA1

FSADJ1

P1D7

P1D8

AD08

C25

0.001F

10F

6.3V

200

AGND;3,4,5

DVDD

FSADJ2

P1D6

AD06

AD07

49.9

DATACLK

REFOUT

P1D5

AD05

RESET

SP-CSB

P1D4

VSSD3

AD04

SP-SDI

SP-CLK

P1D3

VDDD3

AD03

DVDD

C29

0.1F

VSSA1

VSSA2

VSSA3

VSSA4

VSSA5

VSSD6

SP-SDO

P1D1

P1D2

AD02

C24

0.001F

10F

6.3V

P2D0

VDDD6

P1D0

P2D15-IQSEL

AD01

AD00

BD15

Figure 60. AD9777 Clock, Power Supplies, and Output Circuitry

P2D1

P2D2

P2D3

P2D4

P2D12

P2D13

P2D14-OPCLK

VSSD4

BD12

BD13

J26

J32

R39

1k

BD14

J27

J40

AGND;3,4,5

OPCLK_3

P2D5

VSSD5

P2D11

VDDD4

BD11

DVDD

J31

P2D6

VDDD5

P2D10

P2D9

BD10

C23

0.001F

10F

6.3V

OPCLK

P2D7P2D8

BD09

BD08

74VCX86

J34

C45

AD9777

0.01F

AGND;3,4,5

REV. 0–42–

C30

C33

4.7F

0.1F

6.3V

C31

C34

AD9777

0.1F

4.7F

6.3V

C52

C53

4.7F

0.1F

6.3V

DVDD

74VCX86

RP7

DNP

RCON

RP5

50

RCON

CX1

116

DVDD; 14

AGND; 7

AD15

AD14

215

RP1, 22

74VCX86

AD13

314

RP1, 22

CX3

DVDD; 14

AGND; 7

74VCX86

DVDD; 14

AGND; 7

DVDD

74VCX86

DVDD; 14

AGND; 7

74VCX86

DVDD

DVDD; 14

AGND; 7

PRE

111213

CLK

CLR

AGND; 8

DVDD; 16

74LCX112

CX1

AD12

AD11

AD10

AD09

AD08

AD07

AD06

AD05

AD04

AD03

AD02

AD01

AD00

RP8

DNP

DVDD

RCON

413

512

611

710

116

215

314

413

512

611

710

RP1, 22

RP2, 22

RP1, 22

RP2, 22

RP6

50

OPCLK_2

74VCX86

PRE

OPCLK_3

CLK

OPCLK

ADCLK

DVDD; 14

CLR

AGND; 7

74LCX112

RCON

REV. 0

DATA-A

Figure 61. AD9777 Evaluation Board Input (A Channel) and Clock Buffer Circuitry

–43–

R15

220

RIBBON

AD9777

RIBBON

DATA-B

RCON

R221R33R44R55R66R77R88R9

R11R22R33R44R55R66R77R8

DVDD

RP12 50

RCON

R121R13R14R15R16R17R18R1

116

RP3, 22

215

RP3, 22

314

RP3, 22

413

RP3, 22

512

RP3, 22

611

RP3, 22

710

RP3, 22

RP4, 22

116

RP4, 22

215

RP4, 22

314

RP4, 22

413

RP4, 22

512

RP4, 22

611

RP4, 22

710

RP4, 22

RP11

50

R11R22R33R44R55R66R77R8

RCON

DVDD

C43

4.7F

6.3V

C50

0.1F

C44

4.7F

6.3V

C51

0.1F

RP9 DNP

BD15

BD14

BD13

BD12

BD11

BD10

BD09

BD08

BD07

BD06

BD05

BD04

BD03

BD02

BD01

BD00

RP10

DNP

R50 9k

R48 9k

R45 9k

SPCSB

SPCLK

74AC14

AGND; 7 DVDD; 14

12 13

74AC14

AGND; 7 DVDD; 14

10 11

AGND; 7 DVDD; 14

SPSDI

SPSDO

74AC14

AGND; 7 DVDD; 14

74AC14

AGND; 7 DVDD; 14

Figure 62. AD9777 Evaluation Board Input (B Channel) and SPI Port Circuitry

SPI PORT

REV. 0–44–

Figure 63. AD9777 Evaluation Board Components, Top Side

AD9777

REV. 0

Figure 64. AD9777 Evaluation Board Components, Bottom Side

–45–

AD9777

Figure 65. AD9777 Evaluation Board Layout, Layer One (Top)

Figure 66. AD9777 Evaluation Board Layout, Layer Two (Ground Plane)

REV. 0–46–

Figure 67. AD9777 Evaluation Board Layout, Layer Three (Power Plane)

AD9777

REV. 0

Figure 68. AD9777 Evaluation Board Layout, Layer Four (Bottom)

–47–

AD9777

OUTLINE DIMENSIONS

80-Lead, Thermally Enhanced, Thin Plastic Quad Flatpack [TQFP]

(SV-80)

Dimensions shown in millimeters and (inches)

0.75 (0.0295)

0.60 (0.0236)

0.45 (0.0177)

SEATING

PLANE

COPLANARITY

0.15 (0.0059)

0.05 (0.0020)

0.20 (0.0079)

0.09 (0.0035)

1.20 (0.0472) MAX

14.00 (0.5512) SQ

12.00 (0.4724) SQ

PIN 1

TOP VIEW

(PINS DOWN)

0.50 (0.0197) BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-026-ADD

AN APPLICATION NOTE DETAILING THE THERMALLY ENHANCED TQFP CAN BE FOUND AT; www.amkor.com/products/notes_papers/MLF_Appnote_0301.pdf

0.27 (0.0106)

0.22 (0.0087)

0.17 (0.0067)

7

3.5 0

1.05 (0.0413)

1.00 (0.0394)

0.95 (0.0374)

GAGE PLANE

0.25 (0.0098)

BOTTOM

VIEW

C02706–0–5/02(0)

6.00 (0.2362) SQ

–48–

PRINTED IN U.S.A.

REV. 0

Datasheet AD9777EB, AD9777BSV Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

AD9777–SPECIFICATIONS

DC SPECIFICATIONS

DYNAMIC SPECIFICATIONS

DIGITAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

THERMAL CHARACTERISTICS

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

DIGITAL FILTER SPECIFICATIONS

Complex Image Rejection

Complex Modulation

Differential Nonlinearity (DNL)

Gain Error

Glitch Impulse

Group Delay

Impulse Response

Interpolation Filter

Linearity Error (Also Called Integral Nonlinearity or INL)

Monotonicity

Offset Error

Output Compliance Range

Pass Band

Power Supply Rejection

Signal-to-Noise Ratio (SNR)

Spurious-Free Dynamic Range

Settling Time

Stop-Band Rejection

Temperature Drift

Total Harmonic Distortion (THD)

MODE CONTROL (VIA SPI PORT)

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE FOR REGISTER CONTROL

GENERAL OPERATION OF THE SERIAL INTERFACE

INSTRUCTION BYTE

N1, N0

A4, A3, A2, A1, A0

CSB (Pin 56)—Chip Select

SDIO (Pin 54)—Serial Data I/O

SDO (Pin 53)—Serial Data Out

MSB/LSB TRANSFERS

NOTES ON SERIAL PORT OPERATION

DAC OPERATION

1R/2R MODE

CLOCK INPUT CONFIGURATIONS

PROGRAMMABLE PLL

POWER DISSIPATION

ONE/TWO PORT INPUT MODES

ONEPORTCLK DRIVER STRENGTH

PLL DISABLED, TWO PORT MODE

PLL DISABLED, ONE PORT MODE

DIGITAL FILTER MODES

AMPLITUDE MODULATION

MODULATION, NO INTERPOLATION

OPERATIONS ON COMPLEX SIGNALS

COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS

IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS

Region A

Region B

Region C

Region D

APPLYING THE AD9777 OUTPUT CONFIGURATIONS

UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT

DIFFERENTIAL COUPLING USING A TRANSFORMER

DIFFERENTIAL COUPLING USING AN OP AMP

INTERFACING THE AD9777 WITH THE AD8345 QUADRATURE MODULATOR

DAC Compliance Voltage/Input Common-Mode Range

Gain/Offset Adjust

EVALUATION BOARD

DAC Single-Ended Outputs

DAC Differential Outputs

Using the AD8345

OUTLINE DIMENSIONS