Datasheet AD9777 Datasheet (Analog Devices)

Page 1
16-Bit, 160 MSPS 2×/4×/8×
Interpolating Dual TxDAC+

FEATURES

16-bit resolution, 160 MSPS/400 MSPS input/output
data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment
/4, fS/8 digital quadrature modulation capability
f
S
Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPI port Excellent AC performance
SFDR −73 dBc @ 2 MHz to 35 MHz
WCDMA ACPR 71 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thermally enhanced TQFP package

FUNCTIONAL BLOCK DIAGRAM

®
D/A Converter
AD9777

APPLICATIONS

Communications Analog quadrature modulation architecture 3G, multicarrier GSM, TDMA, CDMA systems Broadband wireless, point-to-point microwave radios Instrumentation/ATE

GENERAL DESCRIPTION

The AD97771 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system level options. These options include selectable 2×/4×/8× interpolation filters; f modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface.
1
Protected by U.S. Patent Numbers, 5,568,145; 5,689,257; and 5,703,519.
Other patents pending.
/2, fS/4, or fS/8 digital quadrature
S
(continued on Page 4)
AD9777
HALF­BAND
FILTER1*
DATA
ASSEMBLER
16
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
16
WRITE
SELECT
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
CONTROL
CLOCK OUT
SPI INTERFACE AND
CONTROL REGISTERS
I
LATCH
16
Q
LATCH
MUX
HALF-BAND FILTERS ALSO CAN BE
*
CONFIGURED FOR "ZERO STUFFING ONLY"
/2
HALF-
HALF-
BAND
BAND
FILTER2*
FILTER3*
16
161616
16
16
/2
/2 /2
16
FILTER
BYPASS
COS
SIN
f
/2, 4, 8
DAC
SIN
MUX
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
COS
f
)
(
DAC
PRESCALER
PHASE DETECTOR
AND VCO
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
IDAC
MUX
GAIN DAC
VREF
IDAC
OFFSET
I/Q DAC
GAIN/OFFSET
REGISTERS
DIFFERENTIAL CLK
DAC
IOFFSET
I
OUT
02706-B-001
www.analog.com
Page 2
AD9777

TABLE OF CONTENTS

General Description......................................................................... 4
DATACLK Inversion.................................................................. 30
Products Highlights ..................................................................... 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Definitions of Specifications..................................................... 12
Typical Performance Characteristics ........................................... 13
Mode Control (via SPI Port)..................................................... 18
Register Description................................................................... 20
Functional Description .............................................................. 22
Serial Interface for Register Control........................................ 22
General Operation of the Serial Interface............................... 22
Instruction Byte ..........................................................................23
R/W ..............................................................................................23
DATACLK Driver Strength....................................................... 30
PLL Enabled, One-Port Mode .................................................. 30
ONEPORTCLK Inversion......................................................... 31
ONEPORTCLK Driver Strength.............................................. 31
IQ Pairing.................................................................................... 31
PLL Disabled, Two-Port Mode ................................................. 31
PLL Disabled, One-Port Mode ................................................. 32
Digital Filter Modes ................................................................... 32
Amplitude Modulation.............................................................. 32
Modulation, No Interpolation .................................................. 34
Modulation, Interpolation = 2× ............................................... 35
Modulation, Intermodulation = 4×.......................................... 36
Modulation, Intermodulation = 8×.......................................... 37
Zero Stuffing ............................................................................... 38
Interpolating (Complex Mix Mode) ........................................ 38
N1, N0.......................................................................................... 23
A4, A3, A2, A1, A0....................................................................... 23
Serial Interface Port Pin Descriptions ..................................... 23
MSB/LSB Transfers.....................................................................23
Notes on Serial Port Operation ................................................ 25
DAC Operation ........................................................................... 25
1R/2R Mode ................................................................................ 26
CLOCK Input Configuration ................................................... 26
Programmable PLL .................................................................... 27
Power Dissipation....................................................................... 29
Sleep/Power-Down Modes........................................................ 29
Two Po r t D ata Inp u t Mo d e ....................................................... 29
PLL Enabled, Two-Port Mode ..................................................30
Operations on Complex Signals............................................... 38
Complex Modulation and Image Rejection of Baseband
.......................................................................................... 39
Signals
Image Rejection and Sideband Suppressions of Modulated Carriers
Applying the AD9777 Output Configurations....................... 46
Unbuffered Differential Output, Equivalent Circuit ............. 46
Differential Coupling Using a Transformer............................ 46
Differential Coupling Using an Op Amp................................ 47
Interfacing the AD9777 with the AD8345 Quadrature Modulator
Evaluation Board ........................................................................ 48
Outline Dimensions....................................................................... 58
Ordering Guide .......................................................................... 58
........................................................................................ 41
.................................................................................... 47
Rev. B | Page 2 of 60
Page 3
AD9777
REVISION HISTORY
6/04—Data Sheet Changed from Rev. A to Rev. B.
Changes to DC Specifications ....................................................... 5
Changes to Absolute Maximum Ratings...................................... 8
Changes to DAC Operation Section........................................... 25
Changes to Figure 49, Figure 50, and Figure 51 ........................ 29
Changes to the PLL Enabled, One-Port Mode Section ............ 30
Changes to the PLL Disabled, One-Port Mode Section........... 32
Changes to the Ordering Guide .................................................. 57
Updated the Outline Dimensions............................................... 57
3/03—Data Sheet Changed from Rev. 0 to Rev. A.
Edits to Features .............................................................................. 1
Edits to DC Specifications ............................................................. 3
Edits to Dynamic Specifications.................................................... 4
Edits to Pin Function Descriptions............................................... 7
Edits to Table I............................................................................... 14
Edits to Register Description—Address 02h Section ............... 15
Edits to Register Description—Address 03h Section ............... 16
Edits to Register Description—Address 07h, 0Bh Section ...... 16
Edits to Equation 1........................................................................ 16
Edits to MSB/LSB Transfers Section........................................... 18
Changes to Figure 8 ...................................................................... 20
Edits to Programmable PLL Section........................................... 21
Added new Figure 14.................................................................... 22
Renumbered Figures 15 to 69...................................................... 22
Added Two-Port Data Input Mode Section .............................. 23
Edits to PLL Enabled, Two-Port Mode Section......................... 24
Edits to Figure 19 ......................................................................... 24
Edits to Figure 21 .......................................................................... 25
Edits to PLL Disabled, Two-Port Mode Section ....................... 25
Edits to Figure 22 .......................................................................... 25
Edits to Figure 23 .......................................................................... 26
Edits to Figure 26a ........................................................................ 27
Changes to Figures 53 and 54...................................................... 38
Edits to Evaluation Board Section .............................................. 39
Changes to Figures 56 to 59......................................................... 40
Replaced Figures 60 to 69 ............................................................ 42
Updated Outline Dimensions...................................................... 49
7/02—Revision 0: Initial Version
Rev. B | Page 3 of 60
Page 4
AD9777

GENERAL DESCRIPTION

(continued from Page 1) The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.
The AD9777 features the ability to perform f digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9777 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (i.e., the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.
The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data.
Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9777 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.
/2, fS/4, and fS/8
S

PRODUCTS HIGHLIGHTS

1. The AD9777 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family.
2. Direct IF transmission is possible for 70 MHz + IFs through a novel digital mixing process.
/2, fS/4, and fS/8 digital quadrature modulation and user
3. f
S
selectable image rejection simplify/remove cascaded SAW filter stages.
4. A 2×/4×/8× user selectable interpolating filter eases data rate and output signal reconstruction filter requirements.
5. User selectable twos complement/straight binary data coding.
6. User programmable channel gain control over 1 dB range in 0.01 dB increments.
7. User programmable channel offset control ±10% over the FSR.
8. Ultrahigh speed 400 MSPS DAC conversion rate.
9. Internal clock divider provides data rate clock for easy interfacing.
10. Flexible clock input with single-ended or differential input, CMOS, or 1 V p-p LO sine wave input capability.
11. Low power: Complete CMOS DAC operates on 1.2 W from a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation, and several sleep functions are provided to reduce power during idle periods.
12. On-chip voltage reference: The AD9777 includes a 1.20 V temperature compensated band gap voltage reference.
13. An 80-lead thermally enhanced TQFP.
Targeted at wide dynamic range, multicarrier, and multistandard systems, the superb baseband performance of the AD9777 is ideal for wideband CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high-order QAM modulation schemes. The image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.
Rev. B | Page 4 of 60
Page 5
AD9777

SPECIFICATIONS

T
to T
MIN
Table 1. DC Specifications
Parameter Min Typ Max Unit
RESOLUTION 16 Bits
DC Accuracy
ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
Offset Error −0.025 ±0.01 +0.025 % of FSR Gain Error (with Internal Reference) −1.0 +1.0 % of FSR Gain Matching −1 ±0.1 +1 % of FSR Full-Scale Output Current Output Compliance Range −1.0 +1.25 V Output Resistance 200 kΩ Output Capacitance 3 pF Gain, Offset Cal DACs, Monotonicity Guaranteed
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V Reference Output Current
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V Reference Input Resistance 7 kΩ Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C Gain Drift (with Internal Reference) 50 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
AVDD
CLKVDD (PLL OFF)
CLKVDD (PLL ON)
DVDD
Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V
OPERATING RANGE −40 +85 °C
1
Measured at I
2
Nominal full-scale current, I
3
Use an external amplifier to drive any external load.
4
100 MSPS f
5
400 MSPS f
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I
MAX
1
= 20 mA, unless otherwise noted.
OUTFS
Integral Nonlinearity ±6 LSB Differential Nonlinearity −6.5 ±3 +6.5 LSB
2
3
2 20 mA
100 nA
Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I I
in SLEEP Mode 23.3 26 mA
AVDD
AVDD
4
)
72.5 76 mA
Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I
Clock Supply Current (I
)4 8.5 10.0 mA
CLKVDD
) 23.5 mA
CLKVDD
Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I
)4 34 41 mA
DVDD
Nominal Power Dissipation4 380 410 mW
5
P
DIS
P
in PWDN 6.0 mW
DIS
driving a virtual ground.
OUTA
with f
DAC
OUT
, f
= 50 MSPS, fS/2 modulation, PLL enabled.
DAC
DATA
, is 32× the I
OUTFS
= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
current.
REF
1.75 W
Rev. B | Page 5 of 60
Page 6
AD9777
T
to T
MIN
transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.
Table 2. Dynamic Specifications
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (f Output Settling Time (tST) (to 0.025%) 11 ns Output Rise Time (10% to 90%) Output Fall Time (10% to 90%)1 0.8 ns Output Noise (I
AC LINEARITY—BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (f
Spurious-Free Dynamic Range within a 1 MHz Window
Two-Tone Intermodulation (IMD) to Nyquist (f
Total Harmonic Distortion (THD)
Signal-to-Noise Ratio (SNR)
Adjacent Channel Power Ratio (ACPR)
Four-Tone Intermodulation
AC LINEARITY—IF MODE
Four-Tone Intermodulation at IF = 200 MHz
1
Measured single-ended into 50 Ω load.
, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I
MAX
) 400 MSPS
DAC
1
= 20 mA) 50 pA/√Hz
OUTFS
= 0 dBFS)
OUT
f
= 100 MSPS, f
DATA
f
= 65 MSPS, f
DATA
f
= 65 MSPS, f
DATA
f
= 78 MSPS, f f
DATA
f
= 78 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 0 dBFS, f
OUT
f
= 65 MSPS, f
DATA
f
= 65 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 160 MSPS, f
DATA
f
= 100 MSPS, f
DATA
f
= 78 MSPS, f
DATA
f
= 160 MSPS, f
DATA
= 1 MHz 71 85 dBc
OUT
= 1 MHz 85 dBc
OUT
= 15 MHz 84 dBc
OUT
= 1 MHz 85 dBc
OUT
= 15 MHz 83 dBc
OUT
= 1 MHz 85 dBc
OUT
= 15 MHz 83 dBc
OUT
= 100 MSPS, f
DATA
= 10 MHz; f
OUT1
= 20 MHz; f
OUT1
= 10 MHz; f
OUT1
= 20 MHz; f
OUT1
= 10 MHz; f
OUT1
= 20 MHz; f
OUT1
= 1 MHz; 0 dBFS −71 −83 dB
OUT
= 5 MHz; 0 dBFS 79 dB
OUT
= 5 MHz; 0 dBFS 75 dB
OUT
= 1 MHz 73 99.1 dBc
OUT
= f
OUT1
= 11 MHz 85 dBc
OUT2
= 21 MHz 78 dBc
OUT2
= 11 MHz 85 dBc
OUT2
= 21 MHz 78 dBc
OUT2
= 11 MHz 85 dBc
OUT2
= 21 MHz 84 dBc
OUT2
= –6 dBFS)
OUT2
= 20 mA, Interpolation = 2×, differential
OUTFS
0.8 ns
WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing IF = Baseband, f IF = 19.2 MHz, f
21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f
201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f
= 76.8 MSPS 73 dBc
DATA
= 76.8 MSPS 73 dBc
DATA
= MSPS, Missing Center) 76 dBFS
DATA
= 160 MSPS, f
DATA
= 320 MHz) 72 dBFS
DAC
Rev. B | Page 6 of 60
Page 7
AD9777
T
to T
MIN
Table 3. Digital Specifications
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current –10 +10 µA Logic 0 Current –10 +10 µA Input Capacitance 5 pF
CLOCK INPUTS
Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V
SERIAL CONTROL BUS
Maximum SCLK Frequency (f Mimimum Clock Pulse Width High (t Mimimum Clock Pulse Width Low (t Maximum Clock Rise/Fall Time 1 ms Minimum Data/Chip Select Setup Time (tDS) 25 ns Minimum Data Hold Time (tDH) 0 ns Maximum Data Valid Time (tDV) 30 ns RESET Pulse Width 1.5 ns
Inputs (SDI, SDIO, SCLK, CSB)
Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 µA Logic 0 Current −10 +10 µA Input Capacitance 5 pF
SDIO Output
Logic 1 Voltage DRVDD – 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA
, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I
MAX
) 15 MHz
SLCK
) 30 ns
PWH
) 30 ns
PWL
= 20 mA, unless otherwise noted.
OUTFS
Rev. B | Page 7 of 60
Page 8
AD9777
Digital Filter Specifications
Table 4. Half-Band Filter No. 1 (43 Coefficients)
Tap Coefficient
1, 43 8 2, 42 0 3, 41 −29 4, 40 0 5, 39 67 6, 38 0 7, 37 −134 8, 36 0 9, 35 244 10, 34 0 11, 33 −414 12, 32 0 13, 31 673 14, 30 0 15, 29 −1,079 16, 28 0 17, 27 1,772 18, 26 0 19, 25 −3,280 20, 24 0 21, 23 10,364 22 16,384
Table 5. Half-Band Filter No. 2 (19 Coefficients)
Tap Coefficient
1, 19 19 2, 18 0 3, 17 −120 4, 16 0 5, 15 438 6, 14 0 7, 13 −1,288 8, 12 0 9, 11 5,047 10 8,192
Table 6. Half-Band Filter No. 3 (11 Coefficients)
Tap Coefficient
1, 11 7 2, 10 0 3, 9 −53 4, 8 0 5, 7 302 6 512
ATTENUATION (dBFS)
ATTENUATION (dBFS)
ATTENUATION (dBFS)
–20
–40
–60
–80
–100
–120
–20
–40
–60
–80
–100
–120
–20
–40
–60
–80
–100
–120
20
0
0.50 1.0 1.5 2.0
f
(NORMALIZED TO INPUT DATA RATE)
OUT
02706-B-003
Figure 2. 2× Interpolating Filter Response
20
0
0.50 1.0 1.5 2.0
f
(NORMALIZED TO INPUT DATA RATE)
OUT
02706-B-004
Figure 3. 4× Interpolating Filter Response
20
0
20468
f
(NORMALIZED TO INPUT DATA RATE)
OUT
02706-B-005
Figure 4. 8× Interpolating Filter Response
Rev. B | Page 8 of 60
Page 9
AD9777

ABSOLUTE MAXIMUM RATINGS

Table 7.
Parameter With Respect To Min Max Unit
AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 AVDD + 0.3 V I
, I
OUTA
OUTB
P1B15 to P1B0, P2B15 to P2B0 DGND −0.3 DVDD + 0.3 V DATACLK/PLL_LOCK DGND −0.3 DVDD + 0.3 V CLK+, CLK–, RESET CLKGND −0.3 CLKVDD + 0.3 V LPF CLKGND −0.3 CLKVDD + 0.3 V SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 DVDD + 0.3 V Junction Temperature 125 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
AGND −1.0 AVDD + 0.3 V

THERMAL CHARACTERISTICS

Thermal Resistance
80-Lead Thermally Enhanced TQFP
= 23.5°C/W (With thermal pad soldered to PCB)
θ
JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 9 of 60
Page 10
AD9777

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTA1IOUTA2IOUTB2
AGND
AGND
OUTB1
AGND
AGND
I
I
AD9777
TxDAC+
TOP VIEW
(Not to Scale)
AGND
CLKVDD
LPF CLKVDD CLKGND
CLK+ CLK–
CLKGND
DATACLK/PLL_LOCK
DGND
DVDD
P1B15 (MSB)
P1B14 P1B13 P1B12 P1B11 P1B10
DGND
DVDD
P1B9 P1B8
AVDD
AVDD
AVDD
AGND
PIN 1 IDENTIFIER
AGND
80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AGND
AVDD
AGND
AVDD
AGND
AVDD
60
FSADJ1
59
FSADJ2
58
REFIO
57
RESET
56
SPI_CSB
55
SPI_CLK
54
SPI_SDIO
53
SPI_SDO
52
DGND
51
DVDD
50
P2B0 (LSB)
49
P2B1
48
P2B2
47
P2B3
46
P2B4
45
P2B5
44
DGND
43
DVDD
42
P2B6
41
P2B7
P1B7
P1B6
P1B5
P1B4
P1B3
P1B2
DVDD
DGND
P1B1
DGND
P2B13
P2B12
DVDD
P2B9
P2B8
P2B11
P2B10
P1B0 (LSB)
IQSEL/P2B15 (MSB)
ONEPORTCLK/P2B14
02706-B-002
Figure 5. Pin Configuration
Rev. B | Page 10 of 60
Page 11
AD9777
Table 8. Pin Function Description
Pin No. Mnemonic Description
1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK− Differential Clock Input. 8 DATACLK/PLL_LOCK
9, 17, 25,
DGND Digital Common.
35, 44, 52 10, 18, 26,
DVDD Digital Supply Voltage.
36, 43, 51 11 to 16, 19
P1B15 (MSB) to P1B0 (LSB) Port 1 Data Inputs. to 24, 27 to 30
31 IQSEL/P2B15 (MSB)
32 ONEPORTCLK/P2B14
33, 34, 37 to
P2B13 to P2B0 (LSB) Port 2 Data Inputs. 42, 45 to 50
53 SPI_SDO
54 SPI_SDIO
55 SPI_CLK
56 SPI_CSB
57 RESET
58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65,
AVDD Analog Supply Voltage. 76, 78, 80
62, 64, 66, 67,
AGND Analog Common. 70, 71, 74, 75, 77, 79
68, 69 I 72, 73 I
OUTB2
OUTB1
, I , I
OUTA2
OUTA1
With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate.
In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock will latch the data into the I channel input register. IQSEL = 0 will latch the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB.
With the PLL disabled and the AD9777 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9777 to accept and demux interleaved I and Q data to the I and Q input registers.
In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For more information, see the Two Port Data Input Mode section.
Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is 0, which sets SDIO as an input.
Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge.
Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle.
Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bits in Address 00h.
Differential DAC Current Outputs, Q Channel. Differential DAC Current Outputs, I Channel.
Rev. B | Page 11 of 60
Page 12
AD9777

DEFINITIONS OF SPECIFICATIONS

Adjacent Channel Power Ratio (ACPR)
A ratio in dBc between the measured power within a channel relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.
Offset Error The deviation of the output current from the ideal of 0 is called offset error. For I are all 0. For I
, 0 mA output is expected when the inputs
OUTA
, 0 mA output is expected when all inputs are
OUTB
set to 1.
Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.
Complex Modulation
The process of passing the real and imaginary components of a
jωt
signal through a complex modulator (transfer function = e
= cosωt + jsinωt) and realizing real and imaginary components on the modulator output.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.
Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.
Group Delay Number of input clocks between an impulse applied at the device input and the peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range.
Impulse Response
Response of the device to an impulse applied to the input.
Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of
(interpolation rate), a digital filter can be constructed that
f
DATA
has a sharp transition band near f typically appear around f
(output data rate) can be greatly
DAC
/2. Images that would
DATA
suppressed.
Pass Band
Frequency band in which any input applied therein passes unattenuated to the DAC output.
Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.
Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.
Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
Stop-Band Rejection The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.
Temperature Drift It is specified as the maximum change from the ambient (25°C) value to the value at either T
MIN
or T
. For offset and gain
MAX
drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.
Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.
Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases.
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).
Rev. B | Page 12 of 60
Page 13
AD9777

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I 50 Ω doubly terminated, unless otherwise noted.
10
0
–10
–20
–30
–40
–50
AMPLITUDE (dBm)
–60
–70
–80
–90
0 65 130
FREQUENCY (MHz)
Figure 6. Single-Tone Spectrum @ f
90
85
80
0dBFS
–6dBFS
= 65 MSPS with f
DATA
OUT
= f
DATA
= 20 mA, Interpolation = 2×, differential transformer-coupled output,
OUTFS
10
0
–10
–20
–30
–40
–50
AMPLITUDE (dBm)
–60
–70
–80
–90
0 10050 150
0dBFS
FREQUENCY (MHz)
= 78 MSPS with f
DATA
/3
02706-B-006
Figure 9. Single-Tone Spectrum @ f
90
85
80
OUT
= f
DATA
02706-B-009
/3
75
70
SFDR (dBc)
65
60
55
50
–12dBFS
Figure 7. In-Band SFDR vs. f
90
85
–12dBFS
80
75
70
–6dBFS
SFDR (dBc)
65
60
55
50
0dBFS
Figure 8. Out-of-Band SFDR vs. f
10 150 5 20 25 30
FREQUENCY (MHz)
@ f
OUT
@ f
DATA
DATA
= 65 MSPS
= 65 MSPS
OUT
10 150 5 20 25 30
FREQUENCY (MHz)
75
70
SFDR (dBc)
65
60
55
50
02706-B-007
–12dBFS
Figure 10. In-Band SFDR vs. f
90
85
80
75
70
SFDR (dBc)
65
60
55
50
02706-B-008
Figure 11. Out-of-Band SFDR vs. f
–6dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
@ f
OUT
DATA
0dBFS
–12dBFS
–6dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
@ f
OUT
= 78 MSPS
= 78 MSPS
DATA
02706-B-010
02706-B-011
Rev. B | Page 13 of 60
Page 14
AD9777
10
0
–10
–20
–30
–40
–50
AMPLITUDE (dBm)
–60
–70
–80
–90
0 200100 300
FREQUENCY (MHz)
Figure 12. Single-Tone Spectrum @ f
90
0dBFS
85
= 160 MSPS with f
DATA
OUT
= f
DATA
90
85
80
–3dBFS
75
70
IMD (dBc)
65
60
55
50
02706-B-012
/3
Figure 15. Third-Order IMD Products vs. Two-Tone f
90
85
0dBFS
–6dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
@ f
= 65 MSPS
OUT
DATA
0dBFS
02706-B-015
80
75
70
SFDR (dBc)
65
60
55
50
01020304050
90
85
80
75
70
SFDR (dBc)
65
0dBFS
60
55
–12dBFS–6dBFS
FREQUENCY (MHz)
Figure 13. In-Band SFDR vs. f
–6dBFS
–12dBFS
OUT
@ f
DATA
= 160 MSPS
80
75
–3dBFS
70
IMD (dBc)
65
60
55
50
02706-B-013
Figure 16. Third-Order IMD Products vs. Two-Tone f
90
85
80
–3dBFS
75
70
IMD (dBc)
65
60
55
–6dBFS
–6dBFS
10 150 5 20 25 30
FREQUENCY (MHz)
@ f
= 78 MSPS
OUT
DATA
0dBFS
02706-B-016
50
01020304050
FREQUENCY (MHz)
@ f
Figure 14. Out-of-Band SFDR vs. f
OUT
= 160 MSPS
DATA
02706-B-014
Figure 17. Third-Order IMD Products vs. Two-Tone f
Rev. B | Page 14 of 60
50
20 300 10 405060
FREQUENCY (MHz)
@ f
OUT
= 160 MSPS
DATA
02706-B-017
Page 15
AD9777
90
85
80
75
70
IMD (dBc)
65
4
×
8
×
1
×
2
×
90
85
80
75
70
IMD (dBc)
65
0dBFS
–3dBFS
–6dBFS
60
55
50
Figure 18. Third-Order IMD Products vs. Two-Tone f
Rate, 1× f
90
85
80
75
70
IMD (dBc)
2×
65
60
55
50
–15 –5–10 0
20 300 10 405060
FREQUENCY (MHz)
OUT
= 160 MSPS,
DATA
= 50 MSPS
1×
4× f
DATA
DATA
= 160 MSPS, 2× f
= 80 MSPS, 8× f
A
(dBFS)
OUT
DATA
Figure 19. Third-Order IMD Products vs. Two-Tone A
Rate, f
= 50 MSPS in All Cases, 1× f
DATA
90
85
4× f
DAC
= 200 MSPS, 8× f
DAC
= 50 MSPS, 2× f
= 400 MSPS
DAC
0dBFS
and Interpolation
8×
4×
and Interpolation
OUT
= 100 MSPS,
DAC
60
55
50
02706-B-018
Figure 21. Third-Order IMD Products vs. AVDD @ f
90
85
80
75
70
SNR (dB)
65
60
55
50
0 10050 150
02706-B-019
90
85
3.23.1 3.3 3.4 3.5 AVDD (V)
f
= 320 MSPS, f
DAC
PLL OFF
PLL ON
INPUT DATA RATE (MSPS)
Figure 22. SNR vs. Data Rate for f
78MSPS
= 160 MSPS
DATA
= 5 MHz
OUT
= 10 MHz,
OUT
02706-B-021
02706-B-022
80
75
70
SFDR (dBc)
65
60
55
50
3.23.1 3.3 3.4 3.5
Figure 20. SFDR vs. AVDD f
AVDD (V)
= 10 MHz, f
OUT
–6dBFS
–12dBFS
= 320 MSPS, f
DAC
= 160 MSPS
DATA
02706-B-020
Rev. B | Page 15 of 60
80
75
70
SFDR (dBc)
65
60
55
50
f
= 65MSPS
DATA
–50 500 100
TEMPERATURE (°C)
Figure 23. SFDR vs. Temperature @ f
OUT
160MSPS
= f
DATA
/11
02706-B-023
Page 16
AD9777
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
0 10050 150
FREQUENCY (MHz)
Figure 24. Single-Tone Spurious Performance, f
f
= 150 MSPS, No Interpolation
DATA
0
–20
–40
–60
AMPLITUDE (dBm)
–80
–100
01020304050
FREQUENCY (MHz)
Figure 25. Two-Tone IMD Performance,
= 150 MSPS, No Interpolation
f
DATA
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
100 1500 50 200 250 300
FREQUENCY (MHz)
Figure 26. Single-Tone Spurious Performance, f
f
= 150 MSPS, Interpolation = 2×
DATA
OUT
OUT
= 10 MHz,
= 10 MHz,
0
–20
–40
–60
AMPLITUDE (dBm)
–80
–100
0 5 10 15 20 25 30 35 40 45
02706-B-024
Figure 27. Two-Tone IMD Performance, f
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
02706-B-025
Figure 28. Single-Tone Spurious Performance, f
0
–20
–40
–60
AMPLITUDE (dBm)
–80
–100
0 5 10 15 20 25
02706-B-026
Figure 29. Two-Tone IMD Performance, f
FREQUENCY (MHz)
= 90 MSPS, Interpolation = 4×
DATA
100 1500 50 200 250 300
FREQUENCY (MHz)
f
= 80 MSPS, Interpolation = 4×
DATA
FREQUENCY (MHz)
f
= 50 MSPS, Interpolation = 8×
DATA
OUT
= 10 MHz,
OUT
= 10 MHz,
02706-B-027
02706-B-028
02706-B-029
Rev. B | Page 16 of 60
Page 17
AD9777
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
1000 200 300 400
FREQUENCY (MHz)
Figure 30. Single-Tone Spurious Performance, f
f
= 50 MSPS, Interpolation = 8×
DATA
= 10 MHz,
OUT
02706-B-030
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
200406080
FREQUENCY (MHz)
Figure 31. Eight-Tone IMD Performance, f
= 160 MSPS, Interpolation = 8x
DATA
02706-B-031
Rev. B | Page 17 of 60
Page 18
AD9777

MODE CONTROL (VIA SPI PORT)

Table 9. Mode Control via SPI Port (Default Values Are Highlighted)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h
SDIO Bidirectional 0 = Input 1 = I/O
LSB, MSB First 0 = MSB 1 = LSB
Software Reset on Logic 1
Sleep Mode Logic 1 shuts down the DAC output currents
01h
02h
Filter Interpolation Rate (1×, 2×, 4×, 8×)
0 = Signed Input Data
1 = Unsigned
Filter Interpolation Rate (1×, 2×, 4×, 8×)
0 = Two-Port Mode
1 = One-Port Mode
Modulation Mode (None, f
/4, fS/8)
f
S
DATACLK Driver Strength
S
/2,
Modulation Mode (None, f
/4, fS/8)
f
S
DATACLK Invert
0 = No Invert
1 = Invert
1
03h
Data Rate Clock Output
04h
0 = PLL
1
OFF
1 = PLL ON
0 = Automatic Charge Pump Control
1 = Programmable
05h
IDAC Fine Gain Adjustment
IDAC Fine Gain Adjustment
IDAC Fine Gain Adjustment
IDAC Fine Gain Adjustment
06h
07h
08h
IDAC Offset Adjustment Bit 9
IDAC I
OFFSET
IDAC Offset Adjustment Bit 8
IDAC Offset Adjustment Bit 7
IDAC Offset Adjustment Bit 6
Direction
OFFSET
OFFSET
B
on
on
QDAC Fine Gain Adjustment
QDAC Fine Gain Adjustment
QDAC Fine Gain Adjustment
09h
0 = I I
OUTA
1 = I I
OUT
QDAC Fine Gain Adjustment
Table 9 continued on next page.
S
/2,
Power-Down Mode Logic 1 shuts down all digital and analog functions.
0 = No Zero Stuffing on Interpolation Filters, Logic 1
enables zero stuffing
IDAC Fine Gain Adjustment
IDAC Coarse Gain Adjustment
IDAC Offset Adjustment Bit 5
QDAC Fine Gain Adjustment
1R/2R Mode DAC output current set by one or two external resistors
0 = 2R, 1 = 1R 1 = Real Mix
Mode
0 = Complex Mix Mode
ONEPORTCLK Invert 0 = No Invert 1 = Invert
PLL Charge Pump Control
IDAC Fine Gain Adjustment
IDAC Coarse Gain Adjustment
IDAC Offset Adjustment Bit 4
QDAC Fine Gain Adjustment
PLL_LOCK Indicator
−jωt
0 = e
+jωt
1 = e
IQSEL Invert
0 = No Invert
1 = Invert PLL Divide
(Prescaler) Ratio
PLL Charge Pump Control
IDAC Fine Gain Adjustment
IDAC Coarse Gain Adjustment
IDAC Offset Adjustment Bit 3
IDAC Offset Adjustment Bit 1
QDAC Fine Gain Adjustment
DATACLK/ PLL_LOCK Select
0 = PLL_LOCK
1 = DATACLK
Q First 0 = I First 1 = Q First
PLL Divide (Prescaler) Ratio
PLL Charge Pump Control
IDAC Fine Gain Adjustment
IDAC Coarse Gain Adjustment
IDAC Offset Adjustment Bit 2
IDAC Offset Adjustment Bit 0
QDAC Fine Gain Adjustment
1
Rev. B | Page 18 of 60
Page 19
AD9777
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0Ah
0Bh
QDAC Offset Adjustment Bit 9
QDAC Offset Adjustment Bit 8
QDAC Offset Adjustment
QDAC Offset Adjustment Bit 6
Bit 7
0Ch
QDAC I
OFFSET
Direction
OFFSET
OFFSET
on
on
0 = I I
OUTA
1 = I I
OUTB
0Dh
1
For more information, see the section. Two Port Data Input Mode
QDAC Coarse Gain Adjustment
QDAC Offset Adjustment Bit 5
Version Register
QDAC Coarse Gain Adjustment
QDAC Offset Adjustment Bit 4
Version Register
QDAC Coarse Gain Adjustment
QDAC Offset Adjustment Bit 3
QDAC Offset Adjustment Bit 1
Version Register
QDAC Coarse Gain Adjustment
QDAC Offset Adjustment Bit 2
QDAC Offset Adjustment Bit 0
Version Register
Rev. B | Page 19 of 60
Page 20
AD9777

REGISTER DESCRIPTION

Address 00h
Bit 3: Logic 1 enables zero stuffing mode for interpolation filters.
Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an
input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or output, depending on Bit 7 of the instruction byte.
Bit 6: Logic 0 (default). Determines the direction (LSB/MSB first) of the communications and data transfer communications cycles. Refer to the MSB/LSB Transfers section for more details.
Bit 5: Writing a 1 to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. Register Address 00h bits are not cleared by this software reset. However, a high level at the RESET pin forces all registers, including those in Address 00h, to their default state.
Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC output currents.
Bit 3: Power-Down. Logic 1 shuts down all analog and digital functions except for the SPI port.
Bit 2: 1R/2R Mode. The default (0) places the AD9777 in two resistor mode. In this mode, the I DAC references are set separately by the R
currents for the I and Q
REF
resistors on
SET
FSADJ2 and FSADJ1 (Pins 59 and 60). In 2R mode, assuming the coarse gain setting is full scale and the fine gain setting is 0, I
FULLSCALE1
V
= 32 × V
/FSADJ2. With this bit set to 1, the reference currents for
REF
/FSADJ1 and I
REF
FULLSCALE2
= 32 ×
both I and Q DACs are controlled by a single resistor on Pin 60. I
in one resistor mode for both the I and Q DACs is half
FULLSCALE
of what it would be in 2R mode, assuming all other conditions
, register settings) remain unchanged. The full-scale
(R
SET
current of each DAC can still be set to 20 mA by choosing a resistor of half the value of the R
value used in 2R mode.
SET
Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading this bit will give the status of the PLL. A Logic 1 indicates the PLL is locked. A Logic 0 indicates an unlocked state.
Address 01h
Bits 7, 6: This is the filter interpolation rate according to the
following table.
00 1× 01 2× 10 4× 11 8×
Bits 5, 4: This is the modulation mode according to the following table.
00 none 01 f 10 f 11 f
/2
S
/4
S
/8
S
Bit 2: Default (1) enables the real mix mode. The I and Q data channels are individually modulated by f
/2, fS/4, or fS/8 after the
S
interpolation filters. However, no complex modulation is done. In the complex mix mode (Logic 0), the digital modulators on the I and Q data channels are coupled to create a digital complex modulator. When the AD9777 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second IF frequency (i.e., the LO of the analog quadrature modulator external to the AD9777) according to the bit value of Register 01h, Bit 1.
Bit 1: Logic 0 (default) causes the complex modulation to be of
−jωt
the form e
, resulting in the rejection of the higher frequency image when the AD9777 is used with an external quadrature modulator. A Logic 1 causes the modulation to be of the form
+jωt
, which causes rejection of the lower frequency image.
e
Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act as a lock indicator for the internal PLL. A Logic 1 in this register causes Pin 8 to act as a DATACLK. For more information, see the Two Port Data Input Mode section.
Address 02h
Bit 7: Logic 0 (default) causes data to be accepted on the inputs
as twos complement binary. Logic 1 causes data to be accepted as straight binary.
Bit 6: Logic 0 (default) places the AD9777 in two-port mode. I and Q data enters the AD9777 via Ports 1 and 2, respectively. A Logic 1 places the AD9777 in one-port mode in which interleaved I and Q data is applied to Port 1. See Table 8 for detailed information on how to use the DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK modes.
Bit 5: DATACLK Driver Strength. With the internal PLL disabled and this bit set to Logic 0, it is recommended that DATACLK be buffered. When this bit is set to Logic 1, DATACLK acts as a stronger driver capable of driving small capacitive loads.
Bit 4: Default Logic 0. A value of 1 inverts DATACLK at Pin 8.
Bit 2: Default Logic 0. A value of 1 inverts ONEPORTCLK
at Pin 32.
Bit 1: The default of Logic 0 causes IQSEL = 0 to direct input data to the I channel, while IQSEL = 1 directs input data to the Q channel.
Bit 0: The default of Logic 0 defines IQ pairing as IQ, IQ, …, while programming a Logic 1 causes the pair ordering to be QI, QI,…
Rev. B | Page 20 of 60
Page 21
AD9777
Address 03h
Bit 7: This allows the data rate clock (divided down from the
DAC clock) to be output at either the DATACLK/PLL_LOCK pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this register will enable the data rate clock at DATACLK/PLL_LOCK, while a 1 in this register will cause the data rate clock to be output at SPI_SDO. For more information, see the Two Port Data Input Mode section.
Bits 1, 0: Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run substantially slower. The divider ratio is set according to the following table.
00 ÷1 01 ÷2 10 ÷4 11 ÷8
Address 04h
Bit 7: Logic 0 (default) disables the internal PLL. Logic 1
enables the PLL.
Bit 6: Logic 0 (default) sets the charge pump control to automatic. In this mode, the charge pump bias current is controlled by the divider ratio defined in Address 03h, Bits 1 and 0. Logic 1 allows the user to manually define the charge pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the PLL.
Bits 2, 1, 0: With the charge pump control set to manual, these bits define the charge pump bias current according to the following table.
000 50 µA 001 100 µA 010 200 µA 011 400 µA 111 800 µA
Address 05h, 09h
Bits 7 to 0: These bits represent an 8-bit binary number (Bit 7
MSB) that defines the fine gain adjustment of the I (05h) and Q (09h) DAC according to Equation 1.
Address 06h, 0Ah
Bits 3 to 0: These bits represent a 4-bit binary number (Bit 3
MSB) that defines the coarse gain adjustment of the I (06h) and Q (0Ah) DACs according to Equation 1.
Address 07h, 0Bh
Bits 7 to 0: These bits are used in conjunction with Address 08h,
0Ch, Bits 1, 0.
Address 08h, 0Ch
Bits 1, 0: The 10 bits from these two address pairs (07h, 08h and
0Bh, 0Ch) represent a 10-bit binary number that defines the offset adjustment of the I and Q DACs according to Equation 1. (07h, 0Bh–Bit 7 MSB/08h, 0Ch–Bit 0 LSB).
Address 08h, 0Ch
Bit 7: This bit determines the direction of the offset of the I
(08h) and Q (0Ch) DACs. A Logic 0 will apply a positive offset current to I current to I
, while a Logic 1 will apply a positive offset
OUTA
. The magnitude of the offset current is defined
OUTB
by the bits in Addresses 07h, 0Bh, 08h, 0Ch according to Equation 1. Equation 1 shows I
OUTA
and I
as a function of
OUTB
fine gain, coarse gain, and offset adjustment when using 2R mode. In 1R mode, the current I
is created by a single FSADJ resistor
REF
(Pin 60). This current is divided equally into each channel so that a scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.
I
OUTA
I
OUTB
OFFSET
×
3
1
⎜ ⎝
1
⎜ ⎝
REFREF
25632
×
3
REFREF
25632
×
⎣ ⎡
×
Rev. B | Page 21 of 60
16
16
+
+
)(
A
⎟ ⎠
6
×
=
6
=
×=
4
×
8
II
8
REF
⎟ ⎠
⎟ ⎠
OFFSET
⎛ ⎜
1024
1024
24
1024
24
DATAFINEICOARSEI
⎟ ⎠
⎝ ⎛
A
)(
16
2
16
DATAFINEICOARSEI
16
2
12
(1)
)(
A
Page 22
AD9777

FUNCTIONAL DESCRIPTION

The AD9777 dual interpolating DAC consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9777 capable of 2×, 4× or 8× interpolation. High speed input and output data rates can be achieved within the following limitations.
Interpolation Rate (MSPS)
1× 160 160 2× 160 320 4× 100 400 8× 50 400
Both data channels contain a digital modulator capable of mixing the data stream with an LO of f where f
is the output data rate of the DAC. A zero stuffing
DAC
feature is also included and can be used to improve pass-band flatness for signals being attenuated by the SIN(x)/x characteristic of the DAC output. The speed of the AD9777, combined with its digital modulation capability, enables direct IF conversion architectures at 70 MHz and higher.
The digital modulators on the AD9777 can be coupled to form a complex modulator. By using this feature with an external analog quadrature modulator, such as the Analog Devices AD8345, an image rejection architecture can be enabled. To optimize the image rejection capability, as well as LO feedthrough in this architecture, the AD9777 offers program­able (via the SPI port) gain and offset adjust for each DAC.
Also included on the AD9777 are a phase-locked loop (PLL) clock multiplier and a 1.20 V band gap voltage reference. With the PLL enabled, a clock applied to the CLK+/CLK− inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. Each 16-bit DAC provides two complementary current outputs whose full-scale currents can be determined either from a single external resistor or independently from two separate resistors (see the 1R/2R Mode section). The AD9777 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square wave input. Separate voltage supply inputs are provided for each functional block to ensure optimum noise and distortion performance.
Sleep and power-down modes can be used to turn off the DAC output current (sleep) or the entire digital and analog sections (power-down) of the chip. An SPI compliant serial port is used to program the many features of the AD9777. Note that in power-down mode, the SPI port is the only section of the chip still active.
Input Data Rate (MSPS)
DAC Sample Rate (MSPS)
/2, f
DAC
/4, or f
DAC
DAC
/8,
SDO (PIN 53)
SDIO (PIN 54)
SCLK (PIN 55)
CSB (PIN 56)
AD9777 SPI PORT
INTERFACE
Figure 32. SPI Port Interface
02706-B-032

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9777 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9777. Single- or multiple-byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9777’s serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9777. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9777 coincident with the first eight SCLK rising edges. The instruction byte provides the AD9777 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9777.
A Logic 1 on the SPI_CSB pin, followed by a logic low, will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the middle of an instruction cycle or a data transfer cycle, none of the present data will be written.
The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9777 and the system controller. Phase 2 of the communication cycle is a transfer of one to four data bytes, as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.
Rev. B | Page 22 of 60
Page 23
AD9777

INSTRUCTION BYTE

The instruction byte contains the information shown below.
N1 N0 Description
0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes
R/W
Bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic 1 indicates read operation. Logic 0 indicates a write operation.
SPI_CSB (Pin 56)—Chip Select
Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SPI_SDO and SPI_SDIO pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.
SPI_SDIO (Pin 54)—Serial Data I/O
Data is always written into the AD9777 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 00h. The default is Logic 0, which configures the SPI_SDIO pin as unidirectional.

N1, N0

Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the following table.
MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0 R/W N1 N0 A4 A3 A2 A1 A0

A4, A3, A2, A1, A0

Bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9777.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SPI_CLK (Pin 55)—Serial Clock
The serial clock pin is used to synchronize data to and from the AD9777 and to run the internal state machines. SPI_CLK maximum frequency is 15 MHz. All data input to the AD9777 is registered on the rising edge of SPI_CLK. All data is driven out of the AD9777 on the falling edge of SCLK.
SPI_SDO (Pin 53)—Serial Data Out
Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9777 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.

MSB/LSB TRANSFERS

The AD9777 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB first bit in Register 0. The default is MSB first.
When this bit is set active high, the AD9777 serial port is in LSB first format. In LSB first mode, the instruction byte and data bytes must be written from LSB to MSB. In LSB first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle.
When this bit is set default low, the AD9777 serial port is in MSB first format. In MSB first mode, the instruction byte and data bytes must be written from MSB to LSB. In MSB first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle.
When incrementing from 1Fh, the address generator changes to 00h. When decrementing from 00h, the address generator changes to 1Fh.
Rev. B | Page 23 of 60
Page 24
AD9777
SCLK
S
CS
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SDIO
SDO
I6
R/W I4 I3 I2 I1 I0 D7
(N)I5(N)
N
D7ND6
D6
N
N
D20D10D0
D20D10D0
0
0
02706-B-033
Figure 33. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS
CLK
SDIO
SDO
I0 I1 I2 I3 I4 I5
(N)I6(N)
R/W D00D10D2
D00D10D2
0
0
D6ND7
D6ND7
N
N
02706-B-034
Figure 34. Serial Register Interface Timing LSB First
t
PWH
t
SCLK
t
PWL
CS
t
DS
SCLK
SDIO
t
DS
INSTRUCTION BIT 7 INSTRUCTION BIT 6
t
DH
T
02706-B-035
Figure 35. Timing Diagram for Register Write to AD9777
CS
SCLK
t
DV
SDIO
DATA BIT N
SDO
DATA BIT N–1
02706-B-036
Figure 36. Timing Diagram for Register Read from AD9777
Rev. B | Page 24 of 60
Page 25
AD9777
8

NOTES ON SERIAL PORT OPERATION

The AD9777 serial port configuration bits reside in Bits 6 and 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle.
The same considerations apply to setting the reset bit in Register Address 00h. All other registers are set to their default values, but the software reset doesn’t affect the bits in Register Address 00h.
The offset control defines a small current that can be added to
or I
I
OUTA
of which I
(not both) on the IDAC and QDAC. The selection
OUTB
this offset current is directed toward is
OUT
programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch, Bit 7 (QDAC). Figure 42 shows the scale of the offset current that can be added to one of the complementary outputs on the IDAC and QDAC. Offset control can be used for suppression of LO leakage resulting from modulation of dc signal components. If the AD9777 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9777 as well as the input offset on the modulator. Figure 42 shows a typical example of the effect that the offset control has on LO suppression.
It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset.
A write to Bits 1, 2, and 3 of Address 00h with the same logic levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 00h with reset bit low and serial port configuration as specified above (XY) reprograms the OSC IN multiplier setting. A changed f
cycles (equals wake-up time).
f
MCLK
frequency is stable after a maximum of 200
SYSCLK

DAC OPERATION

The dual 16-bit DAC output of the AD9777, along with the reference circuitry, gain, and offset registers, is shown in Figure 37 and Figure 38. Note that an external reference can be used by simply overdriving the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external R The fine gain DAC subtracts a small amount from this and the result is input to IDAC and QDAC, where it is scaled by an amount equal to 1024/24. Figure 39 and Figure 40 show the scaling effect of the coarse and fine adjust DACs. IDAC and QDAC are PMOS current source arrays, segmented in a 5-4-7 configuration. The five MSB control an array of 31 current sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current source. The seven LSB are binary weighted fractions of the middle bits’ current sources. All current sources are switched to either I depending on the input code.
The fine adjustment of the gain of each channel allows for improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. In the Interfacing the AD9777 with the AD8345 Quadrature Modulator section, the performance data shows to what degree image rejection can be improved when the AD9777 is used with an AD8345 quadrature modulator from Analog Devices, Inc.
resistor, and the values in the coarse gain register.
SET
or I
OUTA
OUTB
OFFSET
OFFSET
OFFSET
DAC
OFFSET
DAC
I
OUTA1
I
OUTB1
I
OUTA2
I
OUTB2
02706-B-037
GAIN
CONTROL
REGISTERS
1.2VREF
REFIO
0.1µF
FSADJ1
RSET1
FINE GAIN
DAC
FINE GAIN
DAC
COARSE
GAIN
FSADJ2
RSET2
DAC
COARSE
GAIN
DAC
GAIN
CONTROL
REGISTERS
CONTROL
REGISTERS
IDAC
QDAC
CONTROL
REGISTERS
Figure 37. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust.
AVDD
4µA
REFIO
7k
0.7V
02706-B-038
Figure 38. Internal Reference Equivalent Circuit
25
20
,
15
10
5
COARSE REFERENCE CURRENT (mA)
0
2R MO DE
1R MODE
50101520 COARSE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9k
Figure 39. Coarse Gain Effect on I
)
FULLSCALE
02706-B-039
Rev. B | Page 25 of 60
Page 26
AD9777
V
0
0
–0.5
–1.0
–1.5
–2.0
FINE REFERENCE CURRENT (mA)
–2.5
–3.0
0
200 400 600 800 1000
FINE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9k
Figure 40. Fine G ain Effec t on I
1R MODE
2R MODE
FULLSCALE
)
In Figure 42, the negative scale represents an offset added to I
, while the positive scale represents an offset added to I
OUTB
OUTA
of the respective DAC. Offset Register 1 corresponds to IDAC, while Offset Register 2 corresponds to QDAC. Figure 42 represents the AD9777 synthesizing a complex signal that is then dc-coupled to an AD8345 quadrature modulator with an LO of 800 MHz. The dc coupling allows the input offset of the AD8345 to be calibrated out as well. The LO suppression at the AD8345 output was optimized first by adjusting Offset Register 1 in the AD9777. When an optimal point was found (roughly Code 54), this code was held in Offset Register 1, and Offset Register 2 was adjusted. The resulting LO suppression is 70 dBFS. These are typical numbers, and the specific code for optimization will vary from part to part.
5
4
–10
–20
–30
–40
–50
LO SUPPRESSION (dBFS)
–60
–70
–80
02706-B-040
DAC1, DAC2 (OFFSET REGISTER CODES)
Figure 42. Offset Adjust Control, Effect on LO Suppression
OFFSET REGISTER 1 ADJUSTED
OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE
0–256–768 –512–1024 256 512 768 1024
02706-B-042

1R/2R MODE

In 2R mode, the reference current for each channel is set independently by the FSADJ resistor on that channel. The AD9777 can be programmed to derive its reference current from a single resistor on Pin 60 by putting the part into 1R mode. The transfer functions in Equation 1 are valid for 2R mode. In 1R mode, the current developed in the single FSADJ resistor is split equally between the two channels. The result is that in 1R mode, a scale factor of 1/2 must be applied to the formulas in Equation 1. The full-scale DAC current in 1R mode can still be set to as high as 20 mA by using the internal 1.2 V reference and a 950 Ω resistor instead of the 1.9 kΩ resistor typically used in 2R mode.

CLOCK INPUT CONFIGURATION

The clock inputs to the AD9777 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources.
3
Figure 43 shows the AD9777 driven from a single-ended clock source. The CLK+/CLK− pins form a differential input
2
OFFSET CURRENT (mA)
1
0
0 200 400 600 800 1000
0
COARSE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9k
2R MODE
Figure 41. DAC Output Offset Current
1R MODE
)
02706-B-041
(CLKIN) so that the statically terminated input must be dc­biased to the midswing voltage level of the clock driven input.
AD9777
R
SERIES
THRESHOLD
0.1µF
Figure 43. Single-Ended Clock Driving Clock Inputs
CLK+
CLKVDD
CLK–
CLKGND
02706-B-043
Rev. B | Page 26 of 60
Page 27
AD9777
(
=
A configuration for differentially driving the clock inputs is given in Figure 44. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed CLKVDD or CLKGND. If the driver voltage swings are within the supply range of the AD9777, the dc-blocking capacitors and bias resistors are not necessary.
AD9777
1k
1k
1k
1k
CLK+
CLKVDD
CLK–
CLKGND
02706-B-044
ECL/PECL
0.1µF
0.1µF
0.1µF
Figure 44. Differential Clock Driving Clock Inputs
A transformer, such as the T1-1T from Mini-Circuits, can also be used to convert a single-ended clock to differential. This method is used on the AD9777 evaluation board so that an external sine wave with no dc offset can be used as a differential clock.
PECL/ECL drivers require varying termination networks, the details of which are left out of Figure 43 and Figure 44 but can be found in application notes such as AND8020/D from On Semiconductor. These networks depend on the assumed transmission line impedance and power supply voltage of the clock driver. Optimum performance of the AD9777 is achieved when the driver is placed very close to the AD9777 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch.
The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry should provide the AD9777 with a low jitter clock input that meets the minimum/maximum logic levels while providing fast edges. Although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain bandwidth product of the AD9777’s clock input comparator can tolerate differential sine wave inputs as low as 0.5 V p-p, with minimal degradation of the output noise floor.

PROGRAMMABLE PLL

CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled) according to the state of Address 02h, Bit 7 in the SPI port register. The internal operation of the AD9777 clock circuitry in these two modes is illustrated in Figure 45 and Figure 46.
The PLL clock multiplier and distribution circuitry produce the necessary internal synchronized 1×, 2×, 4×, and 8× clocks for the rising edge triggered latches, interpolation filters, modulators, and DACs. This circuitry consists of a phase dete ctor, charge pump, voltage controlled osci llator (VCO), prescaler, clock distribution, and SPI port control. The charge pump,VCO, differential clock input buffer, phase detector, prescaler, and clock distribution are all powered from CLKVDD. PLL lock status is indicated by the logic signal at the PLL_LOCK pin, as well as by the status of Bit 1, Register 00h. To ensure optimum phase noise performance from the PLL clock multiplier and distribution, CLKVDD should originate from a clean analog supply. Table 10 defines the minimum input data rates versus the interpolation and PLL divider setting. If the input data rate drops below the defined minimum under these conditions, VCO phase noise may increase significantly. The VCO speed is a function of the input data rate, the interpolation rate, and the VCO prescaler, according to the following function:
)
INPUT
DATA
LATCHES
INTERPOLATION
RATE
CONTROL
MHzSpeedVCO
()
CLK+ CLK–
PLL_LOCK
1 = LOCK
0 = NO LOCK
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2148
CLOCK
DISTRIBUTION
CIRCUITRY
INTERNAL SPI
CONTROL
REGISTERS
MODULATION
SPI PORT
RATE
CONTROL
Figure 45. PLL and Clock Circuitry with PLL Enabled
AD9777
PHASE
DETECTOR
PRESCALER VCO
CONTROL
(PLL ON)
PrescalerRateionInterpolatMHzRateDataInput
××
PLLVDD
CHARGE
PUMP
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
LPF
02706-B-045
Rev. B | Page 27 of 60
Page 28
AD9777
CLK+ CLK–
PLL_LOCK
1 = LOCK
0 = NO LOCK
INPUT
DATA
LATCHES
INTERPOLATION
RATE
CONTROL
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2148
CLOCK
DISTRIBUTION
CIRCUITRY
INTERNAL SPI
CONTROL
REGISTERS
SPI PORT
MODULATION
PHASE
DETECTOR
PRESCALER VCO
RATE
CONTROL
Figure 46. PLL and Clock Circuitry with PLL Disabled
In addition, if the zero stuffing option is enabled, the VCO will double its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 47 illustrates typical phase noise performance of the AD9777 with 2× interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of f
/4. The repetitive nature of this signal
DATA
eliminates quantization noise and distortion spurs as a factor in the measurement. Although the curves blend together in Figure 47, the different conditions are given for clarity in the table above Figure 47. Figure 47 also contains a table detailing PLL divider settings versus interpolation rate and maximum and minimum f maximum f
rates of 160 MSPS are due to the maximum input
DATA
data rate of the AD9777. However, maximum rates of less than 160 MSPS and all minimum f
rates are due to maximum and
DATA
minimum speeds of the internal PLL VCO. Figure 48 shows typical performance of the PLL lock signal (Pin 8 or 53) when the PLL is in the process of locking.
Table 10. PLL Optimization
Interpolation Rate
Divider Setting
Minimum f
DATA
1 1 32 160 1 2 16 160 1 4 8 112 1 8 4 56 2 1 24 160 2 2 12 112 2 4 6 56 2 8 3 28 4 1 24 100 4 2 12 56 4 4 6 28 4 8 3 14 8 1 24 50 8 2 12 28 8 4 6 14 8 8 3 7
AD9777
CHARGE
PUMP
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
CONTROL
(PLL ON)
DATA
rates. Note that
Maximum f
DATA
02706-B-046
Table 11. Required PLL Prescaler Ration vs. f
f
(MSPS) PLL Prescaler Ratio
DATA
DATA
125 Disabled 125 Enabled div 1 100 Enabled div 2 75 Enabled div 2 50 Enabled div 4
0 –10 –20 –30 –40 –50 –60 –70
PHASE NOISE (dBFS)
–80 –90
–100 –110
012345
FREQUENCY OFFSET (MHz)
Figure 47. Phase Noise Performance
Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking
(Typical Lock Time)
It is important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9777. This will suffice unless the input data rate is below 10 MHz, in which case an external series RC is required between the and CLKVDD pins.
02706-B-047
02706-B-048
Rev. B | Page 28 of 60
Page 29
AD9777

POWER DISSIPATION

The AD9777 has three voltage supplies: DVDD, AVDD, and CLKVDD. Figure 49, Figure 50, and Figure 51 show the current required from each of these supplies when each is set to the
3.3 V nominal specified for the AD9777. Power dissipation (P can easily be extracted by multiplying the given curves by 3.3. As Figure 49 shows, I
is very dependent on the input data
DVDD
rate, the interpolation rate, and the activation of the internal digital modulator. I modulation rate by itself. In Figure 50, I
, however, is relatively insensitive to the
DVDD
shows the same
AVD D
type of sensitivity to data, interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 51,
varies over a wide range yet is responsible for only a
I
CLKVDD
small percentage of the overall AD9777 supply current requirement.
(mA)
DVDD
I
400
350
300
250
200
150
100
50
0
Figure 49. I
8×, (MOD. ON)
4×, (MOD. ON)
8× 4×
500 100 150 200
f
(MHz)
DATA
vs. f
DVDD
vs. Interpolation Rate, PLL Disabled
DATA
2×, (MOD. ON)
2×
1×
76.0
75.5
75.0
74.5
(mA)
74.0
AVDD
I
73.5
73.0
72.5
8×, (MOD. ON)
8×
4×, (MOD. ON)
2×, (MOD. ON)
4×
2×
1×
D
35
30
25
)
(mA)
CLKVDD
I
20
15
10
5
0
Figure 51. I
8×
4×
500 100 150 200
f
(MHz)
DATA
vs. f
CLKVDD
vs. Interpolation Rate, PLL Disabled
DATA
2×
1×
02706-B-051

SLEEP/POWER-DOWN MODES

(Control Register 00h, Bits 3 and 4)
The AD9777 provides two methods for programmable reduction in power savings. The sleep mode, when activated, turns off the DAC output currents but the rest of the chip remains functioning. When coming out of sleep mode, the AD9777 will immediately return to full operation. Power-down mode, on the other hand, turns off all analog and digital circuitry in the AD9777 except for the SPI port. When returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. Note that optimal performance with the PLL
02706-B-049
enabled is achieved with the UCO in the PLL control loop running at 450 MHz to 550 MHz.

TWO PORT DATA INPUT MODE

The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In the two-port mode, data at the two input ports is latched into the AD9777 on every rising edge of the data rate clock (DATACLK). Also, in the two-port mode, the AD9777 can be programmed to generate an externally available DATACLK for the purpose of data synchronization. This data rate clock can be programmed to be available at either Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because Pin 8 can also function as a PLL lock indicator when the PLL is enabled, there are several options for configuring Pins 8 and 53. The following describes these options.
72.0
Figure 50. I
500 100 150 200
f
(MHz)
DATA
vs. f
AVDD
vs. Interpolation Rate, PLL Disabled
DATA
PLL Off (Register 4, Bit 7 = 0)
02706-B-050
Register 3, Bit 7 = 0; DATACLK out of Pin 8.
Register 3, Bit 7 = 1; DATACLK out of Pin 53.
PLL On (Register 4, Bit 7 = 1)
Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 8.
Rev. B | Page 29 of 60
Page 30
AD9777
S
Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53.
Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8.
Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53.
In one-port mode, P2B14 and P2B15 from input data port two are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one-port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9777 in this mode for the purpose of data synchronization. ONEPORTCLK runs at the input interleaved data rate, which is 2× the data rate at the internal input to either channel.
Test configurations showing the various clocks that are required and generated by the AD9777 with the PLL enabled/disabled and in the one-port/two-port modes are given in Figure 101 to Figure 104. Jumper positions needed to operate the AD9777 evaluation board in these modes are given as well.

PLL ENABLED, TWO-PORT MODE

(Control Register 02h, Bits 6 to 0 and 04h, Bits 7 to 1)
With the phase-locked loop (PLL) enabled and the AD9777 in two-port mode, the speed of CLKIN is inherently that of the input data rate. In two-port mode, Pin 8 (DATACLK/PLL_ LOCK) can be programmed (Control Register 01h, Bit 0) to function as either a lock indicator for the internal PLL or as a clock running at the input data rate. When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of CLKIN. Data at the input ports is latched into the AD9777 on the rising edge of the CLKIN. Figure 52 shows the delay, t
OD
, inherent between the rising edge of CLKIN and the rising edge of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2. The setup and hold times given in Figure 52 are the input data transitions with respect to CLKIN. Note that in two-port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at Ports 1 and 2.
The DAC output sample rate in two-port mode is equal to the clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.

DATACLK INVERSION

(Control Register 02h, Bit 4)
By programming this bit, the DATACLK signal shown in Figure 53 can be inverted. With inversion enabled, t between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing will occur.
will refer to the time
OD
t
OD
CLKIN
DATACLK
DATA AT PORT
1 AND 2
t
= 0.0ns (MAX)
S
t
= 2.5ns (MAX)
t
t
S
H
Figure 52. Timing Requirements in Two-Port Input Mode with PLL Enabled
H

DATACLK DRIVER STRENGTH

(Control Register 02h, Bit 5)
The DATACLK output driver strength is capable of driving >10 mA into a 330 Ω load while providing a rise time of 3 ns. Figure 53 shows DATACLK driving a 330 Ω resistive load at a frequency of 50 MHz. By enabling the drive strength option (Control Register 02h, Bit 5), the amplitude of DATACLK under these conditions will be increased by approximately 200 mV.
3.0
2.5
2.0
1.5
1.0
AMPLITUDE (V)
0.5
0
–0.5
0 1020304050
Figure 53. DATACLK Driver Capability into 330at 50 MHz
DELTA APPROX. 2.8ns
TIME (ns)
02706-B-053

PLL ENABLED, ONE-PORT MODE

(Control Register 02h, Bits 6 to 1 and 04h, Bits 7 to 1)
In one-port mode, the I and Q channels receive their data from an interleaved stream at digital input Port 1. The function of Pin 32 is defined as an output (ONEPORTCLK) that generates a clock at the interleaved data rate, which is 2× the internal input data rate of the I and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. The selection of the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9777 is
02706-B-052
Rev. B | Page 30 of 60
Page 31
AD9777
in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 will latch the data into the I channel on the clock rising edge, while IQSEL = 1 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic 1). Figure 54 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in one-port mode.

IQ PAIRING

(Control Register 02h, Bit 0)
In one-port mode, the interleaved data is latched into the AD9777 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. The following is an example of the effect this has on incoming interleaved data.
The DAC output sample rate in one-port mode is equal to CLKIN multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.

ONEPORTCLK INVERSION

(Control Register 02h, Bit 2)
By programming this bit, the ONEPORTCLK signal shown in Figure 54 can be inverted. With inversion enabled, t
refers to
OD
the delay between the rising edge of the external clock and the falling edge of ONEPORTCLK. The setup and hold times, t
, will be with respect to the falling edge of ONEPORTCLK.
t
H
and
S
There will be no other effect on timing.

ONEPORTCLK DRIVER STRENGTH

The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for performance under load conditions.
t
OD
t
= 4.0ns (MIN)
OD
CLKIN
ONEPORTCLK
TO 5.5ns (MAX)
t
= 3.0ns (MAX)
S
t
= –0.5ns (MAX)
H
t
= 3.5ns (MAX)
IQS
t
= –1.5ns (MAX
IQH
Given the following interleaved data stream, where the data indicates the value with respect to full scale.
I Q I Q I Q I Q I Q
0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5
With the control register set to 0 (I first), the data will appear at the internal channel inputs in the following order in time.
I Channel 0.5 1 0.5 0 0.5 Q Channel 0.5 1 0.5 0 0.5
With the control register set to 1 (Q first), the data will appear at the internal channel inputs in the following order in time.
I Channel 0.5 1 0.5 0 0.5 x Q Channel y 0.5 1 0.5 0 0.5
The values x and y represent the next I value and the previous Q value in the series.

PLL DISABLED, TWO-PORT MODE

With the PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal clock dividers in the AD9777 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Ports 1 and 2 of the AD9777 on the rising edge of DATACLK. DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate. With zero stuffing enabled, this division increases by a factor of 2. Figure 55 illustrates the delay between the rising edge of CLKIN and the rising edge of DATACLK, as well as t
and tH in this mode.
S
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
IQSEL
Figure 54. Timing Requirements in One-Port
t
t
S
H
t
IQS
Input Mode, with the PLL Enabled
t
IQH
The programmable modes DATACLK inversion and DATACLK driver strength described in the previous section (PLL Enabled, Two-Port Mode) have identical functionality with the PLL disabled.
The data rate CLK created by dividing down the DAC clock in this mode can be programmed (via Register x03h, Bit 7) to be output from the SPI_SDO pin, rather than the DATACLK pin. In some applications, this may improve complex image
02706-B-054
rejection. t data rate clock out.
Rev. B | Page 31 of 60
will increase by 1.6 ns when SPI_SDO is used as
OD
Page 32
AD9777
S
DATA AT PORT
1 AND 2
CLKIN
DATACLK
t
OD
t
= 6.5ns (MIN) TO 8.0ns (MAX)
tSt
OD
t
= 5.0ns (MAX)
H
S
t
= –3.2ns (MAX)
H
Figure 55. Timing Requirements in Two-Port Input Mode, with PLL Disabled

PLL DISABLED, ONE-PORT MODE

In one-port mode, data is received into the AD9777 as an interleaved stream on Port 1. A clock signal (ONEPORTCLK), running at the interleaved data rate, which is 2× the input data rate of the internal I and Q channels, is available for data synchronization at Pin 32.
With PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal dividers synthesize the ONEPORTCLK signal at Pin 32. The selection of the data for the I or Q channel is determined by the state of the logic level applied to Pin 31 (IQSEL when the AD9777 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 will latch the data into the I channel on the clock rising edge, while IQSEL = 1 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic 1). Figure 56 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one-port mode.
One-port mode is very useful when interfacing with devices, such as the Analog Devices AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed). The programmable modes’ ONEPORTCLK inversion, ONEPORTCLK driver strength, and IQ pairing described in the previous section (PLL Enabled, One-Port Mode) have identical functionality with the PLL disable.
t
OD
CLKIN
ONEPORTCLK
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
02706-B-055
t
t
S
H
t
= 4.0ns (MIN)
OD
TO 5.5ns (MAX)
t
= 4.7ns (MAX)
OD
t
= 3.0ns (MAX)
S
t
= –1.0ns (MAX)
H
t
= 3.5ns (MAX)
IQS
t
= –1.5ns (MAX)
IQH
(TYP SPECS)
IQSEL
t
IQS
t
IQH
02706-B-056
Figure 56. Timing Requirements in One-Port Input Mode, with PLL Disabled

DIGITAL FILTER MODES

The I and Q data paths of the AD9777 have their own independent half-band FIR filters. Each data path consists of three FIR filters, providing up to 8× interpolation for each channel. The rate of interpolation is determined by the state of Control Register 01h, Bits 7 and 6. Figure 2 to Figure 4 show the response of the digital filters when the AD9777 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs have been normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than 75 dB of out-of­band rejection.
An online tool is available for quick and easy analysis of the AD9777 interpolation filters in the various modes. The link can be accessed at
http://www.analog.com/Analog_Root/static/techsupport/design tools/interactiveTools/dac/ad9777image.html
.

AMPLITUDE MODULATION

Given two sine waves at the same frequency but with a 90° phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative frequency images. This is shown graphically in the frequency domain in Figure 57.
Rev. B | Page 32 of 60
Page 33
AD9777
–jωt
/2j
e
–jωt
/2 e
e
DC
DC
–jωt
e
SINE
–jωt
COSINE
/2j
/2
02706-B-057
Figure 57. Real and Imaginary Components of
Sinusoidal and Cosinusoidal Waveforms
Amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of 2. This scaling will be very important in the discussion
of the various modulation modes. The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. Examples of sine and cosine modulation are given in Figure 58.
–jωt
Ae
/2j
SINUSOIDAL MODULATION
DC
–jωt
/2j
Ae
–jωt
/2 Ae
Ae
DC
Figure 58. Baseband Signal, Amplitude Modulated with Sine and Cosine Carriers
–jωt
/2
COSINUSOIDAL MODULATION
02706-B-058
Rev. B | Page 33 of 60
Page 34
AD9777

MODULATION, NO INTERPOLATION

With Control Register 01h, Bits 7 and 6 set to 00, the interpolation function on the AD9777 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9777 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. By comparing the digital domain spectrum to the DAC SIN(x)/x roll-off, an estimate can
The Effects of Digital Modulation on DAC Output Spectrum, Interpolation Disabled
be made for the characteristics required for the DAC reconstruction filter. Note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to f the situation where the modulation is f spectral components add constructively, and there is no scaling effect.
/4 or fS/8) are scaled by a factor of 2. In
S
/2, the modulated
S
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
–100
0 0.2 0.4 0.6 0.8 1.0
f
(
×
f
DATA
)
OUT
Figure 59. No Interpolation, Modulation Disabled
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
–100
0 0.2 0.4 0.6 0.8 1.0
f
(
×
f
DATA
)
/4
DAC
02706-B-061
02706-B-059
OUT
Figure 61. No Interpolation, Modulation = f
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
–100
0 0.2 0.4 0.6 0.8 1.0
f
(
×
f
DATA
)
OUT
Figure 60. No Interpolation, Modulation = f
DAC
/2
02706-B-060
Rev. B | Page 34 of 60
–100
0 0.2 0.4 0.6 0.8 1.0
f
(
×
f
DATA
)
OUT
Figure 62. No Interpolation, Modulation = f
DAC
/8
02706-B-062
Page 35
AD9777

MODULATION, INTERPOLATION = 2×

With Control Register 01h, Bits 7 and 6 set to 01, the interpolation rate of the AD9777 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1). Figure 63 to Figure 66 represent the spectral response of the AD9777 DAC output with 2× interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic). The advantage of interpolation becomes clear in Figure 63 to Figure 66, where it can be seen that the images that would normally appear in the spectrum around the significant point is
The Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 2x
that the interpolation filtering is done previous to the digital modulator. For this reason, as Figure 63 to Figure 66 show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high-pass digital filter.
Note that when using the f stop band as the band edges coincide with each other. In the f
/4 modulation mode, there is no true
S
/8
S
modulation mode, amplitude scaling occurs over only a portion of the digital filter pass band due to constructive addition over just that section of the band
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–100
0.50 1.0 1.5 2.0
f
(
×
f
DATA
)
OUT
Figure 63. 2× Interpolation, Modulation = Disabled
0
–20
–40
–60
–80
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
–100
02706-B-063
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
0.50 1.0 1.5 2.0
f
(
×
f
DATA
)
OUT
Figure 65. 2× Interpolation, Modulation = f
DAC
/4
02706-B-065
–100
0.50 1.0 1.5 2.0
f
(
×
f
DATA
)
OUT
Figure 64. 2× Interpolation, Modulation = f
DAC
/2
02706-B-064
Rev. B | Page 35 of 60
–100
0.50 1.0 1.5 2.0
f
(
×
f
DATA
)
OUT
Figure 66. 2× Interpolation, Modulation = f
DAC
/8
02706-B-066
Page 36
AD9777

MODULATION, INTERMODULATION = 4×

With Control Register 01h, Bits 7 and 6 set to 10, the interpolation rate of the AD9777 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). Figure 67 to Figure 70
The Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 4x
represent the spectral response of the AD9777 DAC output with 4× interpolation in the various modulation modes to a narrow band baseband signal.
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–20
–40
–60
–80
0
10234
f
(
×
f
DATA
)
OUT
Figure 67. 4x Interpolation, Modulation Disabled
0
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
–100
02706-B-067
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
10234
f
(
×
f
DATA
)
OUT
Figure 69. 4x Interpolation, Modulation = f
DAC
/4
02706-B-069
–100
10234
f
(
×
f
DATA
)
OUT
Figure 68. 4x Interpolation, Modulation = f
DAC
/2
02706-B-068
–100
10234
f
(
×
f
DATA
)
OUT
Figure 70. 4x Interpolation, Modulation = f
DAC
/8
02706-B-070
Rev. B | Page 36 of 60
Page 37
AD9777

MODULATION, INTERMODULATION = 8×

With Control Register 01h, Bits 7 and 6, set to 11, the interpolation rate of the AD9777 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, –0.707, −1, +0.707). Figure 71 to Figure 74 represent the spectral response of the AD9777 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal. Looking
The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8×
at Figure 59 to Figure 75, the user can see how higher interpolation rates reduce the complexity of the reconstruction filter needed at the DAC output. It also becomes apparent that the ability to modulate by f
/2, fS/4, or fS/8 adds a degree of
S
flexibility in frequency planning
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–20
–40
–60
–80
0
10234
f
(
×
f
DATA
)
OUT
Figure 71. 8× Interpolation, Modulation Disabled
0
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
–100
02706-B-071
Figure 73. 8x Interpolation, Modulation = f
0
–20
–40
–60
AMPLITUDE (dBFS)
–80
4312056
f
(×
f
DATA
)
OUT
78
/4
DAC
02706-B-073
–100
10234
f
(
×
f
DATA
)
OUT
Figure 72. 8x Interpolation, Modulation = f
DAC
/2
02706-B-072
Rev. B | Page 37 of 60
–100
Figure 74. 8x Interpolation, Modulation = f
43120567
f
(
×
f
DATA
)
OUT
8
02706-B-074
/8
DAC
Page 38
AD9777

ZERO STUFFING

(Control Register 01h, Bit 3)
As shown in Figure 75, a 0 or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f is due to the inherent SIN(x)/x roll-off response in the digital­to-analog conversion. In applications where the desired frequency content is below f Note that at f
/2 the loss due to SIN(x)/x is 4 dB. In direct RF
DAC
/2, this may not be a problem.
DAC
applications, this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced amplitude of the desired signal.
Consider an application where the digital data into the AD9777 represents a baseband signal around f
/10. The reconstructed signal out of the AD9777 would
f
DAC
/4 with a pass band of
DAC
experience only a 0.75 dB amplitude variation over its pass band. However, the image of the same signal occurring at 3×
/4 will suffer from a pass-band flatness variation of 3.93 dB.
f
DAC
This image may be the desired signal in an IF application using one of the various modulation modes in the AD9777. This roll­off of image frequencies can be seen in Figure 59 to Figure 74, where the effect of the interpolation and modulation rate is apparent as well.
10
0
–10
–20
–30
SIN (X)/X ROLL-OFF (dBFS)
–40
–50
ZERO STUFFING
DISABLED
0.50 1.0 1.5 2.0
f
, NORMALIZED TO
OUT
Figure 75. Effect of Zero Stuffing on DAC’s SIN(x)/x Response
f
DATA
ZERO STUFFING
ENABLED
WITH ZERO STUFFING DISABLED (Hz)
To improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to a Logic 1. This option increases the ratio of f
DAC/fDATA
by a factor of 2 by doubling the DAC sample rate and inserting a midscale sample (i.e., 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This is important as it will affect the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the DAC.
DAC
). This
02706-B-075
The net effect is to increase the DAC output sample rate by a factor of 2× with the 0 in the SIN(x)/x DAC transfer function occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident, as can be seen in Figure 76.
It is important to realize that the zero stuffing option by itself does not change the location of the images but rather their amplitude, pass-band flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the image at 3× f
/4 is now improved to 0.59 dB
DATA
while the signal level has increased slightly from −10.5 dBFS to –8.1 dBFS.

INTERPOLATING (COMPLEX MIX MODE)

(Control Register 01h, Bit 2)
In the complex mix mode, the two digital modulators on the AD9777 are coupled to provide a complex modulation function. In conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. The complex modulation function can be
+jωt
−jωt
or e
programmed for e
to give upper or lower image rejection. As in the real modulation mode, the modulation frequency ω can be programmed via the SPI port for f f
DAC
/4, and f
/8, where f
DAC
represents the DAC output rate.
DAC
DAC
/2,

OPERATIONS ON COMPLEX SIGNALS

Truly complex signals cannot be realized outside of a computer simulation. However, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. I (real) and Q (imaginary) data paths are often defined this way. By using the architecture defined in Figure 76, a system that operates on complex signals can be realized, giving a complex (real and imaginary) output.
+jωt
If a complex modulation function (e imaginary components of the system correspond to the real and
+jωt
imaginary components of e
or cosωt and sinωt. As Figure 77 shows, the complex modulation function can be realized by applying these components to the structure of the complex system defined in Figure 76.
a(t)
INPUT OUTPUT
COMPLEX FILTER
= (c + jd)
b(t)
IMAGINARY
INPUT OUTPUT
Figure 76. Realization of a Complex System
) is desired, the real and
c(t) × b(t) + d × b(t)
b(t) × a(t) + c × b(t)
02706-B-076
Rev. B | Page 38 of 60
Page 39
AD9777
(
)
INPUT
(REAL)
INPUT
IMAGINARY
90°
–jωt
e
= COSωt + jSINωt
Figure 77. Implementation of a Complex Modulator
OUTPUT (REAL)
OUTPUT (IMAGINARY)
02706-B-077

COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS

In traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an IF (intermediate frequency) and then modulated a second time to the transmit frequency. Although this approach has several benefits, a major drawback is that two images are created near the transmit frequency. Only one image is needed, the other being an exact duplicate. Unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced.
A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. Figure 78 is a block diagram of a quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal.
INPUT
(REAL)
INPUT
(IMAGINARY)
SINωt
Figure 78. Quadrature Modulation
90°
COSωt
OUTPUT
02706-B-078
The entire upconversion from baseband to transmit frequency is represented graphically in Figure 79. The resulting spectrum shown in Figure 79 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. It is important to remember that in this application (two baseband data channels), the image rejection is not dependent on the data at either of the AD9777 input channels.
In fact, image rejection will still occur with either one or both of the AD9777 input channels active. Note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. This is easily done in
+jωt
the AD9777 by selecting the e
bit (Register 01h, Bit 1). In purely complex terms, Figure 79 represents the two-stage upconversion from complex baseband to carrier.
Rev. B | Page 39 of 60
Page 40
AD9777
REAL CHANNEL (IN)
REAL CHANNEL (OUT)
A/2
1
–F
C
A/2
F
C
A
DC
IMAGINARY CHANNEL (IN)
B
DC
REAL
QUADRATURE
MODULATOR
IMAGINARY
COMPLEX
MODULATOR
OUT
–B/2J B/2J
–F
C
IMAGINARY CHANNEL (OUT)
–A/2J A/2J
–F
C
B/2 B/2
–F
C
A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J
2
–F
–F
–A/4 – B/4J
Q
– F
Q
A/2 + B/2J A/2– B/2J
–FQ+ F
C
A/4 – B/4J A/4 + B/4J –A/4 + B/4J
–F
Q
F
C
–F
C
F
C
C
REJECTED IMAGES
FQ– F
TO QUADRATURE MODULATOR
F
Q
FQ+ F
C
F
Q
C
NOTES
1
FC = COMPLEX MODULATION FREQUENCY
2
FQ = QUADRATURE MODULATION FREQUENCY
–F
Q
F
Q
02706-B-079
Figure 79. Two-Stage Upconversion and Resulting Image Rejection
Rev. B | Page 40 of 60
Page 41
AD9777
N
COMPLEX BASEBAND
SIGNAL
1
j(ω1 + ω2)t
OUTPUT = REAL
= REAL
1/2 1/2
ω1–ω2DC
×
e
ω1 + ω2
FREQUENCY
02706-B-080
Figure 80. Two-Stage Complex Upconversion
IMAGE REJECTION AND SIDEBAND SUPPRESSIONS OF MODULATED CARRIERS
As shown in Figure 79, image rejection can be achieved by applying baseband data to the AD9777 and following the AD9777 with a quadrature modulator. To process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. As Figure 80 shows, single or multiple complex modulators can be used to synthesize complex carriers. These complex carriers are then summed and applied to the real and imaginary inputs of the AD9777. A system in which multiple baseband signals are complex
BASEBAND CHANNEL 1
BASEBAND CHANNEL 2
REAL INPUT
IMAGINARY INPUT
REAL INPUT
IMAGINARY INPUT
COMPLEX
MODULATOR 1
COMPLEX
MODULATOR 2
R(1)
R(1)
R(2)
R(2)
modulated and then applied to the AD9777 real and imaginary inputs, followed by a quadrature modulator, is shown in Figure 82, which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in Figure 82 and Figure 80.Figure 82 adds an additional complex modulator stage for the purpose of summing multiple carriers at the AD9777 inputs. Also, as in Figure 79, the image rejection is not dependent on the real or imaginary baseband data on any channel. Image rejection on a channel will occur if either the real or imaginary data, or both, is present on the baseband channel.
It is important to remember that the magnitude of a complex signal can be 1.414× the magnitude of its real or imaginary components. Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9777 must be kept at least 3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator will result in severe distortion at the DAC output.
MULTICARRIER REAL OUTPUT = R(1) + R(2) + . . .R(N) (TO REAL INPUT OF AD9777)
MULTICARRIER IMAGINARY OUTPUT = I(1) + I(2) + . . .I(N) (TO IMAGINARY INPUT OF AD9777)
BASEBAND CHANNEL
REAL INPUT
IMAGINARY INPUT
COMPLEX
MODULATOR N
R(N) = REAL OUTPUT OF N
R(N)
I(N) = IMAGINARY OUTPUT OF N
R(N)
02706-B-081
Figure 81. Synthesis of Multicarrier Complex Signal
MULTIPLE BASEBAND CHANNELS
REAL
IMAGINARY
MULTIPLE COMPLEX
MODULATORS
FREQUENCY = ω
ω
ωC– ω
1
, ω2...ω
1
Q
REAL
IMAGINARY
N
COMPLEX BASEBAND
SIGNAL
OUTPUT = REAL
REJECTED IMAGES
FREQUENCY = ω
DC
AD9777
COMPLEX
MODULATOR
×
j(ωN + ωC + ωQ)t
e
C
Figure 82. Image Rejection with Multicarrier Signals
REAL REAL
IMAGINARY
ω1 + ωC + ω
Q
QUADRATURE
MODULATOR
FREQUENCY = ω
Q
02706-B-082
Rev. B | Page 41 of 60
Page 42
AD9777
The complex carrier synthesized in the AD9777 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at f only functions with modulation rates of f
Regions A and B of Figure 83 to Figure 88 are the result of the complex signal described previously, when complex modulated in the AD9777 by +e complex signal described previously, again with positive frequency components only, modulated in the AD9777 by −e The analog quadrature modulator after the AD9777 inherently modulates by +e
jωt
Region A
Region A is a direct result of the upconversion of the complex signal near baseband. If viewed as a complex signal, only the images in Region A will remain. The complex Signal A, consisting of positive frequency components only in the digital domain, has images in the positive odd Nyquist zones (1, 3, 5...), as well as images in the negative even Nyquist zones. The appearance and rejection of images in every other Nyquist zone will become more apparent at the output of the quadrature modulator. The A images will appear on the real and the imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale now represents the frequency offset from this LO.
Region B
Region B is the image (complex conjugate) of Region A. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region B will appear in the spectrum. However, on the output of the quadrature modulator, Region B will be rejected.
/2. As a result, complex mo dulation
DAC
/4 and f
DAC
jωt
. Regions C and D are the result of the
.
DAC
/8.
jωt
Region C
Region C is most accurately described as a down conversion, as
jωt
the modulating carrier is −e
. If viewed as a complex signal, only the images in Region C will remain. This image will appear on the real and imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale will represent the frequency offset from this LO.
.
Region D
Region D is the image (complex conjugate) of Region C. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region D will appear in the spectrum. However, on the output of the quadrature modulator, Region D will be rejected.
Figure 89 to Figure 96 show the measured response of the AD9777 and AD8345 given the complex input signal to the AD9777 in Figure 89. The data in these graphs was taken with a data rate of 12.5 MSPS at the AD9777 inputs. The interpolation rate of 4× or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result, the high end of the DAC output spectrum in these graphs is the first null point for the SIN(x)/x roll-off, and the asymmetry of the DAC output images is representative of the SIN(x)/x roll-off over the spectrum. The internal PLL was enabled for these results. In addition, a 35 MHz third-order low-pass filter was used at the AD9777/AD8345 interface to suppress DAC images.
An important point can be made by looking at Figure 91 and Figure 93. Figure 91 represents a group of positive frequencies modulated by complex +f group of negative frequencies modulated by complex −f
/4, while Figure 93 represents a
DAC
DAC
/4. When looking at the real or imaginary outputs of the AD9777, as shown in Figure 91 and Figure 93, the results look identical. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figure 92 and Figure 94.
Rev. B | Page 42 of 60
Page 43
AD9777
0
–20
DABCDABC
–40
–60
–80
–100
Figure 83. 2× Interpolation, Complex f
0
–20
D A BC DA BC
–40
–60
0–0.5–1.5 –1.0–2.0 0.5 1.0 1.5 2.0
(LO)
f
(×
f
DATA
)
/4 Modulation
DAC
OUT
0
–20
–40
DA B CD A BC
–60
–80
100
02706-B-083
Figure 86. 2× Interpolation, Complex f
0
–20
–40
DA B CD A B C
–60
0–0.5–1.5 –1.0–2.0 0.5 1.0 1.5 2.0
(LO)
f
(×
f
DATA
)
/8 Modulation
DAC
OUT
02706-B-086
–80
–100
0–1.0–3.0 –2.0–4.0 1.0 2.0 3.0 4.0
(LO)
f
(×
f
DATA
)
OUT
Figure 84. 4× Interpolation, Complex f
0
–20
DA B C DA B C
–40
–60
–80
–100
0–2.0–6.0 –4.0–8.0 2.0 4.0 6.0 8.0
(LO)
f
(×
f
DATA
)
OUT
Figure 85. 8× Interpolation, Complex f
/4 Modulation
DAC
/4 Modulation
DAC
–80
–100
02706-B-084
Figure 87. 4× Interpolation, Complex f
0
–20
DA DABC BC
–40
–60
–80
–100
02706-B-085
Figure 88. 8× Interpolation, Complex f
0–1.0–3.0 –2.0–4.0 1.0 2.0 3.0 4.0
(LO)
f
(
×
f
OUT
f
OUT
)
DATA
/8 Modulation
DAC
0–2.0–6.0 –4.0–8.0 2.0 4.0 6.0 8.0
(LO)
(
×
f
)
DATA
/8 Modulation
DAC
02706-B-087
02706-B-088
Rev. B | Page 43 of 60
Page 44
AD9777
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
01020304050
FREQUENCY (MHz)
Figure 89. AD9777, Real DAC Output of Complex Input Signal Near Baseband
(Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9777
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
750 760 770 780 790 800 810 820 830 840 850
FREQUENCY (MHz)
Figure 90. AD9777 Complex Output from Figure 89, Now Quadrature
Modulated by AD8345 (LO = 800 MHz)
02706-B-089
02706-B-090
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
0 1020304050
FREQUENCY (MHz)
02706-B-091
Figure 91. AD9777, Real DAC Output of Complex Input Signal Near
Baseband (Positive Frequencies Only), Interpolation = 4×,
Complex Modulation in AD9777 = +f
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
750 760 770 780 790 800 810 820 830 840 850
FREQUENCY (MHz)
DAC
/4
02706-B-092
Figure 92. AD9777 Complex Output from Figure 91, Now Quadrature
Modulated by AD8345 (LO = 800 MHz)
Rev. B | Page 44 of 60
Page 45
AD9777
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
0 1020304050
FREQUENCY (MHz)
Figure 93. AD9777, Real DAC Output of Complex Input Signal Near
Baseband (Negative Frequencies Only), Interpolation = 4×,
Complex Modulation in AD9777 = −f
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
750 760 770 780 790 800 810 820 830 840 850
FREQUENCY (MHz)
DAC
/4
Figure 94. AD9777 Complex Output from Figure 93, Now Quadrature
Modulated by AD8345 (LO = 800 MHz)
02706-B-093
02706-B-094
0
–20
–40
–60
AMPLITUDE (dBm)
–80
–100
0 20 40 60 80 100
FREQUENCY (MHz)
Figure 95. AD9777, Real DAC Output of Complex Input Signal Near
Baseband (Positive Frequencies Only), Interpolation = 8×,
Complex Modulation in AD9777 = +f
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
700 720 740 760 780 800 820 840 860 880 900
FREQUENCY (MHz)
DAC
/8
Figure 96. AD9777 Complex Output from Figure 95, Now Quadrature
Modulated by AD8345 (LO = 800 MHz)
02706-B-095
02706-B-096
Rev. B | Page 45 of 60
Page 46
AD9777

APPLYING THE AD9777 OUTPUT CONFIGURATIONS

The following sections illustrate typical output configurations for the AD9777. Unless otherwise noted, it is assumed that I is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configuration is suggested. A simple differential output may be achieved by converting I
OUTA
and I
to a voltage output by terminating
OUTB
them to AGND via equal value resistors. This type of configuration may be useful when driving a differential voltage input device such as a modulator. If a conversion to a single­ended signal is desired and the application allows for ac coupling, an RF transformer may be useful; if power gain is required, an op amp may be used. The transformer configuration provides optimum high frequency noise and distortion performance. The differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or level shifting within the bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if I
OUTA
and/or I
is connected to a load resistor, R
OUTB
referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting I
OUTA
or I
OUTB
into a negative unipolar voltage. This configuration provides the best DAC dc linearity as I
OUTA
or I
are maintained at ground or
OUTB
virtual ground.

UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT

In many applications, it may be necessary to understand the equivalent DAC output circuit. This is especially useful when designing output filters or when driving inputs with finite input impedances. Figure 97 illustrates the output of the AD9777 and the equivalent circuit. A typical application where this information may be useful is when designing an interface filter between the AD9777 and the Analog Devices AD8345 quadrature modulator.
V
I
OUTA
OUT
+
OUTFS
LOAD
,
For the typical situation, where I
= 20 mA and RA and RB
OUTFS
both equal 50 Ω, the equivalent circuit values become:
= 2 V
V
R
OUT
SOURCE
= 100 Ω
P-P
Note that the output impedance of the AD9777 DAC itself is greater than 100 kΩ and typically has no effect on the impedance of the equivalent output circuit.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to­single ended signal conversion, as shown in Figure 98. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes.
MINI-CIRCUITS
I
OUTA
DAC I
OUTB
Figure 98. Transformer-Coupled Output Circuit
The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path for both I at I
OUTA
OUTA
and I
and I
OUTB
OUTB
(i.e., V around AGND and should be maintained within the specified output compliance range of the AD9777. A differential resistor,
, may be inserted in applications where the output of the
R
DIFF
transformer is connected to the load, R reconstruction filter or cable. R transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approx­mately half the signal power will be dissipated across R
T1-1T
R
LOAD
02706-B-098
. The complementary voltages appearing
OUTA
and V
) swing symmetrically
OUTB
, via a passive
LOAD
is determined by the
DIFF
DIFF
.
I
OUTB
R
+ R
A
B
=
V
SOURCE
× (RA + RB)
I
OUTFS
p-p
Figure 97. DAC Output Equivalent Circuit
V
OUT
V
OUT
(DIFFERENTIAL)
02706-B-097
Rev. B | Page 46 of 60
Page 47
AD9777

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-single ended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9777 is configured with two equal load resistors, R 25 Ω. The differential voltage developed across I
OUTA
LOAD
and I
, of
OUTB
is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across I
OUTA
and I
, forming a real pole in a low-pass filter. The
OUTB
addition of this capacitor also enhances the op amp’s distortion performance by preventing the DAC’s fast slewing output from overloading the input of the op amp.
500
I
OUTA
DAC
I
OUTB
25 25
Figure 99. Op Amp-Coupled Output Circuit
225
AD8021
C
OPT
225
500
R 225
OPT
AVDD
02706-B-099
The common-mode (and second-order distortion) rejection of this configuration is typically determined by the resistor matching. The op amp used must operate from a dual supply since its output is approximately ±1.0 V. A high speed amplifier, such as the AD8021, capable of preserving the differential performance of the AD9777 while meeting other system level objectives (i.e., cost, power) is recommended. The op amp’s differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. R
is necessary only if level shifting is
OPT
required on the op amp output. In Figure 99, AVDD, which is the positive analog supply for both the AD9777 and the op amp, is also used to level shift the differential output of the AD9777 to midsupply (i.e., AVDD/2).

INTERFACING THE AD9777 WITH THE AD8345 QUADRATURE MODULATOR

The AD9777 architecture was defined to operate in a transmit signal chain using an image reject architecture. A quadrature modulator is also required in this application and should be designed to meet the output characteristics of the DAC as much as possible. The AD8345 from Analog Devices meets many of the requirements for interfacing with the AD9777. As with any DAC output interface, there are a number of issues that have to be resolved. Among the major issues are the following.

DAC Compliance Voltage/Input Common-Mode Range

The dynamic range of the AD9777 is optimal when the DAC outputs swing between ±1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components.

Gain/Offset Adjust

The matching of the DAC output to the common-mode input of the AD8345 allows the two components to be dc-coupled, with no level shifting necessary. The combined voltage offset of the two parts can therefore be compensated for via the AD9777 programmable offset adjust. This allows excellent LO cancellation at the AD8345 output. The programmable gain adjust allows for optimal image rejection as well.
The AD9777 evaluation board includes an AD8345 and recommended interface (Figure 105 and Figure 106). On the output of the AD9777, R9 and R10 convert the DAC output current to a voltage. R16 may be used to do a slight common­mode shift if necessary. The (now voltage) signal is applied to a low-pass reconstruction filter to reject DAC images. The components installed on the AD9777 provide a 35 MHz cutoff but may be changed to fit the application. A balun (Mini­Circuits ADTL1-12) is used to cross the ground plane boundary to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, therefore a single connection between the AD9777 and AD8345 ground planes is recommended.
The performance of the AD9777 and AD8345 in an image reject transmitter, reconstructing three WCDMA carriers, can be seen in Figure 100. The LO of the AD8345 in this application is 800 MHz. Image rejection (50 dB) and LO feedthrough (−78 dBFS) have been optimized with the programmable features of the AD9777. The average output power of the digital waveform for this test was set to −15 dBFS to account for the peak-to-average ratio of the WCDMA signal.
0
–10
–20
–30
–40
–50
–60
AMPLITUDE (dBm)
–70
–80
–90
–100
782.5762.5 802.5 822.5 842.5 FREQUENCY (MHz)
Figure 100. AD9777/AD8345 Synthesizing a
Three-Carrier WCDMA Signal at an LO of 800 MHz
02706-B-100
Rev. B | Page 47 of 60
Page 48
AD9777

EVALUATION BOARD

The AD9777 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from Windows® 95, Windows 98, or Windows NT®/2000. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9777 in an image reject transmit signal chain.
Figure 101 to Figure 104 describe how to configure the evaluation board in the one-port and two-port input modes with the PLL enabled and disabled. Refer to Figure 105 to Figure 114, the schematics, and the layout for the AD9777 evaluation board for the jumper locations described below. The AD9777 outputs can be configured for various applications by referring to the following instructions.

DAC Single-Ended Outputs

Remove Transformers T2 and T3. Solder jumper link JP4 or JP28 to look at the DAC1 outputs. Solder jumper link JP29 or JP30 to look at the DAC2 outputs. Jumpers 8 and 13 to 17 should remain unsoldered. Jumpers JP35 to JP38 may be used to ground one of the DAC outputs while the other is measured single-ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4.

DAC Differential Outputs

Transformers T2 and T3 should be in place. Note that the lower band of operation for these transformers is 300 kHz to 500 kHz. Jumpers 4, 8, 13 to 17, and 28 to 30 should remain unsoldered. The outputs are taken from S3 and S4.

Using the AD8345

Remove Transformers T2 and T3. Jumpers JP4 and 28 to 30 should remain unsoldered. Jumpers 13 to 16 should be soldered. The desired components for the low-pass interface filters L6, L7, C55, and C81 should be in place. The LO drive is connected to the AD8345 via J10 and the balun T4, and the AD8345 output is taken from J9.
Rev. B | Page 48 of 60
Page 49
AD9777
INPUT CLOCK
AWG2021
OR
DG2020
LECROY PULSE GENERATOR
40-PIN RIBBON CABLE
TRIG
INP
DAC1, DB15–DB0 DAC2, DB15–DB0
SIGNAL GENERATOR
CLK+/CLK–DATACLK
AD9777
JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON
× ×
×
× ×
UNSOLDERED/OUT
×
× × ×
× × × ×
02706-B-101
2
Figure 101.
SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –
JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –
1
Test Configuration for AD9777 in Two-Port Mode with PLL Enabled Signal Generator Frequency = Input Data Rate,
DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
Figure 102.
LECROY PULSE GENERATOR
INPUT CLOCK
AWG2021
OR
DG2020
JUMPER CONFIGURATION FOR ONE PORT MODE PLL ON
SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –
JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –
1
Test Configuration for AD9777 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,
× ×
× ×
×
TRIG
INP
DAC1, DB15–DB0 DAC2, DB15–DB0
UNSOLDERED/OUT
× ×
× × ×
×
× ×
SIGNAL GENERATOR
CLK+/CLK–ONEPORTCLK
AD9777
02706-B-102
ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
1
To use PECL clock driver (U8), solder JP41 and JP42 and remove Transformer T1.
2
In two-port mode, if DATACLK/PLL_LOCK is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL_LOCK is programmed to output Pin 53,
JP46 and JP47 should be soldered. See the Two P section for more information. ort Data Input Mode
Rev. B | Page 49 of 60
Page 50
AD9777
INPUT CLOCK
AWG2021
OR
DG2020
LECROY PULSE GENERATOR
40-PIN RIBBON CABLE
TRIG
INP
DAC1, DB15–DB0 DAC2, DB15–DB0
SIGNAL GENERATOR
CLK+/CLK–DATACLK
AD9777
JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF
× ×
×
× ×
UNSOLDERED/OUT
×
× × ×
× × × ×
02706-B-103
2
Figure 103.
SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –
JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –
1
Test Configuration for AD9777 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
DATACLK = Signal Generator Frequency/Interpolation Rate
Figure 104.
LECROY PULSE GENERATOR
INPUT CLOCK
AWG2021
OR
DG2020
JUMPER CONFIGURATION FOR ONE PORT MODE PLL OFF
SOLDERED/IN
JP1 – JP2 – JP3 – JP5 –
JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –
1
Test Configuration for AD9777 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
× ×
× ×
×
TRIG
INP
DAC1, DB15–DB0 DAC2, DB15–DB0
UNSOLDERED/OUT
× ×
× × ×
×
× ×
SIGNAL GENERATOR
CLK+/CLK–ONEPORTCLK
AD9777
02706-B-104
ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate.
1
To use PECL clock driver (U8), solder JP41 and JP42 and remove Transformer T1.
2
In two-port mode, if DATACLK/PLL_LOCK is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL_LOCK is programmed to output Pin 53,
JP46 and JP47 should be soldered. See the Two P section for more information. ort Data Input Mode
Rev. B | Page 50 of 60
Page 51
AD9777
C79
DNP
R32
RC0603
51
L6
LC0805
DNP
O2N
JP45
VDDM
L8
LC1210
FERRITE
POWER INPUT FILTERS
VDDMIN
W11
CC0603
R34
RC0603
JP19
R33
RC0603
3
1
CC0805
C81
DNP
L7
LC0805
CC0805
C55
DNP
O2P
C28
DNP
51
P
DNP
C32
JP44
JP43
CC0805
BLK
TP4
RED
JP10
AVDD
C68
16V
DCASE
CC0805
TP5
22µF
0.1µF
C61
+
DVDD
TP2
RED
16V
DCASE
TP3
22µF
C66
+
JP9
C67
0.1µF
0.1µF
CC0805
BLK
TP6
RED
JP11
CLKVDD
TP7
BLK
C62
16V
22µF
+
DCASE
C69
0.1µF
CC0805
2
16V
DCASE
c
22µF
CGND
J7
AGND
J6
L1
FERRITE
CLKVDD_IN
LC1210
C63 +
J3
L3
LC1210
FERRITE
C65
16V
16V
22µF
+
DCASE
DGND2
DVDD_IN
W12
22µF
+
DCASE
J8
DGND
J5
L2
FERRITE
AVDD_IN
LC1210
C64
16V
22µF
+
DCASE
J4
2
J10
2
JP7
JP21
DGND2; 3, 4, 5
RC0603
LOCAL OSC INPUT
0
R28
2
R30
100pF
CC0603
0.1µF
43
ETC1-1-13
CC0603
DNP
RC0603
5
T4
SP
1
C77
100pF
CC0603
6
2
S
4
T6
P
ADTL1-12
31
C80
DNP
RC0603
CC0603
R37
DNP
JP20
RC0603
R35
51
L4
LC0805
DNP
O1N
RC0603
R36
51
CC0805
C73
DNP L5
LC0805
DNP
CC0805
C54
DNP
O1P
02706-B-105
2
C76
C78
MODULATED OUTPUT
T5
J9
DGND2; 3, 4, 5
0
R23
C74
100pF
S
ADTL1-12
64
VDDM
2
RC0603
CC0603
C75
C35
C72
+
2
G2ENBL G3
VOUT
VPS2 G4A G4B
QBBP
16 15 14 13 12 11 10 9
0.1µF
CC0603
100pF
CC0603
10V
10µF
BCASE
VDDM
U2
AD8345
QBBN
2
R26
1k
RC0603
VPS1 LOIP LOIN G1B G1A IBBN IBBP
1 2 3 4 5 6 7 8
JP18
Figure 105. AD8345 Circuitry on AD9777 Evaluation Board
Rev. B | Page 51 of 60
Page 52
AD9777
5
JP8
C70
R10
JP30
S4
AGND; 3, 4,
OUT 2
456
T3
3
2
1
R43
49.9k JP17
T1-1T
C70
R12
CC0603
R17
10k
0.1µF
RC0603
RC0603 RC0603
51k
R11
51k
SPSDO
JP47
9
10
U4
74VCX86
8
DVDD; 14
DGND; 7
S3
O1N
O1P
O2N
JP13
JP15
O2P
JP14
JP29
JP16
RC1206
AGND; 3, 4, 5
OUT1
R42
456
2
3
49.9k
T1-1T
1
CC0603
R16
10k
0.1µF
T2
JP4
RC0603
RC0603 RC0603
JP28
51k
R9
51k
R3
R2
C41
C40
C39
C38
C37
C36
DVDD
1k
RC0603 RC0603
1k
R8
1k
FSADJ2
REFOUT
R7
2k
+
C4
C16
RESET
SP-CSB
0.01%
0.01%
6.3V
10µF
CC0603 BCASE
0.1µF
R6
RC1206
SPCSP
SPCLK
SP-CLK
1k
SPSDI
SP-SDI
SP-SDO
SPSDO
VSSD6
DVDD
DVDD
P2D0
VDDD6
BD00
J37
J35
AVDD
0.1µF
CC0805
0.1µF
CC0805
0.1µF
CC0805
0.1µF
CC0805
C2
+
C14
C19
C20
6.3V
10µF
BCASECC0603
0.1µF C58
DNP
C58
DNP
CC0603
CC0603
CC0603
0.1µF
0.1µF
CC0603
C57
CC0603
DNP
C59
DNP
CC0603
JP36
AVDD
JP38
C3
+
C15
C17
C18
6.3V
10µF
BCASECC0805
TP8
WHT
0.1µF
CC0603CC0603
TP9
WHT
0.1µF
TP10
WHT
0.1µF TP11
WHT
0.1µF
807978777675747372717069686766656463626160595857565554535251504948474645444342
CC0805
0.1µF VSSA9
VSSA8
VSSA7
VSSA6
VSSA5
VSSA4
VSSA3
VSSA2
VDDA5
VDDA4
CC0805
VSSA10
IOUT1P
IOUT1N
IOUT2P
IOUT2N
VDDA3
VSSA1
VDDA2
VDDA1
FSADJ1
U1
CLKVDD
VDDC1 VDDA6
LF
VDDC2
VSSC1
CLKP
CLKN
VSSC2
DCLK-PLLL
VSSD1
VDDD1
P1D15
P1D14
P1D13
P1D12
P1D11
P1D10
VSSD2
VDDD2
P1D9
P1D8
P1D7
P1D6
P1D5
P1D4
VSSD3
VDDD3
P1D3
P1D2
P1D1
P1D0
AD03
CC0603
C24
C8
+
BCASE
10µF
AD02
0.001µF
6.3V
AD01
P2D15-IQSEL
AD00
JP5
BD15
CC0603
123456789
1pF
C27
C42
0.1µF
C11
0.1µF
CC0603 CC0603 CC0603
C12
0.1µF
BCASE
c
+
C1
6.3V
10µF
123
JP22
654
CC0603
C13
0.1µF
WHT
TP15
c
CLKP
RC0603
CLKN
R1
JP23
200
JP1
T1
10111213141516171819202122232425262728293031323334353637383940
c
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
JP33
T1-1T
JP2
R38 10k
ADCLK
JP39
S1
CLKIN
CC0603
C26
0.001µF
6.3V
C10
10µF
+
BCASE
DVDD
JP24
c
ACLKX CGND; 3, 4, 5
JP25
CX3
74VCX86
12
11
U3
CX2
DVDD; 14
13
CX1
CC0603
C25
C9
10µF
+
BCASE
DVDD
TP14
DGND; 7
RC0603
R40
JP12
DVDD
0.001µF
6.3V
RC0603
R5
WHT
5k
DGND; 3, 4, 5
DATACLK
DVDD
49.9
CC0605
JP3
C29
0.1µF
S2
Figure 106. AD9777 Clock, Power Supplies, and Output Circuitry
BCASE
+
C5
6.3V
10µF
C21
CC0603
0.001µF
BD01
BD02
BD03
BD04
P2D1
P2D2
P2D3
P2D4
P2D14-OPCLK
P2D13
P2D12
VSSD4
BD13
BD12
JP32
JP26
R39
1k
JP27
JP40
DGND; 3, 4, 5
OPCLK_3
BD05
P2D5
VSSD5
P2D11
VDDD4
C23
C7
DVDD
BD14
IQ
S6
JP46
IQ
DVDD
P2D6
VDDD5
P2D10
P2D9
BD11
BD10
CC0603
0.001µF
6.3V
10µF
+
BCASE
JP31
12
U4
74VCX86
11
OPCLK
IQ
BD06
BD09
13
BCASE
+
C6
10µF
C22
CC0603
BD07
41
P2D7
P2D8
BD08
DVDD; 14
JP34
6.3V
0.001µF
AD9777+TSP
DGND; 7
C45
0.01µF
CC0805
OPCLK
S5
AGND; 3, 4, 5
02706-B-106
Rev. B | Page 52 of 60
Page 53
AD9777
CC0805ACASE
CC0805ACASE
CC0805ACASE
R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9
RP7
RCOM
RP5
DNP
21 34567891021 345678910
50
C33
0.1µF
+
C30
6.3V
4.7µF
CX3
DVDD
8
DVDD; 14
DVDD; 14
AGND; 7
U3
74VCX86
231
AGND; 7
U3
74VCX86
564
CX1
AD15
AD14
AD13
AD12
AD11
AD10
DVDD; 14
AGND; 7
U3
74VCX86
9
10
CX2
AD09
AD08
AD07
AD06
AD05
AD04
AD03
RP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22
RP1 22
116
215
314
413
512
611
710
89
116
215
314
413
512
DVDD
AD02
AD01
611
C34
0.1µF
+
C31
6.3V
4.7µF
DVDD; 14
U4
74VCX86
564
AD00
710
89
AGND; 7
RP8
21 345678910
RP6
50
DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
DVDD
DVDD
4 10
C53
0.1µF
+
C52
6.3V
4.7µF
9
7
AGND; 8
CLR
DVDD; 16
14
U7
Q
Q
PRE
J
CLK
K
11
12
13
74LCX112
OPCLK_3
DVDD; 14
AGND; 7
U4
OPCLK_2
74VCX86
231
5
6
Q
Q
15
PRE
3
CLR
J
CLK
K
1
2
U7
74LCX112
RCOM
DATA-A
21 345678910
R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
1
2
357
468
9
11
13151719212325272931333537
101214161820222426283032343638
39
40
Figure 107. AD9777 Evaluation Board Input (A Channel) and Clock Buffer Circuitry
Rev. B | Page 53 of 60
J1
RIBBON
OPCLK
ADCLK
R15
RC1206
220
02706-B-107
Page 54
AD9777
RC0805
R21
DNP
C47
R14
CLKVDD
1nF
200
c
R20
CC805
RC0805
c
CLKVDD
RC0805
DNP
MC100EPT22
R4
120
RC0805
C46
JP42
1
0.1µF
CLKP
JP41
U8
7
CLKN
2
CGND; 5
CC805
R22
CLKVDD
RC0805
DNP
C48
CLKVDD; 8
R13
120
RC0805
RC0805
R24
DNP
1nF
RC0805
ACLKX
CC805
R18
c
c
c
200
3
MC100EPT22
6
CLKDD
C51
DVDD
0.1µF
CC805
6.3V
C44
4.7µF
ACASE
P1
SPI PORT
12345
RC0805
R50
9k
RC0805
R48
9k
6
RC0805
R45
9k
4
CLKVDD; 8
CGND; 5
U8
c
C60
0.1µF
CC805
6.3V
C49
4.7µF
+
c
ACASE
12
13
1
2
DGND; 7
U5
74AC14
DGND; 7
U5
74AC14
DVDD; 14
11
10
DVDD; 14
43
DGND; 7
U5
74AC14
DGND; 7
U5
74AC14
DVDD; 14
U5
89
DVDD; 14
U5
65
DGND; 7
DVDD; 14
74AC14
DGND; 7
DVDD; 14
74AC14
12
13
2
1
DGND; 7
U6
DGND; 7
U6
DGND; 7
DVDD; 14
DGND; 7
DVDD; 14
10
U6
11
4
74AC14
DGND; 7
DVDD; 14
74AC14
DVDD; 14
U6
3
74AC14
74AC14
DVDD; 14
8
U6
9
74AC14
DGND; 7
DVDD; 14
6
U6
5
74AC14
C50
0.1µF
R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9
RP9
RCOM
RP12
RCOM
DNP
21 34567891021 345678910
50
DATA-B
BD15
BD14
RP3 22
RP3 22
116
135
246
BD13
BD12
RP3 22
RP3 22
215
314
413
7
8
BD11
BD10
BD09
BD08
BD07
BD06
BD05
BD04
BD03
BD02
BD01
BD00
RP3 22
RP3 22
RP3 22
RP3 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
512
611
710
89
116
215
314
413
9
11
13151719212325272931333537
101214161820222426283032343638
512
611
RP4 22
710
89
21 345678910
RP11
21 345678910
RP10
50
DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
R1 R2 R3 R4 R5 R6 R7 R8 R9
RCOM
39
40
J2
RIBBON
SPCSB
SPCLK
CC805
6.3V
C43
4.7µF
+ +
ACASE
SPSDI
SPSDO
DVDD
Figure 108. AD9777 Evaluation Board Input (B Channel) and SPI Port Circuitry
Rev. B | Page 54 of 60
02706-B-108
Page 55
AD9777
02706-B-109
Figure 109. AD9777 Evaluation Board Components, Top Side
02706-B-110
Figure 110. AD9777 Evaluation Board Components, Bottom Side
Rev. B | Page 55 of 60
Page 56
AD9777
Figure 111. AD9777 Evaluation Board Layout, Layer One ( Top)
02706-B-111
02706-B-112
Figure 112. AD9777 Evaluation Board Layout, Layer Two (Ground Plane)
Rev. B | Page 56 of 60
Page 57
AD9777
02706-B-113
Figure 113. AD9777 Evaluation Board Layout, Layer Three (Power Plane)
02706-B-114
Figure 114. AD9777 Evaluation Board Layout, Layer Four (Bottom)
Rev. B | Page 57 of 60
Page 58
AD9777

OUTLINE DIMENSIONS

0.75
0.60
0.45
SEATING
PLANE
0.15
0.05
1.20
MAX
0.20
0.09
COPLANARITY
0.08
14.00 SQ
12.00 SQ
80
1
PIN 1
TOP VIEW
(PINS DOWN)
20
21
1.05
1.00
0.95
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
0.27
0.22
0.17
61
60
41
40
GAGE PLANE
0.25
3.5°
61
60
BOTTOM
VIEW
41
40
7° 0°
Figure 115. 80-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/ED]
(SV-80)
Dimensions shown in millimeters
80
1
6.00 SQ
20
21

ORDERING GUIDE

Models Temperature Range Package Description Package Option
AD9777BSV −40°C to +85°C 80-Lead Thin Plastic Quad Flatpack (TQFP) SV-80 AD9777BSVRL −40°C to +85°C 80-Lead Thin Plastic Quad Flatpack (TQFP) SV-80 AD9777-EB Evaluation Board
Rev. B | Page 58 of 60
Page 59
AD9777
NOTES
Rev. B | Page 59 of 60
Page 60
AD9777
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
C02706–0–6/04(B)
Rev. B | Page 60 of 60
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