Datasheet AD9775 Datasheet (ANALOG DEVICES)

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Page 1

14-Bit, 160 MSPS, 2×/4×/8× Interpolating

Dual TxDAC+® Digital-to-Analog Converter

FEATURES

14-bit resolution, 160 MSPS/400 MSPS input/output

data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment f

/4, fS/8 digital quadrature modulation capability

Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPI® port Excellent ac performance

SFDR: −71 dBc @ 2 MHz to 35 MHz

W-CDMA ACPR: −71 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL

compatible

FUNCTIONAL BLOCK DIAGRAM

AD9775

Versatile input data interface

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: 1.2 W @ 3.3 V typical On-chip, 1.2 V reference 80-lead, thin quad flat package, exposed pad (TQFP_EP)

APPLICATIONS

Communications

Analog quadrature modulation architecture

3G, multicarrier GSM, TDMA, CDMA systems

Broadband wireless, point-to-point microwave radios

Instrumentation/ATE

AD9775

I AND Q

NONINTERLEAVED

OR INTERLEAVED

DATA

WRITE

SELECT

CLOCK OUT

SPI INTERFACE AND

CONTROL REGISTERS

HALFBAND

DATA

ASSEMBLER

LATCH

MUX

CONTROL

HALF-BAND FILTERS ALSO CAN BE

CONFIGURED FOR ZERO STUFFING ONLY

FILTER1*

HALFBAND

FILTER2*

/2 /2

FILTER3*

161616

HALFBAND

COS

SIN

FILTER

BYPASS

MUX

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

/2, 4, 8

DAC

SIN

COS

)

(

DAC

PRESCALER

PHASE DETECTOR

AND VCO

Figure 1.

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

GAIN DAC

VREF

IDAC

I/Q DAC

GAIN/OFFSET

REGISTERS

DIFFERENTIAL CLK

OFFSET

DAC

OUT

IOFFSET

02858-001

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

AD9775

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Product Highlights....................................................................... 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

Dynamic Specifications ............................................................... 6

Digital Specifications ................................................................... 7

Digital Filter Specifications......................................................... 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Thermal Resistance ...................................................................... 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 17

Mode Control (via SPI Port) ......................................................... 18

Address 0x00............................................................................... 19

Address 0x01............................................................................... 19

Address 0x02............................................................................... 19

Address 0x03............................................................................... 20

Address 0x04............................................................................... 20

Address 0x05, Address 0x09 ..................................................... 20

Address 0x06, Address 0x0A..................................................... 20

Address 0x07, Address 0x0B..................................................... 20

Address 0x08, Address 0x0C..................................................... 20

Functional Description.................................................................. 21

Serial Interface for Register Control........................................ 21

General Operation of the Serial Interface............................... 21

Instruction Byte .......................................................................... 22

Serial Interface Port Pin Descriptions..................................... 22

MSB/LSB Transfers.....................................................................22

Notes on Serial Port Operation ................................................22

DAC Operation........................................................................... 24

1R/2R Mode ................................................................................ 25

Clock Input Configurations...................................................... 25

Programmable PLL .................................................................... 26

Power Dissipation....................................................................... 27

Sleep/Power-Down Modes........................................................ 28

Two-Port Data Input Mode ...................................................... 28

PLL Enabled, Two-Port Mode .................................................. 28

DATACLK Inversion.................................................................. 29

DATACLK Driver Strength....................................................... 29

PLL Enabled, One-Port Mode.................................................. 29

ONEPORTCLK Inversion......................................................... 29

ONEPORTCLK Driver Strength.............................................. 30

IQ Pairing.................................................................................... 30

PLL Disabled, Two-Port Mode................................................. 30

PLL Disabled, One-Port Mode................................................. 30

Digital Filter Modes ................................................................... 31

Amplitude Modulation.............................................................. 31

Modulation, No Interpolation.................................................. 32

Modulation, Interpolation = 2×............................................... 33

Modulation, Interpolation = 4×............................................... 34

Modulation, Interpolation = 8×............................................... 35

Zero Stuffing ............................................................................... 36

Interpolating (Complex Mix Mode)........................................ 36

Operations on Complex Signals............................................... 36

Complex Modulation and Image Rejection of Baseband

Signals .......................................................................................... 37

Image Rejection and Sideband Suppression of Modulated

Carriers ........................................................................................ 38

Applying the Output Configurations........................................... 42

Unbuffered Differential Output, Equivalent Circuit ............. 42

Differential Coupling Using a Transformer............................ 42

Differential Coupling Using an Op Amp................................ 43

Interfacing the AD9775 with the AD8345 Quadrature

Modulator.................................................................................... 43

Evaluation Board............................................................................ 44

Outline Dimensions....................................................................... 54

Ordering Guide .......................................................................... 54

Rev. E | Page 2 of 56

Page 3

AD9775

REVISION HISTORY

12/06—Rev. D to Rev. E

Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29

1/06—Rev. C to Rev. D

Updated Formatting..........................................................Universal

Changes to Figure 32 ....................................................................22

Changes to Figure 108 .................................................................. 55

Updated Outline Dimensions...................................................... 58

Changes to Ordering Guide......................................................... 58

6/04—Rev. B to Rev. C

Updated Layout.................................................................Universal

Changes to DC Specifications ....................................................... 5

Changes to Absolute Maximum Ratings...................................... 9

Changes to the DAC Operation Section .................................... 25

Inserted Figure 38.......................................................................... 25

Changes to Figure 40 ....................................................................26

Changes to Table 11 ...................................................................... 28

Changes to Programmable PLL Section..................................... 28

Changes to Figures 49, 50, and 51............................................... 29

Changes to the PLL Enabled, One-Port Mode Section............ 30

Changes to the PLL Disabled, One-Port Mode Section........... 31

Changes to the Ordering Guide .................................................. 57

Updated Outline Dimensions...................................................... 57

3/03—Rev. A to Rev. B

Changes to Register Description—Address 04h....................... 16

Changes to Equation 1.................................................................. 16

Changes to Figure 8....................................................................... 20

2/03—Rev. 0 to Rev. A

Edits to Features ...............................................................................1

Edits to DC Specifications ..............................................................3

Edits to Dynamic Specifications ....................................................4

Edits to Pin Function Descriptions ...............................................8

Edits to Table I............................................................................... 14

Edits to Register Description—Address 02h............................. 15

Edits to Register Description—Address 03h............................. 16

Edits to Register Description—Address 07h, 0Bh.................... 16

Edits to Equation 1........................................................................ 16

Edits to MSB/LSB Transfers......................................................... 18

Edits to Programmable PLL......................................................... 21

Added New Figure 14................................................................... 22

Renumbered Figures 15–69......................................................... 22

Added Two-Port Data Input Mode Section............................... 23

Edits to PLL Enabled, Two-Port Mode ...................................... 24

Edits to Figure 19 .......................................................................... 24

Edits to Figure 21 .......................................................................... 25

Edits to PLL Disabled, Two-Port Mode ..................................... 25

Edits to Figure 22 .......................................................................... 25

Edits to Figure 23 .......................................................................... 26

Edits to Figure 26a ........................................................................ 27

Edits to Complex Modulation and Image Rejection of Baseband

Signals............................................................................................. 31

Edits to Evaluation Board ............................................................ 39

Edits to Figures 56–59.................................................................. 40

Replaced Figures 60–69................................................................ 42

Updated Outline Dimensions...................................................... 49

Rev. E | Page 3 of 56

Page 4

AD9775

GENERAL DESCRIPTION

The AD97751 is the 14-bit member of the AD977x pincompatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpolation filters; f

/2, fS/4, or fS/8 digital quadrature

modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface.

The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the pass-band noise/distortion performance of TxDAC+ devices. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.

The AD9775 can perform f

/2, fS/4, and fS/8 digital modulation

and image rejection when combined with an analog quadrature modulator. In this mode, the AD9775 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (that is, the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.

The AD977x family includes a flexible clock interface that accepts differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data.

Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range.

Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other patents pending.

The AD9775 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.

Targeted at wide dynamic range, multicarrier and multistandard systems, the superb baseband performance of the AD9775 is ideal for wideband CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high order QAM modulation schemes. The image rejection feature simplifies and can help reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.

PRODUCT HIGHLIGHTS

1. The AD9775 is the 14-bit member of the AD977x pin-

compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family.

2. Direct IF transmission capability for 70 MHz + IFs through

a novel digital mixing process.

/2, fS/4, and fS/8 digital quadrature modulation and user-

3. f

selectable image rejection to simplify/remove cascaded SAW filter stages.

4. A 2×/4×/8× user-selectable, interpolating filter eases data

rate and output signal reconstruction filter requirements.

5. User-selectable, twos complement/straight binary data

coding.

6. User-programmable, channel gain control over 1 dB range

in 0.01 dB increments.

7. User programmable channel offset control ±10% over the

FSR.

8. Ultrahigh speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for easy

interfacing.

10. Flexible clock input with single-ended or differential input,

CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: complete CMOS DAC operates on 1.2 W from

a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation and several sleep functions are provided to reduce power during idle periods.

12. On-chip voltage reference. The AD9775 includes a 1.20 V

temperature compensated band gap voltage reference.

13. 80-lead, thin quad flat package, exposed pad (TQFP_EP).

Rev. E | Page 4 of 56

Page 5

AD9775

SPECIFICATIONS

DC SPECIFICATIONS

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 14 Bits

DC Accuracy1

ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)

Offset Error −0.02 ±0.01 +0.02 % of FSR Gain Error (with Internal Reference) −1.0 +1.0 % of FSR Gain Matching −1.0 ±0.1 +1.0 % of FSR Full-Scale Output Current2 2 20 mA Output Compliance Range −1.0 +1.25 V Output Resistance 200 kΩ Output Capacitance 3 pF Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V Reference Output Current3 100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V Reference Input Resistance 7 kΩ Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C Gain Drift (with Internal Reference) 50 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

AVDD

CLKVDD

CLKVDD (PLL ON)

DVDD

Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V

OPERATING RANGE −40 +85 °C

Measured at I

Nominal full-scale current, I

Use an external amplifier to drive any external load.

100 MSPS f

400 MSPS f

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

Integral Nonlinearity −5 ±1.5 +5 LSB Differential Nonlinearity −3 ±1.0 +3 LSB

Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I I

in SLEEP Mode 23.3 26 mA

AVDD

)

72.5 76 mA

Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

Clock Supply Current (I

)4 8.5 10.0 mA

CLKVDD

) 23.5 mA

CLKVDD

Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I

)4 34 41 mA

DVDD

Nominal Power Dissipation 380 410 mW

DIS

IN PWDN 6.0 mW

DIS

driving a virtual ground.

OUTA

with f

DAC

OUT

= 50 MSPS, fS/2 modulation, PLL enabled.

DAC

, is 32 × the I

OUTFS

= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

current.

REF

1.75 W

Rev. E | Page 5 of 56

Page 6

AD9775

DYNAMIC SPECIFICATIONS

to T

MIN

transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f

Output Settling Time (tST) to 0.025% 11 ns

Output Rise Time 10% to 90%1 0.8 ns

Output Fall Time 10% to 90%

Output Noise, I AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

Spurious-Free Dynamic Range Within a 1 MHz Window

Two-Tone Intermodulation (IMD) to Nyquist (f

Total Harmonic Distortion (THD)

Signal-to-Noise Ratio (SNR)

Adjacent Channel Power Ratio (ACPR)

IF = Baseband, f IF = 19.2 MHz, f

Four-Tone Intermodulation

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I

MAX

) 400 MSPS

DAC

= 20 mA 50 pA/√Hz

OUTFS

= 0 dBFS)

OUT

= 100 MSPS, f

DATA

= 65 MSPS, f

DATA

= 65 MSPS, f

DATA

= 78 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 160 MSPS, f

DATA

= 0 dBFS, f

OUT

= 65 MSPS, f

DATA

= 65 MSPS, f

DATA

= 78 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 160 MSPS, f

DATA

= 100 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 1 MHz 71 84.5 dBc

OUT

= 1 MHz 84 dBc

OUT

= 15 MHz 80 dBc

OUT

= 1 MHz 84 dBc

OUT

= 15 MHz 80 dBc

OUT

= 1 MHz 82 dBc

OUT

= 15 MHz 80 dBc

OUT

= 100 MSPS, f

DATA

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 1 MHz; 0 dBFS −71 −82.5 dB

OUT

= 5 MHz; 0 dBFS 76 dB

OUT

= 5 MHz; 0 dBFS 74 dB

OUT

= 1 MHz 73 91.3 dBc

OUT

= f

OUT1

= 11 MHz 81 dBc

OUT2

= 21 MHz 76 dBc

OUT2

= 11 MHz 81 dBc

OUT2

= 21 MHz 76 dBc

OUT2

= 11 MHz 81 dBc

OUT2

= 21 MHz 76 dBc

OUT2

= −6 dBFS)

OUT2

= 20 mA, interpolation = 2×, differential

OUTFS

0.8 ns

W-CDMA with 3.84 MHz BW, 5 MHz Channel Spacing

= 76.8 MSPS 71 dBc

DATA

= 76.8 MSPS 71 dBc

DATA

21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f

201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f

= MSPS, Missing Center) 75 dBFS

DATA

= 160 MSPS, f

DATA

= 320 MHz) 72 dBFS

DAC

Rev. E | Page 6 of 56

Page 7

AD9775

DIGITAL SPECIFICATIONS

to T

MIN

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V

SERIAL CONTROL BUS

Maximum SCLK Frequency (f Minimum Clock Pulse Width High (t Minimum Clock Pulse Width Low (t

) 15 MHz

SLCK

) 30 ns

PWH

) 30 ns

PWL

Maximum Clock Rise/Fall Time 1 ms Minimum Data/Chip Select Setup Time (tDS) 25 ns Minimum Data Hold Time (tDH) 0 ns Maximum Data Valid Time (tDV) 30 ns RESET Pulse Width 1.5 ns Inputs (SDI, SDIO, SCLK, CSB)

Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF

SDIO Output

Logic 1 Voltage DRVDD − 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA

= 20 mA, unless otherwise noted.

OUTFS

Rev. E | Page 7 of 56

Page 8

AD9775

DIGITAL FILTER SPECIFICATIONS

Table 4. Half-Band Filter No. 1 (43 Coefficients)

Tap Coefficient

1, 43 8 2, 42 0 3, 41 −29 4, 40 0 5, 39 67 6, 38 0 7, 37 −134 8, 36 0 9, 35 244 10, 34 0 11, 33 −414 12, 32 0 13, 31 673 14, 30 0 15, 29 −1079 16, 28 0 17, 27 1772 18, 26 0 19, 25 −3280 20, 24 0 21, 23 10,364 22 16,384

Table 5. Half-Band Filter No. 2 (19 Coefficients)

Tap Coefficient

1, 19 19 2, 18 0 3, 17 −120 4, 16 0 5, 15 438 6, 14 0 7, 13 −1288 8, 12 0 9, 11 5,047 10 8,192

–20

–40

–60

ATTENUATION (dBFS)

–80

–100

–120

OUT

Figure 2. 2× Interpolating Filter Response

–20

–40

–60

ATTENUATION (dBFS)

–80

–100

–120

OUT

Figure 3. 4× Interpolating Filter Response

–20

0.50 1.0 1.5 2.0 (NORMALIZED TO INPUT DATA RATE)

02858-002

02858-003

Table 6. Half-Band Filter No. 3 (11 Coefficients)

Tap Coefficient

1, 11 7 2, 10 0 3, 9 −53 4, 8 0 5, 7 302 6 512

Rev. E | Page 8 of 56

–40

–60

ATTENUATION (dBFS)

–80

–100

–120

OUT

Figure 4. 8× Interpolating Filter Response

2046

(NORMALIZED TO INPUT DATA RATE)

02858-004

Page 9

AD9775

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter With Respect To Rating

AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 V to +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 V to +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 V to +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 V to AVDD + 0.3 V I

, I

OUTA

P1B13 to P1B0, P2B13 to P2B0, RESET DGND −0.3 V to DVDD + 0.3 V DATACLK, PLL_LOCK DGND −0.3 V to DVDD + 0.3 V CLK+, CLK– CLKGND −0.3 V to CLKVDD + 0.3 V LPF CLKGND −0.3 V to CLKVDD + 0.3 V SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 V to DVDD + 0.3 V Junction Temperature 125°C Storage Temperature −65°C to +150°C Lead Temperature (10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

AGND −1.0 V to AVDD + 0.3 V

OUTB

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 8. Thermal Resistance

Package Type θJA Unit

80-Lead Thin Quad Flat Package (TQFP_EP), Exposed Pad

23.5 °C/W

Rev. E | Page 9 of 56

Page 10

AD9775

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLKVDD

LPF

CLKVDD

CLKGND

CLK+ CLK–

CLKGND

DATACLK/PLL_LOCK

DGND

DVDD

P1B13 (MSB)

P1B12 P1B11 P1B10

P1B9 P1B8

DGND

DVDD

P1B7 P1B6

NC = NO CONNECT

OUTA1

AVDD

AGND

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PIN 1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P1B5

P1B4

AVDD

AGND

P1B3

P1B2

DVDD

DGND

AGND

(Not to Scale)

P1B1

OUTB1

AD9775

TxDAC+

TOP VIEW

AGND

OUTA

OUTB

P2B11

AGND

P2B10

AGND

DGND

P1B0 (LSB)

AVDD

DVDD

AGND

AVDD

P2B9

P2B8

AGND

P2B7

AVDD

P2B6

FSADJ1

FSADJ2

REFIO

RESET

SPI_CSB

SPI_CLK

SPI_SDIO

SPI_SDO

DGND

DVDD

P2B0 (LSB)

P2B1

P2B2

P2B3

DGND

DVDD

P2B4

P2B5

IQSEL/P2B13 (MSB)

ONEPORTCLK/P2B12

Figure 5. Pin Configuration

02858-005

Rev. E | Page 10 of 56

Page 11

AD9775

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK− Differential Clock Input. 8 DATACLK/PLL_LOCK

9, 17, 25, 35, 44, 52 DGND Digital Common. 10, 18, 26, 36, 43, 51 DVDD Digital Supply Voltage. 11 to 16, 19 to 24, 27, 28

P1B13 (MSB) to P1B0

(LSB) 29, 30, 49, 50 NC No Connect. 31 IQSEL/P2B13 (MSB)

32 ONEPORTCLK/P2B12

33, 34, 37 to 42, 45 to 48 P2B11 to P2B0 (LSB) Port 2 Data Inputs. 53 SPI_SDO

54 SPI_SDIO

55 SPI_CLK

56 SPI_CSB

57 RESET

58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65, 76, 78, 80 AVDD Analog Supply Voltage. 62, 64, 66, 67, 70, 71,

AGND Analog Common. 74, 75, 77, 79

68, 69 I 72, 73 I

, I

OUTB2

OUTA2

OUTB1, IOUTA1

Differential DAC Current Outputs, Q Channel.

Differential DAC Current Outputs, I Channel.

With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate.

Port 1 Data Inputs.

In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock latches the data into the I channel input register. IQSEL = 0 latches the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB.

With the PLL disabled and the AD9775 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9775 to accept and demux interleaved I and Q data to the I and Q input registers.

In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For more information, see the

Two-Port Data Input Mode section.

Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 0x00. The default setting for this bit is 0, which sets SDIO as an input.

Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge.

Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle.

Logic 1 resets all of the SPI port registers, including Address 0x00, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bit in Address 0x00.

Rev. E | Page 11 of 56

Page 12

AD9775

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I 50 Ω doubly terminated, unless otherwise noted.

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 65 130

FREQUENCY (MHz)

Figure 6. Single-Tone Spectrum @ f

0dBFS

= 65 MSPS with f

DATA

–6dBFS

OUT

= f

DATA

= 20 mA, interpolation = 2×, differential transformer-coupled output,

OUTFS

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 10050 150

FREQUENCY (MHz)

= 78 MSPS with f

DATA

0dBFS

02858-006

Figure 9. Single-Tone Spectrum @ f

OUT

= f

DATA

02858-009

SFDR (dBc)

–12dBFS

Figure 7. In-Band SFDR vs. f

SFDR (dBc)

–6dBFS

0dBFS

–12dBFS

Figure 8. Out-of-Band SFDR vs. f

10 150 5 20 25 30

FREQUENCY (MHz)

@ f

OUT

@ f

DATA

= 65 MSPS

OUT

10 150 5 20 25 30

FREQUENCY (MHz)

02858-007

02858-008

–12dBFS

SFDR (dBc)

–6dBFS

Figure 10. In-Band SFDR vs. f

–6dBFS

SFDR (dBc)

0dBFS

–12dBFS

Figure 11. Out-of-Band SFDR vs. f

10 150 5 20 25 30

FREQUENCY (MHz)

@ f

OUT

@ f

DATA

= 78 MSPS

OUT

10 150 5 20 25 30

FREQUENCY (MHz)

02858-010

02858-011

Rev. E | Page 12 of 56

Page 13

AD9775

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 200100 300

FREQUENCY (MHz)

Figure 12. Single-Tone Spectrum @ f

–6dBFS

0dBFS

= 160 MSPS with f

DATA

OUT

= f

DATA

02858-012

IMD (dBc)

–6dBFS

0dBFS

10 150 5 20 25 30

FREQUENCY (MHz)

Figure 15. Third-Order IMD Products vs. f

–6dBFS

–3dBFS

OUT

@ f

= 65 MSPS

DATA

0dBFS

02858-015

–12dBFS

SFDR (dBc)

0 1020304050

FREQUENCY (MHz)

Figure 13. In-Band SFDR vs. f

SFDR (dBc)

–6dBFS

0dBFS

–12dBFS

0 1020304050

FREQUENCY (MHz)

Figure 14. Out-of-Band SFDR vs. f

OUT

@ f

= 160 MSPS

DATA

= 160 MSPS

DATA

02858-013

02858-014

IMD (dBc)

10 150 5 20 25 30

FREQUENCY (MHz)

Figure 16. Third-Order IMD Products vs. f

IMD (dBc)

–3dBFS

20 300 10 405060

FREQUENCY (MHz)

Figure 17. Third-Order IMD Products vs. f

0dBFS

–3dBFS

@ f

OUT

–6dBFS

@ f

OUT

= 78 MSPS

DATA

= 160 MSPS

DATA

02858-016

02858-017

Rev. E | Page 13 of 56

Page 14

AD9775

–3dBFS

IMD (dBc)

Figure 18. Third-Order IMD Products vs. f

= 160 MSPS, 2× f

1× f

DATA

IMD (dBc)

–15 –5–10 0

Figure 19. Third-Order IMD Products vs. A

= 50 MSPS for All Cases, 1× f

DATA

4× f

20 300 10 405060

FREQUENCY (MHz)

8× f

= 200 MSPS, 8× f

DAC

= 160 MSPS, 4× f

DATA

= 50 MSPS

DATA

4×

2×

(dBFS)

OUT

= 50 MSPS, 2× f

DAC

and Interpolation Rate,

OUT

DATA

8×

1×

and Interpolation Rate,

OUT

= 400 MSPS

= 80 MSPS,

= 100 MSPS,

DAC

02858-018

02858-019

SFDR (dBc)

–6dBFS

3.23.1 3.3 3.4 3.5

0dBFS

AVDD (V)

Figure 21. Third-Order IMD Products vs. AVDD @ f

= 320 MSPS, f

DAC

SNR (dB)

0 10050 150

PLL ON

INPUT DATA RATE (MSPS)

Figure 22. SNR vs. Data Rate for f

DATA

PLL OFF

= 160 MSPS

OUT

= 5 MHz

= 10 MHz,

02858-021

02858-022

SFDR (dBc)

–12dBFS

3.23.1 3.3 3.4 3.5

Figure 20. SFDR vs. AVDD @ f

AVDD (V)

= 10 MHz, f

OUT

–6dBFS

DAC

0dBFS

= 320 MSPS, f

= 160 MSPS

DATA

02858-020

Rev. E | Page 14 of 56

SFDR (dBc)

–50 500 100

78MSPS

= 65MSPS

DATA

TEMPERATURE (

Figure 23. SFDR vs. Temperature @ f

160MSPS

= f

OUT

DATA

/11

02858-023

Page 15

AD9775

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 10050 150

FREQUENCY (MHz)

Figure 24. Single-Tone Spurious Performance, f

= 150 MSPS, No Interpolation

DATA

= 10 MHz,

OUT

02858-024

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 5 10 15 20 25 30 35 40 45 50

FREQUENCY (MHz)

Figure 27. Two-Tone IMD Performance, f

= 150 MSPS, Interpolation = 4×

DATA

02858-027

–20

–40

–60

AMPLITUDE (dBm)

–80

–100

01020304050

FREQUENCY (MHz)

Figure 25. Two-Tone IMD Performance, f

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

100 1500 50 200 250 300

FREQUENCY (MHz)

Figure 26. Single-Tone Spurious Performance, f

= 150 MSPS, Interpolation = 2×

DATA

= 150 MSPS, No Interpolation

DATA

= 10 MHz,

OUT

02858-025

02858-026

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

100 1500 50 200 250 300

FREQUENCY (MHz)

Figure 28. Single-Tone Spurious Performance, f

= 80 MSPS, Interpolation = 4×

DATA

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 5 10 15 20 25

FREQUENCY (MHz)

Figure 29. Two-Tone IMD Performance, f

= 50 MSPS, Interpolation = 8×

DATA

OUT

= 10 MHz,

OUT

= 10 MHz,

02858-028

02858-029

Rev. E | Page 15 of 56

Page 16

AD9775

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

1000 200 300 400

FREQUENCY (MHz)

Figure 30. Single-Tone Spurious Performance, f

= 50 MSPS, Interpolation = 8×

DATA

= 10 MHz,

OUT

02858-030

–20

–40

–60

–80

AMPLITUDE (dBm)

–100

–120

2004060

FREQUENCY (MHz)

Figure 31. Eight-Tone IMD Performance, f

Interpolation = 8×

= 160 MSPS,

DATA

02858-031

Rev. E | Page 16 of 56

Page 17

AD9775

TERMINOLOGY

Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Complex Modulation

The process of passing the real and imaginary components of a signal through a complex modulator (transfer function = e

jωt

= cosωt + jsinωt) and realizing real and imaginary components on the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.

Group Delay

Number of input clocks between an impulse applied at the device input and the peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range.

Impulse Response

Response of the device to an impulse applied to the input.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

(interpolation rate), a digital filter can be constructed with

DATA

a sharp transition band near fDATA/2. Images that would typically appear around f

(output data rate) can be greatly

DAC

suppressed.

Linearity Error

(Also called integral nonlinearity or INL.) It is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of 0 is called offset error. For I are all 0. For I

, 0 mA output is expected when the inputs

OUTA

, 0 mA output is expected when all inputs are

OUTB

set to 1.

Output Compliance Range

The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Pass Band

Frequency band in which any input applied therein passes unattenuated to the DAC output.

Power Supply Rejection

The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.

Tem p er at u re Dr i ft

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

MAX

. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).

Rev. E | Page 17 of 56

Page 18

AD9775

MODE CONTROL (VIA SPI PORT)

Table 10. Mode Control via SPI Port1

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x00 SDIO

Bidirectional 0 = Input 1 = I/O

0x 01 Filter

Interpolation Rate (1×, 2×, 4×, 8×)

0x 02

0 = Signed Input Data

1 = Unsigned

0x 03 Data Rate

Clock Output

0x 04

0 = PLL OFF

1 = PLL ON

0x 05 IDAC Fine Gain Adjustment 0x 06 IDAC Coarse Gain Adjustment 0x 07 IDAC Offset

Adjustment Bit 9

0x 08 IDAC I

OFFSET

Direction

0 = I

OFFSET

on I

OUTA

OFFSET

OUTB

1 = I

on I 0x 09 QDAC Fine Gain Adjustment 0x 0A QDAC Coarse Gain Adjustment

0x 0B QDAC Offset

Adjustment

Bit 9 0x 0C QDAC I

OFFSET

Direction

0 = I

OFFSET

on I

OUTA

OFFSET

OUTB

1 = I

on I 0x 0D Version Register

Default values are shown in bold.

See the Two-Port Data Input Mode section.

LSB, MSB First, 0 = MSB 1 = LSB

Software Reset on Logic 1

Sleep Mode Logic 1 Shuts Down the DAC Output Currents

Power-Down Mode Logic 1 Shuts Down All Digital and Analog Functions

1R/2R Mode DAC Output Current Set by One or Two External Resistors

PLL_LOCK Indicator

0 = 2R, 1 = 1R

Filter Interpolation Rate (1×, 2×, 4×, 8×)

Modulation Mode

/4, fS/8)

/2,

(None, f f

Modulation Mode

/4, fS/8)

/2,

(None, f f

0 = No Zero Stuffing on Interpolation Filters, Logic 1

1 = Real Mix Mode

0 = Complex Mix Mode

0 = e

1 = e

−jωt

+jωt

Enables Zero Stuffing.

0 = Two-Port Mode

1 = One-Port

DATACLK Driver Strength

Mode PLL Divide

DATACLK Invert

0 = No Invert

1 = Invert

ONEPORTCLK

Invert

0 = No Invert

IQSEL Invert

0 = No Invert

1 = Invert

(Prescaler) Ratio

0 = Automatic Charge Pump Control, 1 =

PLL Charge

Pump Control

PLL Charge Pump Control

Programmable

IDAC Offset Adjustment Bit 8

IDAC Offset Adjustment Bit 7

IDAC Offset Adjustment Bit 6

IDAC Offset Adjustment Bit 5

IDAC Offset Adjustment Bit 4

IDAC Offset Adjustment Bit 3

IDAC Offset

Adjustment Bit 1

QDAC Offset Adjustment Bit 8

QDAC Offset

QDAC Offset Adjustment Bit 7

QDAC Offset Adjustment Bit 6

QDAC Offset Adjustment Bit 5

QDAC Offset Adjustment Bit 4

QDAC Offset Adjustment Bit 3

Adjustment Bit 1

DATACLK/ PLL_LOCK

Select

0 = PLLLOCK

1 = DATACLK

Q First 0 = I First 1 = Q First

PLL Divide (Prescaler) Ratio

PLL Charge Pump Control

IDAC Offset Adjustment Bit 2

IDAC Offset Adjustment Bit 0

QDAC Offset Adjustment Bit 2

QDAC Offset Adjustment Bit 0

Rev. E | Page 18 of 56

Page 19

AD9775

REGISTER DESCRIPTIONS

ADDRESS 0x00

Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or output, depending on Bit 7 of the instruction byte.

Bit 6: Logic 0 (default) determines the direction (LSB/MSB first) of the communications and data transfer communications cycles. Refer to the

MSB/LSB Transfers section for more details.

Bit 5: Writing 1 to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. Register Address 0x00 bits are not cleared by this software reset. However, a high level at the RESET pin forces all registers, including those in Address 0x00, to their default state.

Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC output currents.

Bit 3: Power Down. Logic 1 shuts down all analog and digital functions except for the SPI port.

Bit 2: 1R/2R Mode. The default (0) places the AD9775 in tworesistor mode. In this mode, the I DAC references are set separately by the R

currents for the I and Q

REF

resistors on FSADJ1

SET

and FSADJ2 (Pin 60 and Pin 59). In 2R mode, assuming the coarse gain setting is full scale and the fine gain setting is zero, I

FULLSCALE1

= 32 × V

/FSADJ1 and I

REF

FULLSCALE2

= 32 × V

/FSADJ2.

REF

With this bit set to 1, the reference currents for both I and Q DACs are controlled by a single resistor on Pin 60. I

FULLSCALE

in one-resistor mode for both of the I and Q DACs is half of what it would be in 2R mode, assuming all other conditions (R

SET

, register settings) remain unchanged. The full-scale current of each DAC can still be set to 20 mA by choosing a resistor of half the value of the R

value used in 2R mode.

SET

Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading this bit gives the status of the PLL. A Logic 1 indicates the PLL is locked. A Logic 0 indicates an unlocked state.

ADDRESS 0x01

Bit 7 and Bit 6: This is the filter interpolation rate according to the following table.

Table 11.

00 1× 01 2× 10 4× 11 8×

Bit 5 and Bit 4: This is the modulation mode according to the following table.

Table 12.

00 None 01 fS/2 10 fS/4 11 fS/8

Bit 3: Logic 1 enables zero-stuffing mode for interpolation filters.

Bit 2: Default (1) enables the real mix mode. The I and Q data

channels are individually modulated by f

/2, fS/4, or fS/8 after

the interpolation filters. However, no complex modulation is done. In the complex mix mode (Logic 0), the digital modulators on the I and Q data channels are coupled to create a digital complex modulator. When the AD9775 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second IF frequency (that is, the LO of the analog quadrature modulator external to the AD9775) according to the bit value of Register 0x01, Bit 1.

Bit 1: Logic 0 (default) causes the complex modulation to be of the form e

− jωt

, resulting in the rejection of the higher frequency image when the AD9775 is used with an external quadrature modulator. A Logic 1 causes the modulation to be of the form

+jωt

, which causes rejection of the lower frequency image.

Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act as a lock indicator for the internal PLL. A Logic 1 in this register causes Pin 8 to act as a DATACLK. For more information, see the

Two - Port D ata Input Mo d e section.

ADDRESS 0x02

Bit 7: Logic 0 (default) causes data to be accepted on the inputs as twos complement binary. Logic 1 causes data to be accepted as straight binary.

Bit 6: Logic 0 (default) places the AD9775 in two-port mode. I and Q data enters the AD9775 via Ports 1 and 2, respectively. A Logic 1 places the AD9775 in one-port mode in which interleaved I and Q data is applied to Port 1. See detailed information on how to use the DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK modes.

Bit 5: DATACLK Driver Strength. With the internal PLL disabled and this bit set to Logic 0, it is recommended that DATACLK be buffered. When this bit is set to Logic 1, DATACLK acts as a stronger driver capable of driving small capacitive loads.

Bit 4: Logic 0 (default). A value of 1 inverts DATACLK at Pin 8.

Bit 2: Logic 0 (default). A value of 1 inverts ONEPORTCLK at

Pin 32.

Bit 1: Logic 0 (default) causes IQSEL = 0 to direct input data to the I channel, while IQSEL = 1 directs input data to the Q channel.

Bit 0: Logic 0 (default) defines IQ pairing as IQ, IQ… while programming a Logic 1 causes the pair ordering to be QI, QI…

Table 9 for

Rev. E | Page 19 of 56

Page 20

AD9775

ADDRESS 0x03

Bit 7: Allows the data rate clock (divided down from the DAC clock) to be output at either the DATACLK/PLL_LOCK pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this register enables the data rate clock at DATACLK/ PLL_LOCK, while a 1 in this register causes the data rate clock to be output at SPI_SDO. For more information, see the Two-Port Data Input Mode section.

Bit 1 and Bit 0: Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run substantially slower. The divider ratio is set according to the following table.

Table 13.

00 ÷1 01 ÷2 10 ÷4 11 ÷8

ADDRESS 0x04

Bit 7: Logic 0 (default) disables the internal PLL. Logic 1 enables the PLL.

Bit 6: Logic 0 (default) sets the charge pump control to automatic. In this mode, the charge pump bias current is controlled by the divider ratio defined in Address 0x03, Bits 1 and 0. Logic 1 allows the user to manually define the charge pump bias current using Address 0x04, Bits 2, 1, and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the PLL.

Bit 2 to Bit 0: With the charge pump control set to manual, these bits define the charge pump bias current according to the following table.

Table 14.

000 50 A 001 100 µA 010 200 µA 011 400 µA 111 800 µA

ADDRESS 0x05, ADDRESS 0x09

Bit 7 to Bit 0: These bits represent an 8-bit binary number (Bit 7 MSB) that defines the fine gain adjustment of the I (0x05) and Q (0x09) DAC, according to Equation 1.

ADDRESS 0x06, ADDRESS 0x0A

Bit 3 to Bit 0: These bits represent a 4-bit binary number (Bit 3 MSB) that defines the coarse gain adjustment of the I (0x06) and Q (0x0A) DACs, according to Equation 1.

ADDRESS 0x07, ADDRESS 0x0B

Bit 7 to Bit 0: These bits are used in conjunction with Address 0x08, 0x0C, Bit 1 and Bit 0.

ADDRESS 0x08, ADDRESS 0x0C

Bit 1 and Bit 0: The 10 bits from these two address pairs (0x07, 0x08 and 0x0B, 0x0C) represent a 10-bit binary number that defines the offset adjustment of the I and Q DACs, according to Equation 1 (0x07, 0x0B—Bit 7 MSB/0x08, 0x0C— Bit 0 LSB).

ADDRESS 0x08, ADDRESS 0x0C

Bit 7: This bit determines the direction of the offset of the I (0x08) and Q (0x0C) DACs. A Logic 0 applies a positive offset current to I to I

. The magnitude of the offset current is defined by the

OUTB

bits in Addresses 0x07, 0x0B, 0x08, and 0x0C, according to Equation 1.

Equation 1 shows I coarse gain, and offset adjustment when using the 2R mode. In 1R mode, the current I (Pin 60). This current is divided equally into each channel so that a scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.

, while a Logic 1 applies a positive offset current

OUTA

and I

REF

as a function of fine gain,

OUTB

is created by a single FSADJ resistor

OUTA

OUTB

OFFSET

⎡

⎛ ⎜

⎢

⎜

⎢

⎝

⎣

⎡

⎛ ⎜

⎢

⎜

⎢

⎝

⎣

×=

REF

⎛

⎞

⎜

⎟

⎜

⎠

⎝

⎛

⎞

⎜

⎟

⎜

⎠

⎝

OFFSET

⎛ ⎜

1024

⎝

⎞

(A)

⎟ ⎠

⎞ ⎟

⎟ ⎠

⎞ ⎟

⎟ ⎠

ICOARSEI

⎛ ⎜

−

⎜ ⎝

⎛ ⎜

−

⎜ ⎝

⎞

⎛

REFREF

⎟

⎜

⎟

⎝

⎠

ICOARSEI

⎞

⎛

REFREF

⎟

⎜

⎟

⎝

⎠

⎤

⎞

⎟

⎥

25632

⎠

⎥

⎦

⎡

⎤

FINE

⎞

⎢

⎟

⎥

25632

⎢

⎠

⎥

⎦

⎣

Rev. E | Page 20 of 56

⎡

⎛ ⎜

⎢

⎝

⎣

⎛ ⎜

⎝

1024

DATAFINE

⎤

⎛

⎞

⎜

⎟

⎝

⎠

⎛

⎞

⎜

⎟

⎜

⎠

⎝

⎞

(A)

⎟

⎥

224

⎠

⎦

DATA

⎤

⎞

−− ⎟

⎥

(A)

(1)

⎟

⎥

⎠

⎦

Page 21

AD9775

FUNCTIONAL DESCRIPTION

The AD9775 dual interpolating DAC consists of two data channels that can be operated independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9775 capable of 2×, 4×, or 8× interpolation. High speed input and output data rates can be achieved within the following limitations.

Table 15.

Interpolation Rate (MSPS)

1× 160 160 2× 160 320 4× 100 400 8× 50 400

Input Data Rate (MSPS)

DAC Sample Rate (MSPS)

Both data channels contain a digital modulator capable of mixing the data stream with an LO of f where f

is the output data rate of the DAC. A zero-stuffing

DAC

/4, or f

DAC

/8,

/2, f

feature is also included and can be used to improve pass-band flatness for signals being attenuated by the sin(x)/x characteristic of the DAC output. The speed of the AD9775, combined with the digital modulation capability, enables direct IF conversion architectures at 70 MHz and higher.

The digital modulators on the AD9775 can be coupled to form a complex modulator. By using this feature with an external analog quadrature modulator, such as the Analog Devices AD8345, an image rejection architecture can be enabled. To optimize the image rejection capability, as well as LO feedthrough in this architecture, the AD9775 offers programmable (via the SPI port) gain and offset adjust for each DAC.

Also included on the AD9775 are a phase-locked loop (PLL) clock multiplier and a 1.20 V band gap voltage reference. With the PLL enabled, a clock applied to the CLK+/CLK− inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. Each 14-bit DAC provides two complementary current outputs whose full-scale currents can be determined either from a single external resistor or independently from two separate resistors (see the

1R/2R Mode section). The AD9775 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square wave input. Separate voltage supply inputs are provided for each functional block to ensure optimum noise and distortion performance.

Sleep and power-down modes can be used to turn off the DAC output current (sleep) or the entire digital and analog sections (power-down) of the chip. An SPI-compliant serial port is used to program the many features of the AD9775. Note that in power-down mode, the SPI port is the only section of the chip still active.

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9775 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9775. Single- or multiple-byte transfers are supported, as well as MSB-first or LSB-first transfer formats. The AD9775 serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9775. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9775 coincident with the first eight SCLK rising edges. The instruction byte provides the AD9775 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9775.

A Logic 1 on the SPI_CSB pin, followed by a logic low, resets the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the middle of an instruction cycle or a data transfer cycle, none of the present data is written.

The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9775 and the system controller. Phase 2 of the communication cycle is a transfer of one to four data bytes as determined by the instruction byte. Typically, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.

SDO (PIN 53)

SDIO (PIN 54)

PI_CLK (PIN 55)

CSB (PIN 56)

AD9775 SPI PORT

INTERFACE

Figure 32. SPI Port Interface

02858-032

Rev. E | Page 21 of 56

Page 22

AD9775

INSTRUCTION BYTE

The instruction byte contains the information shown next

Table 16.

N1 N0 Description

0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes

R/W

Bit 7 of the instruction byte determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates read operation. Logic 0 indicates a write operation.

N1, N0

Bit 6 and Bit 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown next.

Table 17.

MSB LSB

I7 I6 I5 I4 I3 I2 I1 I0 R/W N1 N0 A4 A3 A2 A1 A0

A4, A3, A2, A1, A0

Bit 4 to Bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9775.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SPI_CLK (Pin 55)—Serial Clock

The serial clock pin is used to synchronize data to and from the AD9775 and to run the internal state machines. SPI_CLK maximum frequency is 15 MHz. All data input to the AD9775 is registered on the rising edge of SPI_CLK. All data is driven out of the AD9775 on the falling edge of SPI_CLK.

SPI_CSB (Pin 56)—Chip Select

Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.

SPI_SDIO (Pin 54)—Serial Data I/O

Data is always written into the AD9775 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 0x00. The default is Logic 0, which configures the SDIO pin as unidirectional.

SPI_SDO (Pin 53)—Serial Data Out

Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9775 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.

MSB/LSB TRANSFERS

The AD9775 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB-first bit in Register 0. The default is MSB first.

When this bit is set active high, the AD9775 serial port is in LSB-first format. In LSB-first mode, the instruction byte and data bytes must be written from LSB to MSB. In LSB-first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle.

When this bit is set default low, the AD9775 serial port is in MSB-first format. In MSB-first mode, the instruction byte and data bytes must be written from MSB to LSB. In MSB-first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle.

When incrementing from 0x1F, the address generator changes to 0x00. When decrementing from 0x00, the address generator changes to 0x1F.

NOTES ON SERIAL PORT OPERATION

The AD9775 serial port configuration bits reside in Bit 6 and Bit 7 of Register Address 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle.

The same considerations apply to setting the reset bit in Register Address 0x00. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 0x00.

It is recommended to use only single-byte transfers when changing serial port configurations or initiating a software reset.

A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the same logic levels as for Bit 7, Bit 6, and Bit 5 (bit pattern is XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 0x00 with reset bit low and serial port configuration as specified above (XY) reprograms the OSC IN multiplier setting. A changed f maximum of 200 f

cycles (equals wake-up time).

MCLK

frequency is stable after a

SYSCLK

Rev. E | Page 22 of 56

Page 23

AD9775

SCLK

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SDIO

SDO

R/W I4 I3 I2 I1 I0 D7

(N)I5(N)

D7ND6

D20D10D0

02858-033

Figure 33. Serial Register Interface Timing MSB First

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SCLK

SDIO

SDO

I0 I1 I2 I3 I4 I5

(N)I6(N)

R/W D00D10D2

D00D10D2

D6ND7

02858-034

Figure 34. Serial Register Interface Timing LSB First

PWH

SCLK

PWL

SCLK

SDIO

INSTRUCTION BIT 7 INSTRUCTION BIT 6

02858-035

Figure 35. Timing Diagram for Register Write to AD9775

SCLK

SDIO

DATA BIT N

SDO

DATA BIT N–1

02858-036

Figure 36. Timing Diagram for Register Read from AD9775

Rev. E | Page 23 of 56

Page 24

AD9775

DAC OPERATION

The dual, 14-bit DAC output of the AD9775, along with the reference circuitry, gain, and offset registers, is shown in Note that an external reference can be used by simply overdriving the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external R

resistor, and the values

SET

in the coarse gain register. The fine gain DAC subtracts a small amount from this and the result is input to IDAC and QDAC, where it is scaled by an amount equal to 1024/24. Figure 39 show the scaling effect of the coarse and fine adjust DACs. IDAC and QDAC are PMOS current source arrays, segmented in a 5-4-5 configuration. The 5 MSBs control an array of 31 current sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current source. The 5 LSBs are binary weighted fractions of the middle bits’ current sources. All current sources are switched to either I

or I

OUTA

, depending on the input code.

OUTB

The fine adjustment of the gain of each channel allows for improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection.

In the section Quadrature Modulator

Interfacing the AD9775 with the AD8345

, the performance data shows to what degree image rejection can be improved when the AD9775 is used with an AD8345 quadrature modulator from Analog Devices, Inc.

AVDD

4μA

REFIO

7kΩ

0.7V

Figure 37.

Figure 38 and

COARSE REFERENCE CURRENT (mA)

–0.5

–1.0

–1.5

–2.0

FINE REFERENCE CURRENT (mA)

–2.5

–3.0

Figure 38. Coarse Gain Effect on I

2R M ODE

1R MODE

501015 COARSE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

FULLSCALE

1R MODE

2R MODE

200 400 600 800 1000

FINE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

Figure 39. Fine Gain Effect on I

FULLSCALE

02858-039

02858-040

02858-038

Figure 37. Equivalent Internal Reference Circuit

OFFSET

DAC

OFFSET

DAC

OUTA1

OUTB1

OUTA2

OUTB2

02858-037

GAIN

CONTROL

REGISTERS

1.2VREF

REFIO

0.1μF

FSADJ1

RSET1

FINE GAIN DAC

COARSE

GAIN

RSET2

DAC

FSADJ2

COARSE

GAIN

DAC

GAIN

CONTROL

REGISTERS

CONTROL

REGISTERS

IDAC

QDAC

CONTROL

REGISTERS

Figure 40. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust

Rev. E | Page 24 of 56

Page 25

AD9775

The offset control defines a small current that can be added to I

or I

OUTA

of which I via Register

(not both) on the IDAC and QDAC. The selection

OUTB

this offset current is directed toward is programmable

OUT

0x08, Bit 7 (IDAC) and Register 0x0C, Bit 7 (QDAC). Figure 41 shows the scale of the offset current that can be added to one of the complementary outputs on the IDAC and QDAC. Offset control can be used for suppression of LO leakage resulting from modulation of dc signal components. If the AD9775 is dccoupled to an external modulator, this feature can be used to cancel the output offset on the AD9775 as well as the input offset on the modulator.

Figure 42 shows a typical example of the effect

that the offset control has on LO suppression.

Figure 42, the negative scale represents an offset added to I

while the positive scale represents an offset added to I

OUTA

OUTB

of the

respective DAC. Offset Register 1 corresponds to IDAC, while Offset Register 2 corresponds to QDAC.

Figure 42 represents the AD9775 synthesizing a complex signal that is then dc-coupled to an AD8345 quadrature modulator with an LO of 800 MHz. The dc coupling allows the input offset of the AD8345 to be calibrated out as well. The LO suppression at the AD8345 output was optimized first by adjusting Offset Register 1 in the AD9775. When an optimal point was found (roughly Code 54), this code was held in Offset Register 1, and Offset Register 2 was adjusted. The resulting LO suppression is 70 dBFS. These are typical numbers; the specific code for optimization varies from part to part.

–10

–20

–30

–40

–50

LO SUPPRESSION (dBFS)

–60

–70

–80

DAC1, DAC2 (OFFSET REGISTER CODES)

OFFSET REGISTER 1 ADJUSTED

OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE

0–256–768 –512–1024 256 512 768 1024

Figure 42. Offset Adjust Control, Effect on LO Suppression

CLOCK INPUT CONFIGURATIONS

The clock inputs to the AD9775 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources.

Figure 43 shows the AD9775 driven from a single-ended clock source. The CLK+/CLK− pins form a differential input (CLKIN) so that the statically terminated input must be dcbiased to the midswing voltage level of the clock driven input.

02858-042

1R/2R MODE

In 2R mode, the reference current for each channel is set independently by the FSADJ resistor on that channel. The AD9775 can be programmed to derive its reference current from a single resistor on Pin 60 by placing the part into 1R mode. The transfer functions in Equation 1 are valid for 2R mode. In 1R mode, the current developed in the single FSADJ resistor is split equally between the two channels. The result is that in 1R mode, a scale factor of 1/2 must be applied to the formulas in Equation 1. The full-scale DAC current in 1R mode can still be set to as high as 20 mA by using the internal 1.2 V reference and a 950 Ω resistor instead of the 1.9 kΩ resistor typically used in the 2R mode.

OFFSET CURRENT (mA)

0 200 400 600 800 1000

COARSE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

Figure 41. DAC Output Offset Current

2R MODE

1R MODE

02858-041

AD9775

THRESHOLD

SERIES

0.1μF

CLK+

CLKVDD

CLK–

CLKGND

02858-043

Figure 43. Single-Ended Clock Driving Clock Inputs

A configuration for differentially driving the clock inputs is given in

Figure 44. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed CLKVDD or CLKGND. If the driver voltage swings are within the supply range of the AD9775, the dc-blocking capacitors and bias resistors are not necessary.

AD9775

0.1μF

ECL/PECL

0.1μF

Figure 44. Differential Clock Driving Clock Inputs

1kΩ

CLK+

CLKVDD

CLK–

CLKGND

02858-044

Rev. E | Page 25 of 56

Page 26

AD9775

A transformer, such as the T1-1T from Mini-Circuits®, can also be used to convert a single-ended clock to differential. This method is used on the AD9775 evaluation board so that an external sine wave with no dc offset can be used as a differential clock.

PECL/ECL drivers require varying termination networks, the details of which are left out of

Figure 43 and Figure 44 but can be found in application notes such as AND8020/D from ON Semiconductor®. These networks depend on the assumed transmission line impedance and power supply voltage of the clock driver.

Optimum performance of the AD9775 is achieved when the driver is placed very close to the AD9775 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch.

The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry should provide the AD9775 with a low jitter clock input that meets the minimum/maximum logic levels while providing fast edges. Although fast clock edges help minimize any jitter that manifests itself as phase noise on a reconstructed waveform, the high gain bandwidth product of the AD9775 clock input comparator can tolerate differential sine wave inputs as low as 0.5 V p-p with minimal degradation of the output noise floor.

PROGRAMMABLE PLL

CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled) according to the state of Address 0x02, Bit 7 in the SPI port register. The internal operation of the AD9775 clock circuitry in these two modes is illustrated in

The PLL clock multiplier and distribution circuitry produce the necessary internal synchronized 1×, 2×, 4×, and 8× clocks for the rising edge triggered latches, interpolation filters, modulators, and DACs. This circuitry consists of a phase detector, charge pump, voltage controlled oscillator (VCO), prescaler, clock distribution, and SPI port control.

The charge pump, VCO, differential clock input buffer, phase detector, prescaler, and clock distribution are all powered from CLKVDD. PLL lock status is indicated by the logic signal at the DATACLK_PLL_LOCK pin, as well as by the status of Bit 1, Register 0x00. To ensure optimum phase noise performance from the PLL clock multiplier and distribution, CLKVDD should originate from a clean analog supply. the minimum input data ra divider setting. If the input data rate drops below the defined minimum under these conditions, VCO noise may increase significantly. The VCO speed is a function of the input data rate, the interpolation rate, and the VCO prescaler, according to the following function:

VCO Speed (MHz) = Input Data Rate (MHz) × Interpolation Rate × Prescaler

Figure 45 and Figure 46.

Tabl e 1 8 defines

tes vs. the interpolation and PLL

PLL_LOCK

1 = LOCK

0 = NO LOCK

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

2148

INPUT

DATA

LATCHES

INTERPOLATION

RATE

CONTROL

CLOCK

DISTRIBUTION

CIRCUITRY

INTERNAL SPI

CONTROL

REGISTERS

SPI PORT

Figure 45. PLL and Clock Circuitry with PLL Enabled

PLL_LOCK

1 = LOCK

0 = NO LOCK

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

2148

INPUT

DATA

LATCHES

INTERPOLATION

RATE

CONTROL

CLOCK

DISTRIBUTION

CIRCUITRY

INTERNAL SPI

CONTROL

REGISTERS

SPI PORT

Figure 46. PLL and Clock Circuitry with PLL Disabled

Table 18. PLL Optimization

Interpolation Rate

Divider Setting

1 1 32 160 1 2 16 160 1 4 8 112 1 8 4 56 2 1 24 160 2 2 12 112 2 4 6 56 2 8 3 28 4 1 24 100 4 2 12 56 4 4 6 28 4 8 3 14 8 1 24 50 8 2 12 28 8 4 6 14 8 8 3 7

CLK+ CLK–

PHASE

DETECTOR

PRESCALER VCO

MODULATION

RATE

CONTROL

CLK+ CLK–

PHASE

DETECTOR

PRESCALER VCO

MODULATION

RATE

CONTROL

Minimum f

DATA

AD9775

CHARGE

PUMP

PLL DIVIDER

(PRESCALER)

CONTROL

PLL

CONTROL

(PLL ON)

AD9775

CHARGE

PUMP

PLL DIVIDER

(PRESCALER)

CONTROL

PLL

CONTROL

(PLL ON)

PLLVDD

Maximum f

DATA

LPF

02858-045

02858-046

Rev. E | Page 26 of 56

Page 27

AD9775

In addition, if the zero-stuffing option is enabled, the VCO doubles its speed again. Phase noise may be slightly higher with the PLL enabled.

Figure 47 illustrates typical phase noise performance of the AD9775 with 2× interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of f

/4. The repetitive

DATA

nature of this signal eliminates quantization noise and distortion spurs as a factor in the measurement. Although the curves blend together in

Tabl e 1 9 . Figure 47 also contains a table detailing the maximum

in and minimum f

Figure 47, the different conditions are given for clarity

rates for each combination of interpolation

DATA

rate and PLL divider setting. These rates are guaranteed over the entire supply and operating temperature range.

Figure 48 shows typical performance of the PLL lock signal (Pin 8 or Pin 53) when the PLL is in the process of locking.

Table 19. Required PLL Prescaler Ratio vs. f

PLL Prescaler Ratio

DATA

125 MSPS Disabled 125 MSPS Enabled Div 1 100 MSPS Enabled Div 2 75 MSPS Enabled Div 2 50 MSPS Enabled Div 4

0 –10 –20 –30 –40 –50 –60 –70

PHASE NOISE (dBFS)

–80 –90

–100 –110

012345

FREQUENCY OFFSET (MHz)

Figure 47. Phase Noise Performance

02858-047

It is important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9775. This suffices unless the input data rate is below 10 MHz, in which case an external series RC is required between the LPF pin and CLKVDD pins.

POWER DISSIPATION

The AD9775 has three voltage supplies: DVDD, AVDD, and CLKVDD. required from each of these supplies when each is set to the 3.3 V nominal specified for the AD9775. Power dissipation (P easily be extracted by multiplying the given curves by 3.3. As Figure 49 shows, I the interpolation rate, and the activation of the internal digital modulator. I modulation rate by itself. In of sensitivity to the data, the interpolation rate, and the modulator function but to a much lesser degree (<10%). In I

CLKVDD

percentage of the overall AD9775 supply current requirements.

(mA)

DVDD

Figure 49 through Figure 51 show the current

) can

is very dependent on the input data rate,

DVDD

, however, is relatively insensitive to the

DVDD

Figure 50, I

shows the same type

AVD D

Figure 51,

varies over a wide range yet is responsible for only a small

400

350

300

250

200

150

100

Figure 49. I

76.0

75.5

75.0

8×, (MOD. ON)

DVDD

8×, (MOD. ON)

, (MOD. ON)

500 100 150 200

(MHz)

DATA

vs. f

vs. Interpolation Rate, PLL Disabled

DATA

, (MOD. ON)

2×, (MOD. ON)

02858-049

Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking

(Typical Lock Time)

02858-048

Rev. E | Page 27 of 56

74.5

(mA)

74.0

AVDD

73.5

73.0

72.5

72.0

Figure 50. I

500 100 150 200

AVDD

(MHz)

DATA

vs. f

vs. Interpolation Rate, PLL Disabled

DATA

02858-050

Page 28

AD9775

500 100 150 200

(MHz)

DATA

vs. f

CLKVDD

vs. Interpolation Rate, PLL Disabled

DATA

(mA)

CLKVDD

Figure 51 I

SLEEP/POWER-DOWN MODES

(Control Register 0x00, Bit 3 and Bit 4)

The AD9775 provides two methods for programmable reduction in power savings. The sleep mode, when activated, turns off the DAC output currents but the rest of the chip remains functioning. When coming out of sleep mode, the AD9775 immediately returns to full operation. Power-down mode, on the other hand, turns off all analog and digital circuitry in the AD9775 except for the SPI port. When returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle.

TWO-PORT DATA INPUT MODE

The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In two-port mode, data at the two input ports is latched into the AD9775 on every rising edge of the data rate clock (DATACLK). Also, in two-port mode, the AD9775 can be programmed to generate an externally available DATACLK for the purpose of data synchronization.

This data rate clock can be programmed to be available at either Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because Pin 8 can also function as a PLL lock indicator when the PLL is enabled, there are several options for configuring Pin 8 and Pin 53. The following sections describe the options.

PLL Off (Register 4, Bit 7 = 0)

02858-051

PLL On (Register 4, Bit 7 = 1)

Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53. Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53.

In one-port mode, P2B14 and P2B15 from Input Data Port 2 are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one-port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9775 in this mode for the purpose of data synchronization. ONEPORTCLK runs at the input interleaved data rate, which is 2× the data rate at the internal input to either channel.

Figure 101 through Figure 104 illustrate the test configurations showing the various clocks that are required and generated by the AD9775 with the PLL enabled/disabled and in the oneport/two-port modes. Jumper positions needed to operate the AD9775 evaluation board in these modes are given as well.

PLL ENABLED, TWO-PORT MODE

(Control Register 0x02, Bit 6 to Bit 0 and Control Register 0x04, Bit 7 to Bit 1)

With the phase-locked loop (PLL) enabled and the AD9775 in two-port mode, the speed of CLKIN is inherently that of the input data rate. In two-port mode, Pin 8 (DATACLK/PLL_ LOCK) can be programmed (Control Register 0x01, Bit 0) to function as either a lock indicator for the internal PLL or as a clock running at the input data rate. When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of CLKIN. Data at the input ports is latched into the AD9775 on the rising edge of the CLKIN. inherent between the rising edge of CLKIN and the rising edge of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2. The setup and hold times given in Figure 52 are the input data transitions with respect to CLKIN. Note that in two-port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at Port 1 and Port 2.

The DAC output sample rate in two-port mode is equal to the clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.

Figure 52 shows the delay, tOD,

Rev. E | Page 28 of 56

Page 29

AD9775

DATACLK INVERSION

(Control Register 0x02, Bit 4)

By programming this bit, the DATACLK signal shown in Figure 52 can be inverted. With inversion enabled, t

refers to

the time between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing occurs.

CLKIN

DATACLK

DATA AT PORTS

1 AND 2

= 1.5ns (MIN) TO 2.5ns (MAX)

= 0.0ns (MIN)

Figure 52. Timing Requirements in Two-Port Input Mode, with PLL Enabled

= 2.5ns (MIN)

DATACLK DRIVER STRENGTH

(Control Register 0x02, Bit 5)

The DATACLK output driver strength is capable of driving >10 mA into a 330  load while providing a rise time of 3 ns. Figure 53 shows DATACLK driving a 330 Ω resistive load at a frequency of 50 MHz. By enabling the drive strength option (Control Register 0x02, Bit 5), the amplitude of DATACLK under these conditions increases by approximately 200 mV.

3.0

2.5

2.0

02858-052

PLL ENABLED, ONE-PORT MODE

(Control Register 0x02, Bit 6 to Bit 1 and Control Register 0x04, Bit 7 to Bit 1)

In one-port mode, the I and Q channels receive their data from an interleaved stream at digital input Port 1. The function of Pin 32 is defined as an output (ONEPORTCLK) that generates a clock at the interleaved data rate, which is 2× the internal input data rate of the I and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. The selection of the data for the I or the Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9775 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 0x02, Bit 1 to the invert state (Logic 1). Figure 54 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one-port mode.

The DAC output sample rate in one-port mode is equal to CLKIN multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.

ONEPORTCLK INVERSION

(Control Register 0x02, Bit 2)

By programming this bit, the ONEPORTCLK signal shown in Figure 54 can be inverted. With inversion enabled, t the delay between the rising edge of the external clock and the falling edge of ONEPORTCLK. The setup and hold times, t and t

, are with respect to the falling edge of ONEPORTCLK.

There is no other effect on timing.

CLKIN

TO 5.5ns (MAX)

= 3.0ns (MIN)

= –0.5ns (MIN)

IQS

IQH

refers to

= 4.0ns (MIN)

= 3.5ns (MIN) = –1.5ns (MIN)

1.5

1.0

AMPLITUDE (V)

0.5

–0.5

0 1020304050

DELTA APPROX. 2.8ns

TIME (ns)

Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

02858-053

Rev. E | Page 29 of 56

ONEPORTCLK

IQSEL

IQS

IQH

Figure 54. Timing Requirements in One-Port

Input Mode with the PLL Enabled

02858-054

Page 30

AD9775

ONEPORTCLK DRIVER STRENGTH

The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to

Figure 53 for

performance under load conditions.

IQ PAIRING

(Control Register 0x02, Bit 0)

In one-port mode, the interleaved data is latched into the AD9775 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. The following is an example of the effect that this has on incoming interleaved data.

Given the following interleaved data stream, where the data indicates the value with respect to full scale:

Table 20.

I Q I Q I Q I Q I Q

0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5

With the control register set to 0 (I first), the data appears at the internal channel inputs in the following order in time:

Table 21.

I Channel 0.5 1 0.5 0 0.5 Q Channel 0.5 1 0.5 0 0.5

With the control register set to 1 (Q first), the data appears at the internal channel inputs in the following order in time:

Table 22.

I Channel 0.5 1 0.5 0 0.5 x Q Channel y 0.5 1 0.5 0 0.5

The values x and y represent the next I value and the previous Q value in the series.

PLL DISABLED, TWO-PORT MODE

With the PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal clock dividers in the AD9775 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Port 1 and Port 2 of the AD9775 on the rising edge of DATACLK. DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate. With zero stuffing enabled, this division increases by a factor of 2. illustrates the delay between the rising edge of CLKIN and the rising edge of DATACLK, as well as t

and tH in this mode.

The programmable modes DATACLK inversion and DATACLK driver strength described in the previous section ( Two-Po r t Mode

) have identical functionality with the PLL

disabled.

The data rate clock created by dividing down the DAC clock in this mode can be programmed (via Register 0x03, Bit 7) to be output from the SPI_SDO pin rather than the DATACLK/ PLL_LOCK pin. In some applications, this may improve complex image rejection. When SPI_SDO is used as data rate clock out, t

increases by 1.6 ns.

Figure 55

PLL Enabled,

CLKIN

DATACLK

DATA AT PORT

1 AND 2

= 6.5ns (MIN) TO 8.0ns (MAX)

tSt

= 5.0ns (MIN)

= –3.2ns (MIN)

Figure 55. Timing Requirements in Two-Port Input Mode with PLL Disabled

CLKIN

ONEPORTCLK

I AND Q INTERLEAVED

INPUT DATA AT PORT

= 4.0ns (MIN)

TO 5.5ns (MAX)

= 3.0ns (MIN)

= –1.0ns (MIN)

= 3.5ns (MIN)

IQS

= –1.5ns (MIN)

IQH

IQSEL

IQS

IQH

Figure 56. Timing Requirements in One-Port Input Mode with PLL Disabled

PLL DISABLED, ONE-PORT MODE

In one-port mode, data is received into the AD9775 as an interleaved stream on Port 1. A clock signal (ONEPORTCLK) running at the interleaved data rate, which is 2× the input data rate of the internal I and Q channels, is available for data synchronization at Pin 32.

With PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal dividers synthesize the ONEPORTCLK signal at Pin 32. The selection of the data for the I or Q channel is determined by the state of the logic level applied to Pin 31 (IQSEL when the AD9775 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel.

02858-055

02858-056

Rev. E | Page 30 of 56

Page 31

AD9775

It is possible to invert the I and Q selection by setting control Register 0x02, Bit 1 to the invert state (Logic 1).

Figure 56 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one-port mode.

One-port mode is very useful when interfacing with devices such as the Analog Devices AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed).

The programmable modes’ ONEPORTCLK inversion, ONEPORTCLK driver strength, and IQ pairing described in the

PLL Enabled, One-Port Mode section have identical

functionality with the PLL disabled.

DIGITAL FILTER MODES

The I and Q datapaths of the AD9775 have their own independent half-band FIR filters. Each datapath consists of three FIR filters, providing up to 8× interpolation for each channel. The rate of interpolation is determined by the state of Control Register

0x01, Bit 7 and Bit 6.

Figure 2 to Figure 4 show the response of the digital filters when the AD9775 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs are normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than 75 dB of out-of-band rejection.

An online tool is available for quick and easy analysis of the AD9775 interpolation filters in the various modes. The link can be accessed at

www.analog.com/ad9777image.

AMPLITUDE MODULATION

Given two sine waves at the same frequency, but with a 90 degree phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative

frequency images. This is shown graphically in the frequency domain in

Figure 57.

–jωt

/2j

SINE

–jωt

/2j

–jωt

/2 e

Figure 57. Real and Imaginary Components of

Sinusoidal and Cosinusoidal Waveforms

–jωt

COSINE

02858-057

Amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of 2.

This scaling is very important in the discussion of the various modulation modes. The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. Examples of sine and cosine modulation are given in

Figure 58.

–jωt

/2j

SINUSOIDAL MODULATION

–jωt

/2j

–jωt

/2 Ae

Figure 58. Baseband Signal, Amplitude Modulated

with Sine and Cosine Carriers

–jωt

COSINUSOIDAL MODULATION

02858-058

Rev. E | Page 31 of 56

Page 32

AD9775

MODULATION, NO INTERPOLATION

With Control Register 0x01, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9775 is disabled. through

Figure 62 show the DAC output spectral characteristics of the AD9775 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 0x01, Bit 5 and Bit The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. By comparing the digital

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation Disabled

Figure 59

domain spectrum to the DAC sin(x)/x roll-off, an estimate can be made for the characteristics required for the DAC reconstruction filter.

Note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to f

/4 or fS/8) are scaled by a factor of 2. In the situation

where the modulation is f

/2, the modulated spectral

components add constructively, and there is no scaling effect.

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

0 0.2 0.4 0.6 0.8 1.0

(

DATA

)

OUT

Figure 59. No Interpolation, Modulation Disabled

–20

–40

–60

AMPLITUDE (dBFS)

–80

02858-059

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

0 0.2 0.4 0.6 0.8 1.0

(

DATA

)

OUT

Figure 61. No Interpolation, Modulation = f

–20

–40

–60

AMPLITUDE (dBFS)

–80

DAC

02858-061

–100

0 0.2 0.4 0.6 0.8 1.0

(

DATA

)

OUT

Figure 60. No Interpolation, Modulation = f

DAC

02858-060

Rev. E | Page 32 of 56

–100

0 0.2 0.4 0.6 0.8 1.0

(

DATA

)

OUT

Figure 62. No Interpolation, Modulation = f

DAC

02858-062

Page 33

AD9775

MODULATION, INTERPOLATION = 2×

With Control Register 0x01, Bit 7 and Bit 6 set to 01, the interpolation rate of the AD9775 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1).

Figure 63 through Figure 66 represent the spectral response of the AD9775 DAC output with 2× interpolation in the various modulation modes to a narrowband baseband signal (the tall rectangles in the graphic). The advantage of interpolation becomes clear in

Figure 63 through Figure 66, where the images that would normally appear in the spectrum around the input data rate frequency are suppressed by >70 dB.

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 2×

Another significant point is that the interpolation filtering is done previous to the digital modulator. For this reason, as Figure 63 through Figure 66 show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high-pass digital filter.

Note that when using the f

/4 modulation mode, there is no

true stop band as the band edges coincide with each other. In the f

/8 modulation mode, amplitude scaling occurs over only a

portion of the digital filter pass band due to constructive addition over just that section of the band.

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

0.50 1.0 1.5 2.0

(×

DATA

)

OUT

Figure 63. 2× Interpolation, Modulation = Disabled

–20

–40

–60

–80

02858-063

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

–20

–40

–60

–80

0.50 1.0 1.5 2.0

(×

OUT

DATA

Figure 65. 2× Interpolation, Modulation = f

)

DAC

02858-065

–100

0.50 1.0 1.5 2.0

(×

DATA

)

OUT

Figure 64. 2× Interpolation, Modulation = f

DAC

02858-064

Rev. E | Page 33 of 56

–100

0.50 1.0 1.5 2.0

(×

DATA

)

OUT

Figure 66. 2× Interpolation, Modulation = f

DAC

02858-066

Page 34

AD9775

MODULATION, INTERPOLATION = 4×

With Control Register 0x01, Bit 7 and Bit 6 set to 10, the interpolation rate of the AD9775 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1).

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 4×

Figure 67 through Figure 70 represent the spectral response of the AD9775 DAC output with 4× interpolation in the various modulation modes to a narrow-band baseband signal.

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

–20

–40

–60

–80

1023

(×

DATA

)

OUT

Figure 67. 4× Interpolation, Modulation Disabled

AMPLITUDE (dBFS)

02858-067

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

–20

–40

–60

–80

1023

(×

OUT

DATA

Figure 69. 4× Interpolation, Modulation = f

)

DAC

02858-069

–100

1023

(×

DATA

)

DAC

OUT

Figure 68. 4× Interpolation, Modulation = f

02858-068

Rev. E | Page 34 of 56

–100

1023

(×

DATA

)

DAC

OUT

Figure 70. 4× Interpolation, Modulation = f

02858-070

Page 35

AD9775

MODULATION, INTERPOLATION = 8×

With Control Register 0x01, Bit 7 and Bit 6 set to 11, the interpolation rate of the AD9775 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1, +0.707).

Figure 71 through Figure 74 represent the spectral response of the AD9775 DAC output with 8× interpolation in the various modulation modes to a narrow-band baseband signal.

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8×

Looking at

Figure 63 through Figure 74, the user can see how higher interpolation rates reduce the complexity of the reconstruction filter needed at the DAC output. It also becomes apparent that the ability to modulate by f

/2, fS/4, or fS/8 adds a

degree of flexibility in frequency planning.

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

–20

–40

–60

–80

1023

(×

DATA

)

OUT

Figure 71. 8× Interpolation, Modulation Disabled

02858-071

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

–20

–40

–60

–80

43120 5678

(×

OUT

DATA

Figure 73. 8× Interpolation, Modulation = f

)

DAC

02858-073

–100

1023

(×

DATA

)

DAC

OUT

Figure 72. 8× Interpolation, Modulation = f

02858-072

Rev. E | Page 35 of 56

–100

43120 5678

(×

DATA

)

OUT

Figure 74. 8× Interpolation, Modulation = f

DAC

02858-074

Page 36

AD9775

(

)

ZERO STUFFING

(Control Register 0x01, Bit 3)

As shown in Figure 75, a 0 or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f is due to the inherent sin(x)/x roll-off response in the digital-toanalog conversion. In applications where the desired frequency content is below f f

/2 the loss due to sin(x)/x is 4 dB. In direct RF applications,

DAC

/2, this may not be a problem. Note that at

DAC

this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced amplitude of the desired signal.

Consider an application where the digital data into the AD9775 represents a baseband signal around f

/10. The reconstructed signal out of the AD9775 would

DAC

/4 with a pass band of

DAC

experience only a 0.75 dB amplitude variation over its pass band. However, the image of the same signal occurring at 3 × f suffers from a pass-band flatness variation of 3.93 dB. This image may be the desired signal in an IF application using one of the various modulation modes in the AD9775. This roll-off of image frequencies can be seen in

Figure 59 to Figure 74, where the effect

of the interpolation and modulation rate is apparent as well.

–10

–20

–30

SIN (X)/X ROLL-OFF (dBFS)

–40

–50

ZERO STUFFING

DISABLED

0.50 1.0 1.5 2.0

, NORMALIZED TO

OUT

Figure 75. Effect of Zero Stuffing on DAC’s sin(x)/x Response

DATA

ZERO STUFFING

ENABLED

WITH ZERO STUFFING DISABLED (Hz)

To improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to Logic 1. This option increases the ratio of f

DAC/fDATA

by a factor of 2 by doubling the DAC sample rate and inserting a midscale sample (that is, 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This is important as it affects the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator before the DAC.

The net effect is to increase the DAC output sample rate by a factor of 2× with the 0 in the sin(x)/x DAC transfer function occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident (see

Figure 75).

DAC

). This

02858-075

Note that the zero-stuffing option by itself does not change the location of the images but rather their amplitude, pass-band flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the image at 3 × f

/4 improved to +0.59 dB while the signal level increased

DATA

slightly from −10.5 dBFS to −8.1 dBFS.

INTERPOLATING (COMPLEX MIX MODE)

(Control Register 0x01, Bit 2)

In the complex mix mode, the two digital modulators on the AD9775 are coupled to provide a complex modulation function. In conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. The complex modulation function can be

+jωt

programmed for e

−jωt

or e

to give upper or lower image rejection. As in the real modulation mode, the modulation frequency ω can be programmed via the SPI port for f f

/4, and f

DAC

/8, where f

DAC

represents the DAC output rate.

DAC

/2,

OPERATIONS ON COMPLEX SIGNALS

Truly complex signals cannot be realized outside of a computer simulation. However, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. I (real) and Q (imaginary) datapaths are often defined this way. By using the architecture defined in a system can be realized that operates on complex signals, giving a complex (real and imaginary) output.

If a complex modulation function (e

+jωt

) is desired, the real and imaginary components of the system correspond to the real and imaginary components of e

+jωt

or cosωt and sinωt. As Figure 77 shows, the complex modulation function can be realized by applying these components to the structure of the complex system defined in

IMAGINARY

Figure 76.

a(t)

INPUT OUTPUT

COMPLEX FILTER

= (c + jd)

b(t)

Figure 77. Implementation of a Complex Modulator

IMAGINARY

INPUT OUTPUT

Figure 76. Realization of a Complex System

INPUT

(REAL)

INPUT

–jωt

= COSωt + jSINωt

90°

c(t) × b(t) + d × b(t)

b(t) × a(t) + c × b(t)

OUTPUT (REAL)

OUTPUT (IMAGINARY)

Figure 76,

02858-076

02858-077

Rev. E | Page 36 of 56

Page 37

AD9775

COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS

In traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an intermediate frequency (IF) and then modulated a second time to the transmit frequency. Although this approach has several benefits, a major drawback is that two images are created near the transmit frequency. Only one image is needed, the other being an exact duplicate. Unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced.

A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal.

The entire upconversion, from baseband to transmit frequency, is represented graphically in shown in

Figure 79 represents the complex data consisting of

Figure 78 is a block diagram of a

Figure 79. The resulting spectrum

REAL CHANNEL (OUT)

A/2

the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. It is important to remember that in this application (two baseband data channels) the image rejection is not dependent on the data at either of the AD9775 input channels. In fact, image rejection still occurs with either one or both of the AD9775 input channels active. Note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. This is easily done in the AD9775 by selecting the e purely complex terms,

+jωt

bit (Register 0x01, Bit 1). In

Figure 79 represents the two-stage

upconversion from complex baseband to carrier.

INPUT

A/2

(REAL)

INPUT

(IMAGINARY)

SINωt

90°

Figure 78. Quadrature Modulator

COSωt

OUTPUT

02858-078

REAL CHANNEL (IN)

IMAGINARY CHANNEL (IN)

REAL

QUADRATURE

MODULATOR

IMAGINARY

COMPLEX

MODULATOR

OUT

–F

–B/2J B/2J

–F

IMAGINARY CHANNEL (OUT)

–A/2J A/2J

–F

B/2 B/2

–F

A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J

–F

– FC–FQ+ F

–A/4 – B/4J

A/4 – B/4J A/4 + B/4J –A/4 + B/4J

–F

A/2 + B/2J A/2 – B/2J

–F

REJECTED IMAGES

FQ– F

TO QUADRATURE MODULATOR

FQ+ F

–F

FC = COMPLEX MODULATION FREQUENCY

FQ = QUADRATURE MODULATION FREQUENCY

Figure 79. Two-Stage Upconversion and Resulting Image Rejection

Rev. E | Page 37 of 56

02858-079

Page 38

AD9775

IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS

As shown in Figure 79, image rejection can be achieved by applying baseband data to the AD9775 and following the AD9775 with a quadrature modulator. To process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. As or multiple complex modulators can be used to synthesize complex carriers. These complex carriers are then summed and applied to the real and imaginary inputs of the AD9775.

A system in which multiple baseband signals are complex modulated and then applied to the AD9775 real and imaginary inputs followed by a quadrature modulator is shown in which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in

Figure 82 and Figure 80. Figure 82 adds an additional complex modulator stage for the purpose of summing multiple carriers at the AD9775 inputs. Also, as in rejection is not dependent on the real or imaginary baseband

Figure 80 shows, single

Figure 82,

Figure 79, the image

data on any channel. Image rejection on a channel occurs if either the real or imaginary data, or both, is present on the baseband channel.

It is important to remember that the magnitude of a complex signal can be 1.414× the magnitude of its real or imaginary components. Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9775 must be kept at least 3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator results in severe distortion at the DAC output.

COMPLEX BASEBAND

SIGNAL

j(ω1 + ω2)t

OUTPUT = REAL

= REAL

1/2 1/2

–ω1–ω2DC

Figure 80. Two-Stage Complex Upconversion

ω1 + ω2

FREQUENCY

02858-080

BASEBAND CHANNEL 1

BASEBAND CHANNEL 2

BASEBAND CHANNEL

REAL INPUT

IMAGINARY INPUT

REAL INPUT

IMAGINARY INPUT

REAL INPUT

IMAGINARY INPUT

COMPLEX

MODULATOR 1

COMPLEX

MODULATOR 2

COMPLEX

MODULATOR N

R(1)

R(2)

R(N) = REAL OUTPUT OF N

R(N)

I(N) = IMAGINARY OUTPUT OF N

R(N)

MULTICARRIER REAL OUTPUT = R(1) + R(2) + . . .R(N) (TO REAL INPUT OF AD9775)

MULTICARRIER IMAGINARY OUTPUT = I(1) + I(2) + . . .I(N) (TO IMAGINARY INPUT OF AD9775)

02858-081

Figure 81. Synthesis of Multicarrier Complex Signal

MULTIPLE

BASEBAND

CHANNELS

REAL

IMAGINARY

MULTIPLE COMPLEX

MODULATORS

FREQUENCY = ω

, ω2...ω

REAL

IMAGINARY

COMPLEX BASEBAND

SIGNAL

OUTPUT = REAL

AD9775

COMPLEX

MODULATOR

FREQUENCY = ω

j(ωN + ωC + ωQ)t

REAL REAL

IMAGINARY

QUADRATURE

MODULATOR

FREQUENCY = ω

–ω

– ωC– ω

REJECTED IMAGES

ω1 + ωC + ω

02858-082

Figure 82. Image Rejection with Multicarrier Signals

Rev. E | Page 38 of 56

Page 39

AD9775

The complex carrier synthesized in the AD9775 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at f tion only functions with modulation rates of f

Regions A and B of

Figure 83 to Figure 88 are the result of the

/2. As a result, complex modula-

DAC

/4 and f

DAC

/8.

complex signal described previously, when complex modulated in the AD9775 by +e

jωt

. Regions C and D are the result of the complex signal described previously, again with positive frequency components only, modulated in the AD9775 by –e

jωt

The analog quadrature modulator after the AD9775 inherently modulates by +e

jωt

Region A

Region A is a direct result of the upconversion of the complex signal near baseband. If viewed as a complex signal, only the images in Region A remain. The complex Signal A, consisting of positive frequency components only in the digital domain, has images in the positive odd Nyquist zones (1, 3, 5, …), as well as images in the negative even Nyquist zones. The appearance and rejection of images in every other Nyquist zone becomes more apparent at the output of the quadrature modulator. The A images appear on the real and the imaginary outputs of the AD9775, as well as on the output of the quadrature modulator, where the center of the spectral plot now represents the quadrature modulator LO, and the horizontal scale now represents the frequency offset from this LO.

Region B

Region B is the image (complex conjugate) of Region A. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9775, Region B appears in the spectrum. However, on the output of the quadrature modulator, Region B is rejected.

Region C

Region C is most accurately described as a downconversion, as

jωt

the modulating carrier is –e

. If viewed as a complex signal, only the images in Region C remain. This image appears on the real and imaginary outputs of the AD9775, as well as on the output of the quadrature modulator, where the center of the spectral plot now represents the quadrature modulator LO and the horizontal scale represents the frequency offset from this LO.

Region D

Region D is the image (complex conjugate) of Region C. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9775, Region D appears in the spectrum. However, on the output of the quadrature modulator, Region D is rejected.

Figure 89 to Figure 96 show the measured response of the AD9775 and AD8345 given the complex input signal to the AD9775 in Figure 89. The data in these graphs was taken with a data rate of

12.5 MSPS at the AD9775 inputs. The interpolation rate of 4× or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result,

the high end of the DAC output spectrum in these graphs is the first null point for the sin(x)/x roll-off, and the asymmetry of the DAC output images is representative of the sin(x)/x roll-off over the spectrum. The internal PLL was enabled for these results. In addition, a 35 MHz third-order low-pass filter was used at the AD9775/AD8345 interface to suppress DAC images.

An important point can be made by looking at

Figure 91 and Figure 93. Figure 91 represents a group of positive frequencies modulated by complex +fDAC/4, while

Figure 93 represents a group of negative frequencies modulated by complex −fDAC/4. When looking at the real or imaginary outputs of the AD9775, as shown in

Figure 91 and Figure 93, the results look identical. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figure 92 and Figure 94.

–20

DABCDABC

–40

–60

–80

–100

Figure 83. 2× Interpolation, Complex f

0–0.5–1.5 –1.0–2.0 0.5 1.0 1.5 2.0

(LO)

(×

DATA

)

/4 Modulation

DAC

OUT

02858-083

–20

DABC DA BC

–40

–60

–80

–100

Figure 84. 4× Interpolation, Complex fDAC/4 Modulation

0–1.0–3.0 –2.0–4.0 1.0 2.0 3.0 4.0

(LO)

(×

DATA

)

OUT

02858-084

Rev. E | Page 39 of 56

Page 40

AD9775

–

–20

DA B C DA B C

–40

–60

–80

–100

Figure 85. 8× Interpolation, Complex f

–20

–40

DA B CD A BC

–60

–80

100

Figure 86. 2× Interpolation, Complex f

–20

–40

DA B CD A B C

–60

–80

–100

Figure 87. 4× Interpolation, Complex f

0–2.0–6.0 –4.0–8.0 2.0 4.0 6.0 8.0

(LO)

(×

)

DATA

DAC

0–0.5–1.5 –1.0–2.0 0.5 1.0 1.5 2.0

(LO) (×

)

DATA

DAC

0–1.0–3.0 –2.0–4.0 1.0 2.0 3.0 4.0

(LO)

(×

)

DATA

DAC

OUT

/4 Modulation

/8 Modulation

02858-085

02858-086

02858-087

–20

DA DABC BC

–40

–60

–80

–100

Figure 88. 8× Interpolation, Complex f

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

01020304050

0–2.0–6.0 –4.0–8.0 2.0 4.0 6.0 8.0

(LO)

(×

DATA

)

DAC

OUT

FREQUENCY (MHz)

/8 Modulation

02858-088

Figure 89. AD9775 Real DAC Output of Complex Input Signal Near Baseband

(Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9775

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

750 760 770 780 790 800 810 820 830 840 850

FREQUENCY (MHz)

Figure 90. AD9775 Complex Output from

Figure 89,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

02858-089

02858-090

Rev. E | Page 40 of 56

Page 41

AD9775

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 1020304050

FREQUENCY (MHz)

Figure 91. AD9775 Real DAC Output of Complex Input Signal Near

Baseband (Positive Frequencies Only), Interpolation = 4×,

Complex Modulation in AD9775 = +fDAC/4

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

750 760 770 780 790 800 810 820 830 840 850

FREQUENCY (MHz)

Figure 92. AD9775 Complex Output from

Figure 91,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 1020304050

FREQUENCY (MHz)

Figure 93. AD9775 Real DAC Output of Complex Input Signal Near

Baseband (Negative Frequencies Only), Interpolation = 4×,

Complex Modulation in AD9775 = −f

DAC

02858-091

02858-092

02858-093

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

750 760 770 780 790 800 810 820 830 840 850

FREQUENCY (MHz)

Figure 94. AD9775 Complex Output from

Figure 93,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 20 40 60 80 100

FREQUENCY (MHz)

Figure 95. AD9775 Real DAC Output of Complex Input Signal Near

Baseband (Positive Frequencies Only), Interpolation = 8×,

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

700 720 740 760 780 800 820 840 860 880 900

FREQUENCY (MHz)

Figure 96. AD9775 Complex Output from

Complex Modulation in AD9775 = +f

DAC

Figure 95,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

02858-094

02858-095

02858-096

Rev. E | Page 41 of 56

Page 42

AD9775

APPLYING THE OUTPUT CONFIGURATIONS

The following sections illustrate typical output configurations for the AD9775. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configuration is suggested. A simple differential output may be achieved by converting IOUTA and IOUTB to a voltage output by terminating them to AGND via equal value resistors. This type of configuration may be useful when driving a differential voltage input device such as a modulator. If a conversion to a single-ended signal is desired and the application allows for ac coupling, an RF transformer may be useful, or if power gain is required, an op amp may be used. The transformer configuration provides optimum high frequency noise and distortion performance. The differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or level shifting within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if I

OUTA

and/or I

is connected to a load resistor, R

OUTB

LOAD

referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting I

OUTA

or I

OUTB

into a negative unipolar voltage. This configuration provides the best DAC dc linearity as I

OUTA

or I

are maintained at ground or

OUTB

virtual ground.

UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT

In many applications, it may be necessary to understand the equivalent DAC output circuit. This is especially useful when designing output filters or when driving inputs with finite input impedances. the equivalent circuit. A typical application where this information may be useful is when designing an interface filter between the AD9775 and Analog Devices’ AD8345 quadrature modulator.

Figure 97 illustrates the output of the AD9775 and

OUTA

OUTB

OUT

–

OUT

For the typical situation, where I both equal 50 Ω, the equivalent circuit values become

V V p-p

SOURCE

OUT

100=

Note that the output impedance of the AD9775 DAC itself is greater than 100 kΩ and typically has no effect on the impedance of the equivalent output circuit.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in ferentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of common-mode distortion (that is, even-order harmonics) and

noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios can also be used for impedance matching purposes.

MINI-CIRCUITS

OUTA

DAC I

OUTB

Figure 98. Transformer-Coupled Output Circuit

The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path for both I at I

OUTA

and I

(that is, V

OUTB

. The complementary voltages appearing

OUTB

OUTA

around AGND and should be maintained within the specified output compliance range of the AD9775. A differential resistor, R

, can be inserted in applications where the output of the

DIFF

transformer is connected to the load, R reconstruction filter or cable. R transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power dissipates across R

= 20 mA and RA and RB

OUTFS

Figure 98. A dif-

T1-1T

LOAD

and V

DIFF

) swing symmetrically

OUTB

, via a passive

LOAD

is determined by the

DIFF

02858-098

+ R

SOURCE

× (RA + RB)

OUTFS

p-p

Figure 97. DAC Output Equivalent Circuit

OUT

(DIFFERENTIAL)

02858-097

Rev. E | Page 42 of 56

Page 43

AD9775

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-singleended conversion, as shown in benefit of providing signal gain as well. In AD9775 is configured with two equal load resistors, R 25 . The differential voltage developed across I

Figure 99. This has the added

Figure 99, the

, of

LOAD

and I

OUTA

OUTB

is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across I

OUTA

and I

, forming a real pole in a low-pass filter. The

OUTB

addition of this capacitor also enhances the op amp distortion performance by preventing the DAC fast slewing output from overloading the input of the op amp.

500Ω

OUTA

DAC

OUTB

25Ω 25Ω

Figure 99. Op Amp-Coupled Output Circuit

225Ω

AD8021

OPT

225Ω

500Ω

R 225Ω

OPT

AVDD

02858-099

The common-mode (and second-order distortion) rejection of this configuration is typically determined by the resistor matching. The op amp used must operate from a dual supply because its output is approximately ±1.0 V. A high speed amplifier, such as the AD8021, capable of preserving the differential performance of the AD9775 while meeting other system level objectives (such as cost and power) is recommended. The op amp differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. R

OPT

is only necessary if level shifting is required on the op amp output. In Figure 99, AVDD, which is the positive analog supply for both the AD9775 and the op amp, is also used to level shift the differential output of the AD9775 to midsupply, that is, AV DD / 2 .

INTERFACING THE AD9775 WITH THE AD8345 QUADRATURE MODULATOR

The AD9775 architecture was defined to operate in a transmit signal chain using an image reject architecture. A quadrature modulator is also required in this application and should be designed to meet the output characteristics of the DAC as much as possible. The AD8345 from Analog Devices meets many of the requirements for interfacing with the AD9775. As with any DAC output interface, there are a number of issues that have to be resolved. The following sections list some of these issues.

DAC Compliance Voltage/Input Common-Mode Range

The dynamic range of the AD9775 is optimal when the DAC outputs swing between ±1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components.

Gain/Offset Adjust

The matching of the DAC output to the common-mode input of the AD8345 allows the two components to be dc-coupled, with no level shifting necessary. The combined voltage offset of the two parts can therefore be compensated for via the AD9775 programmable offset adjust. This allows excellent LO cancellation at the AD8345 output. The programmable gain adjust allows for optimal image rejection as well.

The AD9775 evaluation board includes an AD8345 and recommended interface (

Figure 104 and Figure 105). On the output of the AD9775, R9 and R10 convert the DAC output current to a voltage. R16 may be used to do a slight commonmode shift if necessary. The (now voltage) signal is applied to a low-pass reconstruction filter to reject DAC images. The components installed on the AD9775 provide a 35 MHz cutoff but may be changed to fit the application. A balun (MiniCircuits ADTL1-12) is used to cross the ground plane boundary to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, so a single connection between the AD9775 and AD8345 ground planes is recommended.

The performance of the AD9775 and AD8345 in an image reject transmitter, reconstructing three W-CDMA carriers, can be seen in Figure 100. The LO of the AD8345 in this application is 800 MHz. Image rejection (50 dB) and LO feedthrough (−78 dBFS) have been optimized with the programmable features of the AD9775. The average output power of the digital waveform for this test was set to −15 dBFS to account for the peak-to-average ratio of the W-C DMA signal .

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

Figure 100. AD9775/AD8345 Synthesizing a Three-Carrier

782.5762.5 802.5 822.5 842.5 FREQUENCY (MHz)

W-CDMA Signal at an LO of 800 MHz

02858-100

Rev. E | Page 43 of 56

Page 44

AD9775

EVALUATION BOARD

The AD9775 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from PCs running Windows® 95, Windows 98, or Windows NT®/2000. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9775 in an image reject transmit signal chain.

Figure 101 to Figure 104 show how to configure the evaluation board in the one-port and two-port input modes with the PLL enabled and disabled. Refer to schematics, and the layout for the AD9775 evaluation board for the jumper locations described in the Outputs various applications by referring to the following instructions.

section. The AD9775 outputs can be configured for

Figure 105 to Figure 114, the

DAC Single-Ended

DAC Single-Ended Outputs

Remove Transformers T2 and T3. Solder jumper links JP4 or JP28 to look at the DAC1 outputs. Solder jumper links JP29 or JP30 to look at the DAC2 outputs. Jumper 8 and Jumper 13 to Jumper 17 should remain unsoldered. Jumper JP35 to Jumper JP38 can be used to ground one of the DAC outputs while the other is measured single ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4.

DAC Differential Outputs

Transformers T2 and T3 should be in place. Note that the lower band of operation for these transformers is 300 kHz to 500 kHz. Jumper 4, Jumper 8, Jumper 13 to Jumper 17, and Jumper 28 to Jumper 30 should remain unsoldered. The outputs are taken from S3 and S4.

Using the AD8345

Remove Transformers T2 and T3. Jumper JP4 and Jumper 28 to Jumper 30 should remain unsoldered. Jumper 13 to Jumper 16 should be soldered. The desired components for the low-pass interface filter L6, L7, C55, and C81 should be in place. The LO drive is connected to the AD8345 via J10 and the balun T4, and the AD8345 output is taken from J9.

Rev. E | Page 44 of 56

Page 45

AD9775

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

INPUT CLOCK

AWG2021

DG2020

40-PIN RIBBON CABLE

DAC1, DB13–DB0 DAC2, DB13–DB0

CLK+/CLK–DATACLK

AD9775

JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON

× ×

UNSOLDERED/OUT

× × ×

× × × ×

02858-101

SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –

JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP2 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPU PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE FOR MORE INFORMATION.

Figure 101. Test Configuration for AD9775 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate,

DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

INPUT CLOCK

AWG2021

DG2020

JUMPER CONFIGURATION FOR ONE-PORT MODE PLL ON

SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –

JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

× ×

UNSOLDERED/OUT

DAC1, DB13–DB0 DAC2, DB13–DB0

× ×

× × ×

× ×

CLK+/CLK–ONEPORTCLK

AD9775

02858-102

Figure 102. Test Configuration for AD9775 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,

ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

Rev. E | Page 45 of 56

Page 46

AD9775

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

INPUT CLOCK

AWG2021

DG2020

40-PIN RIBBON CABLE

DAC1, DB13–DB0 DAC2, DB13–DB0

CLK+/CLK–DATACLK

AD9775

JUMPER CONFIGURATION FOR TWO-PORT MODE PLL OFF

× ×

UNSOLDERED/OUT

× × ×

× × × ×

02858-103

SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –

JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE FOR MORE INFORMATION.

Figure 103. Test Configuration for AD9775 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

DATACLK = Signal Generator Frequency/Interpolation Rate

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

INPUT CLOCK

AWG2021

DG2020

JUMPER CONFIGURATION FOR ONE-PORT MODE PLL OFF

× ×

UNSOLDERED/OUT

SOLDERED/IN

JP1 – JP2 – JP3 – JP5 –

JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

DAC1, DB13–DB0 DAC2, DB13–DB0

× ×

× × ×

× ×

CLK+/CLK–ONEPORTCLK

AD9775

02858-104

Figure 104. Test Configuration for AD9775 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate

Rev. E | Page 46 of 56

Page 47

AD9775

JP44

TP2

DVDD

RED

TP4

AVDD

RED

TP6

CLKVDD

RED

TP7

BLK

JP45

C68

16V

DCASE

CC0805

TP5

BLK

22μF

0.1μF

JP11

C62

16V

22μF

DCASE

C69

0.1μF

CC0805

VDDM

C32

CC0805

JP43

0.1μF

JP9

TP3

C66

16V

DCASE

C67

CC0805

BLK

22μF

0.1μF

JP10

C61

16V

DCASE

22μF

CGND

LC1210

FERRITE

C28

16V

22μF

POWER INPUT FILTERS

DCASE

VDDMIN

W11

DGND2

W12

FERRITE

DVDD_IN

LC1210

C65

16V

22μF

DCASE

DGND

LC1210

FERRITE

AVDD_IN

C64

16V

22μF

DCASE

AGND

FERRITE

CLKVDD_IN

LC1210

C63

DGND2; 3, 4, 5

MODULATED OUTPUT

0Ω

RC0603

R23

C75

C35

C72

CC0603

BCASE

16 15 14 13 12 11 10 9

0.1μF

CC0603

100pF

10V

10μF

VDDM

R26

G2ENBL G3

VOUT

VPS2 G4A G4B

AD8345

QBBN QBBP

1kΩ

RC0603

VPS1 LOIP LOIN G1B G1A IBBN IBBP

1 2 3 4 5 6 7 8

JP18

CC0603

C74

100pF

C79

DNP

CC0603

R34

RC0603

DNP

JP19

RC0603

LC0805

O2N

RC0603

R33

51Ω

DNP

ADTL1-12

CC0805

C81

DNP

LC0805

CC0805

C55

DNP

O2P

R32

51Ω

DNP

VDDM

J10

JP7

JP21

DGND2; 3, 4, 5

RC0603

LOCAL OSC INPUT

0Ω

R28

R30

100pF

CC0603

0.1μF

ETC1-1-13

CC0603

DNP

RC0603

C77

100pF

CC0603

ADTL1-12

C80

DNP

CC0603

R37

RC0603

DNP

JP20

RC0603

R35

51Ω

LC0805

DNP

O1N

RC0603

R36

51Ω

CC0805

C73

DNP L5

LC0805

DNP

CC0805

C54

DNP

O1P

02858-105

C76

C78

Figure 105. AD8345 Circuitry on AD9775 Evaluation Board

Rev. E | Page 47 of 56

Page 48

AD9775

JP30

AGND; 3, 4,

OUT 2

456

R43

49.9kΩ JP17

C70

T1-1T

R12

CC0603

R17

10kΩ

0.1μF

RC0603

RC0603 RC0603

51kΩ

R11

51kΩ

SPSDO

JP47

74VCX86

DVDD; 14

DGND; 7

O1N

O1P

O2N

RC1206

AGND; 3, 4, 5

OUT1

R42

456

49.9kΩ

T1-1T

JP8

CC0603

R16

10kΩ

C70

0.1μF

JP4

RC0603

RC0603 RC0603

R10

51kΩ

JP28

51kΩ

O2P

JP15

JP14

JP29

JP13

JP16

BD03

BD04

P2D3

P2D4

P2D5

P2D12

VSSD4

VDDD4

BD12

JP32

JP26

1kΩ

JP40

DGND; 3, 4, 5

BD05

VSSD5

P2D11

C23

DVDD

BD14

JP46

VDDD5

P2D10

BD11

CC0603

10μF

BCASE

JP31

74VCX86

DVDD

BD10

0.001μF

6.3V

C22

BD06

BD07

P2D6

P2D7

P2D9

P2D8

BD09

BD08

JP34

OPCLK

BCASE

6.3V

10μF

CC0603

0.001μF

AD9775+TSP

DGND; 7

DVDD; 14

OPCLK

C45

0.01μF

CC0805

AGND; 3, 4, 5

02858-106

1kΩ

REFOUT

P1D5

AD06

49.9Ω

RESET

P1D4

AD05

JP3

2kΩ

C16

SP-CSB

VSSD3

AD04

CC0603 BCASE

SPCSP

C29

0.01%

10μF

RC1206

SPCLK

SP-CLK

VDDD3

DVDD

0.1μF

6.3V

0.1μF

CC0605

1kΩ

SP-SDI

P1D3

C24

SPSDI

SP-SDO

P1D2

AD03

CC0603

10μF

BCASE

SPSDO

VSSD6

P1D1

AD02

0.001μF

6.3V

VDDD6

P1D0

AD01

DVDD

BD00

P2D0

P2D15-IQSEL

AD00

JP5

BD15

+ C5

C21

BD01

P2D1

P2D14-OPCLK

JP27

BCASE

10μF

CC0603

P2D2

P2D13

R39

6.3V

0.001μF

BD02

BD13

OPCLK_3

J37

C41

C40

C39

C38

C37

C36

AVDD

0.1μF

CC0805

0.1μF

CC0805

0.1μF

CC0805

0.1μF

CC0805

C14

C19

C20

0.1μF

807978777675747372717069686766656463626160595857565554535251504948474645444342

CC0805

0.1μF

CC0805

VSSA10

DVDD

CLKVDD

1kΩ

VDDC1 VDDA6

123456789

1pF

0.1μF

6.3V

10μF

123

JP22

C27

C42

C11

C12

+ C1

CC0603

CC0603 CC0603 CC0603

BCASE

654

CC0603

RC0603 RC0603

C13

TP15

0.1μF

WHT

1kΩ

10μF

6.3V

BCASECC0603

0.1μF

CC0603

0.1μF

CC0603

0.1μF

VSSA9

VDDA5

VDDC2

VSSC1

CLKP

RC0603

CLKN

200Ω

JP23

JP1

VDDA4

CLKP

J35

C58

VSSA8

CLKN

JP33

T1-1T

JP2

JP36

JP38

10μF

6.3V

AVDD

BCASECC0805

TP8

CC0603CC0603

0.1μF

VSSA1

VDDA2

WHT

TP9

WHT

TP10

WHT

TP11

WHT

VDDA1

FSADJ1

FSADJ2

VSSA7

DNP

CC0603

IOUT1P

C58

IOUT1N

DNP

CC0603

C57

VSSA6

CC0603

DNP

VSSA5

C15

C17

C59

DNP

C18

CC0603

VSSA4

VSSA3

VSSA2

IOUT2P

VDDA3

IOUT2N

VSSC2

DCLK-PLLL

VSSD1

VDDD1

P1D15

P1D14

P1D13

P1D12

P1D11

P1D10

VSSD2

VDDD2

P1D9

P1D8

P1D7

P1D6

10111213141516171819202122232425262728293031323334353637383940

AD15

AD14

AD13

AD12

AD11

AD10

AD09

AD08

AD07

R38 10kΩ

ADCLK

JP39

CLKIN

CC0603

C26

0.001μF

C10

10μF

6.3V

BCASE

DVDD

JP24

ACLKX CGND; 3, 4, 5

JP25

CX3

74VCX86

CX2

CX1

DVDD

DVDD; 14

DGND; 7

JP12

C25

C9 +

TP14

RC0603

R40

CC0603

10μF

BCASE

WHT

5kΩ

DVDD

0.001μF

6.3V

RC0603

DGND; 3, 4, 5

DATACLK

Figure 106. AD9775 Clock, Power Supplies, and Output Circuitry

Rev. E | Page 48 of 56

Page 49

AD9775

CC0805ACASE

R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9

RP7

RCOM

RP5

DNP

21 34567891021 345678910

50Ω

C33

0.1μF

C30

6.3V

4.7μF

CX3

DVDD

DVDD; 14

AGND; 7

74VCX86

231

AGND; 7

74VCX86

564

CX1

AD15

AD14

AD13

AD12

AD11

AD10

DVDD; 14

AGND; 7

74VCX86

CX2

AD09

AD08

AD07

AD06

AD05

AD04

AD03

RP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22

RP1 22

116

215

314

413

512

611

710

116

215

314

413

512

DVDD

AD02

AD01

611

C34

0.1μF

C31

6.3V

4.7μF

DVDD; 14

AGND; 7

74VCX86

564

AD00

710

RP6

21 345678910

RP8

50Ω

DNP

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

DVDD

4 10

C53

0.1μF

C52

6.3V

4.7μF

AGND; 8

CLR

DVDD; 16

PRE

CLK

74LCX112

OPCLK_3

DVDD; 14

AGND; 7

OPCLK_2

74VCX86

231

PRE

CLR

CLK

74LCX112

RCOM

DATA-A

21 345678910

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

135

246

13151719212325272931333537

101214161820222426283032343638

RIBBON

Figure 107. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry

Rev. E | Page 49 of 56

OPCLK

ADCLK

R15

RC1206

220Ω

02858-107

Page 50

AD9775

C51

DVDD

DGND; 7

0.1μF

CC805

C44

4.7μF

6.3V

ACASE

DVDD; 14

DGND; 7

DVDD; 14

74AC14

DVDD; 14

74AC14

DGND; 7

DVDD; 14

74AC14

C50

74AC14

0.1μF

CLKVDD

RC0805

R21

R20

DNP

JP42

CC805

1nF

C47

RC0805

MC100EPT22

120Ω

RC0805

C46

0.1μF

CLKVDD

R14

200Ω

R19

JP41

100Ω

CLKN

R22

CGND; 5

CLKVDD; 8

R13

CC805

CLKVDD

RC0805

DNP

C48

120Ω

RC0805

ACLKX

R24

1nF

RC0805

DNP

CC805

R18

200Ω

CLKDD

MC100EPT22

CC805

C49

C60

4.7μF

ACASE

CLKVDD; 8

0.1μF

6.3V

CGND; 5

SPI PORT

12345

RC0805

R50

9kΩ

DGND; 7

R48

DVDD; 14

74AC14

DVDD; 14

74AC14

RC0805

9kΩ

DGND; 7

DVDD; 14

74AC14

DGND; 7

DVDD; 14

74AC14

RC0805

R45

9kΩ

DGND; 7

DVDD; 14

74AC14

DGND; 7

DVDD; 14

74AC14

DGND; 7

DVDD; 14

74AC14

DVDD; 14

74AC14

CLKP

R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9

RP9

RCOM

RP12

RCOM

DNP

21 34567891021 345678910

50Ω

DATA-B

BD15

BD14

RP3 22Ω

116

135

246

BD13

BD12

RP3 22Ω

215

314

BD11

BD10

BD09

BD08

BD07

BD06

BD05

BD04

BD03

BD02

BD01

BD00

RP3 22Ω

RP4 22Ω

413

512

611

710

116

215

314

413

13151719212325272931333537

101214161820222426283032343638

512

611

RP4 22Ω

710

21 345678910

RP11

21 345678910

RP10

50Ω

DNP

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

RIBBON

SPCSB

SPCLK

CC805

C43

4.7μF

6.3V

+ +

ACASE

SPSDI

SPSDO

DVDD

02858-108

Figure 108. AD9775 Evaluation Board Input (B Channel) and SPI Port Circuitry

Rev. E | Page 50 of 56

Page 51

AD9775

02858-109

Figure 109. AD9775 Evaluation Board Components, Top Side

Figure 110. AD9775 Evaluation Board Components, Bottom Side

Rev. E | Page 51 of 56

02858-110

Page 52

AD9775

02858-111

Figure 111. AD9775 Evaluation Board Layout, Layer One (Top)

Figure 112. AD9775 Evaluation Board Layout, Layer Two (Ground Plane)

Rev. E | Page 52 of 56

02858-112

Page 53

AD9775

02858-113

Figure 113. AD9775 Evaluation Board Layout, Layer Three (Power Plane)

02858-114

Figure 114. AD9775 Evaluation Board Layout, Layer Four (Bottom)

Rev. E | Page 53 of 56

Page 54

AD9775

OUTLINE DIMENSIONS

14.20

0.75

0.60

0.45

1.20

MAX

14.00 SQ

13.80

PIN 1

12.20

12.00 SQ

11.80

6180

61 80

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0° MIN

0.08 MAX COPLANARITY

0.20

0.09

3.5°

0.50 BSC

EXPOSED

PAD

BOTTOM VIEW

(PINS UP)

0.27

0.22

0.17

TOP VIEW

(PINS DOWN)

7°

0°

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD

40 40

LEAD PITCH

6.00

BSC SQ

Figure 115. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-80-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9775BSV −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9775BSVRL −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9775BSVZ AD9775BSVZRL1−40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1 AD9775-EB Evaluation Board

Z = Pb-free part.

−40°C to +85°C 80-Lead, Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-1

Rev. E | Page 54 of 56

Page 55

AD9775

NOTES

Rev. E | Page 55 of 56

Page 56

AD9775

NOTES

Rev. E | Page 56 of 56

Datasheet AD9775 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

SPECIFICATIONS

DC SPECIFICATIONS

DYNAMIC SPECIFICATIONS

DIGITAL SPECIFICATIONS

DIGITAL FILTER SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

THERMAL RESISTANCE

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

MODE CONTROL (VIA SPI PORT)

REGISTER DESCRIPTIONS

ADDRESS 0x00

ADDRESS 0x01

ADDRESS 0x02

ADDRESS 0x03

ADDRESS 0x04

ADDRESS 0x05, ADDRESS 0x09

ADDRESS 0x06, ADDRESS 0x0A

ADDRESS 0x07, ADDRESS 0x0B

ADDRESS 0x08, ADDRESS 0x0C

ADDRESS 0x08, ADDRESS 0x0C

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE FOR REGISTER CONTROL

GENERAL OPERATION OF THE SERIAL INTERFACE

N1, N0

A4, A3, A2, A1, A0

MSB/LSB TRANSFERS

NOTES ON SERIAL PORT OPERATION

DAC OPERATION

CLOCK INPUT CONFIGURATIONS

1R/2R MODE

PROGRAMMABLE PLL

POWER DISSIPATION

SLEEP/POWER-DOWN MODES

(Control Register 0x00, Bit 3 and Bit 4)

TWO-PORT DATA INPUT MODE

PLL Off (Register 4, Bit 7 = 0)

PLL On (Register 4, Bit 7 = 1)

PLL ENABLED, TWO-PORT MODE

(Control Register 0x02, Bit 6 to Bit 0 and Control Register 0x04, Bit 7 to Bit 1)

DATACLK INVERSION

(Control Register 0x02, Bit 4)

DATACLK DRIVER STRENGTH

(Control Register 0x02, Bit 5)

PLL ENABLED, ONE-PORT MODE

(Control Register 0x02, Bit 6 to Bit 1 and Control Register 0x04, Bit 7 to Bit 1)

ONEPORTCLK INVERSION

(Control Register 0x02, Bit 2)

ONEPORTCLK DRIVER STRENGTH

IQ PAIRING

(Control Register 0x02, Bit 0)

PLL DISABLED, TWO-PORT MODE

DIGITAL FILTER MODES

AMPLITUDE MODULATION

MODULATION, NO INTERPOLATION

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation Disabled

MODULATION, INTERPOLATION = 2×

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 2×

MODULATION, INTERPOLATION = 4×

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 4×

MODULATION, INTERPOLATION = 8×

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8×

ZERO STUFFING

(Control Register 0x01, Bit 3)

INTERPOLATING (COMPLEX MIX MODE)

(Control Register 0x01, Bit 2)

OPERATIONS ON COMPLEX SIGNALS