Datasheet AD9773 Datasheet (Analog Devices)

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Page 1

12-Bit, 160 MSPS, 2×/4×/8×

Interpolating Dual TxDAC+® D/A Converter

FEATURES

12-bit resolution, 160 MSPS/400 MSPS

input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment

/4, fS/8 digital quadrature modulation capability

Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fully compatible SPI® port Excellent AC performance

SFDR −69 dBc @ 2 MHz to 35 MHz

WCDMA ACPR −69 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock divider Versatile clock input

Differential/single-ended sine wave or

TTL/CMOS/LVPECL compatible

Versatile input data interface

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data Single 3.3 V supply operation Power dissipation: typical 1.2 W @ 3.3 V On-chip 1.2 V reference 80-lead thermally enhanced TQFP package

AD9773

APPLICATIONS

Communications

Analog quadrature modulation architecture 3G, multicarrier GSM, TDMA, CDMA systems Broadband wireless, point-to-point microwave radios Instrumentation/ATE

GENERAL DESCRIPTION

The AD97731 is the 12-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing for enhanced system-level options. These options include selectable 2×/4×/8× interpolation filters; f modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface.

Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other

patents pending.

/2, fS/4, or fS/8 digital quadrature

(continued on Page 4)

FUNCTIONAL BLOCK DIAGRAM

AD9773

HALFBAND

FILTER1*

DATA

ASSEMBLER

I AND Q

NONINTERLEAVED

OR INTERLEAVED

DATA

WRITE

SELECT

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

CONTROL

CLOCK OUT

SPI INTERFACE AND

CONTROL REGISTERS

LATCH

MUX

HALF-BAND FILTERS ALSO CAN BE

CONFIGURED FOR "ZERO STUFFING ONLY"

HALF-

BAND

FILTER2*

FILTER3*

161616

/2 /2

COS

SIN

FILTER

BYPASS

MUX

Figure 1.

/2, 4, 8

DAC

SIN

COS

(

)

DAC

PRESCALER

PHASE DETECTOR

AND VCO

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

GAIN DAC

VREF

IDAC

I/Q DAC

GAIN/OFFSET

REGISTERS

IDAC

OFFSET

DAC

DIFFERENTIAL CLK

OUT

IOFFSET

02857-B-001

Page 2

AD9773

General Description ......................................................................... 4

PLL Enabled, One-Port Mode .................................................. 31

Product Highlights....................................................................... 4

Specifications..................................................................................... 5

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Terminology ....................................................................................12

Typical Performance Characteristics ...........................................13

Mode Control (Via SPI Port).................................................... 18

Functional Description.............................................................. 22

Serial Interface for Register Control........................................ 22

General Operation of the Serial Interface ............................... 22

Instruction Byte .......................................................................... 23

Serial Interface Port Pin Descriptions ..................................... 23

MSB/LSB Transfers..................................................................... 23

Notes on Serial Port Operation ................................................ 25

DAC Operation........................................................................... 25

1R/2R Mode ................................................................................26

Clock Input Configurations...................................................... 26

Programmable PLL ....................................................................27

Power Dissipation....................................................................... 29

Sleep/Power-Down Modes........................................................ 29

Two-Port Data Input Mode....................................................... 29

One-/Two-Port Input Modes.................................................... 30

PLL Enabled, Two-Port Mode .................................................. 30

DATACLK Inversion.................................................................. 30

ONEPORTCLK Inversion......................................................... 31

IQ Pairing.................................................................................... 31

PLL Disabled, Two-Port Mode ................................................. 32

PLL Disabled, One-Port Mode ................................................. 32

Digital Filter Modes ................................................................... 32

Amplitude Modulation.............................................................. 33

Modulation, No Interpolation .................................................. 34

Modulation, Interpolation = 2× ............................................... 35

Modulation, Interpolation = 4× ............................................... 36

Modulation, Interpolation = 8× ............................................... 37

Zero Stuffing ............................................................................... 38

Interpolating (Complex Mix Mode) ........................................ 38

Operations on Complex Signals............................................... 38

Complex Modulation and Image Rejection of Baseband

Signals .......................................................................................... 39

Image Rejection and Sideband Suppression of Modulated

Carriers ........................................................................................ 41

Applying the AD9773 Output Configurations....................... 46

Unbuffered Differential Output, Equivalent Circuit ............. 46

Differential Coupling Using a Transformer............................ 46

Differential Coupling Using an Op Amp................................ 47

Interfacing the AD9773 with the AD8345 Quadrature

Modulator.................................................................................... 47

Evaluation Board........................................................................ 48

Outline Dimensions....................................................................... 58

Ordering Guide .......................................................................... 58

DATACLK Driver Strength....................................................... 31

Rev. B | Page 2 of 60

Page 3

AD9773

REVISION HISTORY

4/04—Data Sheet Changed from Rev. A to Rev. B.

Update Layout....................................................................Universal

Changes to DC Specifications ....................................................... 5

Changes to Absolute Maximum Ratings...................................... 9

Changes to DAC Operation Section........................................... 25

Inserted Figure 38.......................................................................... 25

Changes to Figure 40 ....................................................................26

Changes to Table 11 ...................................................................... 28

Changes to Programmable PLL Section..................................... 29

Changes to Power Dissipation Section....................................... 29

Changes to Figures 49, 50, and 51 ............................................... 29

Changes to PLL Enabled, One-Port Mode Section................... 31

Changes to PLL Disabled, One-Port Mode Section.................. 32

Changes to Figure 102 .................................................................. 49

Changes to Figure 104 .................................................................. 50

Updated Ordering Guide ............................................................. 58

Updated Outline Dimensions...................................................... 58

3/03—Data Sheet Changed from Rev. 0 to Rev. A.

Edits to Features ...............................................................................1

Edits to DC Specifications ..............................................................3

Edits to Dynamic Specifications ....................................................4

Edits to Pin Function Descriptions ...............................................7

Edits to Table I............................................................................... 14

Edits to Register Description—Address 02h Section............... 15

Edits to Register Description—Address 03h Section............... 16

Edits to Register Description—Address 07h, 0Bh Section ...... 16

Edits to Equation 1........................................................................ 16

Edits to MSB/LSB Transfers Section........................................... 18

Changes to Figure 8 ...................................................................... 20

Edits to Programmable PLL Section........................................... 21

Added new Figure 14.................................................................... 22

Renumbered Figures 15 through 69........................................... 22

Add Two-Port Data Input Mode Section................................... 23

Edits to PLL Enabled, Two-Port Mode Section......................... 24

Edits to Figure 19 .......................................................................... 24

Edits to Figure 21 .......................................................................... 25

Edits to PLL Disabled, Two-Port Mode Section ....................... 25

Edits to Figure 22 .......................................................................... 25

Edits to Figure 23 .......................................................................... 26

Edits to Figure 26a ........................................................................ 27

Edits to Complex Modulation and Image Rejection of Baseband

Signals Section............................................................................... 31

Changes to Figures 53 and 54...................................................... 38

Edits to Evaluation Board Section .............................................. 39

Changes to Figures 56 through 59.............................................. 40

Replaced Figures Figures 60 through 69.................................... 42

Updated Outline Dimensions...................................................... 49

Rev. B | Page 3 of 60

Page 4

AD9773

GENERAL DESCRIPTION

(continued from Page 1)

The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC.

The AD9773 features the ability to perform f digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9773 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (i.e., the direct IF mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate.

The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data.

Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9773 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power.

Targeted at a wide dynamic range, multicarrier, and multistandard systems, the superb baseband performance of the AD9773 is ideal for wide band CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high order QAM modulation schemes. The image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems.

/2, fS/4, and fS/8

PRODUCT HIGHLIGHTS

1. The AD9773 is the 12-bit member of the AD977x pin

compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family.

2. Direct IF transmission is possible for 70 MHz + IFs

through a novel digital mixing process.

/2, fS/4, and fS/8 digital quadrature modulation and user

3. f

selectable image rejection simplify/remove cascaded SAW filter stages.

4. A 2×/4×/8× user selectable interpolating filter eases data

rate and output signal reconstruction filter requirements.

5. User selectable twos complement/straight binary

data coding.

6. User programmable channel gain control over 1 dB range

in 0.01 dB increments.

7. User programmable channel offset control ±10% over

the FSR.

8. Ultrahigh speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for

easy interfacing.

10. Flexible clock input with single-ended or differential input,

CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: Complete CMOS DAC operates on 1.2 W from

a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation, and several sleep functions reduce power during idle periods.

12. On-chip voltage reference: The AD9773 includes a 1.20 V

temperature compensated band gap voltage reference.

13. 80-lead thermally enhanced TQFP.

Rev. B | Page 4 of 60

Page 5

AD9773

SPECIFICATIONS

to T

MIN

Table 1. DC Specifications

Parameter Min Typ Max Unit

RESOLUTION 12 Bits

DC Accuracy1

ANALOG OUTPUT (for IR and 2R Gain Setting Modes)

Offset Error −0.02 ± 0.01 +0.02 % of FSR

Gain Error (With Internal Reference) −1.0 +1.0 % of FSR

Gain Matching −1.0 ± 0.1 +1.0 % of FSR

Full-Scale Output Current2 2 20 mA

Output Compliance Range −1.0 +1.25 V

Output Resistance 200 kΩ

Output Capacitance 3 pF

Gain, Offset Cal DACs, Monotonicity Guaranteed REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V

Reference Output Current3 100 nA REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance 7 kΩ

Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C

Gain Drift (With Internal Reference) 50 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C POWER SUPPLY

AVDD

CLKVDD

CLKVDD (PLL ON)

DVDD

DIS

Power Supply Rejection Ratio—AVDD ±0.4 % of FSR/V OPERATING RANGE −40 +85 °C

Measured at I

Nominal full-scale current, I

Use an external amplifier to drive any external load.

100 MSPS f

400 MSPS f

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

Integral Nonlinearity −1.5 ± 0.4 +1.5 LSB Differential Nonlinearity −1 ± 0.2 +1 LSB Monotonicity Guaranteed over Specified Temperature Range

Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I I

in SLEEP Mode 23.3 26 mA

AVDD

)4 72.5 76 mA

AVDD

Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

Clock Supply Current (I

)4 8.5 10.0 mA

CLKVDD

) 23.5 mA

CLKVDD

Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I

)4 34 41 mA

DVDD

Nominal Power Dissipation 380 410 mW

5 1.75 W in PWDN 6.0 mW

driving a virtual ground.

OUTA

with f

DAC

OUT

, f

= 50 MSPS, fS/2 modulation, PLL enabled.

DAC

DATA

, is 32× the I

OUTFS

= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

current.

REF

Rev. B | Page 5 of 60

Page 6

AD9773

to T

MIN

transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.

Table 2. Dynamic Specifications

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f Output Settling Time (tST) (to 0.025%) 11 ns Output Rise Time (10% to 90%)1 0.8 ns Output Fall Time (10% to 90%)1 0.8 ns Output Noise (I

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

Spurious-Free Dynamic Range within a 1 MHz Window

Two-Tone Intermodulation (IMD) to Nyquist (f

Total Harmonic Distortion (THD)

Signal to Noise Ratio (SNR)

Adjacent Channel Power Ratio (ACPR)

Four-Tone Intermodulation

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I

MAX

) 400 MSPS

DAC

= 20 mA) 50 pA√Hz

OUTFS

= 0 dBFS)

OUT

= 100 MSPS, f

DATA

= 65 MSPS, f

DATA

= 65 MSPS, f

DATA

= 78 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 160 MSPS, f

DATA

= 0 dBFS, f

OUT

= 65 MSPS, f

DATA

= 65 MSPS, f

DATA

= 78 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 160 MSPS, f

DATA

= 100 MSPS, f

DATA

= 78 MSPS, f

DATA

= 160 MSPS, f

DATA

= 1 MHz 70 84.5 dBc

OUT

= 1 MHz 83 dBc

OUT

= 15 MHz 79 dBc

OUT

= 1 MHz 83 dBc

OUT

= 15 MHz 77 dBc

OUT

= 1 MHz 75 dBc

OUT

= 15 MHz 77 dBc

OUT

= 100 MSPS, f

DATA

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 10 MHz; f

OUT1

= 20 MHz; f

OUT1

= 1 MHz; 0 dBFS −70 −82.4 dB

OUT

= 5 MHz; 0 dBFS 70 dB

OUT

= 5 MHz; 0 dBFS 69 dB

OUT

= 1 MHz 72 92.6 dBc

OUT

= f

OUT1

= 11 MHz 80 dBc

OUT2

= 21 MHz 75 dBc

OUT2

= 11 MHz 80 dBc

OUT2

= 21 MHz 75 dBc

OUT2

= 11 MHz 80 dBc

OUT2

= 21 MHz 75 dBc

OUT2

= −6 dBFS)

OUT2

= 20 mA, Interpolation = 2×, differential

OUTFS

WCDMA with 3.84 MHz BW, 5 MHz Channel Spacing

IF = Baseband, f

IF = 19.2 MHz, f

21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f

201 MHz, 202 MHz, 203 MHz, and 204 MHz at -12 dBFS (f

= 76.8 MSPS 69 dBc

DATA

= 76.8 MSPS 69 dBc

DATA

= MSPS, Missing Center) 73 dBFS

DATA

= 160 MSPS, f

DATA

= 320 MHz) 69 dBFS

DAC

Rev. B | Page 6 of 60

Page 7

AD9773

to T

MIN

Table 3. Digital Specifications

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V

Logic 0 Voltage 0 0.9 V

Logic 1 Current −10 +10 µA

Logic 0 Current −10 +10 µA

Input Capacitance 5 pF CLOCK INPUTS

Input Voltage Range 0 3 V

Common-Mode Voltage 0.75 1.5 2.25 V

Differential Voltage 0.5 1.5 V SERIAL CONTROL BUS

Maximum SCLK Frequency (f

Mimimum Clock Pulse Width High (t

Mimimum Clock Pulse Width Low (t

Maximum Clock Rise/Fall Time 1 ms

Minimum Data/Chip Select Setup Time (tDS) 25 ns

Minimum Data Hold Time (tDH) 0 ns

Maximum Data Valid Time (tDV) 30 ns

RESET Pulse Width 1.5 ns

Inputs (SDI, SDIO, SCLK, CSB)

SDIO Output

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

) 15 MHz

SLCK

) 30 ns

PWH

) 30 ns

PWL

= 20 mA, unless otherwise noted.

OUTFS

Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 µA Logic 0 Current −10 +10 µA Input Capacitance 5 pF

Logic 1 Voltage DRVDD − 0.6 V Logic 0 Voltage 0.4 V Logic 1 Current 30 50 mA Logic 0 Current 30 50 mA

Rev. B | Page 7 of 60

Page 8

AD9773

Digital Filter Specifications

Table 4. Half-Band Filter No. 1 (43 Coefficients)

Tap Coefficient

1, 43 8 2, 42 0 3, 41 −29 4, 40 0 5, 39 67 6, 38 0 7, 37 −134 8, 36 0 9, 35 244 10, 34 0 11, 33 −414 12, 32 0 13, 31 673 14, 30 0 15, 29 −1,079 16, 28 0 17, 27 1,772 18, 26 0 19, 25 −3,280 20, 24 0 21, 23 10,364 22 16,384

Table 5. Half-Band Filter No. 2 (19 Coefficients)

Tap Coefficient

1, 19 19 2, 18 0 3, 17 −120 4, 16 0 5, 15 438 6, 14 0 7, 13 −1,288 8, 12 0 9, 11 5,047 10 8,192

Table 6. Half-Band Filter No. 3 (11 Coefficients)

Tap Coefficient

1, 11 7 2, 10 0 3, 9 −53 4, 8 0 5, 7 302 6 512

ATTENUATION (dBFS)

–20

–40

–60

–80

–100

–120

–20

–40

–60

–80

–100

–120

–20

–40

–60

–80

–100

–120

0.50 1.0 1.5 2.0

(NORMALIZED TO INPUT DATA RATE)

OUT

02857-B-002

Figure 2. 2× Interpolating Filter Response

0.50 1.0 1.5 2.0

(NORMALIZED TO INPUT DATA RATE)

OUT

02857-B-003

Figure 3. 4× Interpolating Filter Response

20468

(NORMALIZED TO INPUT DATA RATE)

OUT

02857-B-004

Figure 4. 8× Interpolating Filter Response

Rev. B | Page 8 of 60

Page 9

AD9773

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter With Respect To Min Max Unit

AVDD, DVDD, CLKVDD AGND, DGND, CLKGND −0.3 +4.0 V AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD −4.0 +4.0 V AGND, DGND, CLKGND AGND, DGND, CLKGND −0.3 +0.3 V REFIO, FSADJ1/FSADJ2 AGND −0.3 AVDD + 0.3 V I

, I

OUTA

P1B11 to P1B0, P2B11 to P2B0 DGND −0.3 DVDD + 0.3 V DATACLK, PLL_LOCK DGND −0.3 DVDD + 0.3 V CLK+, CLK–, RESET CLKGND −0.3 CLKVDD + 0.3 V LPF CLKGND −0.3 CLKVDD + 0.3 V SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO DGND −0.3 DVDD + 0.3 V Junction Temperature 125 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C

AGND −1.0 AVDD + 0.3 V

OUTB

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to

THERMAL CHARACTERISTICS

Thermal Resistance

80-Lead Thermally Enhanced TQFP Package

= 23.5°C/W (with thermal pad soldered to PCB)

absolute maximum ratings for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 9 of 60

Page 10

AD9773

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTA1IOUTA2IOUTB2

AGND

DVDD

AGND

NCNCNC

OUTB1

AGND

AD9773

TxDAC+

TOP VIEW

(Not to Scale)

P2B9

CLKVDD

LPF CLKVDD CLKGND

CLK+ CLK–

CLKGND

DATACLK/PLL_LOCK

DGND

DVDD

P1B11 (MSB)

P1B10

P1B9 P1B8 P1B7 P1B6

DGND

DVDD

P1B5 P1B4

NC = NO CONNECT

AVDD

AGND

PIN 1 IDENTIFIER

P1B3

P1B2

P1B1

AGND

DGND

P1B0 (LSB)

80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

AGND

P2B8

AGND

AVDD

DVDD

DGND

AGND

AVDD

P2B7

P2B6

AGND

AVDD

P2B5

P2B4

FSADJ1

FSADJ2

REFIO

RESET

SPI_CSB

SPI_CLK

SPI_SDIO

SPI_SDO

DGND

DVDD

P2B0 (LSB)

P2B1

DGND

DVDD

P2B2

P2B3

IQSEL/P2B11 (MSB)

ONEPORTCLK/P2B10

02857-B-005

Figure 5. Pin Configuration

Rev. B | Page 10 of 60

Page 11

AD9773

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3 CLKVDD Clock Supply Voltage. 2 LPF PLL Loop Filter. 4, 7 CLKGND Clock Supply Common. 5 CLK+ Differential Clock Input. 6 CLK– Differential Clock Input. 8 DATACLK/PLL_LOCK

9, 17, 25,

DGND Digital Common.

35, 44, 52 10, 18, 26,

DVDD Digital Supply Voltage.

36, 43, 51 11 to 16,

P1B11 (MSB) to P1B0 (LSB) Port 1 Data Inputs.

19 to 24, 27 to 30,

NC No Connect.

47 to 50 31 IQSEL/P2B11 (MSB)

32 ONEPORTCLK/P2B10

33, 34, 37 to

P2B9 to P2B0 (LSB) Port 2 Data Inputs.

42, 45, 46 53 SPI_SDO

54 SPI_SDIO

55 SPI_CLK

56 SPI_CSB

57 RESET

58 REFIO Reference Output, 1.2 V Nominal. 59 FSADJ2 Full-Scale Current Adjust, Q Channel. 60 FSADJ1 Full-Scale Current Adjust, I Channel. 61, 63, 65,

AVDD Analog Supply Voltage.

76, 78, 80 62, 64, 66,

AGND Analog Common. 67, 70, 71, 74, 75, 77, 79

68, 69 I 72, 73 I

OUTB2

OUTB1

, I

Differential DAC Current Outputs, Q Channel.

OUTA2

, I

Differential DAC Current Outputs, I Channel.

OUTA1

With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1 indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate.

In one-port mode, IQSEL = 1 followed by a rising edge of the differential input clock will latch the data into the I channel input register. IQSEL = 0 will latch the data into the Q channel input register. In two-port mode, this pin becomes the Port 2 MSB.

With the PLL disabled and the AD9773 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9773 to accept and demux interleaved I and Q data to the I and Q input registers.

In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. This pin can also be used as an output for the data rate clock. For more information, see the Two-Port Data Input Mode section.

Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is 0, which sets SDIO as an input.

Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge.

Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle.

Logic 1 resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic 1 to SPI Register 00h, Bit 5. However, the software reset has no effect on the bits in Address 00h.

Rev. B | Page 11 of 60

Page 12

AD9773

TERMINOLOGY

Adjacent Channel Power Ratio (ACPR)

A ratio, in dBc, between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection

In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Offset Error

The deviation of the output current from the ideal of 0 is called offset error. For I are all 0s. For I

, 0 mA output is expected when the inputs

OUTA

, 0 mA output is expected when all inputs are

OUTB

set to 1.s

Output Compliance Range

The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Complex Modulation

The process of passing the real and imaginary components of a

jωt

signal through a complex modulator (transfer function = e

= cosωt + jsinωt) and realizing real and imaginary components on the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.

Group Delay

Number of input clocks between an impulse applied at the device input and the peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range.

Impulse Response

Response of the device to an impulse applied to the input.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

(interpolation rate), a digital filter can be constructed with

DATA

a sharp transition band near f appear around f

(output data rate) can be greatly suppressed.

DAC

/2. Images that would typically

DATA

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Pass Band

Frequency band in which any input applied therein passes unattenuated to the DAC output.

Power Supply Rejection

The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.

Temperature Drift

It is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

. For offset and gain

MAX

drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).

Rev. B | Page 12 of 60

Page 13

AD9773

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I 50 Ω doubly terminated, unless otherwise noted.

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 65 130

FREQUENCY (MHz)

Figure 6. Single-Tone Spectrum @ f

= 65 MSPS with f

DATA

OUT

= f

= 20 mA, Interpolation = 2×, differential transformer-coupled output,

OUTFS

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 10050 150

FREQUENCY (MHz)

= 78 MSPS with f

DATA

02857-B-006

Figure 9. Single-Tone Spectrum @ f

OUT

= f

DATA

02857-B-009

SFDR (dBc)

02010 30

–12dBFS

FREQUENCY (MHz)

Figure 7. In-Band SFDR vs. f

0dBFS

SFDR (dBc)

–6dBFS

–12dBFS

–6dBFS

0dBFS

@ f

OUT

= 65 MSPS

DATA

SFDR (dBc)

02857-B-007

–12dBFS

02010 30

Figure 10. In-Band SFDR vs. f

0dBFS

SFDR (dBc)

–6dBFS

–12dBFS

0dBFS

–6dBFS

FREQUENCY (MHz)

OUT

@ f

= 78 MSPS

DATA

02857-B-010

02010 30

FREQUENCY (MHz)

@ f

Figure 8. Out-of-Band SFDR vs. f

OUT

= 65 MSPS

DATA

02857-B-008

Rev. B | Page 13 of 60

02010 30

FREQUENCY (MHz)

@ f

Figure 11. Out-of-Band SFDR vs. f

OUT

= 78 MSPS

DATA

02857-B-011

Page 14

AD9773

–10

–20

–30

–40

–50

AMPLITUDE (dBm)

–60

–70

–80

–90

0 200100 300

Figure 12. Single-Tone Spectrum @ f

–12dBFS

–6dBFS

SFDR (dBc)

01020304050

Figure 13. In-Band SFDR vs. f

FREQUENCY (MHz)

0dBFS

FREQUENCY (MHz)

= 160 MSPS with f

DATA

@ f

OUT

= 160 MSPS

DATA

OUT

= f

DATA

IMD (dBc)

02010 30

02857-B-012

02857-B-013

Figure 15. Third-Order IMD Products vs. f

IMD (dBc)

02010 30

–3dBFS

0dBFS

FREQUENCY (MHz)

–6dBFS

–3dBFS

FREQUENCY (MHz)

Figure 16. Third-Order IMD Products vs. f

–6dBFS

@ f

OUT

0dBFS

@ f

OUT

= 65 MSPS

DATA

= 78 MSPS

DATA

02857-B-015

02857-B-016

–6dBFS

SFDR (dBc)

–12dBFS

0 1020304050

Figure 14. Out-of-Band SFDR vs. f

0dBFS

FREQUENCY (MHz)

OUT

@ f

= 160 MSPS

DATA

02857-B-014

Rev. B | Page 14 of 60

IMD (dBc)

04020 60

–3dBFS

0dBFS

FREQUENCY (MHz)

Figure 17. Third-Order IMD Products vs. f

–6dBFS

@ f

OUT

= 160 MSPS

DATA

02857-B-017

Page 15

AD9773

IMD (dBc)

–3dBFS –6dBFS

SFDR (dBc)

0dBFS

04020 60

FREQUENCY (MHz)

Figure 18. Third-Order IMD Products vs. f

1× f

= 160 MSPS, 2× f

DATA

IMD (dBc)

–15 –5–10 0

= 160 MSPS, 4× f

DATA

Figure 19. Third-Order IMD Products vs. A

= 50 MSPS for All Cases, 1× f

DATA

4× f

= 200 MSPS, 8× f

DAC

DATA

4×

2×

(dBFS)

OUT

= 50 MSPS, 2× f

DAC

and Interpolation Rate,

OUT

= 80 MSPS, 8× f

8×

1×

and Interpolation Rate,

OUT

DATA

= 100 MSPS,

DAC

= 400 MSPS

= 50 MSPS

02857-B-018

Figure 21. Third-Order IMD Products vs. AVDD @ f

SNR (dB)

0 150

0 10050 150

02857-B-019

3.23.1 3.3 3.4 3.5 AVDD (V)

= 320 MSPS, f

DAC

INPUT DATA RATE (MSPS)

Figure 22. SNR vs. Data Rate for f

DATA

PLL OFF

PLL ON

= 160 MSPS

OUT

= 5 MHz

= 10 MHz,

OUT

02857-B-021

02857-B-022

SFDR (dBc)

–12dBFS

–6dBFS

3.23.1 3.3 3.4 3.5 AVDD (V)

Figure 20. SFDR vs. AVDD @: f

= 320 MSPS, f

DAC

= 160 MSPS

DATA

0dBFS

= 10 MHz,

OUT

02857-B-020

SFDR (dBc)

–50 500 100

= 65MSPS

DATA

160MSPS

TEMPERATURE (°C)

Figure 23. SFDR vs. Temperature @ f

78MSPS

= f

OUT

DATA

/11

02857-B-023

Rev. B | Page 15 of 60

Page 16

AD9773

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 10050

Figure 24. Single-Tone Spurious Performance, f

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

Figure 25. Two-Tone IMD Performance, f

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 50 100 150 200 250

Figure 26. Single-Tone Spurious Performance, f

= 150 MSPS, No Interpolation

DATA

100203040

= 150 MSPS, Interpolation = 2×

DATA

FREQUENCY (MHz)

DATA

FREQUENCY (MHz)

= 10 MHz,

OUT

= 150 MSPS, No Interpolation

= 10 MHz,

OUT

–20

–40

–60

AMPLITUDE (dBm)

–80

–100

02857-B-024

Figure 27. Two-Tone IMD Performance, f

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 50 100 150 200 250

02857-B-025

Figure 28. Single-Tone Spurious Performance, f

= 80 MSPS, Interpolation = 4×

DATA

–20

–40

–60

AMPLITUDE (dBm)

–80

–100

02857-B-026

0 5 10 15 20 25

Figure 29. Two-Tone IMD Performance, f

2015510025303540

FREQUENCY (MHz)

= 150 MSPS, Interpolation = 4×

DATA

FREQUENCY (MHz)

OUT

= 10 MHz, f

= 10 MHz,

= 50 MSPS,

DATA

02857-B-027

02857-B-028

02857-B-029

Interpolation = 8×

Rev. B | Page 16 of 60

Page 17

AD9773

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

0 200100 300

FREQUENCY (MHz)

Figure 30. Single-Tone Spurious Performance, f

= 50 MSPS, Interpolation = 8×

DATA

= 10 MHz,

OUT

02857-B-030

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

04020 60

FREQUENCY (MHz)

Figure 31. Eight-Tone IMD Performance, f

DATA

Interpolation = 8×

= 160 MSPS,

02857-B-031

Rev. B | Page 17 of 60

Page 18

AD9773

MODE CONTROL (VIA SPI PORT)

Table 9. Mode Control via SPI Port (Default Values Are Highlighted)

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h

SDIO Bidirectional 0 = Input

LSB, MSB First 0 = MSB 1 = LSB

Software Reset on Logic 1

1 = I/O

01h

Filter Interpolation Rate (1×, 2×, 4×,

Filter Interpolation Rate (1×, 2×, 4×, 8×)

Modulation Mode (None, f f

/4, fS/8)

/2,

8×)

02h

0 = Signed Input Data

1 = Unsigned

0 = Two-Port Mode

1 = One-Port

DATACLK Driver Strength

Mode

03h

Data Rate Output Clock

04h

0 = PLL OFF

1 = PLL ON

0 = Automatic Charge Pump Control

1 = Programmable

05h

IDAC Fine Gain Adjustment

06h

07h

08h

IDAC Offset Adjustment Bit 9

IDAC I

OFFSET

IDAC Offset Adjustment Bit 8

IDAC Offset Adjustment Bit 7

Direction

OFFSET

OUTA

OFFSET

OUTB

QDAC Fine Gain Adjustment

09h

0 = I on I

1 = I on I

QDAC Fine Gain Adjustment

Sleep Mode Logic 1 shuts down the DAC output currents.

Modulation Mode (None, f f

/4, fS/8)

/2,

DATACLK Invert

0 = No Invert

1 = Invert

IDAC Fine Gain Adjustment

IDAC Offset Adjustment Bit 6

QDAC Fine Gain Adjustment

Power-Down Mode Logic 1 shuts down all digital and analog functions.

0 = No Zero Stuffing on Interpolation Filters, Logic 1

enables zero stuffing.

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 5

QDAC Fine Gain Adjustment

1R/2R Mode DAC output current set by one or two external resistors. 0 = 2R, 1 = 1R

1 = Real Mix Mode

0 = Complex Mix Mode

ONEPORTCLK Invert 0 = No Invert 1 = Invert

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 4

QDAC Fine Gain Adjustment

PLL_LOCK Indicator

–jωt

0 = e

+jωt

1 = e

IQSEL Invert

0 = No Invert

1 = Invert

PLL Divide (Prescaler) Ratio

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 3

IDAC Offset Adjustment Bit 1

QDAC Fine Gain Adjustment

DATACLK/ PLL_LOCK Select

0 = PLLLOCK

1 = DATACLK

Q First 0 = I First 1 = Q First

PLL Divide (Prescaler) Ratio

PLL Charge Pump Control

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset Adjustment Bit 2

IDAC Offset Adjustment Bit 0

QDAC Fine Gain Adjustment

See the Two-Port Data Input Mode section for more information.

Rev. B | Page 18 of 60

Page 19

AD9773

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0Ah

0Bh

0Ch

QDAC Offset Adjustment Bit 9

QDAC I

OFFSET

QDAC Offset Adjustment Bit 8

QDAC Offset Adjustment Bit 7

Direction

0 = I on I

1 = I on I

OFFSET

OUTA

OFFSET

OUTB

0Dh

QDAC Offset Adjustment Bit 6

QDAC Coarse Gain Adjustment

QDAC Offset Adjustment Bit 5

Version Register

QDAC Coarse Gain Adjustment

QDAC Offset Adjustment Bit 4

Version Register

QDAC Coarse Gain Adjustment

QDAC Offset Adjustment Bit 3

QDAC Offset Adjustment Bit 1

Version Register

QDAC Coarse Gain Adjustment

QDAC Offset Adjustment Bit 2

QDAC Offset Adjustment Bit 0

Version Register

Rev. B | Page 19 of 60

Page 20

AD9773

REGISTER DESCRIPTION

Address 00h

Bit 7: Logic 0 (default). Causes the SPI_SDIO pin to act as an

input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or output, depending on Bit 7 of the instruction byte.

Bit 6: Logic 0 (default). Determines the direction (LSB/MSB first) of the communications and data transfer communications cycles. Refer to the MSB/LSB Transfers section for more details.

Bit 5: Writing a 1 to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. Register Address 00h bits are not cleared by this software reset. However, a high level at the RESET pin forces all registers, including those in Address 00h, to their default state.

Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC output currents.

Bit 3: Power-Down Mode. Logic 1 shuts down all analog and digital functions except for the SPI port.

Bit 2: 1R/2R Mode. The default (0) places the AD9773 in two resistor mode. In this mode, the I DAC references are set separately by the R

currents for the I and Q

REF

resistors on

SET

FSADJ1 and FSADJ2 (Pins 59 and 60). In 2R mode, assuming the coarse gain setting is full scale and the fine gain setting is zero, I

FULLSCALE1

/FSADJ2. With this bit set to 1, the reference currents for

× V

REF

= 32 × V

/FSADJ1 and I

REF

FULLSCALE2

= 32

both I and Q DACs are controlled by a single resistor on Pin 60. I

in one resistor mode for both I and Q DACs is half of

FULLSCALE

what it would be in 2R mode, assuming all other conditions

, register settings) remain unchanged. The full-scale

SET

current of each DAC can still be set to 20 mA by choosing a resistor of half the value of the R

value used in 2R mode.

SET

Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading this bit will give the status of the PLL. A Logic 1 indicates the PLL is locked. A Logic 0 indicates an unlocked state.

Bit 3: Logic 1 enables zero stuffing mode for interpolation filters.

Bit 2: Default (1) enables the real mix mode. The I and Q data channels are individually modulated by f

/2, fS/4, or fS/8 after the

interpolation filters. However, no complex modulation is done. In the complex mix mode (Logic 0), the digital modulators on the I and Q data channels are coupled to create a digital complex modulator. When the AD9773 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second IF frequency (i.e., the LO of the analog quadrature modulator external to the AD9773) according to the bit value of Register 01h, Bit 1.

Bit 1: Logic 0 (default) causes the complex modulation to be of

−jωt

the form e

, resulting in the rejection of the higher frequency image when the AD9773 is used with an external quadrature modulator. A Logic 1 causes the modulation to be of the form

+jωt

, which causes rejection of the lower frequency image.

Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act as a lock indicator for the internal PLL. A Logic 1 in this register causes Pin 8 to act as a DATACLK. For more information, see the Two-Port Data Input Mode section.

Address 02h

Bit 7: Logic 0 (default) causes data to be accepted on the inputs

as twos complement. Logic 1 causes data to be accepted as straight binary.

Bit 6: Logic 0 (default) places the AD9773 in two-port mode. I and Q data enters the AD9773 via Ports 1 and 2, respectively. A Logic 1 places the AD9773 in one-port mode in which interleaved I and Q data is applied to Port 1. See Table 8 for detailed information on how the DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK modes.

Address 01h

Bits 7, 6: This is the filter interpolation rate according to the

following table.

00 1× 01 2× 10 4× 11 8×

Bits 5, 4: This is the modulation mode according to the following table.

00 none 01 f 10 f 11 f

Bit 5: DATACLK Driver Strength. With the internal PLL disabled and this bit set to Logic 0, it is recommended that DATACLK be buffered. When this bit is set to Logic 1, DATACLK acts as a stronger driver capable of driving small capacitive loads.

Bit 4: Default Logic 0. A value of 1 inverts DATACLK at Pin 8.

Bit 2: Default Logic 0. A value of 1 inverts ONEPORTCLK at

Pin 32.

Bit 1: The default of Logic 0 causes IQSEL = 0 to direct input data to the I channel, while IQSEL = 1 directs input data to the Q channel.

Rev. B | Page 20 of 60

Page 21

AD9773

Bit 0: The default of Logic 0 defines IQ pairing as IQ, IQ, ... while programming a Logic 1 causes the pair ordering to be QI, QI, ...

Address 03h

Address 05h, 09h

Bits 7 to 0: These bits represent an 8-bit binary number

(Bit 7 MSB) that defines the fine gain adjustment of the I (05h) and Q (09h) DAC according to Equation 1.

Bit 7: Allows the data rate clock (divided down from the DAC clock) to be output at either the DATACLK pin (Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this bit will enable the data rate clock at DATACLK, while a “1” in this bit will cause the data rate clock to be output at SPI_SDO. For more information, see the Two-Port Data Input Mode section.

Bits 1, 0: Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for best performance), while the DAC input and output clocks run substantially slower. The divider ratio is set according to the following table.

00 ÷1 01 ÷2 10 ÷4 11 ÷8

Address 04h

Bit 7: Logic 0 (default) disables the internal PLL. Logic 1 enables

the PLL.

Bit 6: Logic 0 (default) sets the charge pump control to automatic. In this mode, the charge pump bias current is controlled by the divider ratio defined in Address 03h, Bits 1 and 0. Logic 1 allows the user to manually define the charge pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the PLL.

Bits 2, 1, 0: With the charge pump control set to manual, these bits define the charge pump bias current according to the following table.

000 50 µA 001 100 µA 010 200 µA 011 400 µA 111 800 µA

Address 06h, 0Ah

Bits 3 to 0: These bits represent a 4-bit binary number

(Bit 3 MSB) that defines the coarse gain adjustment of the I (06h) and Q (0Ah) DACs according to Equation 1.

Address 07h, 0Bh

Bits 7 to 0: These bits are used in conjunction with Address 08h,

0Ch, Bits 1, 0.

Address 08h, 0Ch

Bits 1, 0: The 10 bits from these two address pairs (07h, 08h and

0Bh, 0Ch) represent a 10-bit binary number that defines the offset adjustment of the I and Q DACs according to the equation below: (07h, 0Bh: Bit 7 MSB; 08h, 0Ch: Bit 0 LSB).

Address 08h, 0Ch

Bit 7: This bit determines the direction of the offset of the I

(08h) and Q (0Ch) DACs. A Logic 0 will apply a positive offset current to I current to I

, while a Logic 1 will apply a positive offset

OUTA

. The magnitude of the offset current is defined

OUTB

by the bits in Addresses 07h, 0Bh, 08h, and 0Ch according to Equation 1.

Equation 1 shows I

OUTA

and I

as a function of fine gain,

OUTB

coarse gain, and offset adjustment when using 2R mode. In 1R mode, the current I

is created by a single FSADJ resistor

REF

(Pin 60). This current is divided equally into each channel so that a scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.

OUTA

OUTB

OFFSET

⎡

⎛

⎜

⎢

⎝

⎣

⎡

⎛

⎜

⎢

⎝

⎣

×=

⎛

⎞

⎜

⎟

⎠

⎝

⎛

⎞

⎜

⎟

⎠

⎝

OFFSET

⎛

⎜

REF

1024

⎝

⎞

)(

⎟ ⎠

⎞

⎛

−

⎟

⎜ ⎝

⎠

⎞

⎛

−

⎟

⎜ ⎝

⎠

⎛

⎞

REFREF

⎟

⎜

25632

⎠

⎝

⎞

⎛

REFREF

⎟

⎜

25632

⎠

⎝

1024

DATAFINEICOARSEI

⎛

⎞

⎜

⎟ ⎠

⎝ ⎛

⎞

⎜

⎟

⎜

⎠

⎝

⎡

⎤

⎞

⎛

⎟

⎜

⎢

⎥

⎝

⎠

⎦

⎣ ⎡

⎤

⎞

⎛

⎟

⎢

⎜

⎥

⎝

⎠

⎦

⎢

⎣

⎤

⎞

)(

⎟

⎥

⎠

⎦

DATAFINEICOARSEI

⎤

⎞

−−

⎟

(1)

)(

⎥

⎟

⎥

⎠

⎦

Rev. B | Page 21 of 60

Page 22

AD9773

FUNCTIONAL DESCRIPTION

The AD9773 dual interpolating DAC consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9773 capable of 2×, 4×, or 8× interpolation. High speed input and output data rates can be achieved within the following limitations.

SDO (PIN 53)

SDIO (PIN 54)

SCLK (PIN 55)

CSB (PIN 56)

AD9773 SPI PORT

INTERFACE

Figure 32. SPI Port Interface

02857-B-032

Interpolation Rate (MSPS)

1× 160 160 2× 160 320 4× 100 400 8× 50 400

Input Data Rate (MSPS)

DAC Sample Rate (MSPS)

Both data channels contain a digital modulator capable of mixing the data stream with an LO of f where f

is the output data rate of the DAC. A zero stuffing

DAC

/2, f

DAC

/4, or f

DAC

/8,

feature is also included and can be used to improve pass-band flatness for signals being attenuated by the SIN(x)/x characteristic of the DAC output. The speed of the AD9773, combined with its digital modulation capability, enables direct IF conversion architectures at 70 MHz and higher.

The digital modulators on the AD9773 can be coupled to form a complex modulator. By using this feature with an external analog quadrature modulator, such as Analog Devices’ AD8345, an image rejection architecture can be enabled. To optimize the image rejection capability, as well as LO feedthrough in this architecture, the AD9773 offers programmable (via the SPI port) gain and offset adjust for each DAC.

Also included on the AD9773 are a phase-locked loop (PLL) clock multiplier and a 1.20 V band gap voltage reference. With the PLL enabled, a clock applied to the CLK+/CLK− inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. Each 12-bit DAC provides two complementary current outputs whose full-scale currents can be determined either from a single external resistor or independently from two separate resistors (see the 1R/2R Mode section). The AD9773 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square wave input. Separate voltage supply inputs are provided for each functional block to ensure optimum noise and distortion performance.

Sleep and power-down modes can be used to turn off the DAC output current (sleep) or the entire digital and analog sections (power-down) of the chip. An SPI compliant serial port is used to program the many features of the AD9773. Note that in power-down mode, the SPI port is the only section of the chip still active.

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9773 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9773. Single- or multiple-byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9773’s serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9773. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9773 coincident with the first eight SCLK rising edges. The instruction byte provides the AD9773 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9773.

A Logic 1 on the SPI_CSB pin, followed by a logic low, will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the middle of an instruction cycle or a data transfer cycle, none of the present data will be written.

The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9773 and the system controller. Phase 2 of the communication cycle is a transfer of one to four data bytes, as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.

Rev. B | Page 22 of 60

Page 23

AD9773

INSTRUCTION BYTE

The instruction byte contains the information shown below.

N1 N0 Description

0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes

R/W

Bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic 1 indicates read operation. Logic 0 indicates a write operation.

N1, N0

Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the following table.

MSB LSB

I7 I6 I5 I4 I3 I2 I1 I0 R/W N1 N0 A4 A3 A2 A1 A0

A4, A3, A2, A1, and A0

Bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9773.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SPI_CLK (Pin 55)—Serial Clock

The serial clock pin is used to synchronize data to and from the AD9773 and to run the internal state machines. The SPI_CLK maximum frequency is 15 MHz. All data input to the AD9773 is registered on the rising edge of SPI_CLK. All data is driven out of the AD9773 on the falling edge of SPI_CLK.

SPI_CSB (Pin 56)—Chip Select

Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SPI_SDO and SPI_SDIO pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.

SPI_SDIO (Pin 54)—Serial Data I/O

Data is always written into the AD9773 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 00h. The default is Logic 0, which configures the SDIO pin as unidirectional.

SPI_SDO (Pin 53)—Serial Data Out

Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9773 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.

MSB/LSB TRANSFERS

The AD9773 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the first LSB bit in Register 0. The default is MSB first.

When this bit is set active high, the AD9773 serial port is in LSB first format. In LSB first mode, the instruction byte and data bytes must be written from LSB to MSB. In LSB first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle.

When this bit is set default low, the AD9773 serial port is in MSB first format. In MSB first mode, the instruction byte and data bytes must be written from MSB to LSB. In MSB first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle.

When incrementing from 1Fh, the address generator changes to 00h. When decrementing from 00h, the address generator changes to 1Fh.

Rev. B | Page 23 of 60

Page 24

AD9773

SCLK

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SDIO

SDO

R/W I4 I3 I2 I1 I0 D7

(N)I5(N)

D7ND6

D20D10D0

02857-B-033

Figure 33. Serial Register Interface Timing MSB First

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CLK

SDIO

SDO

I0 I1 I2 I3 I4 I5

(N)I6(N)

R/W D00D10D2

D00D10D2

D6ND7

02857-B-034

Figure 34. Serial Register Interface Timing LSB First

PWH

SCLK

PWL

SCLK

SDIO

INSTRUCTION BIT 7 INSTRUCTION BIT 6

02857-B-035

Figure 35. Timing Diagram for Register Write to AD9773

SCLK

SDIO

DATA BIT N

SDO

Figure 36. Timing Diagram for Register Read from AD9773

Rev. B | Page 24 of 60

DATA BIT N–1

02857-B-036

Page 25

AD9773

NOTES ON SERIAL PORT OPERATION

The AD9773 serial port configuration bits reside in Bits 6 and 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle.

The same considerations apply to setting the reset bit in Register Address 00h. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 00h.

It is recommended to use only single-byte transfers when changing serial port configurations or initiating a software reset.

A write to Bits 1, 2, and 3 of Address 00h with the same logic levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 00h with reset bit low and serial port configuration as specified above (XY) reprograms the OSC IN multiplier setting. A changed f 200 f

cycles (equals wake-up time).

MCLK

frequency is stable after a maximum of

SYSCLK

DAC OPERATION

The dual 12-bit DAC output of the AD9773, along with the reference circuitry, gain, and offset registers, is shown in Figure 37 and Figure 38 simply overdriving the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external R The fine gain DAC subtracts a small amount from this and the result is input to IDAC and QDAC, where it is scaled by an amount equal to 1024/24. Figure 39 and Figure 40 show the scaling effect of the coarse and fine adjust DACs. IDAC and QDAC are PMOS current source arrays, segmented in a 5-4-3 configuration. The five most significant bits control an array of 31 current sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current source. The three LSBs are binary weighted fractions of the middle bits’ current sources. All current sources are switched to either I

. Note that an external reference can be used by

resistor, and the values in the coarse gain register.

SET

OUTA

or I

, depending on the input code.

OUTB

GAIN

CONTROL

REGISTERS

1.2VREF

REFIO

0.1µF

COARSE REFERENCE CURRENT (mA)

OFFSET

GAIN

CONTROL

REGISTERS

IDAC

QDAC

OFFSET

CONTROL

REGISTERS

FSADJ1

RSET1

FINE GAIN DAC

COARSE

GAIN

RSET2

DAC

FSADJ2

COARSE

GAIN DAC

CONTROL

REGISTERS

Figure 37. DAC Outputs, Reference Current Scaling,

and Gain/Offset Adjust

AVDD

4µA

REFIO

7kΩ

0.7V

02857-B-038

Figure 38. Internal Reference Equivalent Circuit

2R MODE

1R MODE

50101520

COARSE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

Figure 39. Coarse Gain Effect on I

FULLSCALE

OFFSET

DAC

OFFSET

DAC

OUTA1

OUTB1

OUTA2

OUTB2

02857-B-037

02857-B-039

The fine adjustment of the gain of each channel allows for improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. In the Interfacing the AD9773 with the AD8345 Quadrature Modulator section, the performance data shows to what degree image rejection can be improved when the AD9773 is used with an AD8345 quadrature modulator from ADI.

Rev. B | Page 25 of 60

Page 26

AD9773

–0.5

–1.0

–1.5

–2.0

FINE REFERENCE CURRENT (mA)

–2.5

–3.0

200 400 600 800 1000

FINE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

Figure 40. Fine Gain E ffect on I

1R MODE

2R MODE

FULLSCALE

The offset control defines a small current that can be added to I

or I

OUTA

selection of which I

(not both) on the IDAC and QDAC. The

OUTB

this offset current is directed toward is

OUT

programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch, Bit 7 (QDAC). Figure 41 shows the scale of the offset current that can be added to one of the complementary outputs on the IDAC and QDAC. Offset control can be used for suppression of LO leakage resulting from modulation of dc signal components. If the AD9773 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9773 as well as the input offset on the modulator. Figure 42 shows a typical example of the effect that the offset control has on LO suppression.

In Figure 42, the negative scale represents an offset added to I

, while the positive scale represents an offset added to I

OUTB

OUTA

of the respective DAC. Offset Register 1 corresponds to IDAC, while Offset Register 2 corresponds to QDAC. Figure 42 represents the AD9773 synthesizing a complex signal that is then dc-coupled to an AD8345 quadrature modulator with an LO of 800 MHz. The dc-coupling allows the input offset of the AD8345 to be calibrated out as well. The LO suppression at the AD8345 output was optimized first by adjusting Offset Register 1 in the AD9773. When an optimal point was found (roughly Code 54), this code was held in Offset Register 1, and Offset Register 2 was adjusted. The resulting LO suppression is 70 dBFS. These are typical numbers, and the specific code for optimization will vary from part to part.

OFFSET CURRENT (mA)

0 200 400 600 800 1000

COARSE GAIN REGISTER CODE

02857-B-040

(ASSUMING RSET1, RSET2 = 1.9kΩ)

2R MODE

1R MODE

02857-B-041

Figure 41. DAC Output Offset Current

–10

–20

–30

–40

–50

LO SUPPRESSION (dBFS)

–60

–70

–80

DAC1, DAC2 (OFFSET REGISTER CODES)

Figure 42. Offset Adjust Control, Effect on LO Suppression

OFFSET REGISTER 1 ADJUSTED

OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE

0–256–768 –512–1024 256 512 768 1024

02857-B-042

1R/2R MODE

In 2R mode, the reference current for each channel is set independently by the FSADJ resistor on that channel. The AD9773 can be programmed to derive its reference current from a single resistor on Pin 60 by putting the part into 1R mode. The transfer functions in Equation 1 are valid for 2R mode. In 1R mode, the current developed in the single FSADJ resistor is split equally between the two channels. The result is that in 1R mode, a scale factor of 1/2 must be applied to the formulas in Equation 1. The full-scale DAC current in 1R mode can still be set to as high as 20 mA by using the internal 1.2 V reference and a 950 Ω resistor instead of the 1.9 kΩ resistor typically used in 2R mode.

CLOCK INPUT CONFIGURATIONS

The clock inputs to the AD9773 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources.

Rev. B | Page 26 of 60

Page 27

AD9773

(

Figure 43 shows the AD9773 driven from a single-ended clock source. The CLK+/CLK− pins form a differential input (CLKIN) so that the statically terminated input must be dcbiased to the midswing voltage level of the clock driven input.

reconstructed waveform, the high gain bandwidth product of the AD9773’s clock input comparator can tolerate differential sine wave inputs as low as 0.5 V p-p, with minimal degradation of the output noise floor.

AD9773

THRESHOLD

SERIES

0.1µF

CLK+

CLKVDD

CLK–

CLKGND

02857-B-043

Figure 43. Single-Ended Clock Driving Clock Inputs

A configuration for differentially driving the clock inputs is given in Figure 44. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed CLKVDD or CLKGND. If the driver voltage swings are within the supply range of the AD9773, the dc-blocking capacitors and bias resistors are not necessary.

AD9773

1kΩ

CLK+

CLKVDD

CLK–

CLKGND

02857-B-044

ECL/PECL

0.1µF

Figure 44. Differential Clock Driving Clock Inputs

A transformer, such as the T1-1T from Mini-Circuits, can also be used to convert a single-ended clock to differential. This method is used on the AD9773 evaluation board so that an external sine wave with no dc offset can be used as a differential clock.

PECL/ECL drivers require varying termination networks, the details of which are left out of Figure 43 and Figure 44 but can be found in application notes such as the AND8020/D from On Semiconductor. These networks depend on the assumed transmission line impedance and power supply voltage of the clock driver. Optimum performance of the AD9773 is achieved when the driver is placed very close to the AD9773 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch.

The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry should provide the AD9773 with a low jitter clock input that meets the minimum/maximum logic levels while providing fast edges. Although fast clock edges help minimize any jitter that will manifest itself as phase noise on a

PROGRAMMABLE PLL

CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled) according to the state of Address 02h, Bit 7 in the SPI port register. The internal operation of the AD9773 clock circuitry in these two modes is illustrated in Figure 45 and Figure 46.

The PLL clock multiplier and distribution circuitry produce the necessary internal synchronized 1×, 2×, 4×, and 8× clocks for the rising edge triggered latches, interpolation filters, modulators, and DACs. This circuitry consists of a phase detector, charge pump, voltage controlled oscillator (VCO), prescaler, clock distribution, and SPI port control. The charge pump, VCO, differential clock input buffer, phase detector, prescaler, and clock distribution are all powered from CLKVDD. PLL lock status is indicated by the logic signal at the DATACLK_PLL_LOCK pin, as well as by the status of Bit 1, Register 00h. To ensure optimum phase noise performance from the PLL clock multiplier and distribution, CLKVDD should originate from a clean analog supply. The VCO speed is a function of the input data rate, the interpolation rate, and the VCO prescaler, according to the following function:

)

MHzSpeedVCO

()

××

Table 10 defines the minimum input data rates versus the interpolation and PLL divider setting. If the input data rate drops below the defined minimum under these conditions, VCO phase noise may increase significantly.

CLK+ CLK–

CHARGE

PUMP

PLL DIVIDER

(PRESCALER)

CONTROL

PLL

CONTROL

(PLL ON)

PLLVDD

INPUT

DATA

LATCHES

INTERPOLATION

RATE

CONTROL

Figure 45. PLL and Clock Circuitry with PLL Enabled

PLL_LOCK

1 = LOCK

0 = NO LOCK

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

2148

CLOCK

DISTRIBUTION

CIRCUITRY

INTERNAL SPI

CONTROL

REGISTERS

SPI PORT

PHASE

DETECTOR

PRESCALER VCO

MODULATION

RATE

CONTROL

AD9773

escalerPrionRateInterpolatMHzRateDataInput

LPF

02857-B-045

Rev. B | Page 27 of 60

Page 28

AD9773

CLK+ CLK–

PLL_LOCK

1 = LOCK

0 = NO LOCK

INPUT

DATA

LATCHES

INTERPOLATION

RATE

CONTROL

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

2148

CLOCK

DISTRIBUTION

CIRCUITRY

INTERNAL SPI

CONTROL

REGISTERS

SPI PORT

PHASE

DETECTOR

PRESCALER VCO

MODULATION

RATE

CONTROL

Figure 46. PLL and Clock Circuitry with PLL Disabled

In addition, if the zero stuffing option is enabled, the VCO will double its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 47 illustrates typical phase noise performance of the AD9773 with 2× interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of f repetitive nature of this signal eliminates quantization noise and distortion spurs as a factor in the measurement. Although the curves blend together in Figure 47, the different conditions are given for clarity in Table 11. Figure 47 also contains a table detailing PLL divider settings versus interpolation rate and maximum and minimum f f

rates of 160 MSPS are due to the maximum input data rate

DATA

rates. Note that the maximum

DATA

of the AD7773. However, maximum rates of less than 160 MSPS and all minimum f

rates are due to the maximum and

DATA

minimum speeds of the internal PLL VCO. Figure 48 shows typical performance of the PLL lock signal (Pin 8 or 53) when the PLL is in the process of locking.

AD9773

CHARGE

PUMP

PLL DIVIDER

(PRESCALER)

CONTROL

PLL

CONTROL

(PLL ON)

DATA

/4. The

Table 10. PLL Optimization

Interpolation Rate

Divider Setting

Minimum f

DATA

1 1 32 160 1 2 16 160 1 4 8 112 1 8 4 56 2 1 24 160 2 2 12 112 2 4 6 56 2 8 3 28 4 1 24 100 4 2 12 56 4 4 6 28 4 8 3 14

02857-B-046

8 1 24 50 8 2 12 28 8 4 6 14 8 8 3 7

Table 11. Required PLL Prescaler Ratio vs. f

PLL Prescaler Ratio

DATA

125 MSPS Disabled 125 MSPS Enabled div 1 100 MSPS Enabled div 2 75 MSPS Enabled div 2 50 MSPS Enabled div 4

0 –10 –20 –30 –40 –50 –60 –70

PHASE NOISE (dBFS)

–80 –90

–100 –110

012345

FREQUENCY OFFSET (MHz)

Figure 47. Phase Noise Performance

DATA

Maximum f

DATA

02857-B-047

Rev. B | Page 28 of 60

Page 29

AD9773

Figure 48. PLL_LOCK Output Signal (Pin 8) in the

Process of Locking (Typical Lock Time)

It is important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9773. This will suffice unless the input data rate is below 10 MHz, in which case an external series RC is required between the LPF and CLKVDD pins.

POWER DISSIPATION

The AD9773 has three voltage supplies: DVDD, AVDD, and CLKVDD. Figure 49, Figure 50, and Figure 51 show the current required from each of these supplies when each is set to the

3.3 V nominal specified for the AD9773. Power dissipation (P can easily be extracted by multiplying the given curves by 3.3. As Figure 49 shows, I

is very dependent on the input data

DVDD

rate, the interpolation rate, and the activation of the internal digital modulator. I modulation rate by itself. In Figure 50, I

, however, is relatively insensitive to the

DVDD

shows the same

AVD D

type of sensitivity to the data, the interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 51, I

varies over a wide range yet is responsible for

CLKVDD

only a small percentage of the overall AD9773 supply current requirements.

400

(mA)

DVDD

350

300

250

200

150

100

8×, (MOD. ON)

Figure 49. I

4×, (MOD. ON)

8× 4×

500 100 150 200

(MHz)

DATA

vs. f

DVDD

vs. Interpolation Rate, PLL Disabled

DATA

2×, (MOD. ON)

2×

1×

76.0 8×, (MOD. ON)

75.5

75.0

74.5

(mA)

74.0

AVDD

73.5

73.0

72.5

02857-B-048

72.0

Figure 50. I

(mA)

CLKVDD

)

Figure 51. I

8×

500 100 150 200

vs. f

AVDD

DATA

8×

500 100 150 200

vs. f

CLKVDD

DATA

4×, (MOD. ON)

2×, (MOD. ON)

4×

2×

1×

(MHz)

DATA

vs. Interpolation Rate, PLL Disabled

4×

(MHz)

DATA

2×

1×

vs. Interpolation Rate, PLL Disabled

02857-B-050

02857-B-051

SLEEP/POWER-DOWN MODES

(Control Register 00h, Bits 3 and 4)

The AD9773 provides two methods for programmable reduction in power savings. The sleep mode, when activated, turns off the DAC output currents but the rest of the chip remains functioning. When coming out of sleep mode, the AD9773 will immediately return to full operation. Power-down mode, on the other hand, turns off all analog and digital circuitry in the AD9773 except for the SPI port. When returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle.

TWO-PORT DATA INPUT MODE

The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In the

02857-B-049

two-port mode, data at the two input ports is latched into the AD9773 on every rising edge of the data rate clock (DATACLK). Also, in the two-port mode, the AD9773 can be programmed to generate an externally available DATACLK for the purpose of data synchronization. This data rate clock can be

Rev. B | Page 29 of 60

Page 30

AD9773

programmed to be available at either Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because Pin 8 can also function as a PLL lock indicator when the PLL is enabled, there are several options for configuring Pins 8 and 53. The following describes the options.

PLL Off (Register 4, Bit 7 = 0)

PLL On (Register 4, Bit 7 = 1)

Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out of Pin 53. Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8. Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53.

In one-port mode, P2B14 and P2B15 from input data port two are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one-port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9773 in this mode for the purpose of data synchronization. ONEPORTCLK runs at the input interleaved data rate, which is 2× the data rate at the internal input to either channel.

Test configurations showing the various clocks that are required and generated by the AD9773 with the PLL enabled/disabled and in the one-port/two-port modes are given in Figure 101 to Figure 104. Jumper positions needed to operate the AD9773 evaluation board in these modes are given as well.

ONE-/TWO-PORT INPUT MODES

The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In twoport mode, the AD9773 can be programmed to generate an externally available data rate clock (DATACLK) for the purpose of data synchronization. Data at the two input ports can be latched into the AD9773 on every rising clock edge of DATACLK. In one-port mode, P2B10 and P2B11 from input data Port 2 are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one-port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9773 in this mode for the purpose of external data synchronization. ONEPORTCLK runs at the input interleaved data rate which is 2× the data rate at the internal input to either channel.

Test configurations showing the various clocks required and produced by the AD9773 in the PLL and one-/two-port modes are given in Figure 101 to Figure 104. Jumper positions needed to operate the AD9773 evaluation board in these modes are given as well.

PLL ENABLED, TWO-PORT MODE

(Control Register 02h, Bits 6 to 0 and 04h, Bits 7 to 1)

With the phase-locked loop (PLL) enabled and the AD9773 in two-port mode, the speed of CLKIN is inherently that of the

input data rate. In two-port mode, Pin 8 (DATACLK/PLL_

LOCK) can be programmed (Control Register 01h, Bit 0) to function as either a lock indicator for the internal PLL or as a clock running at the input data rate. When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of CLKIN. Data at the input ports is latched into the AD9773 on the rising edge of the CLKIN. Figure 52 shows the delay, t

, inherent between the rising edge of CLKIN and the rising edge of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2. The setup and hold times given in Figure 52 are the input data transitions with respect to CLKIN. Note that in two-port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at Ports 1 and 2.

The DAC output sample rate in two-port mode is equal to the clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate.

DATACLK INVERSION

(Control Register 02h, Bit 4)

By programming this bit, the DATACLK signal shown in Figure 52 can be inverted. With inversion enabled, t to the time between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing will occur.

CLKIN

DATACLK

DATA AT PORT

1 AND 2

Figure 52. Timing Requirements in Two-Port

Input Mode with PLL Enabled

= 0.0ns (max)

= 2.5ns (max)

will refer

02857-B-052

Rev. B | Page 30 of 60

Page 31

AD9773

DATACLK DRIVER STRENGTH

(Control Register 02h, Bit 5)

ONEPORTCLK INVERSION

(Control Register 02h, Bit 2)

The DATACLK output driver strength is capable of driving >10 mA into a 330 Ω load while providing a rise time of 3 ns. Figure 53 shows DATACLK driving a 330 Ω resistive load at a frequency of 50 MHz. By enabling the drive strength option (Control Register 02h, Bit 5), the amplitude of DATACLK under these conditions will be increased by approximately 200 mV.

3.0

2.5

2.0

1.5

1.0

AMPLITUDE (V)

0.5

–0.5

01020304050

DELTA APPROX. 2.8ns

TIME (ns)

Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz

PLL ENABLED, ONE-PORT MODE

(Control Register 02h, Bits 6 to1 and 04h, Bits 7 to 1)

By programming this bit, the ONEPORTCLK signal shown in Figure 54 can be inverted. With inversion enabled, t the delay between the rising edge of the external clock and the falling edge of ONEPORTCLK. The setup and hold times, t t

, will be with respect to the falling edge of ONEPORTCLK.

There is no other effect on timing.

ONEPORTCLK Driver Strength

The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for performance under load conditions.

CLKIN

ONEPORTCLK

02857-B-053

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

refers to

and

= 4.0ns (min)

to 5.5ns (max)

= 3.0ns (max)

= –0.5ns (max)

= 3.5ns (max)

IQS

= –1.5ns (max)

IQH

In one-port mode, the I and Q channels receive their data from an interleaved stream at digital input Port 1. The function of Pin 32 is defined as an output (ONEPORTCLK) that generates a clock at the interleaved data rate, which is 2× the internal input data rate of the I and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. The selection of the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9773 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 will latch the data into the I channel on the clock rising edge, while IQSEL = 1 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic 1). Figure 54 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one-port mode.

The DAC output sample rate in one port mode is equal to CLKIN multiplied by the interpolation rate. If zero stuffing is used, another factor of two must be included to calculate the DAC sample rate.

IQSEL

IQS

IQH

Figure 54. Timing Requirements in One-Port

Input Mode with the PLL Enabled

IQ PAIRING

(Control Register 02h, Bit 0)

In one-port mode, the interleaved data is latched into the AD9773 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. The following is an example of the effect this has on incoming interleaved data.

Given the following interleaved data stream, where the data indicates the value with respect to full scale:

I Q I Q I Q I Q I Q

0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5

With the control register set to 0 (I first), the data will appear at the internal channel inputs in the following order in time:

I Channel 0.5 1 0.5 0 0.5 Q Channel 0.5 1 0.5 0 0.5

02857-B-054

Rev. B | Page 31 of 60

Page 32

AD9773

With the control register set to 1 (Q first), the data will appear at the internal channel inputs in the following order in time:

I Channel 0.5 1 0.5 0 0.5 x Q Channel y 0.5 1 0.5 0 0.5

The values x and y represent the next I value and the previous Q value in the series.

PLL DISABLED, TWO-PORT MODE

With the PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal clock dividers in the AD9773 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Ports 1 and 2 of the AD9773 on the rising edge of DATACLK. DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate. With zero stuffing enabled, this division increases by a factor of two. Figure 55 illustrates the delay between the rising edge of CLKIN and the rising edge of DATACLK, as well as t

The programmable modes DATACLK inversion and DATACLK driver strength described in the previous section (PLL Enabled, Two-Port Mode) have identical functionality with the PLL disabled.

The data rate clock created by dividing down the DAC clock in this mode can be programmed (via Register × 03h, Bit 7) to be output from the SPI_SDO pin, rather than the DATACLK pin. In some applications, this may improve complex image rejection. t

will increase by 1.6 ns when SPI_SDO is used as

data rate clock out.

and tH in this mode.

With PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal dividers synthesize the ONEPORTCLK signal at Pin 32. The selection of the data for the I or Q channel is determined by the state of the logic level applied to Pin 31 (IQSEL when the AD9773 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 will latch the data into the I channel on the clock rising edge, while IQSEL = 1 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic 1). Figure 56 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one-port mode.

One-port mode is very useful when interfacing with devices such as the Analog Devices AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed).

The programmable modes’ ONEPORTCLK inversion, ONEPORTCLK driver strength and IQ pairing described in the previous section (PLL Enabled, One-Port Mode) have identical functionality with the PLL disabled.

CLKIN

ONEPORTCLK

CLKIN

DATACLK

DATA AT PORT

1 AND 2

= 6.5ns (min) to 8.0ns (max)

= 5.0ns (max)

= –3.2ns (max)

tSt

Figure 55. Timing Requirements in Two-Port

Input Mode with PLL Disabled

PLL DISABLED, ONE-PORT MODE

In one-port mode, data is received into the AD9773 as an interleaved stream on Port 1. A clock signal (ONEPORTCLK), running at the interleaved data rate, which is 2× the input data rate of the internal I and Q channels, is available for data synchronization at Pin 32.

Rev. B | Page 32 of 60

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

= 4.0ns (min)

to 5.5ns (max)

= 3.0ns (max)

= –1.0ns (max)

= 3.5ns (max)

IQS

= –1.5ns (max)

IQH

02857-B-055

IQSEL

IQS

IQH

Figure 56. Timing Requirements in One-Port

Input Mode with DLL Disabled

DIGITAL FILTER MODES

The I and Q data paths of the AD9773 have their own independent half-band FIR filters. Each data path consists of three FIR filters, providing up to 8× interpolation for each channel. The rate of interpolation is determined by the state of Control Register 01h, Bits 7 and 6. Figure 2 to Figure 4 show the response of the digital filters when the AD9773 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs have been

02857-B-056

Page 33

AD9773

normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than 75 dB of out-of-band rejection.

An online tool is available for quick and easy analysis of the AD9773 interpolation filters in the various modes. The link can be accessed at www.analog.com/Analog_Root/static/

techsupport/designtools/interactiveTools/dac/ ad9777image.html.

AMPLITUDE MODULATION

Given two sine waves at the same frequency, but with a 90° phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative frequency images. This is shown graphically in the frequency domain in Figure 57.

–jωt

/2j

SINE

–jωt

/2j

–jωt

/2 e

Figure 57. Real and Imaginary Components of Sinusoidal and Cosinusoidal Waveforms

–jωt

COSINE

02857-B-057

Amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of 2. This scaling will be very important in the discussion of the various modulation modes. The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. Examples of sine and cosine modulation are given in Figure 58.

–jωt

/2j

SINUSOIDAL MODULATION

–jωt

/2j

–jωt

/2 Ae

Figure 58. Baseband Signal, Amplitude Modulated

with Sine and Cosine Carriers

–jωt

COSINUSOIDAL MODULATION

02857-B-058

Rev. B | Page 33 of 60

Page 34

AD9773

MODULATION, NO INTERPOLATION

With Control Register 01h, Bits 7 and 6 set to 00, the interpolation function on the AD9773 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9773 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4. The tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. By comparing the digital

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation Disabled

domain spectrum to the DAC SIN(x)/x roll-off, an estimate can be made for the characteristics required for the DAC reconstruction filter. Note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to f the situation where the modulation is f spectral components add constructively, and there is no scaling effect.

/4 or fS/8) are scaled by a factor of 2. In

/2, the modulated

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

0 0.2 0.4 0.6 0.8 1.0

(×f

DATA

)

OUT

Figure 59. No Interpolation, Modulation Disabled

–20

–40

–60

AMPLITUDE (dBFS)

–80

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

0 0.2 0.4 0.6 0.8 1.0

(×f

DATA

)

DAC

02857-B-061

02857-B-059

OUT

Figure 61. No Interpolation, Modulation = f

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

0 0.2 0.4 0.6 0.8 1.0

(×f

DATA

)

OUT

Figure 60. No Interpolation, Modulation = f

DAC

02857-B-060

Rev. B | Page 34 of 60

–100

0 0.2 0.4 0.6 0.8 1.0

(×f

DATA

)

OUT

Figure 62. No Interpolation, Modulation = f

DAC

02857-B-062

Page 35

AD9773

MODULATION, INTERPOLATION = 2×

With Control Register 01h, Bits 7 and 6 set to 01, the interpolation rate of the AD9773 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1). Figure 63 to Figure 66 represent the spectral response of the AD9773 DAC output with 2× interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic). The advantage of interpolation becomes clear in Figure 63 to Figure 66, where it can be seen that the images that would normally appear in the spectrum around the input data rate

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 2x

frequency are suppressed by >70 dB. Another significant point is that the interpolation filtering is done previous to the digital modulator. For this reason, as Figure 63 to Figure 66 show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high-pass digital filter.

Note that when using the f stop band as the band edges coincide with each other. In the f

/4 modulation mode, there is no true

modulation mode, amplitude scaling occurs over only a portion of the digital filter pass band due to constructive addition over just that section of the band.

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

0.50 1.0 1.5 2.0 f

(×f

DATA

)

OUT

Figure 63. 2x Interpolation, Modulation = Disabled

–20

–40

–60

–80

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

02857-B-063

–20

–40

–60

AMPLITUDE (dBFS)

–80

0.50 1.0 1.5 2.0 f

(×f

DATA

)

OUT

Figure 65. 2x Interpolation, Modulation = f

DAC

02857-B-065

–100

0.50 1.0 1.5 2.0 f

(×f

DATA

)

OUT

Figure 64. 2x Interpolation, Modulation = f

DAC

–100

02857-B-064

0.50 1.0 1.5 2.0 f

(×f

DATA

)

OUT

Figure 66. 2x Interpolation, Modulation = f

DAC

02857-B-066

Rev. B | Page 35 of 60

Page 36

AD9773

02857 B 067

02857 B 068

02857 B 069

02857 B 070

MODULATION, INTERPOLATION = 4×

With Control Register 01h, Bits 7 and 6 set to 10, the interpolation rate of the AD9773 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, −1). Figure 67 to Figure 70 represent the spectral response of the AD9773 DAC output with 4× interpolation in the various modulation modes to a narrow band baseband signal.

The Effects of the Digital Modulation on the DAC Output Spectrum Interpolation = 4x

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

10234

(×f

OUT

DATA

Figure 67. 4x Interpolation, Modulation Disabled

–20

–40

–60

–80

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

)

Figure 69. 4x Interpolation, Modulation = f

–20

–40

–60

AMPLITUDE (dBFS)

–80

10234

(×f

DATA

)

DAC

OUT

–100

10234

OUT

Figure 68. 4x Interpolation, Modulation = f

(×f

DATA

)

DAC

–100

10234

OUT

Figure 70. 4x Interpolation, Modulation = f

(×f

DATA

)

DAC

Rev. B | Page 36 of 60

Page 37

AD9773

MODULATION, INTERPOLATION = 8×

With Control Register 01h, Bits 7 and 6 set to 11, the interpolation rate of the AD9773 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1, +0.707). Figure 71 to Figure 74 represent the spectral response of the AD9773 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal.

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8x

Looking at Figure 63 to Figure 75, the user can see how higher interpolation rates reduce the complexity of the reconstruction filter needed at the DAC output. It also becomes apparent that the ability to modulate by f

/2, fS/4, or fS/8 adds a degree of

flexibility in frequency planning.

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

–20

–40

–60

–80

10234

(×f

DATA

)

OUT

Figure 71. 8x Interpolation, Modulation Disabled

–20

–40

–60

AMPLITUDE (dBFS)

–80

–100

02857-B-071

Figure 73. 8x Interpolation, Modulation = f

–20

–40

–60

AMPLITUDE (dBFS)

–80

431205678

(×f

DATA

)

DAC

02857-B-073

OUT

–100

10234

(×f

DATA

)

OUT

Figure 72. 8x Interpolation, Modulation = f

DAC

02857-B-072

Rev. B | Page 37 of 60

–100

Figure 74. 8x Interpolation, Modulation = f

431205678

(×f

DATA

)

DAC

02857-B-074

OUT

Page 38

AD9773

ZERO STUFFING

(Control Register 01h, Bit 3)

As shown in Figure 75, a 0 or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f is due to the inherent SIN(x)/x roll-off response in the digitalto-analog conversion. In applications where the desired frequency content is below f Note that at f

/2 the loss due to SIN(x)/x is 4 dB. In direct RF

DAC

/2, this may not be a problem.

DAC

applications, this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced amplitude of the desired signal.

Consider an application where the digital data into the AD9773 represents a baseband signal around f f

/10. The reconstructed signal out of the AD9773 would

DAC

/4 with a pass band of

DAC

experience only a 0.75 dB amplitude variation over its pass band. However, the image of the same signal occurring at 3 × f

/4 will suffer from a pass-band flatness variation of 3.93 dB.

DAC

This image may be the desired signal in an IF application using one of the various modulation modes in the AD9773. This rolloff of image frequencies can be seen in Figure 59 to Figure 74, where the effect of the interpolation and modulation rate is apparent as well.

–10

–20

–30

SIN (X) /X ROLL-OFF (dBFS)

–40

–50

ZERO STUFFING

DISABLED

0.50 1.0 1.5 2.0

, NORMALIZED TO f

OUT

Figure 75. Effect of Zero Stuffing on DAC’s SIN(x)/x Response

DATA

ZERO STUFFING

ENABLED

WITH ZERO STUFFING DISABLED (Hz)

DAC

). This

The net effect is to increase the DAC output sample rate by a factor of 2× with the 0 in the SIN(x)/x DAC transfer function occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident, as can be seen in Figure 76.

It is important to realize that the zero stuffing option by itself does not change the location of the images but rather their amplitude, pass-band flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the image at 3 × f

/4 is now improved to 0.59 dB

DATA

while the signal level has increased slightly from −10.5 dBFS to

−8.1 dBFS.

INTERPOLATING (COMPLEX MIX MODE)

(Control Register 01h, Bit 2)

In the complex mix mode, the two digital modulators on the AD9773 are coupled to provide a complex modulation function. In conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. The complex modulation function can be

+jωt

programmed for e

−jωt

or e

to give upper or lower image rejection. As in the real modulation mode, the modulation frequency ω can be programmed via the SPI port for f f

DAC

/4, and f

/8, where f

DAC

represents the DAC output rate.

DAC

OPERATIONS ON COMPLEX SIGNALS

Truly complex signals cannot be realized outside of a computer simulation. However, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. I (real) and Q (imaginary) data paths are often defined this way. By using the architecture defined in Figure 76, a system can be realized that operates on complex signals, giving a complex (real and imaginary) output.

+jωt

If a complex modulation function (e imaginary components of the system correspond to the real and imaginary components of e

+jωt

or cosωt and sinωt. As Figure 77

shows, the complex modulation function can be realized by

02857-B-075

applying these components to the structure of the complex system defined in Figure 76.

) is desired, the real and

DAC

/2,

To improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to Logic 1. This option increases the ratio of f

DAC/fDATA

by a factor of 2 by doubling the DAC sample rate and inserting a midscale sample (i.e., 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This is important as it will affect the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the DAC.

Rev. B | Page 38 of 60

a(t)

INPUT OUTPUT

COMPLEX FILTER

= (c + jd)

b(t)

IMAGINARY

INPUT OUTPUT

Figure 76. Realization of a Complex System

c(t) × b(t) + d × b(t)

b(t) × a(t) + c × b(t)

02857-B-076

Page 39

AD9773

)

INPUT

(REAL)

INPUT

(IMAGINARY)

90°

–jωt

= COSωt + jSINωt

Figure 77. Implementation of a Complex Modulator

OUTPUT (REAL)

OUTPUT (IMAGINARY)

02857-B-077

COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS

In traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an IF (intermediate frequency) and then modulated a second time to the transmit frequency. Although this approach has several benefits, a major drawback is that two images are created near the transmit frequency. Only one image is needed, the other being an exact duplicate. Unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced.

INPUT

(REAL)

INPUT

(IMAGINARY

SINωt

Figure 78. Quadrature Modulator

90°

COSωt

OUTPUT

02857-B-078

The entire upconversion from baseband to transmit frequency is represented graphically in Figure 79. The resulting spectrum shown in Figure 79 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. It is important to remember that in this application (two baseband data channels) the image rejection is not dependent on the data at either of the AD9773 input channels. In fact, image rejection will still occur with either one or both of the AD9773 input channels active. Note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. This is easily done in the AD9773 by selecting the e

+jωt

bit (Register 01h, Bit 1). In purely complex terms, Figure 79 represents the two-stage upconversion from complex baseband to carrier.

A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. Figure 78 is a block diagram of a quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal.

Rev. B | Page 39 of 60

Page 40

AD9773

REAL CHANNEL (IN)

REAL CHANNEL (OUT)

A/2

–F

A/2

IMAGINARY CHANNEL (IN)

REAL

QUADRATURE

MODULATOR

IMAGINARY

COMPLEX

MODULATOR

OUT

–B/2J B/2J

–F

IMAGINARY CHANNEL (OUT)

–A/2J A/2J

–F

B/2 B/2

–F

A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J

–F

–A/4 – B/4J

– F

A/2 + B/2J A/2 – B/2J

–FQ+ F

A/4 – B/4J A/4 + B/4J –A/4 + B/4J

–F

REJECTED IMAGES

FQ– F

TO QUADRATURE MODULATOR

FQ+ F

NOTES

FC = COMPLEX MODULATION FREQUENCY

FQ = QUADRATURE MODULATION FREQUENCY

–F

02857-B-079

Figure 79. Two-Stage Upconversion and Resulting Image Rejection

Rev. B | Page 40 of 60

Page 41

AD9773

COMPLEX BASEBAND

OUTPUT = REAL

= REAL

–ω1–ω2DC

SIGNAL

j(ω1 + ω2)t

1/2 1/2

ω1 + ω2

FREQUENCY

02857-B-080

Figure 80. Two-Stage Complex Upconversion

IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS

As shown in Figure 79, image rejection can be achieved by applying baseband data to the AD9773 and following the AD9773 with a quadrature modulator. To process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. As Figure 80 shows, single or multiple complex modulators can be used to synthesize complex carriers. These complex carriers are then summed and applied to the real and imaginary inputs of the AD9773. A

BASEBAND CHANNEL 1

BASEBAND CHANNEL 2

REAL INPUT

IMAGINARY INPUT

REAL INPUT

IMAGINARY INPUT

COMPLEX

MODULATOR 1

COMPLEX

MODULATOR 2

system in which multiple baseband signals are complex modulated and then applied to the AD9773 real and imaginary inputs followed by a quadrature modulator is shown in Figure 82, which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in Figure 82 and Figure 80. Figure 82 adds an additional complex modulator stage for the purpose of summing multiple carriers at the AD9773 inputs. Also, as in Figure 79, the image rejection is not dependent on the real or imaginary baseband data on any channel. Image rejection on a channel will occur if either the real or imaginary data, or both, is present on the baseband channel.

It is important to remember that the magnitude of a complex signal can be 1.414× the magnitude of its real or imaginary components. Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9773 must be kept at least 3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator will result in severe distortion at the DAC output.

R(1)

MULTICARRIER

R(1)

R(2)

REAL OUTPUT = R(1) + R(2) + . . .R(N) (TO REAL INPUT OF AD9773)

MULTICARRIER IMAGINARY OUTPUT = I(1) + I(2) + . . .I(N) (TO IMAGINARY INPUT OF AD9773)

BASEBAND CHANNEL

REAL INPUT

IMAGINARY INPUT

COMPLEX

MODULATOR N

R(N) = REAL OUTPUT OF N

R(N)

I(N) = IMAGINARY OUTPUT OF N

R(N)

02857-B-081

Figure 81. Synthesis of Multicarrier Complex Signal

MULTIPLE BASEBAND CHANNELS

REAL

IMAGINARY

MULTIPLE COMPLEX

MODULATORS

FREQUENCY = ω

– ωC– ω

–ω

, ω2...ω

REAL

IMAGINARY

COMPLEX BASEBAND

SIGNAL

OUTPUT = REAL

REJECTED IMAGES

FREQUENCY = ω

AD9773

COMPLEX

MODULATOR

j(ωN + ωC + ωQ)t

Figure 82. Image Rejection with Multicarrier Signals

REAL REAL

IMAGINARY

ω1 + ωC + ω

QUADRATURE

MODULATOR

FREQUENCY = ω

02857-B-082

Rev. B | Page 41 of 60

Page 42

AD9773

The complex carrier synthesized in the AD9773 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at f only functions with modulation rates of f

Regions A and B of Figure 83 to Figure 88 are the result of the complex signal described previously, when complex modulated in the AD9773 by +e complex signal described previously, again with positive frequency components only, modulated in the AD9773 by −e The analog quadrature modulator after the AD9773 inherently modulates by +e

jωt

Region A

Region A is a direct result of the upconversion of the complex signal near baseband. If viewed as a complex signal, only the images in Region A will remain. The complex Signal A, consisting of positive frequency components only in the digital domain, has images in the positive odd Nyquist zones (1, 3, 5...), as well as images in the negative even Nyquist zones. The appearance and rejection of images in every other Nyquist zone will become more apparent at the output of the quadrature modulator. The A images will appear on the real and the imaginary outputs of the AD9773, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale now represents the frequency offset from this LO.

Region B

Region B is the image (complex conjugate) of Region A. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9773, Region B will appear in the spectrum. However, on the output of the quadrature modulator, Region B will be rejected.

/2. As a result, complex modu lat ion

DAC

/4 and f

DAC

jωt

. Regions C and D are the result of the

DAC

/8.

jωt

Region C

Region C is most accurately described as a down conversion, as the modulating carrier is −e

jωt

. If viewed as a complex signal, only the images in Region C will remain. This image will appear on the real and imaginary outputs of the AD9773, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale will represent the frequency offset from this LO.

Region D

Region D is the image (complex conjugate) of Region C. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9773, Region D will appear in the spectrum. However, on the output of the quadrature modulator, Region D will be rejected.

Figure 89 to Figure 96 show the measured response of the AD9773 and AD8345 given the complex input signal to the AD9773 in Figure 89. The data in these graphs was taken with a data rate of

12.5 MSPS at the AD9773 inputs. The interpolation rate of 4× or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result, the high end of the DAC output spectrum in these graphs is the first null point for the SIN(x)/x roll-off, and the asymmetry of the DAC output images is representative of the SIN(x)/x roll-off over the spectrum. The internal PLL was enabled for these results. In addition, a 35 MHz third-order low-pass filter was used at the AD9773/AD8345 interface to suppress DAC images.

An important point can be made by looking at Figure 91 and Figure 93. Figure 91 represents a group of positive frequencies modulated by complex +f group of negative frequencies modulated by complex −f

/4, while Figure 93 represents a

DAC

/4. When looking at the real or imaginary outputs of the AD9773, as shown in Figure 91 and Figure 93, the results look identical. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figure 92 and Figure 94.

Rev. B | Page 42 of 60

Page 43

AD9773

–

–20

DABCDABC

–40

–60

–80

–100

Figure 83. 2x Interpolation, Complex f

–20

D A BC DA BC

–40

–60

0–0.5–1.5 –1.0–2.0 0.5 1.0 1.5 2.0

(LO)

(×f

DATA

)

/4 Modulation

DAC

OUT

–20

–40

DA B CD A BC

–60

–80

100

02857-B-083

Figure 86. 2x Interpolation, Complex f

–20

–40

DA B CD A B C

–60

0–0.5–1.5 –1.0–2.0 0.5 1.0 1.5 2.0

(LO)

(×f

DATA

)

/8 Modulation

DAC

OUT

02857-B-086

–80

–100

0–1.0–3.0 –2.0–4.0 1.0 2.0 3.0 4.0

(LO)

(×f

DATA

)

OUT

Figure 84. 4x Interpolation, Complex f

–20

DA B C DA BC

–40

–60

–80

–100

0–2.0–6.0 –4.0–8.0 2.0 4.0 6.0 8.0

(LO)

(×f

DATA

)

OUT

Figure 85. 8x Interpolation, Complex f

/4 Modulation

DAC

/4 Modulation

DAC

–80

–100

02857-B-084

Figure 87. 4x Interpolation, Complex f

–20

DA DABC BC

–40

–60

–80

–100

02857-B-085

Figure 88. 8x Interpolation, Complex f

0–1.0–3.0 –2.0–4.0 1.0 2.0 3.0 4.0

(LO)

(×f

)

DATA

/8 Modulation

DAC

0–2.0–6.0 –4.0–8.0 2.0 4.0 6.0 8.0

(LO) (×f

)

DATA

/8 Modulation

DAC

OUT

02857-B-087

02857-B-088

Rev. B | Page 43 of 60

Page 44

AD9773

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

Figure 89. AD9773 Real DAC Output of Complex Input Signal Near Baseband

(Positive Frequencies Only), Interpolation = 4x, No Modulation in AD9773

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

Figure 90. AD9773 Complex Output from Figure 89, Now Quadrature

100203040

FREQUENCY (MHz)

790780760 770750 800 810 820 830

FREQUENCY (MHz)

Modulated by AD8345 (LO = 800 MHz)

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

02857-B-089

100203040

FREQUENCY (MHz)

02857-B-091

Figure 91. AD9773 Real DAC Output of Complex Input Signal Near

Baseband (Positive Frequencies Only), Interpolation = 4x,

Complex Modulation in AD9773 = +f

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

02857-B-090

790780760 770750 800 810 820 830

FREQUENCY (MHz)

DAC

02857-B-092

Figure 92. AD9773 Complex Output from Figure 91, Now Quadrature

Modulated by AD8345 (LO = 800 MHz)

Rev. B | Page 44 of 60

Page 45

AD9773

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

100203040

FREQUENCY (MHz)

Figure 93. AD9773 Real DAC Output of Complex Input Signal Near

Baseband (Negative Frequencies Only), Interpolation = 4x,

DAC

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

Complex Modulation in AD9773 = −f

790780760 770750 800 810 820 830

FREQUENCY (MHz)

Figure 94. AD9773 Complex Output from Figure 93, Now Quadrature

Modulated by AD8345 (LO = 800 MHz)

02857-B-093

02857-B-094

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

200406080

FREQUENCY (MHz)

Figure 95. AD9773 Real DAC Output of Complex Input Signal Near

Baseband (Positive Frequencies Only), Interpolation = 8x,

DAC

–10

–20

–30

–40

–50

–60

AMPLITUDE (dBm)

–70

–80

–90

–100

Complex Modulation in AD9773 = +f

780760720 740700 800 820 840 860

FREQUENCY (MHz)

Figure 96. AD9773 Complex Output from Figure 95, Now Quadrature

Modulated by AD8345 (LO = 800 MHz)

02857-B-095

02857-B-096

Rev. B | Page 45 of 60

Page 46

AD9773

APPLYING THE AD9773 OUTPUT CONFIGURATIONS

The following sections illustrate typical output configurations for the AD9773. Unless otherwise noted, it is assumed that I is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configuration is suggested. A simple differential output may be achieved by converting I

OUTA

and I

to a voltage output by terminating

OUTB

them to AGND via equal value resistors. This type of configuration may be useful when driving a differential voltage input device such as a modulator. If a conversion to a singleended signal is desired and the application allows for ac-coupling, an RF transformer may be useful, or if power gain is required, an op amp may be used. The transformer configuration provides optimum high frequency noise and distortion performance. The differential op amp configuration is suitable for applications requiring dc-coupling, signal gain, and/or level shifting within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if I

OUTA

and/or I

is connected to a load resistor, R

OUTB

referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting I

OUTA

or I

OUTB

into a negative unipolar voltage. This configuration provides the best DAC dc linearity as I

OUTA

or I

are maintained at ground or

OUTB

virtual ground.

UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT

In many applications, it may be necessary to understand the equivalent DAC output circuit. This is especially useful when designing output filters or when driving inputs with finite input impedances. Figure 97 illustrates the output of the AD9773 and the equivalent circuit. A typical application where this information may be useful is when designing an interface filter between the AD9773 and the Analog Devices AD8345 quadrature modulator.

AD9773

OUTA

OUTB

OUT

–

OUT

OUTFS

LOAD

For the typical situation, where I

= 20 mA and RA and RB

OUTFS

both equal 50 Ω, the equivalent circuit values become

= 2 V p-p

SOURCE

= 100 Ω

OUT

Note that the output impedance of the AD9773 DAC itself is greater than 100 kΩ and typically has no effect on the impedance of the equivalent output circuit.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 98. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of commonmode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes.

MINI-CIRCUITS

OUTA

DAC

OUTB

Figure 98. Transformer-Coupled Output Circuit

The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path for both I at I

OUTA

and I

OUTB

. The complementary voltages appearing

OUTB

(i.e., V

OUTA

around AGND and should be maintained within the specified output compliance range of the AD9773. A differential resistor,

, may be inserted in applications where the output of the

DIFF

transformer is connected to the load, R reconstruction filter or cable. R transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across R

T1-1T

and V

) swing symmetrically

OUTB

LOAD

is determined by the

DIFF

LOAD

02857-B-098

, via a passive

DIFF

+ R

SOURCE

× (RA + RB)

OUTFS

p-p

Figure 97. DAC Output Equivalent Circuit

(DIFFERENTIAL)

OUT

02857-B-097

Rev. B | Page 46 of 60

Page 47

AD9773

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9773 is configured with two equal load resistors, R 25 Ω. The differential voltage developed across I

OUTA

LOAD

and I

, of

OUTB

is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across I

OUTA

and I

, forming a real pole in a low-pass filter. The

OUTB

addition of this capacitor also enhances the op amp’s distortion performance by preventing the DAC’s fast slewing output from overloading the input of the op amp.

500Ω

OPT

25Ω

225Ω

500Ω

AD8021

OPT

225Ω

AVDD

02857-B-099

OUTA

DAC

OUTB

25Ω

Figure 99. Op Amp-Coupled Output Circuit

The common-mode (and second-order distortion) rejection of this configuration is typically determined by the resistor matching. The op amp used must operate from a dual supply since its output is approximately ±1.0 V. A high speed amplifier, such as the AD8021, capable of preserving the differential performance of the AD9773 while meeting other system level objectives (i.e., cost, power) is recommended. The op amp’s differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. R

is necessary only if level shifting is

OPT

required on the op amp output. In Figure 99, AVDD, which is the positive analog supply for both the AD9773 and the op amp, is also used to level shift the differential output of the AD9773 to midsupply (i.e., AVDD/2).

INTERFACING THE AD9773 WITH THE AD8345 QUADRATURE MODULATOR

The AD9773 architecture was defined to operate in a transmit signal chain using an image reject architecture. A quadrature modulator is also required in this application and should be designed to meet the output characteristics of the DAC as much as possible. The AD8345 from Analog Devices meets many of the requirements for interfacing with the AD9773. As with any DAC output interface, there are a number of issues that have to be resolved. Among the major issues are the following.

DAC Compliance Voltage/Input Common-Mode Range

The dynamic range of the AD9773 is optimal when the DAC outputs swing between ±1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components.

Gain/Offset Adjust

The matching of the DAC output to the common-mode input of the AD8345 allows the two components to be dc-coupled, with no level shifting necessary. The combined voltage offset of the two parts can therefore be compensated for via the AD9773 programmable offset adjust. This allows excellent LO cancellation at the AD8345 output. The programmable gain adjust allows for optimal image rejection as well.

The AD9773 evaluation board includes an AD8345 and recommended interface (Figure 105 and Figure 106). On the output of the AD9773, R9 and R10 convert the DAC output current to a voltage. R16 may be used to do a slight commonmode shift if necessary. The (now voltage) signal is applied to a low-pass reconstruction filter to reject DAC images. The components installed on the AD9773 provide a 35 MHz cutoff but may be changed to fit the application. A balun (MiniCircuits ADTL1-12) is used to cross the ground plane boundary to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, so a single connection between the AD9773 and AD8345 ground planes is recommended.

The performance of the AD9773 and AD8345 in an image reject transmitter, reconstructing three WCDMA carriers, can be seen in Figure 100. The LO of the AD8345 in this application is 800 MHz. Image rejection (50 dB) and LO feedthrough (−78 dBFS) have been optimized with the programmable features of the AD9773. The average output power of the digital waveform for this test was set to −15 dBFS to account for the peak-to-average ratio of the WCDMA signal.

–10

–20 –30

–40

–50 –60

AMPLITUDE (dBm)

–70

–80

–90

–100

762.5

Figure 100. AD9773/AD8345 Synthesizing a Three-Carrier

782.5 802.5 822.5 842.5 FREQUENCY (MHz)

WCDMA Signal at an LO of 800 MHz

02857-B-100

Rev. B | Page 47 of 60

Page 48

AD9773

EVALUATION BOARD

The AD9773 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from Win95®, Win98®, or Windows NT®/2000. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9773 in an image reject transmit signal chain.

Figure 101 through Figure 104 describe how to configure the evaluation board in the one- and two-port input modes with the PLL enabled and disabled. Refer to Figure 105 through Figure 114, the schematics, and the layout for the AD9773 evaluation board for the jumper locations described below. The AD9773 outputs can be configured for various applications by referring to the following instructions.

DAC Single-Ended Outputs

Remove transformers T2 and T3. Solder jumper link JP4 or JP28 to look at the DAC1 outputs. Solder jumper link JP29 or JP30 to look at the DAC2 outputs. Jumper 8 and Jumpers 13 to 17 should remain unsoldered. Jumpers JP35 to JP38 may be used to ground one of the DAC outputs while the other is measured single ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4.

DAC Differential Outputs

Transformers T2 and T3 should be in place. Note that the lower band of operation for these transformers is 300 kHz to 500 kHz. Jumpers 4, 8, 13 to 17, and 28 to 30 should remain unsoldered. The outputs are taken from S3 and S4.

Using the AD8345

Remove Transformers T2 and T3. Jumpers JP4 and 28 to 30 should remain unsoldered. Jumpers 13 to 16 should be soldered. The desired components for the low-pass interface filters L6, L7, C55, and C81 should be in place. The LO drive is connected to the AD8345 via J10 and the balun T4; and the AD8345 output is taken from J9.

Rev. B | Page 48 of 60

Page 49

AD9773

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

INPUT CLOCK

AWG2021

DG2020

40-PIN RIBBON CABLE

DAC1, DB11–DB0 DAC2, DB11–DB0

CLK+/CLK–DATACLK

AD9773

JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON

× ×

UNSOLDERED/OUT

× × ×

× × × ×

02857-B-101

Figure 101.

SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –

JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

Test Configuration for AD9773 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate,

DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

CLK+/CLK–ONEPORTCLK

AD9773

02857-B-102

Figure 102.

INPUT CLOCK

AWG2021

DG2020

JUMPER CONFIGURATION FOR ONE PORT MODE PLL ON

× ×

UNSOLDERED/OUT

SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –

JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

Test Configuration for AD9773 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,

DAC1, DB11–DB0 DAC2, DB11–DB0

× ×

× × ×

× ×

ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

To use PECL driver (U8), solder JP41 and JP42 and remove transformer T1.

In two-port mode, if DATACLK/PLL_LOCK is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL_LOCK is programmed to output Pin 53,

JP46 and JP47 should be soldered. For more information, see the Two-Port Data Input Mode section.

Rev. B | Page 49 of 60

Page 50

AD9773

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

INPUT CLOCK

AWG2021

DG2020

40-PIN RIBBON CABLE

DAC1, DB11–DB0 DAC2, DB11–DB0

CLK+/CLK–DATACLK

AD9773

JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF

UNSOLDERED/OUT

× × ×

× × × ×

02857-B-103

Figure 103.

SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –

JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

Test Configuration for AD9773 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

DATACLK = Signal Generator Frequency/Interpolation Rate

LECROY PULSE GENERATOR

TRIG

INP

SIGNAL GENERATOR

CLK+/CLK–ONEPORTCLK

AD9773

02857-B-104

Figure 104.

INPUT CLOCK

AWG2021

DG2020

JUMPER CONFIGURATION FOR ONE PORT MODE PLL OFF

× ×

UNSOLDERED/OUT

SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 –

JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 –

Test Configuration for AD9773 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

DAC1, DB11–DB0 DAC2, DB11–DB0

× ×

× × ×

× ×

ONEPORTCLK = Interleaved Input Data Rate = 2x Signal Generator Frequency/Interpolation Rate

To use PECL driver (U8), solder JP41 and JP42 and remove transformer T1.

In two-port mode, if DATACLK/PLL_LOCK is programmed to output Pin 8, JP25 and JP39 should be soldered. If DATACLK/PLL_LOCK is programmed to output Pin 53,

JP46 and JP47 should be soldered. For more information, see the Two-Port Data Input Mode section.

Rev. B | Page 50 of 60

Page 51

AD9773

POWER INPUT FILTERS

CC0603

C79

DNP

JP19

RC0603

R32

51Ω

CC0805

C81

DNP

LC0805

CC0805

C55

DNP

O2N

FERRITE

RC0603

LC0805

JP45

VDDM

LC1210

VDDMIN

W11

R34

R33

O2P

C28

DNP

51Ω

DNP

C32

CC0805

JP44

JP43

0.1µF

TP2

RED

JP9

DVDD

C66

TP3

16V

22µF

DCASE

C67

0.1µF

CC0805

BLK

TP4

AVDD

RED

JP10

16V

DCASE

22µF

MODULATED OUTPUT

DGND2

W12

DGND2; 3, 4, 5

0Ω

R23

LC1210

FERRITE

C65

16V

22µF

DCASE

DVDD_IN

RC0603

DGND

FERRITE

AVDD_IN

LC1210

DGND2; 3, 4, 5

LOCAL OSC INPUT

R28

C74

100pF

CC0603

VDDM

JP18

R26

1kΩ

RC0603

G2ENBL

VOUT

VPS2

AD8345

QBBN

QBBP

VPS1 LOIP

C76

100pF

LOIN G1B G1A IBBN IBBP

1 2 3 4 5 6 7 8

CC0603

C78

0.1µF

ADTL1-12

VDDM

C75

C35

C72

16 15 14 13 12 11 10 9

CC0603

BCASE

0.1µF

CC0603

100pF

10V

10µF

G4A G4B

Figure 105. AD8345 Circuitry on AD9773 Evaluation Board

C61

16V

22µF

DCASE

C68

0.1µF

CC0805

C64

16V

22µF

DCASE

AGND

J10

RC0603

0Ω

R30

DNP

RC0603

ETC1-1-13

CC0603

CLKVDD

TP6

TP5

BLK

RED

JP11

FERRITE

C62

C69

LC1210

C63

16V

DCASE

CC0805

16V

DCASE

TP7

BLK

22µF

0.1µF

22µF

CGND

CLKVDD_IN

JP7

JP21

CC0603

RC0603

LC0805

O1N

C73

C54

JP20

R36

CC0805

DNP L5

CC0805

DNP

RC0603

51Ω

DNP

RC0603

LC0805

O1P

R37

DNP

02857-B-105

C80

DNP

C77

100pF

R35

51Ω

ADTL1-12

DNP

Rev. B | Page 51 of 60

Page 52

AD9773

JP8

C70

0.1µF

R10

51kΩ

C41

C40

C39

C38

C37

C36

DVDD

1kΩ

RC0603 RC0603

1kΩ

JP30

10µF

BCASECC0805

C15

CC0603CC0603

C17

C18

VSSA2

AGND; 3, 4, 5

OUT 2

456

6.3V

TP8

0.1µF

TP9

0.1µF

TP10

0.1µF TP11

VSSA1

VDDA2

VDDA1

R43

WHT

FSADJ1

FSADJ2

49.9kΩ JP17

C70

T1-1T

R12

RESET

REFOUT

CC0603

0.1µF

RC0603

51kΩ

1kΩ

0.01%

2kΩ

0.01%

6.3V

10µF

C16

CC0603 BCASE

0.1µF

RC1206

SPCSP

SPCLK

SP-CLK

SP-CSB

R17

10kΩ

RC0603 RC0603

R11

51kΩ

1kΩ

SPSDI

SP-SDI

SP-SDO

SPSDO

VSSD6

DVDD

P2D0

VDDD6

O1N

O1P

O2N

C58

DNP

CC0603

JP13

C57

CC0603

JP15

DNP

O2P

JP16

JP14

C59

CC0603

JP36

AVDD

DNP

JP29

JP38

RC1206

AGND; 3, 4, 5

OUT1

R42

456

6.3V

0.1µF

49.9kΩ

T1-1T

J35

C58

DNP

CC0603

R16

10kΩ

JP4

RC0603

RC0603 RC0603

JP28

51kΩ

J37

AVDD

0.1µF

CC0805

0.1µF

CC0805

0.1µF

CC0805

0.1µF

CC0805

C2 +

C14

C19

C20

10µF

BCASECC0603

CC0603

0.1µF

807978777675747372717069686766656463626160595857565554535251504948474645444342

CC0805

0.1µF VSSA4

VSSA7

IOUT1P

VSSA6

IOUT1N

VSSA9

VSSA8

VDDA5

VDDA4

CC0805

VSSA10

VSSA5

IOUT2P

IOUT2N

VSSA3

VDDA3

CLKVDD

C27

C42

C11

C12

VDDC2

VDDC1 VDDA6

CC0603

123456789

1pF

0.1µF

CC0603 CC0603 CC0603

0.1µF

BCASE

6.3V

10µF

123

JP22

654

CC0603

C13

0.1µF

WHT

TP15

VSSC1

CLKP

RC0603

CLKN

200Ω

JP23

JP1

CLKP

CLKN

JP33

T1-1T

JP2

VSSC2

DCLK-PLLL

VSSD1

VDDD1

P1D15

P1D14

P1D13

P1D12

P1D11

P1D10

VSSD2

VDDD2

P1D9

P1D8

P1D7

P1D6

P1D5

P1D4

VSSD3

VDDD3

P1D3

P1D2

P1D1

P1D0

AD03

C24

CC0603

10µF

BCASE

AD02

0.001µF

6.3V

AD01

P2D15-IQSEL

AD00

JP5

BD15

10111213141516171819202122232425262728293031323334353637383940

R38 10kΩ

ADCLK

JP39

CLKIN

AD15

CC0603

C26

C10

BCASE

DVDD

ACLKX CGND; 3, 4, 5

10µF

AD14

0.001µF

6.3V

JP24

AD13

AD12

AD11

JP25

CX3

74VCX86

AD10

CX2

DVDD

DVDD; 14

DGND; 7

CX1

AD09

C25

TP14

RC0603

R40

JP12

CC0603

10µF

BCASE

WHT

5kΩ

DVDD

AD08

AD07

AD06

0.001µF

6.3V

RC0603

49.9Ω

DGND; 3, 4, 5

DATACLK

AD05

JP3

AD04

C29

DVDD

CC0605

0.1µF

Figure 106. AD9773 Clock, Power Supplies, and Output Circuitry

BCASE

6.3V

10µF

C21

CC0603

0.001µF

BD00

BD01

BD02

BD03

P2D1

P2D2

P2D3

P2D14-OPCLK

P2D13

P2D12

BD13

BD12

JP32

R39

1kΩ

JP27

OPCLK_3

SPSDO

JP47

74VCX86

JP46

BD04

BD05

P2D4

P2D5

VSSD5

VDDD5

P2D11

P2D10

VSSD4

VDDD4

BD11

CC0603

C23

10µF

BCASE

DVDD

JP26

JP31

BD14

74VCX86

JP40

DGND; 3, 4, 5

DVDD

P2D6

P2D9

BD10

0.001µF

6.3V

OPCLK

DVDD; 14

DGND; 7

BCASE

10µF

C22

CC0603

BD06

BD07

P2D7

P2D8

BD09

BD08

DVDD; 14

JP34

6.3V

0.001µF

AD9773+TSP

DGND; 7

C45

0.01µF

CC0805

OPCLK

AGND; 3, 4, 5

02857-B-106

Rev. B | Page 52 of 60

Page 53

AD9773

DVDD

CC0805ACASE

C34

0.1µF

C31

6.3V

4.7µF

DVDD; 14

AGND; 7

74VCX86

564

RP8

AD01

AD00

DNP

CC0805ACASE

C33

0.1µF

C30

6.3V

4.7µF

CX3

DVDD

DVDD; 14

AGND; 7

74VCX86

231

74VCX86

564

CX1

AD15

AD14

AD13

AD12

RP7

DNP

AD11

DVDD; 14

AGND; 7

AD10

DVDD; 14

AGND; 7

74VCX86

CX2

AD09

AD08

AD07

AD06

AD05

AD04

AD03

AD02

DVDD

CC0805ACASE

C53

0.1µF

C52

6.3V

4.7µF

AGND; 8

CLR

DVDD; 16

PRE

CLK

74LCX112

OPCLK_3

DVDD; 14

AGND; 7

OPCLK_2

74VCX86

231

R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

21 34567891021 345678910

50Ω

RP5

DATA-A

21 345678910

Ω

RCOM

RP1 22

RP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP1 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22ΩRP2 22

116

215

314

413

512

611

710

116

215

314

413

512

611

710

50Ω

RP6

21 345678910

RCOM

357

468

13151719212325272931333537

101214161820222426283032343638

Figure 107. AD9773 Evaluation Board Input (A Channel) and Clock Buffer Circuitry

R1 R2 R3 R4 R5 R6 R7 R8 R9

RIBBON

DVDD

4 10

PRE

CLK

CLR

74LCX112

OPCLK

ADCLK

R15

RC1206

220Ω

02857-B-107

Rev. B | Page 53 of 60

Page 54

AD9773

R21

CLKVDD

C47

R14

RC0805

DNP

1nF

200Ω

R20

CC805

RC0805

CLKVDD

RC0805

DNP

MC100EPT22

120Ω

RC0805

JP42

C46

CLKP

0.1µF

JP41

CLKN

R22

CGND; 5

CC805

CLKVDD

RC0805

DNP

C48

CLKVDD; 8

R13

120Ω

RC0805

R24

DNP

1nF

RC0805

ACLKX

CC805

R18

200Ω

CLKDD

MC100EPT22

C60

CC805

C49

ACASE

4.7µF

CLKVDD; 8

0.1µF

6.3V

CGND; 5

C51

DVDD

DGND; 7

0.1µF

CC805

6.3V

C44

4.7µF

ACASE

DGND; 7

DVDD; 14

74AC14

DVDD; 14

74AC14

DVDD; 14

74AC14

C50

74AC14

0.1µF

SPI PORT

12345

RC0805

R50

9kΩ

DGND; 7

R48

DVDD; 14

74AC14

DVDD; 14

74AC14

RC0805

9kΩ

DGND; 7

DVDD; 14

74AC14

DGND; 7

DVDD; 14

74AC14

RC0805

R45

9kΩ

DGND; 7

DVDD; 14

74AC14

DGND; 7

DVDD; 14

74AC14

DGND; 7

DVDD; 14

74AC14

DVDD; 14

74AC14

R1 R2 R3 R4 R5 R6 R7 R8 R9R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

RP9

DNP

50Ω

RP12

21 34567891021 345678910

DATA-B

BD15

BD14

RP3 22Ω

116

357

468

BD13

BD12

RP3 22Ω

215

314

BD11

BD10

BD09

BD08

BD07

BD06

BD05

BD04

BD03

BD02

BD01

BD00

RP3 22Ω

RP4 22Ω

413

512

611

710

116

215

314

413

13151719212325272931333537

101214161820222426283032343638

512

611

RP4 22Ω

710

21 345678910

RP11

21 345678910

RP10

50Ω

RCOM

DNP

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCOM

R1 R2 R3 R4 R5 R6 R7 R8 R9

RIBBON

SPCSB

SPCLK

CC805

6.3V

C43

4.7µF

+ +

ACASE

SPSDI

SPSDO

DVDD

02857-B-108

Figure 108. AD9773 Evaluation Board Input (B Channel) and SPI Port Circuitry

Rev. B | Page 54 of 60

Page 55

AD9773

02857-B-109

Figure 109. AD9773 Evaluation Board Components, Top Side

02857-B-110

Figure 110. AD9773 Evaluation Board Components, Bottom Side

Rev. B | Page 55 of 60

Page 56

AD9773

Figure 111. AD9773 Evaluation Board Layout, Layer One ( Top)

02857-B-111

02857-B-112

Figure 112. AD9773 Evaluation Board Layout, Layer Two (Ground Plane)

Rev. B | Page 56 of 60

Page 57

AD9773

02857-B-113

Figure 113. AD9773 Evaluation Board Layout, Layer Three (Power Plane)

02857-B-114

Figure 114. AD9773 Evaluation Board Layout, Layer Four (Bottom)

Rev. B | Page 57 of 60

Page 58

AD9773

OUTLINE DIMENSIONS

0.75

0.60

0.45

SEATING

PLANE

0.15

0.05

1.20 MAX

0.20

0.09

COPLANARITY

0.08

14.00 SQ

12.00 SQ

PIN 1

TOP VIEW

(PINS DOWN)

1.05

1.00

0.95

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD

0.27

0.22

0.17

GAGE PLANE

0.25

7°

3.5° 0°

BOTTOM

VIEW

6.00 SQ

Figure 115. 80-Lead Thin Plastic Quad Flat Package, Exposed Pad

[TQFP/ED]

(SV-80)

ORDERING GUIDE

Models Temperature Range Package Description Package Option

AD9773BSV −40°C to +85°C 80-Lead Thin Plastic Quad Flatpack (TQFP) SV-80 AD9773BSVRL −40°C to +85°C 80-Lead Thin Plastic Quad Flatpack (TQFP) SV-80 AD9773-EB Evaluation Board

Rev. B | Page 58 of 60

Page 59

AD9773

NOTES

Rev. B | Page 59 of 60

Page 60

AD9773

NOTES

C02857-0-4/04(B)

Rev. B | Page 60 of 60

Datasheet AD9773 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

MODE CONTROL (VIA SPI PORT)

REGISTER DESCRIPTION

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE FOR REGISTER CONTROL

GENERAL OPERATION OF THE SERIAL INTERFACE

INSTRUCTION BYTE

SERIAL INTERFACE PORT PIN DESCRIPTIONS

MSB/LSB TRANSFERS

NOTES ON SERIAL PORT OPERATION

DAC OPERATION

1R/2R MODE

CLOCK INPUT CONFIGURATIONS

PROGRAMMABLE PLL

POWER DISSIPATION

SLEEP/POWER-DOWN MODES

TWO-PORT DATA INPUT MODE

ONE-/TWO-PORT INPUT MODES

PLL ENABLED, TWO-PORT MODE

DATACLK INVERSION

DATACLK DRIVER STRENGTH

ONEPORTCLK INVERSION

PLL ENABLED, ONE-PORT MODE

IQ PAIRING

PLL DISABLED, TWO-PORT MODE

PLL DISABLED, ONE-PORT MODE

DIGITAL FILTER MODES

AMPLITUDE MODULATION

MODULATION, NO INTERPOLATION

MODULATION, INTERPOLATION = 2×

MODULATION, INTERPOLATION = 4×

MODULATION, INTERPOLATION = 8×

ZERO STUFFING

INTERPOLATING (COMPLEX MIX MODE)

OPERATIONS ON COMPLEX SIGNALS

COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS

APPLYING THE AD9773 OUTPUT CONFIGURATIONS

UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT

DIFFERENTIAL COUPLING USING A TRANSFORMER

DIFFERENTIAL COUPLING USING AN OP AMP

INTERFACING THE AD9773 WITH THE AD8345 QUADRATURE MODULATOR

DAC Compliance Voltage/Input Common-Mode Range

Gain/Offset Adjust

EVALUATION BOARD

DAC Single-Ended Outputs

DAC Differential Outputs

Using the AD8345

OUTLINE DIMENSIONS

ORDERING GUIDE