Datasheet AD9772A Datasheet (ANALOG DEVICES)

Page 1

14-Bit, 160 MSPS TxDAC+

FEATURES

Single 3.1 V to 3.5 V supply 14-bit DAC resolution and input data width 160 MSPS input data rate

67.5 MHz reconstruction pass band @ 160 MSPS 74 dBc SFDR @ 25 MHz 2× interpolation filter with high- or low-pass response

73 dB image rejection with 0.005 dB pass-band ripple

Zero-stuffing option for enhanced direct IF performance Internal 2×/4× clock multiplier 250 mW power dissipation; 13 mW with power-down mode 48-lead LQFP package

APPLICATIONS

Communication transmit channel

W-CDMA base stations, multicarrier base stations,

direct IF synthesis, wideband cable systems Instrumentation

GENERAL DESCRIPTION

The AD9772A is a single-supply, oversampling, 14-bit digitalto-analog converter (DAC) optimized for baseband or IF waveform reconstruction applications requiring exceptional dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 2× digital interpolation filter and clock multiplier. The on-chip PLL clock multiplier provides all the necessary clocks for the digital filter and the 14-bit DAC. A flexible differential clock input allows for a single-ended or differential clock driver for optimum jitter performance.

For baseband applications, the 2× digital interpolation filter provides a low-pass response, thus providing as much as a threefold reduction in the complexity of the analog reconstruction filter. It does so by multiplying the input data rate by a factor of 2 while suppressing the original upper in-band image by more than 73 dB. For direct IF applications, the 2× digital interpolation filter response can be reconfigured to select the upper in-band image (that is, the high-pass response) while suppressing the original baseband image. To increase the signal level of the higher IF images and their pass-band flatness in direct IF applications, the AD9772A also features a zero-stuffing option in which the data following the 2× interpolation filter is upsampled by a factor of 2 by inserting midscale data samples.

with 2× Interpolation Filter

AD9772A

FUNCTIONAL BLOCK DIAGRAM

CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0

CLK+

CLK–

DATA

INPUTS

(DB13 TO

DB0)

SLEEP

AD9772A

1×

EDGE-

TRIGGERED

LATCHES

DCOM DVDD ACOM AVDD REFLO

CLOCK DISTRI BUTION

AND MODE SELE CT

FILTER

1×/2× 2×/4×

CONTROL

2× FIR

INTER-

POLATION

FILTER

CONTROL

Figure 1.

MUX

ZEROSTUFF

MUX

1.2V REF ERENCE

AND CONTROL AMP

The AD9772A can reconstruct full-scale waveforms with bandwidths of up to 67.5 MHz while operating at an input data rate of 160 MSPS. The 14-bit DAC provides differential current outputs to support differential or single-ended applications.

A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The differential current outputs can be fed into a transformer or a differential op amp topology to obtain a single-ended output voltage using an appropriate resistive load.

The on-chip band gap reference and control amplifier are configured for maximum accuracy and flexibility. The AD9772A can be driven by the on-chip reference or by a variety of external reference voltages. The full-scale current of the AD9772A can be adjusted over a 2 mA to 20 mA range, thus providing additional gain-ranging capabilities.

The AD9772A is available in a 48-lead LQFP package and is specified for operation over the industrial temperature range of –40°C to +85°C.

DIV1

PLL CLOCK MULTIPLIER

14-BIT DAC

PLLCOM

LPF

PLLVDD

OUTA

OUTB

REFIO

FSADJ

2253-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

AD9772A

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Product Highlights........................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Dynamic Specifications ............................................................... 6

Digital Specifications ................................................................... 7

Digital Filter Specifications ......................................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Te r mi n ol o g y ....................................................................................12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 17

Functional Description .............................................................. 17

Digital Modes of Operation ...................................................... 17

PLL Clock Multiplier Operation .............................................. 19

Synchronization of Clock/Data

Using Reset with PLL Disabled................................................. 21

DAC Operation ........................................................................... 22

REVISION HISTORY

2/08—Rev. B to Rev. C

Changes to DVDD Parameter......................................................... 4

Changes to PLL Clock Enabled Parameter ................................... 7

Changes to PLL Clock Disabled Parameter.................................. 7

Changes to Table 8.......................................................................... 10

Changes to Functional Description .............................................17

Change to Power Dissipation Section.......................................... 25

Changes to Power and Grounding Considerations Section ..... 27

Change to Figure 53 ....................................................................... 29

Change to Direct IF Section.......................................................... 30

Changes to Figure 61...................................................................... 34

Updated Outline Dimensions....................................................... 38

Changes to Ordering Guide.......................................................... 38

6/03—Rev. A to Rev. B

Change to Features .......................................................................... 1

Change to DC Specifications .......................................................... 2

DAC Transfer Function ............................................................. 22

Reference Operation .................................................................. 22

Reference Control Amplifier .................................................... 23

Analog Outputs .......................................................................... 23

Digital Inputs/Outputs .............................................................. 24

Sleep Mode Operation ............................................................... 25

Power Dissipation....................................................................... 25

Applying the AD9772A ................................................................. 26

Output Configurations.............................................................. 26

Differential Coupling Using a Transformer ............................... 26

Differential Coupling Using an Op Amp................................ 26

Single-Ended, Unbuffered Voltage Output............................. 26

Single-Ended, Buffered Voltage Output.................................. 27

Power and Grounding Considerations.................................... 27

Applications Information.............................................................. 29

Multicarrier ................................................................................. 29

Baseband Single-Carrier Applications .................................... 30

Direct IF....................................................................................... 30

AD9772A Evaluation Board ......................................................... 32

Schematics................................................................................... 33

Evaluation Board Layout ........................................................... 35

Outline Dimensions ....................................................................... 38

Ordering Guide .......................................................................... 38

Change to Digital Filter Specifications...........................................5

Ordering Guide Updated .................................................................6

Change to Pin Function Descriptions ............................................7

Change to Figure 13a and Figure 13b.......................................... 15

Change to Digital Inputs/Outputs................................................ 18

Change to Sleep Mode Operation................................................ 19

Change to Figure 22....................................................................... 19

Change to Figure 23....................................................................... 19

Change to Power and Ground Considerations .......................... 21

Change to Figure 29....................................................................... 21

Update to Outline Dimensions..................................................... 30

3/02—Rev. 0 to Rev. A

Edits to Digital Specifications..........................................................4

Edits to Absolute Maximum Ratings..............................................6

Change to TPC 11 .......................................................................... 10

Change to Figure 9 Caption.......................................................... 14

Change to Figure 13a and Figure 13b.......................................... 15

Rev. C | Page 2 of 40

Page 3

AD9772A

PRODUCT HIGHLIGHTS

1. A flexible, low power 2× interpolation filter supporting

reconstruction bandwidths of up to 67.5 MHz can be configured for a low- or high-pass response with 73 dB of image rejection for traditional baseband or direct IF applications.

2. A zero-stuffing option enhances direct IF applications.

3. A low glitch, fast settling 14-bit DAC provides exceptional

dynamic range for both baseband and direct IF waveform reconstruction applications.

4. The AD9772A digital interface, consisting of edge-triggered

latches and a flexible differential or single-ended clock input, can support input data rates up to 160 MSPS.

5. An on-chip PLL clock multiplier generates all of the

internal high speed clocks required by the interpolation filter and DAC.

6. The current output(s) of the AD9772A can easily be

configured for various single-ended or differential circuit topologies.

Rev. C | Page 3 of 40

Page 4

AD9772A

SPECIFICATIONS

DC SPECIFICATIONS

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 14 Bits DC ACCURACY

Integral Linearity Error (INL) ±3.5 LSB

Differential Nonlinearity (DNL) ±2.0 LSB

Monotonicity (12-Bit) Guaranteed over specified temperature range ANALOG OUTPUT

Offset Error −0.025 +0.025 % of FSR

Gain Error

Full-Scale Output Current

Output Compliance Range −1.0 +1.25 V

Output Resistance 200 kΩ

Output Capacitance 3 pF REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V

Reference Output Current REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance (REFLO = 3 V) 10 MΩ

Small-Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS

Unipolar Offset Drift 0 ppm of FSR/°C

Gain Drift

Reference Voltage Drift ±50 ppm/°C POWER SUPPLY

AVDD

DVDD

CLKVDD, PLLVDD4 (PLLVDD = 3.3 V)

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

Without Internal Reference −2 ±0.5 +2 % of FSR With Internal Reference −5 ±1.5 +5 % of FSR

20 mA

1 A

Without Internal Reference ±50 ppm of FSR/°C With Internal Reference ±100 ppm of FSR/°C

Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I Analog Supply Current in Sleep Mode (I

) 34 37 mA

AVDD

) 4.3 6 mA

AVDD

Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I

) 37 40 mA

DVDD

Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

CLKVDD

+ I

) 25 30 mA

PLLVDD

Rev. C | Page 4 of 40

Page 5

AD9772A

Parameter Min Typ Max Unit

CLKVDD (PLLVDD = 0 V)

Voltage Range 3.1 3.3 3.5 V

Clock Supply Current (I Nominal Power Dissipation Power Supply Rejection Ratio (PSRR)

PSRR − AVDD −0.6 +0.6 % of FSR/V PSRR − DVDD −0.025 +0.025 % of FSR/V

OPERATING RANGE −40 +85 °C

Measured at I

Nominal full-scale current, I

Use an external amplifier to drive any external load.

Measured at f

Measured with PLL enabled at f

Measured over a 3.0 V to 3.6 V range.

driving a virtual ground.

OUTA

= 100 MSPS and f

DATA

OUTFS

) 6.0 mA

CLKVDD

, is 32× the I

OUT

= 50 MSPS and f

DATA

current.

REF

= 1 MHz with DIV1 and DIV0 = 0 V.

= 1 MHz.

OUT

253 272 mW

Rev. C | Page 5 of 40

Page 6

AD9772A

DYNAMIC SPECIFICATIONS

to T

MIN

output, 50 Ω doubly terminated, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f Output Settling Time (tST) (to 0.025%) 11 ns Output Propagation Delay1 (tPD) 17 ns Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) 0.8 ns Output Noise (I

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

Two-Tone Intermodulation (IMD) to Nyquist (f

Total Harmonic Distortion (THD)

Signal-to-Noise Ratio (SNR)

Adjacent Channel Power Ratio (ACPR)

Four-Tone Intermodulation

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 70 MHz

Propagation delay is delay from the CLK+/CLK− input to the DAC update.

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

) 400 MSPS

DAC

= 20 mA) 50 pA√Hz

OUTFS

= 0 dBFS)

OUT

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 65 MSPS; f

DATA

= 78 MSPS; f

DATA

= 65 MSPS; f

DATA

= 100 MSPS; f

DATA

= 1.01 MHz 82 dBc

OUT

= 10.01 MHz 75 dBc

OUT

= 25.01 MHz 73 dBc

OUT

= 5.02 MHz 82 dBc

OUT

= 20.02 MHz 75 dBc

OUT

= 50.02 MHz 65 dBc

OUT

= f

OUT1

= 5.01 MHz; f

OUT1

= 15.01 MHz; f

OUT1

= 24.1 MHz; f

OUT1

= 10.02 MHz; f

OUT1

= 30.02 MHz; f

OUT1

= 48.2 MHz; f

OUT1

= 1.0 MHz; 0 dBFS −80 dB

OUT

= 10.01 MHz; 0 dBFS −74 dB

OUT

= 16.26 MHz; 0 dBFS 71 dB

OUT

= 25.1 MHz; 0 dBFS 71 dB

OUT

= 6.01 MHz 85 dBc

OUT2

= 17.51 MHz 75 dBc

OUT2

= 26.2 MHz 68 dBc

OUT2

= 12.02 MHz 85 dBc

OUT2

= 35.02 MHz 70 dBc

OUT2

= 52.4 MHz 65 dBc

OUT2

= −6 dBFS)

OUT2

= 20 mA, differential transformer-coupled

OUTFS

0.8 ns

WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing

IF = 16 MHz, f IF = 32 MHz, f

= 65.536 MSPS 78 dBc

DATA

= 131.072 MSPS 68 dBc

DATA

15.6 MHz, 15.8 MHz, 16.2 MHz, and 16.4 MHz at −12 dBFS 88 dBFS f

= 65 MSPS, Missing Center

DATA

68.1 MHz, 69.3 MHz, 71.2 MHz, and 72.0 MHz at −20 dBFS 77 dBFS f

= 52 MSPS, f

DATA

= 208 MHz

DAC

Rev. C | Page 6 of 40

Page 7

AD9772A

DIGITAL SPECIFICATIONS

to T

MIN

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current Logic 0 Current −10 +10 µA Input Capacitance 5 pF

CLOCK INPUTS

Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V

PLL CLOCK ENABLED (SEE Figure 2)

Input Setup Time (tS)

Input Hold Time (tH)

Latch Pulse Width (t

PLL CLOCK DISABLED (SEE Figure 3)

Input Setup Time (tS)

Input Hold Time (tH)

Latch Pulse Width (t CLK+/CLK− to PLLLOCK Delay (tOD)

PLLLOCK (VOH), TA = 25°C 3.0 V PLLLOCK (VOL), TA = 25°C 0.3 V

MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 A.

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

−10 +10 µA

TA = 25°C 1.5 ns TA = −40 to +85°C 2.1 ns

TA = 25°C 1.3 ns TA = −40 to +85°C 1.6 ns

), TA = 25°C 1.5 ns

LPW

TA = 25°C −0.7 ns TA = −40 to +85°C −0.4 ns

TA = 25°C 3.3 ns TA = −40 to +85°C 3.7 ns

), TA = 25°C 1.5 ns

LPW

TA = 25°C 1.9 2.8 ns TA = −40 to +85°C 1.8 3.3 ns

DB0 TO DB13

CLK+ – CLK–

OUTA

OUTB

LPW

0.025%

Figure 2. Timing Diagram—PLL Clock Multiplier Enabled

DB0 TO DB13

CLK+ – CLK–

02253-002

Rev. C | Page 7 of 40

LPW

0.025%

PLLLOCK

OUTA

OUTB

Figure 3. Timing Diagram—PLL Clock Multiplier Disabled

0.025%

02253-003

Page 8

AD9772A

DIGITAL FILTER SPECIFICATIONS

to T

MIN

50 Ω doubly terminated, unless otherwise noted.

Table 4.

Parameter Min Typ Max Unit

MAXIMUM INPUT DATA RATE (f DIGITAL FILTER CHARACTERISTICS

Pass-Bandwidth1: 0.005 dB 0.401 f Pass-Bandwidth: 0.01 dB 0.404 f Pass-Bandwidth: 0.1 dB 0.422 f

Pass-Bandwidth: −3 dB 0.479 f LINEAR PHASE (FIR IMPLEMENTATION) STOP BAND REJECTION 73 dB

0.606 f GROUP DELAY IMPULSE RESPONSE DURATION

−40 dB 36 Input clocks

−60 dB 42 Input clocks

Excludes sin(x)/x characteristic of DAC.

Defined as the number of data clock cycles between impulse input and peak of output response.

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

) 150 MSPS

DATA

to 1.394 f

OUTPUT (dB)

–100

–120

–140

CLOCK

–20

–40

–60

–80

CLOCK

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY (DC TO

DATA

)

1.00. 1

2253-004

Figure 4. FIR Filter Frequency Response—Baseband Mode

1.0

0.8

0.6

0.4

0.2

NORMALIZE D OUTPUT

–0.2

–0.4

10 15 20 25 30 35 40 45

TIME (Samples)

02253-005

Figure 5. FIR Filter Impulse Response—Baseband Mode

= 20 mA, differential transformer-coupled output,

OUTFS

OUT/fDATA

11 Input clocks

Table 5. Integer Filter Coefficients for Interpolation Filter (43-Tap Half-Band FIR Filter)

Lower Coefficient

Upper Coefficient

Integer Value

H(1) H(43) 10 H(2) H(42) 0 H(3) H(41) −31 H(4) H(40) 0 H(5) H(39) 69 H(6) H(38) 0 H(7) H(37) −138 H(8) H(36) 0 H(9) H(35) 248 H(10) H(34) 0 H(11) H(33) −419 H(12) H(32) 0 H(13) H(31) 678 H(14) H(30) 0 H(15) H(29) −1083 H(16) H(28) 0 H(17) H(27) 1776 H(18) H(26) 0 H(19) H(25) −3282 H(20) H(24) 0 H(21) H(23) 10,364 H(22) 16,384

Rev. C | Page 8 of 40

Page 9

AD9772A

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter With Respect to Rating

AVDD, DVDD, CLKVDD,

PLLVDD

AVDD, DVDD, CLKVDD,

PLLVDD

ACOM, DCOM,

CLKCOM, PLLCOM

REFIO, REFLO, FSADJ,

SLEEP

, I

OUTA

OUTB

DB0 to DB13, MOD0,

MOD1, PLLLOCK

CLK+, CLK− CLKCOM

DIV0, DIV1, RESET CLKCOM

LPF PLLCOM

Junction Temperature 125°C Storage Temperature −65°C to +150°C Lead Temperature

(10 sec)

ACOM, DCOM, CLKCOM, PLLCOM

AVDD, DVDD, CLKVDD, PLLVDD

ACOM, DCOM, CLKCOM, PLLCOM

ACOM

DCOM

300°C

−0.3 V to +4.0 V

−4.0 V to +4.0 V

−0.3 V to +0.3 V

−0.3 V to AVDD + 0.3 V

−1.0 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−0.3 V to CLKVDD + 0.3 V

−0.3 V to PLLVDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θ

48-Lead LQFP 91 28 °C/W

Unit

ESD CAUTION

Rev. C | Page 9 of 40

Page 10

AD9772A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

ACOM

AD9772A

TOP VIEW

(Not to Scale)

DB1

MOD0

(LSB) DB0

MOD1

OUTAIOUTB

ACOM

FSADJ

REFIO

REFLOACOM

SLEEP

LPF

PLLVDD

PLLCOM

CLKVDD

CLKCOM

CLK–

CLK+

DIV0

DIV1

RESET

PLLLOCK

DVDD

DCOM

2253-006

DCOM

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

(MSB) DB13

NC = NO CONNECT

DVDD

48 47 46 45 44 39 38 3743 42 41 40

PIN 1 IDENTIFIER

13 14 15 16 17 18 19 20 21 22 23 24

DB3

DB2

Figure 6. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 19, 20 DCOM Digital Common. 3 DB13 Most Significant Data Bit (MSB). 4 to 15 DB12 to DB1 Data Bit 1 to Data Bit 12. 16 DB0 Least Significant Data Bit (LSB). 17 MOD0

Digital High-Pass Filter Response. Active high. This pin invokes the digital high-pass filter response (that is, half-wave digital mixing mode). Note that quarter-wave digital mixing occurs if this pin and the MOD1 pin are set high.

18 MOD1

Zero-Stuffing Mode. Active high. This pin invokes zero-stuffing mode. Note that quarter-wave digital mixing

occurs if this pin and the MOD0 pin are set high. 23, 24 NC No Connect. Leave open. 21, 22, 47, 48 DVDD Digital Supply Voltage (3.1 V to 3.5 V). 25 PLLLOCK

Lock Signal of the Phase-Lock Loop. This pin provides the lock signal of the phase-lock loop when the PLL

clock multiplier is enabled, and provides the 1× clock output when the PLL clock multiplier is disabled. High

indicates that PLL is locked to the input clock. The maximum fanout is 1 (that is, <10 pF). 26 RESET

Internal Divider Reset. This pin can reset the internal driver to synchronize the internal 1× clock to the input

data and/or multiple AD9772A devices. The reset is initiated if this pin is momentarily brought high when

PLL is disabled. 27, 28 DIV1, DIV0 PLL Prescaler Divide Ratio. DIV1 and DIV0 set the prescaler divide ratio of the PLL (refer to Tabl e 10 ). 29 CLK+ Noninverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2). 30 CLK− Inverting Input to Differential Clock. Bias this pin to the midsupply (that is, CLKVDD/2). 31 CLKCOM Clock Input Common. 32 CLKVDD Clock Input Supply Voltage (3.1 V to 3.5 V). 33 PLLCOM Phase-Lock Loop Common. 34 PLLVDD

Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable the PLL clock multiplier, connect PLLVDD to

PLLCOM. 35 LPF

PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than

10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated in

Figure 61. 36 SLEEP Power-Down Control Input. Active high. When this pin is not used, connect it to ACOM. 37, 41, 44 ACOM Analog Common. 38 REFLO

Reference Ground When Internal 1.2 V Reference Is Used. Connect this pin to AVDD to disable the internal reference.

Rev. C | Page 10 of 40

Page 11

AD9772A

Pin No. Mnemonic Description

39 REFIO

40 FSADJ Full-Scale Current Output Adjust. 42 I 43 I

B Complementary DAC Current Output. Full-scale current is selected when all data bits are 0s.

OUTB

OUTA

45, 46 AVDD Analog Supply Voltage (3.1 V to 3.5 V).

Reference Input/Output. This pin serves as the reference input when the internal reference is disabled (that is, when REFLO is tied to AVDD), or it serves as the 1.2 V reference output when the internal reference is activated (that is, when REFLO is tied to ACOM). If the internal reference is activated, a 0.1 µ F capacitor to ACOM is required.

DAC Current Output. Full-scale current is selected when all data bits are 1s.

Rev. C | Page 11 of 40

Page 12

AD9772A

TERMINOLOGY

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual analog output from the ideal output and is determined by a straight line drawn from zero to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale that is associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

Offset error is the deviation of the output current from the ideal of zero. For I 0s. For I

OUTB

, 0 mA output is expected when the inputs are all

OUTA

, 0 mA output is expected when all inputs are set to 1s. B

Gain Error

Gain error is the difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Tem p er at u re Dr i ft

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

. For offset

MAX

and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

Power Supply Rejection

Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time

Settling time is the time required for the output to reach and remain within a specified error band about its final value. It is measured from the start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

Spurious-free dynamic range is the difference, in decibels, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Pass Band

Pass band is the frequency band in which any input applied therein passes unattenuated to the DAC output.

Stop-Band Rejection

Stop-band rejection is the amount of attenuation of a frequency outside the pass band applied to the DAC relative to a full-scale signal applied at the DAC input within the pass band.

Group Delay

Group delay is the number of input clocks between an impulse applied at the device input and the peak DAC output current.

Impulse Response

Impulse response is the response of the device to an impulse applied to the input.

Adjacent-Channel Power Ratio (ACPR)

ACPR is a ratio, in dBc, between the measured power within a channel relative to its adjacent channel.

Rev. C | Page 12 of 40

Page 13

AD9772A

FROM HP8644A SIGNAL GENERATOR

AWG2021

DG2020

EXTERNAL CLOCK

DIGITAL

DATA

1kΩ

CLKVDD

CLKCOM

CLK+

CLK–

SLEEP

3.3V

1×

EDGE-

TRIGGERED

LATCHES

AD9772A

1×/2×

INTERPOLATION

CH1

CH2

MOD0

CLOCK DISTRI BUTION

AND MODE SELECT FILTER

CONTROL

2× FIR

FILTER

CONTROL

HP8130

PULSE GENERAT OR

EXTERNAL INPUT

MOD1

RESET

PLLLOCK

MUX

2×/4×

ZERO

STUFF

MUX

1.2V REFERENCE

AND CONTROL AMP

REFLOAVDDACOMDVDDDCOM

DIV0

DIV1

PLLCLOCK

MULTIPLIER

14-BIT DAC

PLLCOM

LPF

PLLVDD

OUTA

OUTB

REFIO

FSADJ

0.1µF

1.91kΩ

50Ω

MINI-CIRCUIT S

T1-1T

100Ω

20pF

TO FSEA30 SPECTRUM ANALYZER

20pF50Ω

3.3V3.3V

02253-007

Figure 7. Basic AC Characterization Test Setup

Rev. C | Page 13 of 40

Page 14

AD9772A

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.3 V, CLKDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

= 20 mA. PLL disabled.

OUTFS

IN-BAND OUT-OF-BAND

–20

–40

–60

AMPLITUDE (dBm)

–80

–100

40 60 80 100

(MHz)

OUT

Figure 8. Single-Tone Spectral Characteristics @ f

0dBFS

–6dBFS

–12dBFS

SFDR (dBc)

= 65 MSPS with f

DATA

IN-BAND OUT-OF-BAND

–20

–40

–60

AMPLITUDE (d Bm)

–80

120200

02253-008

= f

OUT

DATA

–100

50 100

(MHz)

OUT

Figure 11. Single-Tone Spectral Characteristics @ f

SFDR (dBc)

–6dBFS

–12dBFS

0dBFS

= 78 MSPS with f

DATA

OUT

1500

02253-011

= f

DATA

Figure 9. In-Band SFDR vs. f

SFDR (dBc)

0dBFS

–12dBFS

–6dBFS

Figure 10. Out-of-Band SFDR vs. f

OUT

(MHz)

OUT

(MHz)

@ f

OUT

= 65 MSPS

DATA

20 25105

@ f

DATA

3015020105

2253-009

30150

2253-010

= 65 MSPS

Figure 12. In-Band SFDR vs. f

–6dBFS

0dBFS

AMPLITUDE (dBm)

5101520253035

–12dBFS

Figure 13. Out-of-Band SFDR vs. f

OUT

(MHz)

OUT

20 25105

@ f

DATA

@ f

OUT

= 78 MSPS

DATA

30150

02253-012

2253-013

Rev. C | Page 14 of 40

Page 15

AD9772A

IN-BAND

OUT-OF-

BAND

–6dBFS

–20

–40

AMPLITUDE (dBm)

–60

–80

–100

100 150 200 250

(MHz)

OUT

Figure 14. Single-Tone Spectral Characteristics @ f

= f

OUT

DATA

–6dBFS

with f

)

UDE (

AMPLI

0dBFS

–12dBFS

= 160 MSPS

DATA

–3dBFS

IMD (dBc)

300500

02253-014

Figure 17. Third-Order IMD Products vs. f

IMD (dBc)

0dBFS

5 1015202530

0dBFS

OUT

(MHz)

–6dBFS

@ f

OUT

–3dBFS

= 65 MSPS

DATA

2253-017

10 20 30 40 50 60

Figure 15. In-Band SFDR vs. f

–6dBFS

AMPLITUDE ( dBm)

–12dBFS

10 20 30 40 50 60 70

Figure 16. Out-of-Band SFDR vs. f

OUT

(MHz)

OUT

0dBFS

(MHz)

OUT

@ f

= 160 MSPS

DATA

= 160 MSPS

DATA

5 1015202530

2253-015

Figure 18. Third-Order IMD Products vs. f

IMD (dBc)

10 20 30 40 50 60 70

2253-016

Figure 19. Third-Order IMD Products vs. f

(MHz)

OUT

@ f

OUT

DATA

–6dBFS

–3dBFS

0dBFS

(MHz)

OUT

@ f

OUT

= 160 MSPS

DATA

= 78 MSPS

02253-018

2253-019

Rev. C | Page 15 of 40

Page 16

AD9772A

IMD (dBc)

DATA

= 65MSPS

DATA

= 160MSPS

= 78MSPS

DATA

IMD (dBc)

0dBFS

–3dBFS

–6dBFS

–20

–15

–10 0–5

(dBFS)

OUT

Figure 20. Third-Order IMD Products vs. A

= 160MSPS

DATA

–10 –5 0–15

(dBFS)

OUT

IMD (dBc)

–20

Figure 21. Third-Order IMD Products vs. A

DATA

OUT

DATA

@ f

= 78MSPS

= 65MSPS

@ f

OUT

= f

DAC

/11

02253-020

Figure 23. Third-Order IMD Products vs. AVDD @ f

SNR (dBc)

02253-021

3.1 3.2 3.4 3.5

PLL OFF

PLL ON, OPTIMUM DIV0/DIV1 SETTINGS

Figure 24. SNR vs. f

= 320 MSPS

DAC

AVDD (V)

DAC

125 175

(MHz)

@ f

= 10 MHz

OUT

= 10 MHz,

OUT

3.63.33.0

02253-023

2253-024

SFDR (dBc)

Figure 22. SFDR vs. AVDD @ f

–3dBFS

0dBFS

3.1 3.2 3.4 3.5

AVDD (V)

= 10 MHz, f

OUT

–6dBFS

= 320 MSPS

DAC

3.63.33.0

02253-022

Rev. C | Page 16 of 40

SFDR (dBc)

–40

Figure 25. In-Band SFDR vs. Temperature @ f

DATA

= 78MSPS

= 160MSPS

DATA

08–20

TEMPERATURE (° C)

= 65MSPS

DATA

20 40 60

OUT

= f

02253-025

/11

DATA

Page 17

AD9772A

THEORY OF OPERATION

FUNCTIONAL DESCRIPTION

Figure 26 shows a simplified block diagram of the AD9772A. The AD9772A is a complete 2× oversampling, 14-bit DAC that includes a 2× interpolation filter, a phase-locked loop (PLL) clock multiplier, and a 1.20 V band gap voltage reference. Although the AD9772A digital interface can support input data rates as high as 160 MSPS, its internal DAC can operate up to 400 MSPS, thus providing direct IF conversion capabilities. The 14-bit DAC provides two complementary current outputs whose full-scale current is determined by an external resistor. The AD9772A features a flexible, low jitter differential clock input, providing excellent noise rejection while accepting a sine wave input. An on-chip PLL clock multiplier produces all of the necessary synchronized clocks from an external reference clock source. Separate supply inputs are provided for each functional block to ensure optimum noise and distortion performance. A sleep mode is also included for power savings.

CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0

CLK+

CLK–

DATA

INPUTS

(DB13 TO

DB0)

SLEEP

AD9772A

EDGE-

TRIGGERED

LATCHES

DCOM DVDD ACOM AVDD REFLO

Figure 26. Simplified Functional Block Diagram

CLOCK DIST RIBUTIO N

AND MODE SEL ECT

FILTER

1× /2×1×

CONTROL

2× FIR

INTER-

POLATION

FILTER

CONTROL

MUX

2× /4×

ZERO

STUFF

MUX

1.2V REFERENCE

AND CONTROL AMP

DIV1

PLL CLOCK MULTIPLIER

14-BIT DAC

PLLCOM

LPF

PLLVDD

OUTA

OUTB

REFIO

FSADJ

Preceding the 14-bit DAC is a 2× digital interpolation filter that can be configured for a low-pass (that is, baseband mode) or high-pass (that is, direct IF mode) response. The input data is latched into the edge-triggered input latches on the rising edge of the differential input clock, as shown in

Figure 2, and then interpolated by a factor of 2 by the digital filter. For traditional baseband applications, the 2× interpolation filter has a low-pass response. For direct IF applications, the filter response can be converted into a high-pass response to extract the higher image. The output data of the 2× interpolation filter can update the 14-bit DAC directly or undergo a zero-stuffing process to increase the DAC update rate by another factor of 2. This action enhances the relative signal level and pass-band flatness of the higher frequency images.

DIGITAL MODES OF OPERATION

The AD9772A features four modes of operation controlled by the digital inputs, MOD0 and MOD1. MOD0 controls the 2× digital filter response (that is, low-pass or high-pass), and MOD1 controls the zero-stuffing option. The appropriate mode to select (see requires the reconstruction of a baseband or IF signal.

Tabl e 9) depends on whether the application

02253-026

Table 9. Digital Modes

Digital Mode

MOD0 MOD1

Digital Filter

ZeroStuffing

Baseband 0 0 Low No Baseband 0 1 Low Yes Direct IF 1 0 High No Direct IF 1 1 High Yes

For applications requiring the highest dynamic range over a wide bandwidth, users should consider operating the AD9772A in a baseband mode. Although the zero-stuffing option can be used in this mode, the ratio of the signal to the image power will be reduced.

For applications requiring the synthesis of IF signals, users should consider operating the AD9772A in a direct IF mode. In this case, the zero-stuffing option should be considered when synthesizing and selecting IFs beyond the input data rate, f If the reconstructed IF falls below f

, the zero-stuffing option

DATA

may or may not be beneficial. Note that the dynamic range (that is, SNR/SFDR) can be optimized by disabling the PLL clock multiplier (that is, by connecting PLLVDD to PLLCOM) and by using an external low-jitter clock source operating at the DAC update rate, f

DAC

2× Interpolation Filter Description

The 2× interpolation filter is based on a 43-tap, half-band, symmetric FIR topology that can be configured for a low- or high-pass response, depending on the state of the MOD0 control input. The low-pass response is selected with MOD0 low, and the high-pass response is selected with MOD0 high. The low-pass frequency and the impulse response of the halfband interpolation filter are shown in and the idealized filter coefficients are listed in

Figure 4 and Figure 5,

Tabl e 5. Note that the impulse response of a FIR filter is also represented by its idealized filter coefficients.

The 2× interpolation filter essentially multiplies the input data rate to the DAC by a factor of 2, relative to its original input data rate, while reducing the magnitude of the first image associated with the original input data rate occurring at f

DATA

− f

FUNDAMENTAL

. As a result of the 2× interpolation, the digital filter frequency response is uniquely defined over its Nyquist zone of dc to f

, with mirror

DATA

images occurring in adjacent Nyquist zones.

The benefits of an interpolation filter are clearly seen in Figure 27, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to the 2× digital interpolation filter in a low-pass configuration. Images of the sine wave signal appear around multiples of the input data rate (that is, f

) of the DAC,

DATA

as predicted by sampling theory. These undesirable images also appear at the output of a reconstruction DAC, although they are attenuated by the sin(x)/x roll-off response of the DAC.

Rev. C | Page 17 of 40

Page 18

AD9772A

In many band-limited applications, the images from the reconstruction process must be suppressed by an analog filter following the DAC. The complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression. Adding to the complexity of this analog filter is the requirement of compensating for the sin(x)/x response of the DAC.

Referring to

Figure 27, the new first image associated with the higher data rate of the DAC after interpolation is pushed out further relative to the input signal, because it now occurs at 2× f

DATA

− f

FUNDAMENTAL

. The old first image associated with the lower DAC data rate before interpolation is suppressed by the digital filter. As a result, the transition band for the analog reconstruction filter is increased, thus reducing the complexity of the analog filter. Furthermore, the value of the sin(x)/x rolloff divided by the original input data pass band (that is, dc to f

/2) is significantly reduced.

DATA

As previously mentioned, the 2× interpolation filter can be converted into a high-pass response, thus suppressing the fundamental while passing the original first image occurring at f

DATA

− f

FUNDAMENTAL

. Figure 28 shows the time and frequency

TIME

DOMAIN

representation for a high-pass response of a discrete time sine wave. This action can also be modeled as a half-wave digital mixing process in which the impulse response of the low-pass filter is digitally mixed with a square wave having a frequency of exactly f value of 0 (see

/2. Because the even coefficients have an integer

DATA

Table 5 ), this process simplifies into inverting the center coefficient of the low-pass filter (that is, inverting H(18)). Note that this also corresponds to inverting the peak of the impulse response shown in

Figure 4. The resulting high-pass frequency response becomes the frequency inverted mirror image of the low-pass filter response shown in

Note that the new first image occurs at f reduced transition region of 2 × f selection, thus mandating that the f

FUNDAMENTAL

Figure 5.

+ f

DATA

FUNDAMENTAL

exists for image

be placed

. A

sufficiently high for practical filtering purposes in direct IF applications. In addition, the lower sideband images occurring at f

− f

DATA

FUNDAMENTAL

) experience a frequency inversion while the upper sideband images occurring at f (that is, N × f

1/ 2 ×

DATA

and its multiples (that is, N × f

+ f

DATA

+ f

FUNDAMENTAL

) do not.

FUNDAMENTAL

−

DATA

and its multiples

DATA

FUNDAMENTAL

FREQUENCY

DOMAIN

FIRST IMAGE

DATA

INPUT DATA

LATCH

DATA

2 ×

DATA

FUNDAMENTAL

SUPPRESSED

FIRST IMAGE

DIGITAL

FILTER

RESPONSE

DATA

2× INTERPOLATION

FILTER

2 ×

2×

DATA

NEW

FIRST IMAGE

2 ×

DATA

DAC SIN(x)/x

RESPONSE

DATA

Figure 27. Time and Frequency Domain Example of Low-Pass 2× Digital Interpolation Filter

1/2 ×

DATA

FILTER

2×

DATA

DIGITAL

FILTER

RESPONSE

2 ×

DATA

DAC SIN(x)/x

RESPONSE

DATA

TIME

DOMAIN

FUNDAMENTAL

FREQUENCY

DOMAIN

DATA

INPUT DATA

LATCH

FIRST IMAGE

DATA

2 ×

DATA

SUPPRESSED

LOWER IMAGE

FUNDAMENTAL

2× INTERPO LATIO N

UPPER AND

2 ×

DAC

2 ×

DAC

DATA

02253-027

DATA

2 ×

DATA

02253-028

Figure 28. Time and Frequency Domain Example of High-Pass 2× Digital Interpolation Filter

Rev. C | Page 18 of 40

Page 19

AD9772A

Zero-Stuffing Option Description

As shown in Figure 29, a zero or null in the frequency response (after interpolation and DAC reconstruction) occurs at the final DAC update rate (that is, 2× f

) due to the inherent sin(x)/x

DATA

roll-off response of the DAC. In baseband applications, this rolloff in the frequency response may not be as problematic because much of the desired signal energy remains below f

/2 and the amplitude variation is not as severe. However, in

DATA

direct IF applications interested in extracting an image above f

/2, this roll-off may be problematic due to the increased

DATA

pass-band amplitude variation as well as the reduced signal level of the higher images.

WITH

–10

WITHOUT

BASEBAND

REGION

ZERO-STUFFING

FREQUENCY (

–20

ROLL-O FF (dBF S)

–30

–40

Figure 29. Effects of Zero-Stuffing on the Sin(x)/x Response of the DAC

ZERO-STUFFING

3.0

)

DATA

3.5

4.00.5 1.0 1.5 2.0 2. 5

02253-029

For instance, if the digital data into the AD9772A represents a baseband signal centered around f f

/10, the reconstructed baseband signal output from the

DATA

/4 with a pass band of

DATA

AD9772A experiences only a 0.18 dB amplitude variation over its pass band, with the first image occurring at 7/4 × f

DATA

and exhibiting 17 dB of attenuation relative to the fundamental. However, if the high-pass filter response is selected, the AD9772A produces pairs of images at [(2N + 1) × f

DATA

] ± f

/4, where

DATA

N = 0, 1, and so on. Note that due to the sin(x)/x response of the DAC, only the lower or upper sideband images centered around f

may be useful, although they are attenuated by −2.1 dB and

DATA

−6.54 dB and have a pass-band amplitude roll-off of 0.6 dB and

1.3 dB, respectively.

To improve on the pass-band flatness of the desired image and/or to extract higher images (that is, 3 × f

DATA

± f

FUNDAMENTAL

), the zero-stuffing option should be employed by bringing the MOD1 pin high. This option increases the effective DAC update rate by another factor of 2 because a midscale sample (that is, 10 0000 0000 0000) is inserted after every data sample originating from the 2× interpolation filter. A digital multiplexer switching at a rate of 4 × f

between the interpolation filter

DATA

output and a data register containing the midscale data sample is used as shown in

Figure 28 to implement this option. Therefore, the DAC output is now forced to return to its differential midscale current value (that is, I

OUTA

− I

at 0 mA) after reconstructing

OUTB

each data sample from the digital filter.

Rev. C | Page 19 of 40

The net effect is to increase the DAC update rate such that the zero in the sin(x)/x frequency response occurs at 4 × f

DATA

accompanied by a corresponding reduction in output power as shown in

Figure 29. Note that if the high-pass response of the 2× interpolation filter is also selected, this action can be modeled as a quarter-wave digital mixing process, because this is equivalent to digitally mixing the impulse response of the low-pass filter with a square wave having a frequency of exactly f

DATA

(that is, f

DAC

/4).

It is important to realize that the zero-stuffing option by itself does not change the location of the images, but rather changes their signal level, amplitude flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the lower and upper sideband images centered around f

are improved to 0.14 dB and 0.24 dB, respectively,

DATA

while the signal level changes to −6.5 dBFS and −7.5 dBFS. The lower or upper sideband image centered around 3 × f

DATA

exhibit an amplitude flatness of 0.77 dB and 1.29 dB with signal levels of approximately −14.3 dBFS and −19.2 dBFS.

PLL CLOCK MULTIPLIER OPERATION

The phase-lock loop (PLL) clock multiplier circuitry, along with the clock distribution circuitry, can produce the necessary internally synchronized 1×, 2×, and 4× clocks for the edgetriggered latches, 2× interpolation filter, zero-stuffing multiplier, and DAC. diagram of the PLL clock multiplier, which consists of a phase detector, a charge pump, a voltage controlled oscillator (VCO), a prescaler, and digital control input/output. The clock distribution circuitry generates all the internal clocks for a given mode of operation. The charge pump and VCO are powered from PLLVDD, and the differential clock input buffer, phase detector, prescaler, and clock distribution circuitry are powered from CLKVDD. To ensure optimum phase noise performance from the PLL clock multiplier and clock distribution circuitry, PLLVDD and CLKVDD must originate from the same clean analog supply.

CLKVDD

PLLLOCK

OUT1×

CLOCK

DISTRI BUTION

CLKCOM

MOD1

Figure 30. Clock Multiplier with PLL Clock Multiplier Enabled

Figure 30 shows a functional block

CLK+

CLK–

–+

PHASE

DETECTOR

EXT/INT

CLOCK CONTRO L

PRESCALER

MOD0

RESET

DIV1

CHARGE

DIV0

AD9772A

PUMP

VCO

LPF

PLLVDD

PLLCOM

DNC

2.7V TO

3.6V

02253-030

Page 20

AD9772A

The PLL clock multiplier has two modes of operation. It can be enabled for less demanding applications, providing a reference clock meeting the minimum specified input data rate of 6 MSPS. Alternatively, it can be disabled for applications below this data rate or for applications requiring higher phase noise performance. In this case, a reference clock must be provided at twice the input data rate (that is, 2 × f or at four times the input data rate (that is, 4 × f

) without the zero-stuffing option selected

DATA

) with the zero-

DATA

stuffing option selected. Note that multiple AD9772A devices can be synchronized in either mode if driven by the same reference clock because the PLL clock multiplier, when enabled, ensures synchronization. RESET can be used for synchronization if the PLL clock multiplier is disabled.

Figure 30 shows the proper configuration used to enable the PLL clock multiplier. In this case, the external clock source is applied to CLK+ (and/or CLK−) and the PLL clock multiplier is fully enabled by connecting PLLVDD to CLKVDD.

The settling/acquisition time characteristics of the PLL are also dependent on the divide-by-N ratio as well as the input data rate. In general, the acquisition time increases with increasing data rate (for fixed divide-by-N ratio) or with an increasing divide-by-N ratio (for fixed input data rate).

Because the VCO can operate over a 96 MHz to 400 MHz range, the prescaler divide-by-ratio following the VCO must be set according to

) to ensure optimum phase noise and successful locking. In

DATA

Tabl e 10 for a given input data rate (that is,

general, the best phase noise performance for any prescaler setting is achieved with the VCO operating near its maximum output frequency of 400 MHz. Note that the divide-by-N ratio also depends on whether the zero-stuffing option is enabled because this option requires the DAC to operate at 4× the input data rate. The divide-by-N ratio is set by DIV1 and DIV0.

With the PLL clock multiplier enabled, PLLLOCK serves as an active high control output that can be monitored upon system power-up to indicate that the PLL is successfully locked to the input clock. Note that when the PLL clock multiplier is not locked, PLLLOCK toggles between logic high and low in an asynchronous manner until locking is finally achieved. As a result, it is recommended that PLLLOCK, if monitored, be sampled several times to detect proper locking 100 ms after power-up.

As previously stated, applications requiring input data rates below 6 MSPS must disable the PLL clock multiplier and provide an external reference clock. However, for applications already containing a low phase noise (that is, low jitter) reference clock that is twice (or four times) the input data rate, users should consider disabling the PLL clock multiplier to achieve the best SNR performance from the AD9772A. Note that the SFDR performance and wideband noise performance of the AD9772A remain unaffected with or without the PLL clock multiplier enabled.

The effects of phase noise on the AD9772A SNR performance become more noticeable at higher reconstructed output frequencies and signal levels. of a full-scale sine wave at exactly f

Figure 31 compares the phase noise

/4 for different data rates

DATA

(and therefore carrier frequencies) with the optimum DIV1 and DIV0 settings. The effects of phase noise, and its effect on a signal’s CNR performance, become even more evident at higher IF frequencies, as shown in

Figure 32. In both instances, it is the

narrow-band phase noise that limits the CNR performance.

–10

–20

–30

–40

–50

PLL ENABLED,

–60

–70

–80

NOISE DENSITY (dBm/Hz)

–90

–100

PLL ENABLED,

–110

Figure 31. Phase Noise of PLL Clock Multiplier with a Full-Scale Sine Wave at

Exactly f

= f

/4 for Different f

OUT

DATA

Settings Using the Rohde & Schwarz FSEA30, RBW = 30 kHz

–10

–30

–50

= 160MSPS

DATA

PLL ENABLED,

= 50MSPS

DATA

1234

FREQUENCY OF FSET (M Hz)

DATA

= 100MSPS

DATA

= 75MSPS

DATA

PLL ENABLED,

Settings with Optimum DIV0/DIV1

DATA

= 50MSPS

02253-031

Table 10. Recommended Prescaler Divide-by-N Ratio Settings

DATA

(MSPS)

MOD1 DIV1 DIV0 Divide-by-N Ratio

48 to 160 0 0 0 1 24 to 100 0 0 1 2 12 to 50 0 1 0 4 6 to 25 0 1 1 8 24 to 100 1 0 0 1 12 to 50 1 0 1 2 6 to 25 1 1 0 4 3 to 12.5 1 1 1 8

Rev. C | Page 20 of 40

–70

AMPLITUDE (dBm)

–90

–110

120

Figure 32. Direct IF Mode Reveals Phase Noise Degradation with and

Without PLL Clock Multiplier (IF = 125 MHz and f

122 1 24 126 128 130

FREQUENCY (MHz )

= 100 MSPS)

DATA

To disable the PLL clock multiplier, connect PLLVDD to PLLCOM as shown in

Figure 33. LPF can then remain open

because this portion of the PLL circuitry is disabled. The

2253-032

Page 21

AD9772A

differential clock input should be driven with a reference clock that is twice the data input rate in baseband applications, or that is four times the data input rate in direct IF applications in which the quarter-wave mixing option is employed (that is, MOD1 and MOD0 active high). The clock distribution circuitry remains enabled, providing a 1× internal clock at PLLLOCK. Digital input data is latched into the AD9772A on every other rising edge of the differential clock input. The rising edge that corresponds to the input latch immediately precedes the rising edge of the 1× clock at PLLLOCK. Adequate setup and hold times for the input data, as shown in

Figure 3, should be allowed. Note that enough delay is present between CLK+/CLK− and the data input latch to cause the minimum setup time for input data to be negative. This is noted in the Digital Filter Specifications section. PLLLOCK contains a relatively weak driver output, with its output delay (t

) sensitive to output capacitance loading. Therefore, PLLLOCK should be buffered for fanouts greater than 1 and/or for load capacitance greater than 10 pF. If a data timing issue exists between the AD9772A and its external driver device, the 1× clock appearing at PLLLOCK can be inverted via an external gate to ensure proper setup and hold time.

CLK–

CLK+

CLKVDD

PLLLOCK

–+

AD9772A

OUT1×

CLKCOM

CLOCK

DISTRIBUTI ON

MOD0 RESET

MOD1

PHASE

DETECTOR

EXT/INT

CLOCK CONTRO L

PRESCALER

DIV1 DIV 0

CHARGE

PUMP

VCO

LPF

PLLVDD

PLLCOM

Figure 33. Clock Multiplier with PLL Clock Multiplier Disabled

SYNCHRONIZATION OF CLOCK/DATA USING RESET WITH PLL DISABLED

The relationship between the internal and external clocks in this mode is shown in data rate (2× the input data rate) must be applied to the CLK+ and CLK− inputs. Internal dividers create the internal 1× clock necessary for the input latches. With the PLL disabled, a delayed version of the 1× clock is present at the PLLLOCK pin. The DAC latch is updated on the rising edge of the external 2× clock that corresponds to the rising edge of the 1× clock. Updates to the input data should be synchronized to this rising edge as shown in

Figure 34. To ensure this synchronization, a Logic 1 should be momentarily applied to the RESET pin on power-up before CLK+/CLK− is applied. Momentarily applying a Logic 1 to the RESET pin brings the 1× clock at PLLLOCK to a Logic 1. On the next rising edge of the 2× clock, the 1× clock goes to

Figure 34. A clock at the output update

Rev. C | Page 21 of 40

02253-033

Logic 0. The following rising edge of the 2× clock causes the 1× clock to go to Logic 1 again and updates the data in both of the input latches.

DIGITAL DATA IN

EXTERNAL

2× CLOCK

DELAYED INTERNAL

1× CLOCK

LOAD-DEPENDENT ,

DELAYED 1× CLOCK

AT PLLLOCK

OR I

OUTA

OUTB

Figure 34. Internal Timing of AD9772A with PLL Disabled

DATA

LPW

DATA ENTERS INPUT LATCHES ON THIS EDGE

Figure 35 and Figure 36 illustrate the details of the RESET function timing. The RESET pin going from a high to a low logic level enables the 1× clock output generated by the PLLLOCK pin. If RESET goes low before the rising edge of the 2× clock as shown in

Figure 35, PLLLOCK goes high on the following edge of the 2× clock. If RESET goes from a high to a low logic level 600 ps or later following the rising edge of the 2× clock, as shown in

Figure 36, there is a delay of one 2× clock cycle before PLLLOCK goes high. In either case, as long as RESET remains low, PLLLOCK changes state on every rising edge of the 2× clock. As previously stated, the rising edge of the 2× clock immediately preceding the rising edge of PLLLOCK latches data into the AD9772A input latches.

[T]

CH1 2.00VΩ CH2 2.00VΩ M 10.0ns CH3 2. 00VΩ

Figure 35. RESET Timing with PLL Disabled

[T]

CH1 2.00VV CH2 2.00VV M 10.0ns CH4 1.20V CH3 2.00VΩ

Figure 36. RESET Timing with PLL Disabled and Insufficient Setup Time

EXTERNAL 1× CLOCK

PLLLOCK

RESET

EXTERNAL 2× CLOCK

PLLLOCK

RESET

02253-035

02253-036

02253-034

Page 22

AD9772A

DAC OPERATION

The 14-bit DAC, along with the 1.2 V reference and reference control amplifier, is shown in

Figure 37. The DAC consists of a large PMOS current source array capable of providing up to 20 mA of full-scale current, I

. The array is divided into 31

OUTFS

equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose values are 1/16

of an MSB current source. The remaining LSBs are binary-weighted fractions of the middle bits’ current sources. All of these current sources are switched to one of the two output nodes (that is, I

OUTA

or I

OUTB

) via the PMOS differential current switches. Implementing the middle and lower bits with current sources instead of an R-2R ladder enhances its dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of the DAC.

2.7V TO 3.6V

R 2kΩ

0.1µF

SET

REFLO AVDD

1.2V REF

REFIO

FSADJ I

REF

SEGMENTED

SWITCHES

AD9772A

250pF

INTERPOLATED

DIGITAL DATA

CURRENT

SOURCE

ARRAY

LSB

SWITCHES

ACOM

OUTA

OUTB

OUTA

OUTB

= V

OUTA

LOAD

– V

OUTB

DIFF

LOAD

Figure 37. Block Diagram of Internal DAC, 1.2 V Reference, and Reference

Control Circuits

The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, R

, as shown in Figure 37. R

SET

, in combination with both the reference control amplifier and voltage reference, REFIO, sets the reference current, I

, which

REF

is mirrored to the segmented current sources with the proper scaling factor. The full-scale current, I the value of I

REF

, is exactly 32 times

OUTFS

DAC TRANSFER FUNCTION

The AD9772A provides complementary current outputs, I

. IB

and I

OUTB

provides a near full-scale current output, I

OUTA

when all bits are high (that is, DAC CODE = 16,383), whereas I

B, the complementary output, provides no current. The

OUTB

current output appearing at I the input code and I

= (DAC CODE/16,384) × I

OUTA

= (16,383 − DAC CODE)/16,384 × I

OUTB

and can be expressed as

OUTFS

OUTA

and I

is a function of both

OUTB

(1)

OUTFS

(2)

OUTFS

where DAC CODE = 0 to 16,383 (that is, decimal representation).

As previously mentioned, I current (I (V

REFIO

), which is nominally set by a reference voltage

REF

) and an external resistor (R

OUTFS

= 32 × I

(3)

REF

is a function of the reference

OUTFS

). It can be expressed as

SET

OUTA

OUTFS

02253-037

where:

REF

= V

REFIO/RSET

(4)

The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, I should be directly connected to matching resistive loads, R that are tied to analog common, ACOM. Note that R represent the equivalent load resistance seen by I

OUTA

and I

LOAD

or I

OUTB

LOAD

can

OUTB

, as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the I

OUTA

and I

OUTB

nodes is simply

= I

× R

OUTA

= I

OUTB

× R

OUTB

Note that the full-scale value of V

(5)

LOAD

(6)

LOAD

OUTA

and V

should not

OUTB

exceed the specified output compliance range of 1.25 V to prevent signal compression. To maintain optimum distortion and linearity performance, the maximum voltages at V V

should not exceed ±500 mV p-p. B

OUTB

The differential voltage, V

= (I

DIFF

OUTA

− I

Substituting the values of I

, appearing across I

DIFF

) × R

OUTB

LOAD

OUTA

and I

OUTA

(7)

, I

OUTB

, and IB

REF

, V

DIFF

OUTA

OUTB

can be

and

is B

expressed as

= [(2 DAC CODE − 16,383)/16,384] ×

DIFF

(32 × R

LOAD/RSET

) × V

(8)

REFIO

The last two equations highlight some of the advantages of operating the AD9772A differentially. First, the differential operation helps cancel common-mode error sources, such as noise, distortion, and dc offsets, associated with I

OUTA

and I

OUTB

Second, the differential code-dependent current and subsequent voltage, V voltage output (that is, V

, is twice the value of the single- ended

DIFF

OUTA

or V

), thus providing twice the

OUTB

signal power to the load.

Note that the gain drift temperature performance for a singleended (V

OUTA

and V

OUTB

) or differential output (VB

DIFF

) of the AD9772A can be enhanced by selecting temperature tracking resistors for R

LOAD

and R

due to their ratiometric relationship,

SET

as shown in Equation 8.

REFERENCE OPERATION

The AD9772A contains an internal 1.20 V band gap reference that can easily be disabled and overridden by an external reference. REFIO serves as either an output or input, depending on whether the internal or external reference is selected. If REFLO is tied to ACOM, as shown in reference is activated, and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 μF or greater from REFIO to REFLO. If any additional loading is required, REFIO should be buffered with an external amplifier having an input bias current less than 100 nA.

Figure 38, the internal

Rev. C | Page 22 of 40

Page 23

AD9772A

ADDITIONAL

LOAD

OPTIONAL EXTERNAL

REF BUFFER

REFLO AVDD

1.2V REF

REFIO

0.1µF FSADJ

2kΩ

250pF

2.7V TO 3.6V

CURRENT

SOURCE

ARRAY

AD9772A

Figure 38. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external 1.2 V reference, such as the AD1580, can be applied to REFIO as shown in

Figure 39. The external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage to improve gain control. Note that the 0.1 μF compensation capacitor is not required because the internal reference is disabled and the high input impedance of REFIO minimizes any loading of the external reference.

2.7V TO 3.6V

REFLO AVDD

+1.2V REF

REFIO

FSADJ

AD9772A

250pF

REFERENCE

CONTROL

AMPLIFIER

CURRENT

SOURCE

ARRAY

D1580

10kΩ

REFIO

REF

SET

REFIO/RSET

Figure 39. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9772A also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I control amplifier is configured as a V-I converter, as shown in Figure 39, such that its current output, I ratio of the V Equation 4. I the proper scaling factor to set I

and an external resistor, R

REFIO

is copied to the segmented current sources with

REF

OUTFS

, is determined by the

REF

, as stated in

SET

as stated in Equation 3.

The control amplifier allows a wide (10:1) adjustment span of I

over a 2 mA to 20 mA range by setting I

OUTFS

between

REF

62.5 μA and 625 μA. The wide adjustment span of I vides several application benefits. The first benefit relates directly to the power dissipation of the AD9772A DAC, which is proportional to I

(see the Power Dissipation section).

OUTFS

The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes.

can be controlled using the single-supply circuit shown in

REF

Figure 40 for a fixed R

. In this example, the internal refer-

SET

ence is disabled, and the voltage of REFIO is varied over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply DAC or digital potentiometer, thus allowing I to be digitally controlled for a fixed R

. This particular example

SET

shows the AD5220, an 8-bit serial input digital potentiometer,

OUTFS

. The

pro-

REF

Rev. C | Page 23 of 40

along with the AD1580 voltage reference. Note that because the input impedance of REFIO does interact with and load the digital potentiometer wiper to create a slight nonlinearity in the programmable voltage divider ratio, a digital potentiometer with 10 kΩ or less resistance is recommended.

2.7V TO 3.6V

02253-038

AD1580

1.2V

10kΩ

AD5220

10kΩ

REFLO AVDD

1.2V REF

REFIO

FSADJ

AD9772A

SET

250pF

CURRENT

SOURCE

ARRAY

02253-040

Figure 40. Single-Supply Gain Control Circuit

ANALOG OUTPUTS

The AD9772A produces two complementary current outputs,

and I

OUTA

differential operation. I complementary single-ended voltage outputs, V via a load resistor, R Function differential voltage, V also be converted to a single-ended voltage via a transformer or differential amplifier configuration.

Figure 41 shows the equivalent analog output circuit of the AD9772A, which consists of a parallel combination of PMOS

02253-039

differential current switches associated with each segmented current source. The output impedance of I determined by the equivalent parallel combination of the PMOS switches and is typically 200 kΩ in parallel with 3 pF. Due to the nature of a PMOS device, the output impedance is also slightly dependent on the output voltage (that is, V to a lesser extent, the analog supply voltage, AVDD, and fullscale current, I output impedance can be a source of dc nonlinearity and ac linearity (that is, distortion), its effects can be limited if certain precautions are taken.

and I

OUTA

compliance range. The negative output compliance threshold of −1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown

, which can be configured for single-ended or

OUTB

and I

OUTA

, as described in the

LOAD

can be converted into

OUTB

OUTA

DAC Transfer

and V

OUTB

section, by using Equation 5 through Equation 8. The

, existing between V

DIFF

. Although the signal dependency of the

OUTFS

AD9772A

OUTA

LOAD

Figure 41. Equivalent Analog Output Circuit

also have a negative and positive voltage

OUTB

OUTA

and I

and V

OUTB

AVDD

OUTB

LOAD

OUTB

) and,

, can

02253-041

Page 24

AD9772A

of the output stage and affect the reliability of the AD9772A. The positive output compliance range is slightly dependent on the full-scale output current, I

. Operation beyond the

OUTFS

positive compliance range induces clipping of the output signal, which severely degrades the AD9772A linearity and distortion performance.

Operating the AD9772A with reduced voltage output swings at I

OUTA

and I

in a differential or single-ended output

OUTB

configuration reduces the signal dependency of its output impedance, thus enhancing distortion performance. Although the voltage compliance range of I

OUTA

and I

extends from

OUTB

−1.0 V to +1.25 V, optimum distortion performance is achieved when the maximum full-scale signal at I

OUTA

and I

OUTB

B does not

exceed approximately 0.5 V. Using a properly selected transformer with a grounded center tap allows the AD9772A to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at I

OUTA

and I

OUTB

. DC-coupled applications requiring a differential or singleended output configuration should size R to the

Output Configurations section for examples of various

accordingly. Refer

LOAD

output configurations.

The most significant improvement in the AD9772A distortion and noise performance is realized using a differential output configuration. The common-mode error sources of both I

can be substantially reduced by the common-mode

OUTB

and I

OUTA

rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the reconstructed waveform’s frequency content increases and/or its amplitude decreases. The distortion and noise performance of the AD9772A is also dependent on the full-scale current setting, I can be set between 2 mA and 20 mA, selecting an I

. Although I

OUTFS

of 20 mA

provides the best distortion and noise performance.

In summary, the AD9772A achieves the optimum distortion and noise performance under the following conditions:

• Positive voltage swing at I

• Differential operation

• I

• PLL clock multiplier disabled

set to 20 mA

OUTFS

OUTA

and I

OUTB

limited to 0.5 V B

Note that the majority of the ac characterization curves for the AD9772A are performed with these operating conditions.

DIGITAL INPUTS/OUTPUTS

The AD9772A consists of several digital input pins used for data, clock, and control purposes. It also contains a single digital output pin, PLLLOCK, which is used to monitor the status of the internal PLL clock multiplier or provide a 1× clock output. The 14-bit parallel data inputs follow standard positive binary coding, where DB13 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). I scale output current when all data bits are at Logic 1. I

produces a full-

OUTA

OUTB

produces a complementary output with the full-scale current split between the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered master slave latch and is designed to support an input data rate as high as 160 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width, as shown in

Figure 2 and Figure 3. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met. The digital inputs (excluding CLK+ and CLK−) are CMOS compatible with its logic thresholds, V

THRESHOLD

, set to approximately half the

digital positive supply (that is, DVDD or CLKVDD) or

THRESHOLD

= DVDD/2 (±20%)

The internal digital circuitry of the AD9772A is capable of operating over a digital supply range of 3.1 V to 3.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage of the TTL drivers V

. Although a DVDD of 3.3 V

OH(MAX)

typically ensures proper compatibility with most TTL logic families, series 200 Ω resistors are recommended between the TTL logic driver and digital inputs to limit the peak current through the ESD protection diodes if V by more than 300 mV.

Figure 42 shows the equivalent digital

exceeds DVDD

OH(MAX)

input circuit for the data and control inputs.

DVDD

DIGITAL

INPUT

02253-042

Figure 42. Equivalent Digital Input

The AD9772A features a flexible differential clock input operating from separate supplies (that is, CLKVDD, CLKCOM) to achieve optimum jitter performance. The two clock inputs, CLK+ and CLK−, can be driven from a single-ended or differential clock source. For single-ended operation, CLK+ should be driven by a single-ended logic source, and CLK− should be set to the logic source’s threshold voltage via a resistor divider/capacitor network referenced to CLKVDD as shown in

Figure 43. For differential operation, both CLK+ and CLK− should be biased to CLKVDD/2 via a resistor divider network as shown in transformer as shown in

Figure 7 can also be used to convert a

Figure 44. An RF

single-ended clock input to a differential clock input.

AD9772A

SERIES

1kΩ

THRESHOLD

Figure 43. Single-Ended Clock Interface

1kΩ

0.1µF

CLK+

CLKVDD

CLK–

CLKCOM

02253-043

Rev. C | Page 24 of 40

Page 25

AD9772A

1kΩ

CLK+

CLKVDD

CLK–

CLKCOM

02253-044

ECL/PECL

0.1µF

Figure 44. Differential Clock Interface

The quality of the clock and data input signals is important in achieving the optimum performance. The external clock driver circuitry should provide the AD9772A with a low jitter clock input, which meets the minimum/maximum logic levels while providing fast edges. Although fast clock edges help minimize jitter manifesting as phase noise on a reconstructed waveform, the high gain-bandwidth product of the AD9772A differential comparator can tolerate sine wave inputs as low as 0.5 V p-p, with minimal degradation in its output noise floor.

Digital signal paths should be kept short, and run lengths should match to avoid propagation delay mismatch. The insertion of a low value resistor network (that is, 50 Ω to 200 Ω) between the AD9772A digital inputs and driver outputs may be helpful in reducing overshooting and ringing at the digital inputs that contribute to data feedthrough.

The power dissipation is directly proportional to the analog supply current, I is directly proportional to I

Conversely, I waveform and f scale sine wave output ratios (f

, and the digital supply current, I

AVD D

and is not sensitive to f

OUTFS

is dependent on both the digital input

DVDD

. Figure 45 shows I

DATA

OUT/fDATA

as a function of full-

DVDD

) for various update rates

DVDD

DATA

. I

AVD D

with DVDD = 3.3 V. The supply current from CLKVDD and PLLVDD is relatively insensitive to the digital input waveform but directly proportional to the update rate, as shown in

100

(mA)

DVDD

0.1 0. 2 0.3 0.4 0.5

Figure 45. I

DVDD

= 160MSPS

DATA

= 125MSPS

DATA

= 100MSPS

DATA

= 65MSPS

DATA

= 50MSPS

DATA

= 25MSPS

DATA

RATIO (

)

OUT

DATA

vs. Ratio @ DVDD = 3.3 V

Figure 46.

2253-045

SLEEP MODE OPERATION

The AD9772A has a sleep function that turns off the output current and reduces the analog supply current to less than 6 mA over the specified supply range of 3.1 V to 3.5 V. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The AD9772A takes less than 50 ns to power down and then approximately 15 μs to power up.

POWER DISSIPATION

The power dissipation, PD, of the AD9772A is dependent on several factors, including

• The power supply voltages (AVDD, PLLVDD, CLKVDD,

and DVDD)

• The full-scale current output (I

• The update rate (f

DATA

)

• The reconstructed digital input waveform

OUTFS

)

(MSPS)

and I

CLKVDD

vs. f

PLLVDD

DATA

02253-046

CURRENT (mA)

50 100 150 200

DATA

Figure 46. I

PLLVDD

Rev. C | Page 25 of 40

Page 26

AD9772A

APPLYING THE AD9772A

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configurations for the AD9772A. Unless otherwise noted, it is assumed that I

is set to a nominal 20 mA for optimum

OUTFS

performance. For applications requiring the optimum dynamic performance, a differential output configuration can consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting.

A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if I sized load resistor, R

OUTA

and/or I

LOAD

is connected to an appropriately

OUTB

, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dccoupled, ground-referred output voltage. Alternatively, an amplifier can be configured as an I-V converter, thus converting I I

B into a negative unipolar voltage. This configuration

OUTB

provides the best dc linearity because I

OUTA

or I

OUTB

OUTA

maintained at a virtual ground.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used as shown in Figure 47 to perform a differential-to-single-ended signal conversion. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the pass band of the transformer. An RF transformer such as the Mini-Circuits® T1-1T provides excellent rejection of commonmode distortion (that is, even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios can also be used for impedance matching purposes. Note that the transformer provides ac coupling only, and its linearity performance degrades at the low end of its frequency range due to core saturation.

AD9772A

OUTA

OUTB

OPTIONAL R

Figure 47. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both I at I

OUTA

and I

(that is, V

OUTB

. The complementary voltages appearing

OUTB

OUTA

around ACOM and should be maintained with the specified output compliance range of the AD9772A. A differential resistor, R

, can be inserted into applications in which the

DIFF

output of the transformer is connected to the load, R

DIFF

MINI-CIRCUITS

and V

T1-1T

LOAD

) swing symmetrically

OUTB

LOAD

02253-047

, via a

Rev. C | Page 26 of 40

passive reconstruction filter or cable. R transformer’s impedance ratio and provides the proper source termination, resulting in a low voltage standing wave ratio (VSWR). Note that approximately half the signal power is dissipated across R

DIFF

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-singleended conversion as shown in

Figure 48. The AD9772A is configured with two equal load resistors, R differential voltage developed across I a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across I real pole in a low-pass filter. The addition of this capacitor also enhances the distortion performance of the op amp by preventing the DAC’s high slewing output from overloading the op amp input.

AD9772A

OUTA

OUTB

25Ω

OPT

Figure 48. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8055 is configured to provide some additional signal gain. The op amp must operate from a dual supply because its output is approximately ±1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9772A while meeting other system-level objectives (such as cost and power) should be selected. The op amp’s differential gain, gain-setting resistor values, and full-scale output swing capabilities should be considered when optimizing this circuit.

The differential circuit shown in

Figure 49 provides the necessary level shifting required in a single-supply system. In this case, AVDD, the positive analog supply for both the AD9772A and the op amp, is also used to level-shift the differential output of the AD9772A to midsupply (that is, AVDD/2). The AD8057 is a suitable op amp for this application.

AD9772A

OUTA

OUTB

25Ω 25Ω

Figure 49. Single-Supply DC Differential Coupled Circuit

225Ω

OPT

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

Figure 50 shows the AD9772A configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 Ω cable because the nominal full-scale current, I

is determined by the

DIFF

, each of 25 Ω. The

LOAD

and I

OUTA

225Ω

25Ω

OUTA

AD8057

1kΩ

OUTB

and I

500Ω

AD8055

500Ω

1kΩ

is converted to

, forming a

OUTB

02253-048

AVDD

02253-049

OUTFS

Page 27

AD9772A

of 20 mA flows through the equivalent R case, R I

OUTA

ACOM. Different values of I

represents the equivalent load resistance seen by

LOAD

. The unused output (I

) should be connected directly to

OUTB

and R

OUTFS

as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), as discussed in the

Analog Outputs section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested.

AD9772A

Figure 50. 0 V to 0.5 V Unbuffered Voltage Output

OUTA

OUTB

OUTFS

= 20mA

50Ω 50Ω

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

Figure 51 shows a single-ended, buffered output configuration in which the op amp U1 performs an I-V conversion on the AD9772A output current. U1 maintains I ground, thus minimizing the nonlinear output impedance effect on the INL performance of the DAC, as discussed in the Outputs

section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates is often limited by U1’s slewing capabilities. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of R

and I

. The full-scale output

OUTFS

should be set within U1’s voltage output swing capabilities by scaling I

and/or RFB. An improvement in ac distortion

OUTFS

performance may result in a reduced I current that U1 will be required to sink is subsequently reduced.

AD9772A

= 10mA

OUTFS

OUTA

OUTB

200Ω

Figure 51. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS

The AD9772A contains the following power supply inputs: AVDD, DVDD, CLKVDD, and PLLVDD. The AD9772A is specified to operate over a 3.1 V to 3.5 V supply range, thus accommodating a 3.3 V power supply with up to ±6% regulation. However, the following two conditions must be adhered to when selecting power supply sources for AVDD, DVDD, CLKVDD, and PLLVDD:

• PLLVDD = CLKVDD = 3.1 V to 3.5 V when the PLL clock

multiplier is enabled (otherwise, PLLVDD = PLLCOM)

• DVDD = CLKVDD ± 0.30 V

of 25 Ω. In this

LOAD

can be selected as long

LOAD

= 0V TO 0. 5V

OUTA

(or I

OUTA

because the signal

OUTFS

OPT

200Ω

OUT

OUTB

= –I

OUTFS

) at virtual

02253-050

Analog

× R

02253-051

Rev. C | Page 27 of 40

To meet the first condition, PLLVDD must be driven by the same power source as CLKVDD, with each supply input independently decoupled using a 0.1 μF capacitor connected to its respective ground. To meet the second condition, CLKVDD can share the same power supply source as DVDD by using the decoupling network shown in

Figure 52 to isolate digital noise from the sensitive CLKVDD (and PLLVDD) supply. Alternatively, separate precision voltage regulators can be used to ensure that the second condition is met.

In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection, placement and routing, and supply bypassing and grounding. Figure 60 to Figure 67 illustrate the recommended printed circuit board ground, power, and signal plane layouts that are implemented on the AD9772A evaluation board.

Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9772A features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. AVDD, CLKVDD, and PLLVDD must be powered from a clean analog supply and decoupled to their respective analog common (that is, ACOM, CLKCOM, and PLLCOM) as close to the chip as physically possible. Similarly, the digital supplies (DVDD) should be decoupled to DCOM.

For applications requiring a single 3.3 V supply for the analog, digital, and phase-lock loop supplies, a clean AVDD and/or CLKVDD can be generated using the circuit shown in

Figure 52. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESRtype electrolytic and tantalum capacitors.

FERRITE

TTL/CMOS

LOGIC

CIRCUITS

POWER

SUPPLY

3.3V

BEADS

100µF ELECTROLYTIC

–

10µF TO 22µF TANTALUM

–

0.1µF CERAMIC

AVDD

ACOM

Figure 52. Differential LC Filter for 3.3 V

Maintaining low noise on power supplies and ground is critical for achieving optimum results from the AD9772A. If properly implemented, ground planes can perform a host of functions on high speed circuit boards, such as bypassing and shielding current transport. In mixed-signal designs, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects.

All analog ground pins of the DAC, reference, and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path ⅛ to ¼ inch wide underneath or within ½ inch of the DAC to maintain

02253-052

Page 28

AD9772A

optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC. On the analog side, this includes the DAC output signal, the reference signal, and the supply feeders.

The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part and allowing some capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnections to avoid inducing extraneous voltage

drops in the signal ground paths. It is recommended that all connections be short, direct, and as physically close to the package as possible to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, use of strip line techniques with proper termination resistors should be considered. The necessity and value of these resistors depends on the logic family used.

For a more detailed discussion of the implementation and construction of high speed, mixed-signal printed circuit boards, refer to the AN-333 Application Note.

Rev. C | Page 28 of 40

Page 29

AD9772A

–

APPLICATIONS INFORMATION

MULTICARRIER

The AD9772A’s wide dynamic range performance makes it well suited for next-generation base station applications in which it reconstructs multiple modulated carriers over a designated frequency band. Cellular multicarrier and multimode radios are often referred to as software radios because the carrier tuning and modulation scheme is software programmable and performed digitally. The AD9772A is the recommended TxDAC® in the Analog Devices, Inc., SoftCell® chipset, which comprises the

AD6622 (a quadrature digital upconverter IC), the AD6624

(an Rx digital downconverter IC that acts as a companion to the AD6622), and the AD6644 (a 14-bit, 65 MSPS ADC). Figure 53 shows a generic software radio Tx signal chain using the AD9772A and

Figure 54 shows a spectral plot of the AD9772A operating at

64.54 MSPS, reconstructing eight IS-136-modulated carriers spread over a 25 MHz band. In this example, the AD9772A exhibits an SFDR performance of 74 dBc and a carrier-to-noise ratio (CNR) of 73 dB.

Figure 55 shows a spectral plot of the AD9772A operating at 52 MSPS, reconstructing four equal GSM-modulated carriers spread over a 15 MHz band. The SFDR and CNR (in 100 kHz BW) are measured to be 76 dBc and 83.4 dB, respectively, and have a channel power of −13.5 dBFS. The test vectors were generated using the Rohde & Schwarz WinIQSIM software.

AD6622

SPORT RCF

Figure 53. Generic Multicarrier Signal Chain Using the

–30

–40

–50

–60

–70

AMPLITUDE (dBm)

–80

–90

–100

Figure 54. Spectral Plot of AD9772A Reconstructing Eight IS-136-Modulated

JTAG

AD6622.

CIC

NCO

FILTER

QAM

CIC

NCO

FILTER

QAM

CIC

FILTER

CIC

FILTER

5101520 3025

Carriers @ f

SUMMATION

NCO

QAM

NCO

QAM

µPORT

FREQUENCY (MHz)

= 64.54 MSPS, PLLVDD = 0

DATA

CLK

PLLLOCK CLK+/

OTHER AD6622s FO R INCREASED CHANNEL CAPACITY

AD6622 and AD9772A

CLK–

AD9772A

02253-054

–20

–30

–40

–50

–60

–70

AMPLITUDE (dBm)

–80

–90

–100

–110

10 15

FREQUENCY (MHz)

20 25

02253-055

Figure 55. Spectral Plot of AD9772A Reconstructing Four GSM-Modulated

Carriers @ f

= 52 MSPS, PLLVDD = 0

DATA

Although the above IS-136 and GSM spectral plots are representative of the AD9772A’s performance for a set of test conditions, the following recommendations are offered to maximize the performance and system integration of the AD9772A into multicarrier applications:

1. To achieve the highest possible CNR, the PLL clock

multiplier should be disabled (that is, PLLVDD to PLLCOM) and the AD9772A clock input should be driven with a low jitter, low phase noise clock source at twice the input data rate. In this case, the divide-by-2 clock appearing at PLLLOCK should serve as the master clock for the digital upconverter IC(s), such as the AD6622. PLLLOCK should be limited to a fanout of 1.

2. The AD9772A achieves its optimum noise and distortion

performance when the device is configured for baseband operation and the differential output and full-scale current, I

, are set to approximately 20 mA.

OUTFS

3. Although the frequency roll-off of the 2× interpolation

02253-053

filter provides a maximum reconstruction bandwidth of

0.422 × f

, the optimum adjacent image rejection (due to

DATA

the interpolation process) can be achieved (that is, > 73 dBc) if the maximum channel assignment is kept below 0.400 × f

DATA

4. To simplify the filter requirements (that is, mixer image

and LO rejection) of the subsequent IF stages, it is often advantageous to offset the frequency band from dc to relax the transition band requirements of the IF filter.

5. Oversampling the frequency band often results in improved

SFDR and CNR performance. This implies that the data input rate to the AD9772A is greater than f

is the maximum bandwidth that the AD9772A is

PAS SB AN D

PASSBAND

/0.4 Hz, where

required to reconstruct and place carriers. The improved noise performance results in a reduction in the TxDAC’s noise spectral density due to the added process gain realized with oversampling, and higher oversampling ratios provide greater flexibility in the frequency planning.

Rev. C | Page 29 of 40

Page 30

AD9772A

–

BASEBAND SINGLE-CARRIER APPLICATIONS

The AD9772A is also well suited for wideband single-carrier applications, such as WCDMA and multilevel quadrature amplitude modulation (QAM), whose modulation scheme requires wide dynamic range from the reconstruction DAC to achieve the out-of-band spectral mask as well as the in-band CNR performance. Many of these applications strategically place the carrier frequency at one quarter of the DAC’s input data rate (that is, f

/4) to simplify the digital modulator

DATA

design. Because this constitutes the first fixed IF frequency, the frequency tuning is accomplished at a later IF stage. To enhance the modulation accuracy and reduce the shape factor of the second IF SAW filter, many applications specify that the pass band of the IF SAW filter be greater than the channel bandwidth; however, the trade-off is that this requires that the TxDAC meet the spectral mask requirements of the application within the extended pass band of the second IF, which may include two or more adjacent channels.

Figure 56 shows a spectral plot of the AD9772A reconstructing a test vector similar to those encountered in WCDMA applications. However, WCDMA applications prescribe a root raised cosine filter with an alpha = 0.22, which limits the theoretical ACPR of the TxDAC to about 70 dB, whereas the test vector represents white noise that has been band-limited by a brick wall bandpass filter with a pass band for which the maximum ACPR performance is theoretically 83 dB and the peak-to-rms ratio is 12.4 dB. As

Figure 56 reveals, the AD9772A is capable of approximately 78 dB ACPR performance when one accounts for the additive noise/distortion contributed by the Rohde & Schwarz FSEA30 spectrum analyzer.

–40

–50

–60

–70

–80

–90

AMPLITUDE (d Bm)

–100

–110

–120

–130

C11

CENTER 16.25MHz SPAN 6MHz600kHz

Figure 56. AD9772A Achieves 78 dB ACPR Performance Reconstructing a

WCDMA-Like Test Vector with f

C0 C0

C11

DATA

Cu1 Cu 1

= 65.536 MSPS and PLLVDD = 0

02253-056

DIRECT IF

As discussed in the Digital Modes of Operation section, the AD9772A can be configured to transform digital data representing baseband signals into IF signals appearing at odd multiples of the input data rate (that is, N × f This is accomplished by configuring the MOD1 and MOD0 digital inputs high. Note that the maximum DAC update rate of 400 MSPS limits the data input rate in this mode to 100 MSPS when the

, where N = 1, 3, and so on).

DATA

Rev. C | Page 30 of 40

zero-stuffing operation is enabled (that is, when MOD1 is high). Applications requiring higher IFs (that is, 140 MHz) using higher data rates should disable the zero-stuffing operation. In addition, to minimize the effects of the PLL clock multipliers phase noise as shown in noise clock source equal to 4 × f

Figure 31, an external low jitter/phase

is recommended.

DATA

Figure 57 shows the actual output spectrum of the AD9772A reconstructing a 16-QAM test vector with a symbol rate of 5 MSPS. The particular test vector was centered at f f

= 100 MSPS and f

DATA

the pair of images appearing around f

= 400 MHz. For many applications,

DAC

will be more attractive

DATA

/4 with

because this pair has the flattest pass band and highest signal power. Higher frequency images can also be used, but such images will have reduced pass-band flatness, dynamic range, and signal power, thus reducing the CNR and ACP performance. Figure 58 shows a dual-tone SFDR amplitude sweep at the various IF images with f tones centered around f

= 100 MSPS, f

DATA

= 400 MHz, and the two

DAC

/4. Note that because an IF filter is assumed to precede the AD9772A, the SFDR was measured over a 25 MHz window around the images occurring at 75 MHz, 125 MHz, 275 MHz, and 325 MHz.

–30

–40

–50

–60

–70

AMPLITUDE (dBm)

–80

–90

–100

Figure 57. Spectral Plot of 16-QAM Signal in Direct IF Mode at

SFDR (I N 25MHz W INDOW ) (dBF S)

–14

Figure 58. Dual-Tone Windowed SFDR vs. A

100

75MHz

125MHz

275MHz

325MHz

–12 –10 –8 –6 –2–4

200

FREQUENCY (MHz )

= 100 MSPS

DATA

(dBFS)

OUT

300

@ f

= 100 MSPS

DATA

400

02253-057

02253-058

Page 31

AD9772A

–

Regardless of which image is selected for a given application, the adjacent images must be sufficiently filtered. In most cases, a SAW filter providing differential inputs represents the optimum device for this purpose. For single-ended SAW filters, a balanced-tounbalanced RF transformer is recommended. The high output impedance of the AD9772A provides a certain amount of flexibility in selecting the optimum resistive load, R

LOAD

, as well

as any matching network.

For many applications, the data update rate for the DAC (that is, f

) must be a fixed integer multiple of a system reference

DATA

clock (for example, GSM − 13 MHz). Furthermore, these applications prefer to use standard IF frequencies, which offer a large selection of SAW filter choices with various pass bands (for example, 70 MHz). In addition, these applications may benefit from the AD9772A’s direct IF mode capabilities when used in conjunction with a digital upconverter, such as the Because the

AD6622 can digitally synthesize and tune up to four

AD6622.

modulated carriers, it is possible to judiciously tune these carriers in a region falling within the pass band an IF filter while the AD9772A is reconstructing a waveform.

Figure 59 shows an example in which four carriers are tuned around 18 MHz with a digital upconverter operating at 52 MSPS such that when reconstructed by the AD9772A in the IF mode, these carriers fall around a 70 MHz IF.

–20

–30

–40

–50

–60

–70

AMPLITUDE (dBm)

–80

–90

–110

Figure 59. Spectral Plot of Four Carriers at 60 MHz IF with f

68 70 72 74

FREQUENCY (MHz)

PLLVDD = 0

= 52 MSPS,

DATA

02253-059

Rev. C | Page 31 of 40

Page 32

AD9772A

AD9772A EVALUATION BOARD

The AD9772A-EB is an evaluation board for the AD9772A TxDAC. Careful attention to the layout and circuit design, along with the prototyping area, allows the user to easily and effectively evaluate the AD9772A in different modes of operation.

Referring to AD9772A can be evaluated differentially or in a single-ended fashion using a transformer, differential amplifier, or directly coupled output. To evaluate the output differentially using the transformer, remove Jumper JP12 and Jumper JP13 and monitor the output at J6 (IOUT). To evaluate the output differentially, remove the transformer (T2) and install jumpers JP12 and JP13. The output of the amplifier can be evaluated at J13 (AMPOUT). To evaluate the AD9772A in a single-ended fashion with a directly coupled output, remove the transformer and Jumper JP12 and Jumper JP13, and install Resistor R16 or Resistor R17 with 0 Ω.

The digital data to the AD9772A comes across a ribbon cable that interfaces to a 40-pin IDC connector. Proper termination or voltage scaling can be accomplished by installing the RN2 and/or RN3 SIP resistor networks. The 22 Ω DIP resistor network, RN1, must be installed and helps reduce the digital data edge rates. A single-ended clock input can be supplied via the ribbon cable by installing JP8, or, more preferably, via the SMA connector, J3 (CLOCK). If the clock is supplied by J3, the AD9772A can be configured for a differential clock interface by installing Jumper JP1 and configuring JP2, JP3, and JP9 in the DF position. To configure the AD9772A clock input for a single-ended clock interface, remove JP1 and configure JP2, JP3, and JP9 in the SE position.

Figure 60 and Figure 61, the performance of

The AD9772A PLL clock multiplier can be disabled by configuring Jumper JP5 in the L position. In this case, the user must supply a clock input at twice (2×) the data rate via J3 (CLOCK). The 1× clock is available on the SMA connector J1 (PLLLOCK), and should be used to trigger a pattern generator directly or via a programmable pulse generator. Note that PLLLOCK is capable of providing a 0 V to 0.85 V output into a 50 Ω load. To enable the PLL clock multiplier, JP5 must be configured for the H position. In this case, the clock can be supplied via the ribbon cable (that is, JP8 installed) or J3 (CLOCK). The divide-by-N ratio can be set by configuring JP6 (DIV0) and JP7 (DIV1).

The AD9772A can be configured for baseband or direct IF mode operation by configuring Jumper JP11 (MOD0) and Jumper JP10 (MOD1). For baseband operation, JP10 and JP11 should be configured in the L position. For direct IF operation, JP10 and JP11 should be configured in the H position. For direct IF operation without zero-stuffing, JP11 should be configured in the H position while JP10 should be configured in the low position.

The AD9772A voltage reference can be enabled or disabled via JP4. To enable the reference, configure JP4 in the internal position. A voltage of approximately 1.2 V will appear at the TP6 (REFIO) test point. To disable the internal reference, configure JP4 in the external position and drive TP6 with an external voltage reference. Lastly, the AD9772A can be placed in the sleep mode by driving the TP11 test point with a logic level high input signal.

Rev. C | Page 32 of 40

Page 33

AD9772A

SCHEMATICS

2 P1 1P1

4 P1 3P1

6 P1 5P1

8 P1 7P1

10 P1 9P1

12 P1 11P1

14 P1 13P1

16 P1 15P1

IN12

IN11

IN10

IN9

IN8

IN7

IN6

RN1

VALUE

161IN13

152

143

134

125

116

107

MSB DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

RN2

VALUE

MSB

IN13

IN12

IN11

IN10

IN9

IN8

IN7

IN6

RN3

VALUE

18 P1 17P1

20 P1 19P1

22 P1 21P1

24 P1 23P1

26 P1 25P1

28 P1 27P1

30 P1 29P1

32 P1 31P1

34 P1 33P1

36 P1 35P1

38 P1 37P1

40 P1 39P1

JP12

AMP-A

JP13

AMP-B

IN4

IN3

IN2

IN1

IN0

INCLOCK

INRESET

C16 100pF

R13 50Ω

DGND

RN4

VALUE

500Ω

R11 50Ω

DVDD_IN

R12

RN5

VALUE

161IN5

152

143

134

125

116

LSB

107

R14

500Ω

FBEAD 2

DB5

DB4

DB3

DB2

DB1

DB0

CLOCK

RESET

–IN

+IN

C13 10µF 10V

R15

500Ω

AD8055

OUT

–V

RED

TP22

TP23

DVDD

AMPOUT

LSB

IN5

IN4

IN3

IN2

IN1

IN0

INCLOCK

INRESET

J13

–V

C18

0.1µF

C17

0.1µF

RN6

VALUE

RED

TP20

BLK

TP19

BLK

C14 10µF 10V

C15 10µF 10V

RED

BLK

RED

BLK

J10

J11

J12

FBEAD

AVDD_IN

AGND

CLKVDD_IN

CLKGND

FBEAD

Figure 60. Drafting Schematic of Evaluation Board

Rev. C | Page 33 of 40

TP24

TP25

TP26

TP27

AVDD

CLKVDD

02253-060

Page 34

AD9772A

RED

TP16

AVDD

0.1µF

(MSB) DB13

DB12 DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DVDD

0.1µF

48 47 46 45 44 39 38 3743 42 41 40

PIN 1

IDENTIFIER

13 14 15 16 17 18 19 20 21 22 23 24

DB3

DB2

TP14

TP15

RED

BLK

DVDD

JP10

JP11

DGND

NOTE: LOCATE ALL DECOUPLI NG CAPACITO RS (C5 TO C12) AS CLOSE AS POSSIBLE TO DUT, PREFERABLY UNDER DUT ON THE BOT TOM SIGNAL LAYER.

50Ω

10pF

R9 OPT

C2 10pFR750Ω

DB1

MOD0

R16 VAL

R17 VAL

0.1µF

1µF

AD9772A

(LSB) DB0

TP1

WHT

MOD1

TP2

WHT

BLK

TP17

OUTA

OUTB

C11

0.1µF

C12 1µF

WHT

TP5

FSADJ

REFIO

DVDD

IOUT

TP3

WHT

TP6

REFLO

TP4

WHT

0.1µF

SLEEP WHT

Figure 61. Drafting Schematic of Evaluation Board (Continued)

R10

1.91kΩ

TP11

LPF

CLK–

CLK+

DIV0

DIV1

PLLLOCK

TP28 WHT

AVDD

EXT REF

REFLO

JP4

INT REF

NOTE:

50Ω

SHIELD AROUND R5, C1 CONNECTED TO PLLVDD

VAL

PLLVDD

JP6

C10

0.1µF

JP1

CLKVDD

JP7

WHT TP12

CLOCK

02253-061

C9 1µF

RESET

TP10 WHT

JP8

EDGE

CLKVDD

CLOCK

JP3

50Ω

CLKVDD

JP5

REDTP7

JP2

R2 1kΩ

C19

1kΩ

0.1µF

JP9

Rev. C | Page 34 of 40

Page 35

AD9772A

EVALUATION BOARD LAYOUT

Figure 62. Silkscreen Layer—Top

02253-062

Figure 63. Component-Side PCB Layout (Layer 1)

Rev. C | Page 35 of 40

02253-063

Page 36

AD9772A

Figure 64. Ground Plane PCB Layout (Layer 2)

02253-064

Figure 65. Power Plane PCB Layout (Layer 3)

Rev. C | Page 36 of 40

02253-065

Page 37

AD9772A

Figure 66. Solder-Side PCB Layout (Layer 4)

02253-066

02253-067

Figure 67. Silkscreen Layer—Bottom

Rev. C | Page 37 of 40

Page 38

AD9772A

OUTLINE DIMENSIONS

9.20

0.50 BSC

9.00 SQ

8.80

PIN 1

TOP VIEW

(PINS DO WN)

0.27

0.22

0.17

7.20

7.00 SQ

6.80

051706-A

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.75

0.60

0.45

0.20

0.09 7°

3.5° 0°

0.08 COPLANARIT Y

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

1.60 MAX

VIEW A

LEAD PITCH

Figure 68. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9772AAST −40°C to +85°C 48-Lead LQFP ST-48 AD9772AASTZ AD9772AASTRL −40°C to +85°C 48-Lead LQFP ST-48 AD9772AASTZRL AD9772A-EB Evaluation Board

Z = RoHS Compliant Part.

−40°C to +85°C 48-Lead LQFP ST-48

Rev. C | Page 38 of 40

Page 39

AD9772A

NOTES

Rev. C | Page 39 of 40

Page 40

AD9772A

NOTES

Rev. C | Page 40 of 40

Datasheet AD9772A Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

PRODUCT HIGHLIGHTS

SPECIFICATIONS

DC SPECIFICATIONS

DYNAMIC SPECIFICATIONS

DIGITAL SPECIFICATIONS

DIGITAL FILTER SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

FUNCTIONAL DESCRIPTION

DIGITAL MODES OF OPERATION

2× Interpolation Filter Description

Zero-Stuffing Option Description

PLL CLOCK MULTIPLIER OPERATION

SYNCHRONIZATION OF CLOCK/DATA USING RESET WITH PLL DISABLED

DAC OPERATION

DAC TRANSFER FUNCTION

REFERENCE OPERATION

REFERENCE CONTROL AMPLIFIER

ANALOG OUTPUTS

DIGITAL INPUTS/OUTPUTS

SLEEP MODE OPERATION

POWER DISSIPATION

APPLYING THE AD9772A

OUTPUT CONFIGURATIONS

DIFFERENTIAL COUPLING USING A TRANSFORMER

DIFFERENTIAL COUPLING USING AN OP AMP

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

POWER AND GROUNDING CONSIDERATIONS

APPLICATIONS INFORMATION

MULTICARRIER

BASEBAND SINGLE-CARRIER APPLICATIONS

DIRECT IF

AD9772A EVALUATION BOARD

SCHEMATICS

EVALUATION BOARD LAYOUT

OUTLINE DIMENSIONS

ORDERING GUIDE