Datasheet AD9772A Datasheet (Analog Devices)

®

14-BIT DAC

2 FIR INTER-

POLATION

FILTE

R

EDGE-

TRIGGERED

LATCHES

CLOCK DISTRIBUTION

AND MODE SELECT

2/4



MUX

CONTROL

FILTER

CONTROL

1/2

1

PLL CLOCK

MULTIPLIER

+1.2V REFERENCE

AND CONTROL AMP

AD9772A

CLKCOM

CLKVDD MOD0 MOD1 RESET

PLLLOCK

DIV0

DIV1

CLK+

CLK–

DATA INPUTS (DB13...

DB0)

SLEEP

DCOM DVDD ACOM AVDD

REFLO

PLLCOM

LPF

PLLVDD

I

OUTA

I

OUTB

REFIO

FSADJ

ZEROSTUFF

MUX

14-Bit, 160 MSPS TxDAC+

with 2 Interpolation Filter

AD9772A

FEATURES Single 3.1 V to 3.5 V Supply 14-Bit DAC Resolution and Input Data Width 160 MSPS Input Data Rate

67.5 MHz Reconstruction Pass Band @ 160 MSPS 74 dBc SFDR @ 25 MHz 2 Interpolation Filter with High- or Low-Pass Response

73 dB Image Rejection with 0.005 dB Pass-band Ripple

Zero -Stufng Option for Enhanced Direct IF Performance Internal 2/4 Clock Multiplier 250 mW Power Dissipation; 13 mW with Power-Down

Mode 48-Lead LQFP Package

APPLICATIONS Communication Transmit Channel W-CDMA Base Stations, Multicarrier Base Stations, Direct IF Synthesis, Wideband Cable Systems Instrumentation

GENERAL DESCRIPTION

The AD9772A is a single-supply, oversampling, 14-bit digital-to-analog converter (DAC) optimized for baseband or IF waveform reconstruction applications requiring exceptional dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 2 digital interpolation lter and clock multiplier. The onchip PLL clock multiplier provides all the necessary clocks for the digital lter and the 14-bit DAC. A exible differential clock input allows for a single-ended or differential clock driver for optimum jitter performance.

For baseband applications, the 2 digital interpolation lter provides a low-pass response, thus providing as much as a threefold reduction in the complexity of the analog reconstruction lter. It does so by multiplying the input data rate by a factor of 2 while suppressing the original upper in-band image by more than 73 dB. For direct IF applications, the 2 digital interpolation lter response can be recongured to select the upper in-band image (i.e., high-pass response) while suppressing the original baseband image. To increase the signal the higher IF images and their pass-band atness in di applications, the AD9772A also features a zero-stufng option in which the data following the 2 interpolation lter is upsampled by a factor of 2 by inserting midscale data samples.

The AD9772A can reconstruct full-scale waveforms with bandwidths as high as 67.5 MHz while operating at an input data rate of 160 MSPS. The 14-bit DAC provides differential cur outputs to support differential or single-ended applications.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

level of

rect IF

rent

FUNCTIONAL BLOCK DIAGRAM

A

segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Matching between the two current outputs ensures enhanced dynamic performance in a differential output conguration. The differential current outputs may be fed into a transformer or a differential op amp topology to obtain a single-ended output voltage using an appropriate resistive load.

The on-chip band gap reference and control amplier are congured for maximum accuracy and exibility. The AD9772A can be driven by the on-chip reference or by a variety of external reference voltages. The full-scale current of the AD9772A can be adjusted over a 2 mA to 20 mA range, thus providing additional gain ranging capabilities.

The AD9772A is available in a 48-lead LQFP package and is specied for operation over the industrial temperature range of –40°C to +85°C.

PRODUCT HIGHLIGHTS

1. A exible, low power 2 interpolation lter supporting recon-

struction bandwidths of up to 67.5 MHz can be congured for a low- or high-pass response with 73 dB of image rejection for traditional baseband or direct IF applications.

2. A zero-stufng option enhances direct IF applications.

3. A low glitch, fast settling 14-bit DAC provides exceptional

dynamic range for both baseband and direct IF waveform reconstruction applications.

4. The AD9772A digital interface, consisting of edge-triggered

latches and a exible differential or single-ended clock input, can support input data rates up to 160 MSPS.

5. On-chip PLL clock multiplier generates all of the internal high

speed clocks required by the interpolation lter and DAC.

6. The current output(s) of the AD9772A can easily be congured

for various single-ended or differential circuit topologies.

AD9772A–SPECIFICATIONS

DC SPECIFICATIONS

(T

to T

MIN

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.)

OUTFS

Parameter Min Typ Max Unit

RESOLUTION 14 Bits

DC ACCURACY

1

Integral Linearity Error (INL) ±3.5 LSB Differential Nonlinearity (DNL) ±2.0 LSB Monotonicity (12-Bit) Guaranteed over Specied Temperature Range

ANALOG OUTPUT Offset Error –0.025 +0.025 % of FSR Gain Error (without Internal Reference) –2 ±0.5 +2 % of FSR Gain Error (with Internal Reference) –5 ±1.5 +5 % of FSR Full-Scale Output Current2 20 mA Output Compliance Range –1.0 +1.25 V Output Resistance 200 kW Output Capacitance 3 pF

REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V Reference Output Current

3

1 µA

REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (REFLO = 3 V) 10 MW Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS Unipolar Offset Drift 0 ppm of FSR/°C Gain Drift (without Internal Reference) ±50 ppm of FSR/°C Gain Drift (with Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY AVDD Voltage Range 3.1 3.3 3.5 V Analog Supply Current (I Analog Supply Current in SLEEP Mode (I

) 34 37 mA

AVDD

) 4.3 6 mA

AVDD

DVDD1, DVDD2 Voltage Range 3.1 3.3 3.5 V Digital Supply Current (I

DVDD1

+ I

) 37 40 mA

DVDD2

CLKVDD, PLLVDD4 (PLLVDD = 3.3 V) Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

CLKVDD

+ I

) 25 30 mA

PLLVDD

CLKVDD (PLLVDD = 0 V) Voltage Range 3.1 3.3 3.5 V Clock Supply Current (I

) 6.0 mA

CLKVDD

Nominal Power Dissipation5 253 272 mW Power Supply Rejection Ratio (PSRR)6 – AVDD –0.6 +0.6 % of FSR/V Power Supply Rejection Ratio (PSRR)6 – DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

2

Nominal full-scale current, I

3

Use an external amplier to drive any external load.

4

Measured at f

5

Measured with PLL enabled at f

6

Measured over a 3.0 V to 3.6 V range.

Specications subject to change without notice.

driving a virtual ground.

OUTA

= 100 MSPS and f

DATA

OUTFS

, is 32 the I

OUT

= 50 MSPS and f

DATA

current.

REF

= 1 MHz, DIV1, DIV0 = 0 V.

= 1 MHz.

OUT

–2–

REV. B

AD9772A

(T

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

differential transformer-coupled output, 50  doubly terminated, unless otherwise noted.)

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (f

) 400 MSPS

DAC

Output Settling Time (tST) (to 0.025%) 11 ns Output Propagation Delay1 (tPD) 17 ns Output Rise Time (10% to 90%)2 0.8 ns Output Fall Time (10% to 90%)2 0.8 ns Output Noise (I

= 20 mA) 50 pAHz

OUTFS

AC LINEARITY—BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (f f f f f f f Two-Tone Intermodulation (IMD) to Nyquist (f f f f f f f

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 65 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 160 MSPS; f

DATA

= 1.01 MHz 82 dBc

OUT

= 10.01 MHz 75 dBc

OUT

= 25.01 MHz 73 dBc

OUT

= 5.02 MHz 82 dBc

OUT

= 20.02 MHz 75 dBc

OUT

= 50.02 MHz 65 dBc

OUT

= 5.01 MHz; f

OUT1

= 15.01 MHz; f

OUT1

= 24.1 MHz; f

OUT1

= 10.02 MHz; f

OUT1

= 30.02 MHz; f

OUT1

= 48.2 MHz; f

OUT1

= 6.01 MHz 85 dBc

OUT2

= 17.51 MHz 75 dBc

OUT2

= 26.2 MHz 68 dBc

OUT2

= 12.02 MHz 85 dBc

OUT2

= 35.02 MHz 70 dBc

OUT2

= 52.4 MHz 65 dBc

OUT2

= 0 dBFS)

OUT

= f

OUT2

= –6 dBFS)

Total Harmonic Distortion (THD) f f

= 65 MSPS; f

DATA

= 78 MSPS; f

DATA

= 1.0 MHz; 0 dBFS –80 dB

OUT

= 10.01 MHz; 0 dBFS –74 dB

OUT

Signal-to-Noise Ratio (SNR) f f

= 65 MSPS; f

DATA

= 100 MSPS; f

DATA

= 16.26 MHz; 0 dBFS 71 dB

OUT

= 25.1 MHz; 0 dBFS 71 dB

OUT

Adjacent Channel Power Ratio (ACPR) WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing IF = 16 MHz, f IF = 32 MHz, f

= 65.536 MSPS 78 dBc

DATA

= 131.072 MSPS 68 dBc

DATA

Four-Tone Intermodulation

15.6 MHz, 15.8 MHz, 16.2 MHz, and 16.4 MHz at –12 dBFS 88 dBFS f

= 65 MSPS, Missing Center

DATA

AC LINEARITY—IF MODE Four-Tone Intermodulation at IF = 70 MHz

68.1 MHz, 69.3 MHz, 71.2 MHz, and 72.0 MHz at –20 dBFS 77 dBFS f

NOTES

1

Propagation delay is delay from CLK input to DAC update.

2

Measured single-ended into 50 W load.

Specications subject to change without notice.

= 52 MSPS, f

DATA

= 208 MHz

DAC

OUTFS

= 20 mA,

REV. B

–3–

AD9772A

t

S

0.025%

DB0–DB13

CLK+ – CLK–

IOUTA

OR

IOUTB

t

H

t

LPW

t

PD

t

ST

t

S

DB0–DB13

0.025%

IOUTA

OR

IOUTB

t

OD

PLLLOCK

CLK+ – CLK–

t

H

t

LPW

t

PD

t

ST

(T

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

DIGITAL SPECIFICATIONS

MIN

otherwise noted.)

Parameter Min Typ Max Unit

DIGITAL INPUTS Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current* –10 +10 µA Logic 0 Current –10 +10 µA Input Capacitance 5 pF

CLOCK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V

PLL CLOCK ENABLED—FIGURE 1a Input Setup Time (tS), TA = 25°C 0.5 ns Input Hold Time (tH), TA = 25°C 1.0 ns Latch Pulsewidth (t

), TA = 25°C 1.5 ns

LPW

PLL CLOCK DISABLED—FIGURE 1b Input Setup Time (tS), TA = 25°C –1.2 ns Input Hold Time (tH), TA = 25°C 3.2 ns Latch Pulsewidth (t

), TA = 25°C 1.5 ns

LPW

CLK/PLLLOCK Delay (tOD), TA = 25°C 2.8 3.2 ns PLLLOCK (VOH), TA = 25°C 3.0 V PLLLOCK (VOL), TA = 25°C 0.3 V

*MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 µA.

Specications subject to change without notice.

= 20 mA, unless

OUTFS

Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled

Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled

–4–

REV. B

AD9772A

FREQUENCY (DC TO f

DATA

)

0

–140

0

1.00.1

OUTPUT (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

–20

–40

–60

–80

–100

–120

TIME (Samples)

1.0

–0.4

0

5

NORMALIZED OUTPUT

10 15 20 25 30 35 40 45

0.8

0.6

0.4

0.2

0

–0.2

(T

to T

, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

MAX

DIGITAL FILTER SPECIFICATIONS

MIN

differential transformer-coupled output, 50  doubly terminated, unless otherwise noted.)

Parameter Min Typ Max Unit

MAXIMUM INPUT DATA RATE (f

) 150 MSPS

DATA

DIGITAL FILTER CHARACTERISTICS Pass-Bandwidth1: 0.005 dB 0.401 f Pass-Bandwidth: 0.01 dB 0.404 f Pass-Bandwidth: 0.1 dB 0.422 f Pass-Bandwidth: –3 dB 0.479 f

LINEAR PHASE (FIR IMPLEMENTATION)

STOP BAND REJECTION

0.606 f

GROUP DELAY

CLOCK

to 1.394 f

2

73 dB

CLOCK

11 Input Clocks

IMPULSE RESPONSE DURATION –40 dB 36 Input Clocks –60 dB 42 Input Clocks

NOTES

1

Excludes sin(x)/x characteristic of DAC.

2

Dened as the number of data clock cycles between impulse input and peak of output response.

Specications subject to change without notice.

= 20 mA,

OUTFS

OUT/fDATA

Table I. Integer Filter Coefcients for Interpolation Filter (43-Tap Half-Band FIR Filter)

Lower Upper Integer Coefcient Coefcient Value

H(1) H(43) 10 H(2) H(42) 0 H(3) H(41) –31 H(4) H(40) 0 H(5) H(39) 69 H(6) H(38) 0 H(7) H(37) –138 H(8) H(36) 0 H(9) H(35) 248 H(10) H(34) 0 H(11) H(33) –419

Figure 2a. FIR Filter Frequency Response—Baseband Mode

H(12) H(32) 0 H(13) H(31) 678 H(14) H(30) 0 H(15) H(29) –1083 H(16) H(28) 0 H(17) H(27) 1776 H(18) H(26) 0 H(19) H(25) –3282 H(20) H(24) 0 H(21) H(23) 10364 H(22) 16384

Figure 2b. FIR Filter Impulse Response—Baseband Mode

REV. B

–5–

AD9772A

–7–

REV. B

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect to Min Max Unit

AVDD, DVDD1-2, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM –0.3 +4.0 V AVDD, DVDD1-2, CLKVDD, PLLVDD AVDD, DVDD1-2, CLKVDD, PLLVDD –4.0 +4.0 V ACOM, DCOM1-2, CLKCOM, PLLCOM ACOM, DCOM1-2, CLKCOM, PLLCOM –0.3 +0.3 V REFIO, REFLO, FSADJ, SLEEP ACOM –0.3 AVDD + 0.3 V I

, I

OUTA

DB0–DB13, MOD0, MOD1, PLLLOCK DCOM1-2 –0.3 DVDD + 0.3 V CLK+, CLK– CLKCOM –0.3 CLKVDD + 0.3 V DIV0, DIV1, RESET CLKCOM –0.3 CLKVDD + 0.3 V LPF PLLCOM –0.3 PLLVDD + 0.3 V Junction Temperature 125 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) 300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational sections of this specication is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

ACOM –1.0 AVDD + 0.3 V

OUTB

ORDERING GUIDE

Temperature Package Package Model Range Description Option*

AD9772AAST –40°C to +85°C 48-Lead LQFP ST-48 AD9772AASTRL –40°C to +85°C 48-Lead LQFP ST-48

THERMAL CHARACTERISTIC

Thermal Resistance

48-Lead LQFP

qJA = 91°C/W qJC = 28°C/W

AD9772A-EB Evaluation Board

*ST = Thin Plastic Quad Flatpack.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9772A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–6–

REV. B

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44 39 38 3743 42 41 40

PIN 1 IDENTIFIER

TOP VIEW

(Not to Scale)

SLEEP

LPF

PLLVDD

PLLCOM

CLKVDD

CLKCOM

CLK–

DCOM

(MSB) DB13

DB12

DB11

DB10

DB9

NC = NO CONNECT

DB8

DB7

DB6

DB5

CLK+

DIV0

DIV1

RESET

AD9772A

DB4

PLLLOCK

DVDD

AVDD

ACOM

I

OUTAIOUTB

ACOM

FSADJ

REFIO

REFLO

ACOM

DB3

DB2

DB1

(LSB) DB0

MOD0

MOD1

DCOM

DVDD

NC

AD9772A

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1, 2, 19, 20 DCOM Digital Common.

3 DB13 Most Signicant Data Bit (MSB).

4–15 DB12–DB1 Data Bits 1–12.

16 DB0 Least Signicant Data Bit (LSB).

17 MOD0 Invokes digital high-pass lter response (i. e., half-wave digital mixing mode). Active high.

18 MOD1 Invokes Zero-Stufng Mode. Active high. Note, quarter-wave digital mixing occurs with MOD0 also set high.

23, 24 NC No Connect, Leave Open.

21, 22, 47, 48 DVDD Digital Supply Voltage (3.1 V to 3.5 V).

25 PLLLOCK Phase-Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is locked to input clock. Provides 1 clock output when PLL clock multiplier is disabled. Maximum fanout is 1 (i.e., <10 pF). 26 RESET Resets internal divider by bringing momentarily high when PLL is disabled to synchronize internal 1 clock to the input data and/or multiple AD9772A devices.

27, 28 DIV1, DIV0 DIV1 along with DIV0 sets the PLL’s prescaler divide ratio (refer to Table III).

29 CLK+ Noninverting Input to Differential Clock. Bias to midsupply (i.e., CLKVDD/2).

30 CLK– Inverting Input to Differential Clock. Bias to midsupply (i.e., CLKVDD/2).

31 CLKCOM Clock Input Common.

32 CLKVDD Clock Input Supply Voltage (3.1 V to 3.5 V).

33 PLLCOM Phase-Lock Loop Common.

34 PLLVDD Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable PLL clock multiplier, connect PLLVDD to PLLCOM.

35 LPF PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than 10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated on the evaluation board schematic.

36 SLEEP Power-Down Control Input. Active high. Connect to ACOM if not used.

37, 41, 44 ACOM Analog Common.

38 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.

39 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 F capacitor to ACOM when internal reference activated.

40 FSADJ Full-Scale Current Output Adjust.

42 I

43 I

45, 46 AVDD Analog Supply Voltage (3.1 V to 3.5 V).

REV. B

–7–

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

OUTB

DAC Current Output. Full-scale current when all data bits are 1s.

OUTA

AD9772A

PLLCLOCK

MULTIPLIER

EDGE-

TRIGGERED

LATCHES

2 FIR

INTERPOLATION

FILTER

AD9772A

3.3V3.3V

FROM HP8644A SIGNAL GENERATOR

3.3V

CLKVDD

CLKCOM

CLK+

1

FILTER CONTROL

MUX

CONTROL

MOD0

MOD1

RESET

PLLLOCK

DIV0

DIV1

PLLCOM

LPF

PLLVDD

I

OUTA

I

OUTB

REFIO

FSADJ

REFLOAVDDACOMDVDDDCOM

SLEEP

ZERO

STUFF

MUX

14-BIT DAC

100

MINI-CIRCUITS

T1–1T

20pF50

50

20pF

1.91k

0.1F

+1.2V REFERENCE

AND CONTROL AMP

AWG2021

OR

DG2020

DIGITAL

DATA

EXT.

CLOCK

HP8130

PULSE GENERATOR

CH1

CH2

EXT. INPUT

2/4

CLK–

1k

1/2

CLOCK DISTRIBUTION

AND MODE SELECT

TO FSEA30 SPECTRUM ANALYZER

DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is dened as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital

input code.

Monotonicity

A D/A converter is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is called offset error. For I the inputs are all 0s. For I

, 0 mA output is expected when

OUTA

, 0 mA output is expected

OUTB

when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a currentoutput DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Temperature Drift

Temperature drift is specied as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

MAX

For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies are varied from minimum to maximum specied voltages.

Settling Time

The time required for the output to reach and remain within a specied error band about its nal value, measured from the start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to unde output transients that are quantied by a glitch impulse. It is specied as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specied bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the rst six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).

Signal-to-Noise Ratio (SNR)

S/N is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the rst six harmonics and dc. The value for SNR is expressed in decibels.

Pass Band

Frequency band in which any input applied therein passes unattenuated to the DAC output.

Stop-band Rejection

The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.

Group Delay

.

Number of input clocks between an impulse applied at the device input and peak DAC output current.

Impulse Response

Response of the device to an impulse applied to the input.

Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel relative to its adjacent channel.

sired

Figure 3. Basic AC Characterization Test Setup

–8–

REV. B REV. B

Typical Performance Characteristics–AD9772A

f

OUT

(MHz)

0

–60

–100

120200

AMPLITUDE (dBm)

–40

–80

40 60 80 100

–20

OUT-OF-

BAND

IN-BAND

FREQUENCY (MHz)

0

–60

–100

1500

AMPLITUDE (dBm)

–40

–80

50 100

–20

OUT-OF-

BAND

IN-BAND

FREQUENCY (MHz)

0

–60

–100

300500

AMPLITUDE (dBm)

–40

–80

100 150 200 250

–20

OUT-OF-

BAND

IN-BAND

–12dBFS

0dBFS

–6dBFS

f

OUT

(MHz)

30150 20 25105

90

SFDR (dBc)

85

80

75

70

65

60

55

50

f

OUT

(MHz)

90

30150

SFDR (dBc)

85

80

75

70

65

60

55

50

20 25105

–12dBFS

0dBFS

35

–6dBFS

f

OUT

(MHz)

90

0

AMPLITUDE (dBm)

85

80

75

70

65

60

55

50

10 20 30 40 50 60

–12dBFS

–6dBFS

0dBFS

f

OUT

(MHz)

70

30150

SFDR (dBc)

65

60

55

50

45

40

35

30

20 25105

–12dBFS

0dBFS

–6dBFS

f

OUT

(MHz)

70

0

AMPLITUDE (dBm)

65

60

55

50

45

40

35

30

5 10 15 20 25 30 3

5

–12dBFS

–6dBFS

0dBFS

f

OUT

(MHz)

70

0

AMPLITUDE (dBm)

65

60

55

50

45

40

35

30

10 20 30 40 50 60 70

–12dBFS

–6dBFS

0dBFS

(AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I

TPC 1. Single-Tone Spectral Plot @ f f

= f

OUT

= 65 MSPS with

DATA

/3

DATA

TPC 2. In-Band SFDR vs. f @ f

= 20 mA. PLL disabled.)

OUTFS

= 65 MSPS

DATA

OUT

TPC 3. Out-of-Band SFDR vs. f

OUT

@ f

= 65 MSPS

DATA

TPC 4. Single-Tone Spectral Plot @ f f

= f

OUT

TPC 7. Single-Tone Spectral Plot @ f f

= f

OUT

= 78 MSPS with

DATA

/3

DATA

= 160 MSPS with

DATA

/3

DATA

TPC 5. In-Band SFDR vs. f

@ f

= 78 MSPS

DATA

TPC 8. In-Band SFDR vs. f @ f

= 160 MSPS

DATA

OUT

TPC 6. Out-of-Band SFDR vs. f

OUT

@ f

= 78 MSPS

DATA

TPC 9. Out-of-Band SFDR vs. f

OUT

@ f

= 160 MSPS

DATA

–9–

AD9772A AD9772A

f

OUT

(MHz)

90

0

IMD (dBc)

85

80

75

70

65

60

55

50

5 10 15 20 25 3

0

–3dBFS

0dBFS

–6dBFS

A

OUT

(dBFS)

90

–20

IMD (dBc)

85

80

75

70

65

60

–10 –5 0

f

DATA

= 160MSPS

f

DATA

= 65MSPS

f

DATA

= 78MSPS

–15

AVDD (Volts)

90

70

50

3.63.33.0

IMD (dBc)

80

60

85

75

65

55

3.1 3.2 3.4 3.5

–6dBFS

0dBFS

–3dBFS

f

OUT

(MHz)

90

0

IMD (dBc)

85

80

75

70

65

60

55

50

5 10 15 20 25 3

0

–3dBFS

0dBFS

–6dBFS

35

A

OUT

(dBFS)

90

–20

IMD (dBc)

85

80

75

70

65

60

–10 –5 0

f

DATA

= 160MSPS

f

DATA

= 65MSPS

f

DATA

= 78MSPS

–15

55

50

f

DAC

(MHz)

90

25

SNR (dBc)

85

80

75

70

65

60

125 175

75

55

50

PLL OFF

PLL ON, OPTIMUM DIV0/1 SETTINGS

f

OUT

(MHz)

90

0

IMD (dBc)

85

80

75

70

65

60

55

50

10 20 30 40 50 60 70

–3dBFS

0dBFS

–6dBFS

AVDD (Volts)

90

70

50

3.63.33.0

SFDR (dBc)

80

60

85

75

65

55

3.1 3.2 3.4 3.5

–6dBFS

0dBFS

–3dBFS

TEMPERATURE (C)

90

–40

SFDR (dBc)

85

80

75

70

65

60

0 8

0–20

55

50

f

DATA

= 160MSPS

f

DATA

= 78MSPS

f

DATA

= 65MSPS

20 40 60

TPC 10. Third Order IMD Products vs. f

OUT

@ f

= 65 MSPS

DATA

TPC 13. Third Order IMD Products vs. A

OUT

@ f

OUT

= f

DAC

/11

TPC 11. Third Order IMD Products vs. f

OUT

@ f

= 78 MSPS

DATA

TPC 14. Third Order IMD Products vs. A

OUT

@ f

OUT

= f

DAC

/5

TPC 12. Third Order IMD Products vs. f

@ f

OUT

TPC 15. SFDR vs. AVDD @ f f

= 320 MSPS

DAC

= 160 MSPS

DATA

= 10 MHz,

OUT

TPC 16. Third Order IMD Products vs. AVDD @ f 320 MSPS

= 10 MHz, f

OUT

TPC 18. In-Band SFDR vs. Temperature @ f

OUT

= f

DATA

/11

REV. B REV. B

DAC

=

TPC 17. SNR vs. f

DAC

@ f

= 10 MHz

OUT

–10–

14-BIT DAC

2 FIR INTER-

POLATION

FILTER

EDGE-

TRIGGERED

LATCHES

CLOCK DISTRIBUTION

AND MODE SELECT

2/4



MUX

CONTROL

FILTER

CONTROL

1/2

1

PLL CLOCK

MULTIPLIER

+1.2V REFERENCE

AND CONTROL AMP

AD9772A

CLKCOM

CLKVDD MOD0 MOD1 RESET

PLLLOCK

DIV0

DIV1

CLK+

CLK–

DATA INPUTS (DB13...

DB0)

SLEEP

DCOM DVDD ACOM AVDD

REFLO

PLLCOM

LPF

PLLVDD

I

OUTA

I

OUTB

REFIO

FSADJ

ZERO

STUFF

MUX

FUNCTIONAL DESCRIPTION

Figure 4 shows a simplied block diagram of the AD9772A. The AD9772A is a complete, 2 oversampling, 14-bit DAC that includes a 2 interpolation lter, a phase-locked loop (PLL) clock multiplier, and a 1.20 V band gap voltage reference. While

the AD9772A’s digital interface can support input data

rates

as high as 160 MSPS, its internal DAC can operate up to 400 MSPS, thus providing direct IF conversion capabilities. The 14-bit DAC provides two complementary current outputs whose full-scale current is determined by an external resistor. The AD9772A features a exible, low jitter, differential clock input, providing excellent noise rejection while accepting a sine wave input. An on-chip PLL clock multiplier produces all of the necessary synchronized clocks from an external reference clock source. Separate supply inputs are provided for each functional block to ensure optimum noise and distortion performance. A SLEEP mode is also included for power savings.

Figure 4. Functional Block Diagram

Preceding the 14-bit DAC is a 2 digital interpolation lter that can be congured for a low-pass (i.e., baseband mode) or highpass (i.e., direct IF mode) response. The input data is latched into the edge-triggered input latches on the rising edge of the differential input clock as shown in Figure 1a and then interpolated by a factor of 2 by the digital lter. For traditional baseband applications, the 2 interpolation lter has a low-pass response. For direct IF applications, the lter’s response can be converted into a high-pass response to extract the higher image. The output data of the 2 interpolation lter can update the 14-bit DAC directly or undergo a zero-stufng process to increase the DAC update rate by another factor of 2. This action enhances the relative signal level and pass-band atness of the higher images.

DIGITAL MODES OF OPERATION

The AD9772A features four different digital modes of operation controlled by the digital inputs, MOD0 and MOD1. MOD0 con

trols the 2 digital lter’s response (i.e., low-pass or highpass), while MOD1 controls the zero-stufng option. The selected mode as shown in Table II will depend on whether the application requires the reconstruction of a baseband or IF signal.

Table II. Digital Modes

Digital Digital ZeroMode MOD0 MOD1 Filter Stufng

Baseband 0 0 Low No Baseband 0 1 Low Yes Direct IF 1 0 High No Direct IF 1 1 High Yes

Applications requiring the highest dynamic range over a wide bandwidth should consider operating the AD9772A in a baseband mode. Note, the zero-stufng option can also be used in this mode, however, the ratio of signal to image power will be reduced. Applications requiring the synthesis of IF signals should consider operating the AD9772A in a Direct IF mode. In this case, the zero-stufng option should be considered when synthesizing and selecting IFs beyond the input data rate, f reconstructed IF falls below f

, the zero-stufng option may

DATA

. If the

or may not be benecial. Note, the dynamic range (i.e., SNR/ SFDR) is also optimized by disabling the PLL clock multiplier (i.e., PLLVDD to PLLCOM) and by using an external low jitter clock source operating at the DAC update rate, f

DAC

.

2 Interpolation Filter Description

The 2 interpolation lter is based on a 43-tap half-band symmetric FIR topology that can be congured for a low- or high-pass response, depending on the state of the MOD0 con

trol input. The low-pass response is selected with MOD0 low while the high-pass response is selected with MOD0 high. The low-pass frequency and impulse response of the halfband interpolation lter are shown in Figures 2a and 2b, while Table I lists the idealized lter coefcients. Note that a FIR lter’s impulse response is also represented by its idealized lter coefcients.

The 2 interpolation lter essentially multiplies the input data rate to the DAC by a factor of 2, relative to its original input data rate, while reducing the magnitude of the rst image associated with the original input data rate occurring at f

DATA

– f

FUNDAMENTAL

. Note, as a result of the 2 interpolation, the digital lter’s frequency response is uniquely dened over its Nyquist zone of dc to f

DATA

,

with mirror images occurring in adjacent Nyquist zones.

The benets of an interpolation lter are clearly seen in Figure 5, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to the 2 digital interpolation lter in a low-pass configuration. Images of the sine wave signal appear around multiples of the DAC’s input data rate (i.e., f

) as predicted

DATA

by sampling theory. These undesirable images will also appear at the output of a reconstruction DAC, although attenuated by the DAC’s sin(x)/x roll-off response.

In many band-limited applications, the images from the reconstruction process must be suppressed by an analog lter following the DAC. The complexity of this analog lter is typically determined by the proximity of the desired fundamental to the rst image and the required amount of image suppression. Adding to the complexity of this analog lter may be the requirement of compensating for the DAC’s sin(x)/x response.

–11–

AD9772A

–13–

2

2  f

DATA

f

DATA

DAC

2f

DATA

f

DATA

1

ST

IMAGE

SUPPRESSED

1STIMAGE

2f

DATA

f

DATA

f

FUNDAMENTAL

DIGITAL

FILTER

RESPONSE

NEW

1STIMAGE

2f

DATA

f

DATA

f

FUNDAMENTAL

FREQUENCY

DOMAIN

1/ 2

f

DATA

1/ f

DATA

TIME

DOMAIN

INPUT DATA

LATCH

2 INTERPOLATION

FILTER

DAC'S SIN (X)/X

RESPONSE

2

2  f

DATA

f

DATA

2f

DATA

f

DATA

1

ST

IMAGE

SUPPRESSED

f

FUNDAMENTAL

2f

DATA

f

DATA

DIGITAL

FILTER

RESPONSE

UPPER AND

LOWER IMAGE

2f

DATA

f

DATA

f

FUNDAMENTAL

FREQUENCY

DOMAIN

1/ 2f

DATA

1/ f

DATA

TIME

DOMAIN

DAC

INPUT DATA

LATCH

2 INTERPOLATION

FILTER

DAC'S SIN (X)/X

RESPONSE

REV. B

Referring to Figure 5, the new rst image associated with the DAC’s higher data rate after interpolation is pushed out further relative to the input signal, since it now occurs at 2 f

DATA

– f

FUNDAMENTAL

. The old rst image associated with the lower DAC data rate before interpolation is suppressed by the digital lter. As a result, the transition band for the analog reconstruction lter is increased, thus reducing the complexity of the analog lter. Furthermore, the sin(x)/x roll-off over the original input data pass band (i.e., dc to f

/2) is signicantly reduced.

DATA

As previously mentioned, the 2 interpolation lter can be converted into a high-pass response, thus suppressing the fundamental while passing the original rst image occurring at f

DATA

– f

FUNDAMENTAL

. Figure 6 shows the time and frequency representation for a high-pass response of a discrete time sine wave. This action can also be modeled as a 1/2 wave digital mixing process in which the impulse response of the low-pass lter is digitally mixed with a square wave having a frequency of exactly

f

/2. Since the even coefcients have a zero value (refer to

DATA

Table I), this process simplies into inverting the center coefcient of the low-pass lter (i.e., invert H(18)). Note that this also corresponds to inverting the peak of the impulse response shown in Figure 2a. The resulting high-pass frequency response becomes the frequency inverted mirror image of the low-pass lter response shown in Figure 2b.

It is worth noting that the new rst image now occurs at f f

FUNDAMENTAL

exists for image selection, thus mandating that the f

. A reduced transition region of 2  f

FUNDAMENTAL

DATA

+

be placed sufciently high for practical ltering purposes in direct IF applications. Also, the lower side-band images occurring at f

– f

DATA

f

FUNDAMENTAL

) experience a frequency inversion while the upper sideband images occurring at f multiples (i.e., N  f

and its multiples (i.e., N  f

+ f

DATA

+ f

FUNDAMENTAL

) do not.

–

DATA

and its

Figure 5. Time and Frequency Domain Example of Low-Pass 2 Digital Interpolation Filter

Figure 6. Time and Frequency Domain Example of High-Pass 2 Digital Interpolation Filter

–12–

REV. B

AD9772A

FREQUENCY (f

DATA

)

0

–10

–40

0

4.00.5 1.0 1.5 2.0 2.5

3.0

3.5

–20

–30

WITH ZERO-STUFFING

WITHOUT

ZERO-STUFFING

BASEBAND

REGION

dBFS

CHARGE

PUMP

PHASE

DETECTOR

EXT/IN

T

CLOCK CONTROL

PRESCALER

CLKVDD

OUT1



CLKCOM

MOD1

MOD0

RESET

CLK+

LPF

PLL

VDD

DNC

2.7V TO

3.6V

PLL

COM

DIV1

DIV0

CLOCK

DISTRIBUTION

–+

PLLLOCK

CLK–

VCO

AD9772A

Zero-Stufng Option Description

As shown in Figure 7, a zero or null in the frequency responses (after interpolation and DAC reconstruction) occurs at the nal DAC update rate (i.e., 2 f

) due to the DAC’s inherent

DATA

sin(x)/x roll-off response. In baseband applications, this roll-off in the frequency response may not be as problematic since much of the desired signal energy remains below f

/2 and the ampli-

DATA

tude variation is not as severe. However, in direct IF applications interested in extracting an image above f

/2, this roll-off may

DATA

be problematic due to the increased pass-band amplitude variation as well as the reduced signal level of the higher images.

Figure 7. Effects of Zero-Stufng on DAC’s Sin(x)/x Response

For instance, if the digital data into the AD9772A represented a baseband signal centered around f f

/10, the reconstructed baseband signal out of the AD9772A

DATA

/4 with a pass band of

DATA

would experience only a 0.18 dB amplitude variation over its pass

band with the rst image occurring at 7/4 f

17 dB of at

tenuation relative to the fundamental. However, if the

DATA

high-pass lter response was selected, the AD9772A would now produce pairs of images at [(2N + 1)  f

DATA

] ± f

DATA

N = 0, 1. . . Note, due to the DAC’s sin(x)/x response, only the lower or upper side-band images centered around f

DATA

useful, although they would be attenuated by –2.1 dB and –6.54 dB, respectively, as well as experience a pass-band amplitude roll-off of 0.6 dB and 1.3 dB.

To improve upon the pass-band atness of the desired image and/or to extract higher images (i.e., 3  f

DATA

± f

FUNDAMENTAL

the zero-stufng option should be employed by bringing MOD1 pin high. This option increases the effective DAC up

date rate by another factor of 2 since a midscale sample (i.e., 10 0000 0000 0000) is inserted after every data sample originating from the 2 interpolation lter. A digital multiplexer at a rate of 4  f and a data register containing the midscale data sample is used to

DATA

between the interpolation

lter’s output

implement this option as shown in Figure 6. Therefore, the DAC output is now forced to return to its differential midscale current value (i.e., I

OUTA

– I

@ 0 mA) after reconstructing each data

OUTB

sample from the digital lter.

The net effect is to increase the DAC update rate such that the zero in the sin(x)/x frequency response now occurs at 4  f along with a corresponding reduction in output power as shown

REV. B

with

/4 where

may be

the

switching

DATA

in Figure 7. Note that if the 2 interpolation lter’s high-pass response is also selected, this action can be modeled as a 1/4 wave digital mixing process, since this is equivalent to digitally mixing the impulse response of the low-pass lter with a square wave having a frequency of exactly f

DATA

(i.e., f

DAC

/4).

It is important to realize that the zero-stufng option by itself does not change the location of the images but rather their signal level, amplitude atness, and relative weighting. For instance, in the previous example, the pass-band amplitude atness of the lower and upper side-band images centered around f improved to 0.14 dB and 0.24 dB, respectively, while the signal level has changed to –6.5 dBFS and –7.5 dBFS. The lower or upper side-band image centered around 3  f

DATA

amplitude atness of 0.77 dB and 1.29 dB with signal levels of approximately –14.3 dBFS and –19.2 dBFS.

PLL CLOCK MULTIPLIER OPERATION

The phase-lock loop (PLL) clock multiplier circuitry, along with the clock distribution circuitry, can produce the necessary

internally synchronized 1, 2, and 4 clocks for the

edge

triggered latches, 2 interpolation lter, zero-stufng multiplier, and DAC. Figure 8 shows a functional block diagram of detec

the PLL clock multiplier, which consists of a phase

tor, a charge pump, a voltage controlled oscillator (VCO), a prescaler, and digital control inputs/outputs. The clock distribution circuitry generates all the internal clocks for a given mode of operation. The charge pump and VCO are powered from

PLLVDD, while the differential clock input buffer, phase de

tector, prescaler, and clock distribution circuitry are powered from CLKVDD. To ensure optimum phase noise performance from the PLL clock multiplier and clock dis

tribution circuitry, PLLVDD and CLKVDD must originate

from the same clean analog supply.

)

Figure 8. Clock Multiplier with PLL Clock Multiplier Enabled

The PLL clock multiplier has two modes of operation. It be

enabled for less demanding applications, providing a reference clock meeting the minimum specied input data rate of 6 MSPS. It can be disabled for applications below this data rate or for ap

plications requiring higher phase noise performance. In this case, a reference clock at twice the input data rate (i.e., 2  f must be provided without the zero-stufng option selected and four

–13–

are

DATA

will exhibit an

can

)

DATA

AD9772A

–15–

FREQUENCY OFFSET (MHz)

0

–10

–110

0

NOISE DENSITY (dBm/Hz)

–30

–50

–70

–90

1 2

3

4

5

–100

–80

–60

–40

–20

PLL OFF, f

DATA

= 50MSPS

PLL ON, f

DATA

= 50MSPS

PLL ON, f

DATA

= 75MSPS

PLL ON, f

DATA

= 100MSPS

PLL ON, f

DATA

= 160MSPS

FREQUENCY (MHz)

10

–10

–110

120

AMPLITUDE (dBm)

–30

–50

–70

–90

122 124 126 128 130

REV. B

times the input data rate (i.e., 4  f

) with the zero-stufng

DATA

option selected. Note, multiple AD9772A devices can be synchronized in either mode if driven by the same reference clock, since the PLL clock multiplier when enabled ensures synchronization. RESET can be used for synchronization if the PLL clock multiplier is disabled.

Figure 8 shows the proper conguration used to enable the PLL clock multiplier. In this case, the external clock source is applied to CLK+ (and/or CLK–) and the PLL clock multiplier is fully enabled by connecting PLLVDD to CLKVDD.

The settling/acquisition time characteristics of the PLL are also dependent on the divide-by-N ratio as well as the input data rate. increasing data

In general, the acquisition time increases with

rate (for xed divide-by-N ratio) or increasing

divide-by-N ratio (for xed input data rate).

Since the VCO can operate over a 96 MHz to 400 MHz range, the prescaler divide-by-ratio following the VCO must be set ac

cording to Table III for a given input data rate (i.e., f

DATA

) to ensure optimum phase noise and successful locking. In general, the best phase noise performance for any prescaler setting is achieved with the VCO operating near its maximum output fre

quency of 400 MHz. Note, the divide-by-N ratio also depends on whether the zero-stufng option is enabled since this option requires the DAC to operate at 4 the input data rate. The di

vide-by-N ratio is set by DIV1 and DIV0.

With the PLL clock multiplier enabled, PLLLOCK serves as an active high control output that may be monitored upon system power-up to indicate that the PLL is successfully locked to the input clock. Note, when the PLL clock multiplier is not locked, PLLLOCK will toggle between logic high and low in an asynchronous manner until locking is nally achieved. As a result, it is recommended that PLLLOCK, if monitored, be sampled several times to detect proper locking 100 ms after power-up.

The effects of phase noise on the AD9772A’s SNR performance become more noticeable at higher reconstructed output frequencies and signal levels. Figure 9 compares the phase noise of a full-scale sine wave at exactly f

/4 at different data rates

DATA

(therefore carrier frequency) with the optimum DIV1, DIV0 setting. The effects of phase noise, and its effect on a signal’s CNR performance, become even more evident at higher IF frequencies as shown in Figure 10. In both instances, it is the narrow-band phase noise that limits the CNR performance.

Figure 9. Phase Noise of PLL Clock Multiplier at Exact f

= f

OUT

/4 at Different f

DATA

Settings with Optimum

DATA

DIV0/DIV1 Settings Using R & S FSEA30, RBW = 30 kHz

Table III. Recommended Prescaler Divide-by-N Ratio Settings

f

Divide-by-

DATA

(MSPS) MOD1 DIV1 DIV0 Ratio

48–160 0 0 0 1 24–100 0 0 1 2 12–50 0 1 0 4 6–25 0 1 1 8 24–100 1 0 0 1 12–50 1 0 1 2 6–25 1 1 0 4 3–12.5 1 1 1 8

As stated earlier, applications requiring input data rates below 6 MSPS must disable the PLL clock multiplier and provide an external reference clock. However, applications already containing a low phase noise (i.e., jitter) reference clock that is twice (or four times) the input data rate should consider disabling the PLL clock multiplier to achieve the best SNR performance from the AD9772A. Note that the SFDR performance and wideband noise performance of the AD9772A remain unaffected with or without the PLL clock multiplier enabled.

N

Figure 10. Direct IF Mode Reveals Phase Noise Degradation with and without PLL Clock Multiplier (IF = 125 MHz and f

= 100 MSPS)

DATA

To disable the PLL clock multiplier, connect PLLVDD to PLL

COM as shown in Figure 11. LPF may remain open since this portion of the PLL circuitry is now disabled. The differential clock input should be driven with a reference clock twice the data input rate in baseband applications and four times the data input rate in direct IF applications in which the 1/4 wave mixing option is employed (i.e., MOD1 and MOD0 active high). The clock distribution circuitry remains enabled providing a 1 internal clock at PLLLOCK. Digital input data is latched into the AD9772 on every other rising edge of the differential clock input. The rising

–14–

REV. B

edge that corresponds to the input latch immediately precedes

CHARGE

PUMP

PHASE

DETECTOR

EXT/IN

T

CLOCK CONTROL

PRESCALER

CLKVDD

OUT1



CLKCOM

MOD1

MOD0

RESET

CLK+

LPF

PLL VDD

PLL

COM

DIV1

DIV0

CLOCK

DISTRIBUTION

–+

PLLLOCK

CLK–

VCO

AD9772A

DIGITAL DATA IN

EXTERNAL

2 CLK

DELAYED INTERNAL

1 CLK

LOAD DEPENDENT

DELAYED 1 CLK

AT PLLLOCK

I

OUTA

OR I

OUTB

DATA

t

LPW

t

D

t

PD

t

PD

DATA ENTERS INPUT LATCHES ON THIS EDGE

[ T ]

1

2

3

T

CH1 2.00V CH2 2.00V M 10.0ns CH3 2.00V

T

EXTERNAL

2 CLOCK

PLLLOCK

RESET

[ T ]

1

2

3

T

CH1 2.00V CH2 2.00V M 10.0ns CH4 1.20V CH3 2.00V

EXTERNAL 2 CLOCK

PLLLOCK

RESET

the rising edge of the 1 clock at PLLLOCK. Adequate setup and hold time for the input data as shown in Figure 1b should be allowed. Note that enough delay is present between CLK+/ CLK– and the data input latch to cause the minimum setup time for input data to be negative. This is noted in the Digital Specications section. PLLLOCK contains a relatively weak driver output, with its output delay (tOD) sensitive to output capacitance loading. Thus PLLLOCK should be buffered for fanouts greater than 1, and/or load capacitance greater than 10 pF. If a data timing issue exists between the AD9772A and its external driver device, the 1 clock appearing at PLLLOCK can be inverted via an external gate to ensure proper setup and hold time.

AD9772A

Figure 12. Internal Timing of AD9772A with PLL Disabled

Figures 13a and 13b illustrate the details of the RESET func-

tion timing. RESET going from a high to a low logic level

enables the 1 clock output, generated by the PLLLOCK

pin. If RESET goes low at a time well before the rising edge

of the 2 clock as shown in Figure 13a, then PLLLOCK will

go high on the following edge of the 2 clock. If RESET goes

from a high to a low logic level 600 ps or later following the

rising edge of the 2 clock as shown in Figure 13b, there will

be a delay of one 2 clock cycle before PLLLOCK goes high.

In either case, as long as RESET remains low, PLLLOCK will

change state on every rising edge of the 2 clock. As stated

before, it is the rising edge of the 2 clock that immediately

precedes the rising edge of PLLLOCK that latches data into the

AD9772A input latches.

Figure 11. Clock Multiplier with PLL Clock Multiplier Disabled

SYNCHRONIZATION OF CLK/DATA USING RESET WITH PLL DISABLED

The relationship between the internal and external clocks in this mode is shown in Figure 12. A clock at the output update data rate (2 the input data rate) must be applied to the CLK inputs. Internal dividers create the internal 1 clock necessary for the input latches. With the PLL disabled, a delayed version of the 1 clock is present at the PLLLOCK pin. The DAC latch is updated on the particular rising edge of the external 2 clock, which corresponds to the rising edge of the 1 clock. Updates to the input data should be synchronized to this specic rising edge as shown in Figure 12. To ensure this synchronization, a Logic 1 should be momentarily applied to the RESET pin on power-up, before CLK is applied. Applying a momentary Logic 1 to RESET brings the 1 clock at PLLLOCK to a Logic 1. On the next rising edge of the 2 clock, the 1 clock will go to Logic 0. The following rising edge of the 2 clock will cause the 1 clock to go to Logic 1 again, as well as update the data in both of the input latches.

REV. B

Figure 13a. RESET Timing with PLL Disabled

–15–

Figure 13b. RESET Timing with PLL Disabled and Insufcient Set-Up Time

AD9772A

–17–

REFIO

FSADJ

250pF

REFLO AVDD

AD9772A

R

SET

2k

0.1F

ACOM

CURRENT

SOURCE

ARRAY

I

OUTA

I

OUTB

INTERPOLATED

DIGITAL DATA

R

LOAD

R

LOAD

V

DIFF

= V

OUTA

– V

OUTB

I

OUTA

I

OUTB

SEGMENTED

SWITCHES

LSB

SWITCHES

+1.2V REF

2.7V TO 3.6V

I

REF

I DAC CODE/ I

OUTA OUTFS

=

( )

×16384

I DAC CODE I

OUTB OUTFS

=

( )

×16383 – /16384

I I

OUTFS REF

= ×32

I V R

REF REFIO SET

= /

V I R

OUTA OUTA LOAD

= ×

V I R

OUTB OUTB LOAD

= ×

V I I R

DIFF OUTA OUTB LOAD

=

( )

×–

V DAC CODE –

R R V

DIFF

LOAD SET REFIO

=

( )

[ ]

×

( )

×

2 16383 16384

32

/

REV. B

DAC OPERATION

The 14-bit DAC along with the 1.2 V reference and reference control amplier is shown in Figure 14. The DAC consists of a large PMOS current source array capable of providing up to 20 mA of full-scale current, I

. The array is divided

OUTFS

into 31 equal currents that make up the ve most signicant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose values are 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits’ current sources. All of these current sources are switched to one or the other of two output nodes (i.e., I

OUTA

or I

) via PMOS differential current switches.

OUTB

Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC’s high output impedance.

As previously mentioned, I current I and external resistor, R

, which is nominally set by a reference voltage V

REF

SET

is a function of the reference

OUTFS

. It can be expressed as

REFIO

(3)

where:

(4)

The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, I and I loads, R that R by I

should be directly connected to matching resistive

OUTB

, that are tied to analog common, ACOM. Note

LOAD

may represent the equivalent load resistance seen

LOAD

OUTA

or I

as would be the case in a doubly terminated

OUTB

OUTA

50 W or 75 W cable. The single-ended voltage output appearing at the I

OUTA

and I

nodes is simply

OUTB

(5)

(6)

Note that the full-scale value of V

OUTA

and V

should not

OUTB

exceed the specied output compliance range of 1.25 V to prevent signal compression. To maintain optimum distortion and linearity performance, the maximum voltages at V and V

The differential voltage, V

I

OUTB

should not exceed ±500 mV p-p.

OUTB

, appearing across I

DIFF

, is

OUTA

and

(7)

Substituting the values of I

OUTA

, I

OUTB

and I

REF

; V

DIFF

can be

expressed as

,

Figure 14. Block Diagram of Internal DAC, 1.2 V Reference, and Reference Control Circuits

The full-scale output current is regulated by the reference control amplier and can be set from 2 mA to 20 mA via an external resistor, R

, as shown in Figure 14. R

SET

combination with both the reference control amplier and voltage reference, REFIO, sets the reference current, I which is mirrored to the segmented current sources with the proper scaling factor. The full-scale current, I 32 times the value of I

REF

.

DAC TRANSFER FUNCTION

The AD9772A provides complementary current outputs, I

and I

OUTA

output, = 16383)

I

. I

OUTB

, when all bits are high (i.e., DAC CODE

OUTF S

while I

will provide a near full-scale current

OUTA

, the complementary output,

OUTB

current. The current output appearing at I is a

function of both the input code and I

ex

pressed as

where DAC CODE = 0 to 16383 (i.e., decimal representation).

OUTFS

provides no

and I

OU

TA

and can be

OUTFS

(1)

, in

SET

,

REF

, is exactly

OUTB

(2)

(8)

The last two equations highlight some of the advantages of operating the AD9772A differentially. First, the differential operation will help cancel common-mode error sources such as noise, distortion, and dc offsets associated with I I

. Second, the differential code-dependent current and

OUTB

subsequent voltage, V ended voltage output (i.e., V

, is twice the value of the single-

DIFF

OUTA

or V

), thus providing

OUTB

twice the signal power to the load.

Note that the gain drift temperature performance for a singleended (V

OUTA

and V

) or differential output (V

OUTB

DIFF

AD9772A can be enhanced by selecting temperature tracking resistors for R

LOAD

and R

due to their ratiometric relationship

SET

as shown in Equation 8.

REFERENCE OPERATION

The AD9772A contains an internal 1.20 V band gap that can easily be disabled and overridden by an external reference. REFIO serves as either an output or input, depend- ing on whether the internal or external reference is selected. If REFLO is tied to ACOM, as shown in Figure 15, the internal reference is activated, and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 µF or greater from REFIO to REFLO. If any additional loading is required, REFIO should be buffered with an external amplier having an input bias current less than 100 nA.

–16–

and

OUTA

) of the

refer

ence

REV. B

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO AVDD

AD9772A

2k

0.1F

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

2.7V TO 3.6V

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO AVDD

AD9772A

AD1580

2.7V TO 3.6V

REFERENCE

CONTROL

AMPLIFIER

R

SET

I

REF

=

V

REFIO/RSET

10k

V

REFIO

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO AVDD

AD9772A

AD1580

2.7V TO 3.6V

R

SET

10k

AD5220

1.2V

AD9772A

AVDD

I

OUTA

R

LOAD

R

LOAD

I

OUTB

Figure 15. Internal Reference Conguration

The internal reference can be disabled by connecting RE

FLO to AVDD. In this case, an external 1.2 V reference such as the AD1580 may then be applied to REFIO as shown in Figure 16. The external reference may provide either a xed reference voltage to enhance accuracy and drift performance or a vary

ing reference voltage for gain control. Note that the 0.1 µF compensation capacitor is not required since the internal

reference is disabled, and the high input impedance

of REFIO minimizes any loading of the external reference.

Figure 16. External Reference Conguration

REFERENCE CONTROL AMPLIFIER

The AD9772A also contains an internal control amplier that is used to regulate the DAC’s full-scale output current, I The control amplier is congured as a V-I converter, as shown in Figure 16, such that its current output, I by

the ratio of the V

Equation 4. I

REF

the proper scaling factor to set I

and an external resistor, R

REFIO

is copied to the segmented current sources with

as stated in Equation 3

OUTFS

, is determined

REF

, as stated

SET

The control amplier allows a wide (10:1) adjustment span of I

over a 2 mA to 20 mA range by setting I

OUTFS

62.5

µA and 625 µA. The wide adjustment span of I

between

REF

OUTFS

vides several application benets. The rst benet relates directly to the power dissipation of the AD9772’s DAC, which is proportional to I

(refer to the Power Dissipation section).

OUTFS

second benet relates to the 20 dB adjustment, which is use for system gain control purposes.

I

can be controlled using the single-supply circuit shown in

REF

Figure 17 for a xed R ence is disabled, and the voltage of REFIO is varied over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply DAC or digital potentiometer, thus allowing I

to be digitally controlled for a xed R

REF

example shows the AD5220, an 8-bit serial input digital potentiometer, along with the AD1580 voltage reference. Note, since

REV. B

. In this example, the internal refer-

SET

. This particular

SET

OUTFS

in

pro-

The

ful

AD9772A

the input impedance of REFIO does interact and load the digital potentiometer wiper to create a slight nonlinearity in the pro

grammable voltage divider ratio, a digital potentiometer with

10 kW or less resistance is recommended.

Figure 17. Single-Supply Gain Control Circuit

ANALOG OUTPUTS

The AD9772A produces two complementary current outputs, I

and I

OUTA

or differential operation. I into complementary single-ended voltage outputs, V V

, via a load resistor, R

OUTB

Transfer Function section, by Equations 5 through 8. The differential voltage, V also be converted to a single-ended voltage via a transformer or differential amplier conguration.

Figure 18 shows the equivalent analog output circuit of the AD9772A, which consists of a parallel combination of PMOS differential current switches associated with each segmented current source. The output impedance of I is determined by the equivalent parallel combination of the PMOS switches and is typically 200 kW in parallel with 3 pF. Due to the nature of a PMOS device, the output impedance is also slightly dependent on the output voltage (i.e., V and V

OUTB

AVDD, and full-scale current, I impedance’s signal dependency can be a source of dc non-

.

linearity and ac linearity (i.e., distortion), its effects can be limited if certain precautions are noted.

.

Figure 18. Equivalent Analog Output Circuit

I

and I

OUTA

compliance range. The negative output compliance range of –1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9772A. The positive output compliance range is

–17–

, which may be congured for single-ended

OUTB

, existing between V

DIFF

and I

OUTA

, as described in the DAC

LOAD

can be converted

OUTB

OUTA

and V

and I

OUTA

OUTB

OUTA

and

, can

) and, to a lesser extent, the analog supply voltage,

. Although the output

OUTFS

also have a negative and positive voltage

OUTB

AD9772A

–19–

V

THRESHOLD

DVDD= ±

( )



2 20%

DIGITAL

INPUT

DVDD

R

SERIES

V

THRESHOLD

AD9772A

CLK+

CLKVDD

CLK–

CLKCOM

0.1F

1k

REV. B

slightly dependent on the full-scale output current, I

OUTFS

. Operation beyond the positive compliance range will induce clipping of the output signal, which severely degrades the AD9772A’s linearity and distortion performance.

Operating the AD9772A with reduced voltage output swings at I

OUTA

and I

in a differential or single-ended output

OUTB

conguration reduces the signal dependency of its output impedance, thus enhancing distortion performance. Although the voltage compliance range of I

OUTA

and I

OUTB

extends from –1.0 V to +1.25 V, optimum distortion performance is achieved when the maximum full-scale signal at I and I

does not exceed approximately 0.5 V. A properly

OUTB

OUTA

selected transformer with a grounded center tap will allow the AD9772A to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at I

and I

OUTA

ential or single-ended output conguration should size R

. DC-coupled applications requiring a differ-

OUTB

LOAD

accordingly. Refer to Applying the AD9772A Output Congurations section for examples of various output congurations.

The most signicant improvement in the AD9772A’s distortion and noise performance is realized using a differential output conguration. The common-mode error sources of both I and I

can be substantially reduced by the common-mode

OUTB

OUTA

rejection of a transformer or differential amplier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more signicant as the reconstructed waveform’s frequency content increases and/or its amplitude decreases. The distortion and noise performance of the AD9772A is also dependent on the fullscale current setting, I 2 mA and 20 mA, selecting an I

OUTFS

. Although I

of 20 mA will provide the

OUTFS

can be set between

OUTFS

best distortion and noise performance.

In summary, the AD9772A achieves the optimum distortion and noise performance under the following conditions:

1. Positive voltage swing at I

OUTA

and I

limited to 0.5 V.

OUTB

2. Differential operation.

3. I

set to 20 mA.

OUTFS

4. PLL clock multiplier disabled.

Note that the majority of the ac characterization curves for the AD9772A are performed under the above-mentioned operating conditions.

The digital interface is implemented using an edge-triggered master slave latch and is designed to support an input data high as 160 MSPS.

The clock can be operated at any

rate

duty cy

as

cle that meets the specied latch pulsewidth as shown in Figures 1a and 1b. The setup and hold times can also be varied within the clock cycle as long as the specied minimum times are met. The digital inputs (excluding CLK+ and CLK–) are CMOS compatible with its logic thresholds, V

THRESHOLD

, set to approximately half

the digital positive supply (i.e., DVDD or CLKVDD) or

The internal digital circuitry of the AD9772A is capable of operating over a digital supply range of 3.1 V to 3.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage of the TTL drivers V cally ensure series 200

proper compatibility with most TTL logic families,

W resistors are recommended between the TTL logic

OH(MAX)

. Although a DVDD of 3.3 V will typi-

driver and digital inputs to limit the peak current through the ESD protection diodes if V

exceeds DVDD by more than

OH(MAX)

300 mV. Figure 19 shows the equivalent digital input circuit for the data and control inputs.

Figure 19. Equivalent Digital Input

The AD9772A features a exible differential clock input operating from separate supplies (i.e., CLKVDD, CLKCOM) to achieve optimum jitter performance. The two clock inputs, CLK+ and CLK–, can be driven from a single-ended or differential clock source. For single-ended operation, CLK+ should be driven by a single-ended logic source while CLK– should be set to the logic source’s threshold voltage via a resistor divider/capacitor network referenced to CLKVDD as shown in Figure 20. For differential operation, both CLK+ and CLK– should be biased to CLKVDD/2 via a resistor divider network as shown in Figure 21. An RF transformer as shown in Figure 3 can also be used to convert a single-ended clock input to a differential clock input.

DIGITAL INPUTS/OUTPUTS

The AD9772A consists of several digital input pins used for data, clock, and control purposes. It also contains a single digital output pin, PLLLOCK, which is used to monitor the status of the internal PLL clock multiplier or provide a 1 clock output. The 14-bit parallel data inputs follow standard positive binary coding, where DB13 is the most signicant bit (MSB) and DB0 is the least signicant bit (LSB). I

OUTA

produces a full-scale output current when all data bits are at Logic 1. I full-scale current split between the two outputs as a function of the input code.

produces a complementary output with the

OUTB

–18–

Figure 20. Single-Ended Clock Interface

REV. B

AD9772A

–19

AD9772A

CLK+

CLKVDD

CLK–

CLKCOM

0.1F

1k

ECL/PECL

The quality of the clock and data input signals are important in

will manifest itself as phase noise on a reconstructed waveform,

the high gain-bandwidth product of the AD9772A’s differential

to 200

) between the

AD9772A digital inputs and driver outputs may be helpful in

The AD9772A has a SLEEP function that turns off the output

be activated by applying a Logic Level 1 to the SLEEP pin. The

AD9772A takes less than 50 ns to power down and approximately

The power dissipation, P

D

AVDD, PLLVDD, CLKVDD, and DVDD, the power supply

voltages.

The reconstructed digital input waveform.

The power dissipation is directly proportional to the analog sup-

ply current, I

AVDD

DVDD

AVDD

is

DATA

DVDD

is dependent on both the digital input wave-

DATA

DVDD

as a function of full-scale

/f

DATA

) for various update rates with

proportional to the update rate as shown in Figure 23.

RATIO (f

OUT/fDATA

)

100

90

40

0.0

I

DVDD

(mA)

80

70

60

50

0.1 0.2 0.3 0.4 0.5

30

20

10

0

f

DATA

= 160MSPS

f

DATA

= 125MSPS

f

DATA

= 100MSPS

f

DATA

= 65MSPS

f

DATA

= 50MSPS

f

DATA

= 25MSPS

vs. Ratio @ DVDD = 3.3 V

f

DATA

(MSPS)

25

0

CURRENT (mA)

20

15

10

5

50 100 150 200

I

PLLVDD

I

CLKVDD

and I

vs. f

APPLYING THE AD9772A OUTPUT CONFIGURATIONS

The following sections illustrate some typical output con gura-

tions for the AD9772A. Unless otherwise noted, it is assumed

that I

is set to a nominal 20 mA for optimum performance.

transformer or a differential op amp con guration. The trans-

performance and is recommended for any application allowing

A single-ended output is suitable for applications requiring a uni-

polar voltage output. A positive unipolar output voltage will result

and/or I

is connected to an appropriately sized load

LOAD

be con gured as an I-V converter, thus converting I

or I

best dc linearity since I

or I

is maintained at a virtual

AD9772A

–21–

OPTIONAL R

DIFF

R

LOAD

MINI-CIRCUITS

T1-1T

AD9772A

I

OUTA

I

OUTB

AD9772A

I

OUTA

I

OUTB

AD8055

C

OPT

25

225

500

AD9772A

I

OUTA

I

OUTB

AD8057

C

OPT

25 25

225

500

1k

AVDD

AD9772A

I

OUTA

I

OUTB

50 50

V

OUTA

= 0V TO 0.5V

I

OUTFS

= 20mA

REV. B

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differentialto-single-ended signal conversion as shown in Figure 24. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only and its linearity performance degrades at the low end of its frequency range due to core saturation.

Figure 24. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both I at I

OUTA

and I

OUTB

. The complementary voltages appearing

OUTB

(i.e., V

OUTA

and V

) swing symmetrically

OUTB

around ACOM and should be maintained with the specied output compliance range of the AD9772A. A differential resistor, R of the transformer is connected to the load, R sive reconstruction lter or cable. R

, may be inserted into applications in which the output

DIFF

is determined by the

DIFF

LOAD

, via a pas-

transformer’s impedance ratio and provides the proper source termination that results in a low VSWR (Voltage Standing Wave Ratio). Note that approximately half the signal power will be dissipated across R

DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 25. The AD9772A is congured with two equal load resistors, R differential voltage developed across I

OUTA

LOAD

and I

, of 25 W. The

is converted

OUTB

to a single-ended signal via the differential op amp conguration. An optional capacitor can be installed across I

OUTA

and I

OUTB

, forming a real pole in a low-pass lter. The addition of this ca

pacitor also enhances the op amp’s distortion performance by preventing the DAC’s high slewing output from overloading the op amp’s input.

The common-mode rejection of this conguration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8055 is congured to provide some additional signal gain. The op amp must operate from a dual supply since its output is approximately ±1.0 V. A high speed amplier, capable of preserving the differential performance of the AD9772A while meeting other system level objectives (i.e., cost, power), should be selected. The op amp’s differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit.

The differential circuit shown in Figure 26 provides the necessary level shifting required in a single-supply system. In this case, AVDD, the positive analog supply for both the AD9772A and the op amp, is also used to level-shift the differential output of the AD9772A to midsupply (i.e., AVDD/2). The AD8057 is a suitable op amp for this application.

Figure 26. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 27 shows the AD9772A congured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 W cable since the nominal full-scale current, I 20 mA ows through the equivalent R R

represents the equivalent load resistance seen by I

LOAD

The unused output (I directly. Different values of I

) should be connected to ACOM

OUTB

OUTFS

of 25 W. In this case,

LOAD

and R

can be selected

LOAD

OUTFS

OUTA

, of

.

as long as the positive compliance range is adhered to. One ad

ditional consideration in this mode is the integral nonlinearity (INL) as discussed in the Analog Outputs section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output conguration is suggested.

Figure 27. 0 V to 0.5 V Unbuffered Voltage Output

Figure 25. DC Differential Coupling Using an Op Amp

SINGLE-ENDED BUFFERED VOLTAGE OUTPUT

Figure 28 shows a buffered single-ended output conguration in which the op amp U1 performs an I-V conversion on the AD9772A output current. U1 maintains I

OUTA

(or I

OUTB

virtual ground, thus minimizing the nonlinear output imped effect on the DAC’s INL performance as discussed in the Analog Outputs section. Although this single-ended conguration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates is often limited by slewing capabilities. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of

–20–

) at

ance

U1’s

REV. B

AD9772A

I

OUTA

I

OUTB

U1

R

FB

200

C

OPT

I

OUTFS

= 10mA

V

OUT

= –I

OUTFS

 R

FB

+

–

100F ELECTROLYTIC

+

–

10F–22F TANTALUM

0.1F CERAMIC

AVDD

ACOM

TTL/CMOS

LOGIC

CIRCUITS

3.3V

POWER

SUPPLY

FERRITE

BEADS

RFB and I voltage output swing capabilities by scaling I

. The full-scale output should be set within U1’s

OUTFS

and/or RFB. An improvement in ac distortion performance may result with a reduced I

since the signal current U1 will be required to

OUTFS

sink will be subsequently reduced.

Figure 28. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS

The AD9772A contains the following ve power supply inputs: AVDD, DVDD1, DVDD2, CLKVDD, and PLLVDD. The AD9772A is specied to operate over a 3.1 V to 3.5 V supply range, thus accommodating a 3.3 V power supply with up to ±6% regulation. However, the following two conditions must be adhered to when selecting power supply sources for AVDD, DVDD1–DVDD2, CLKVDD, and PLLVDD:

1.

PLLVDD = CLKVDD = 3.1 V–3.5 V when PLL clock multi

plier enabled. (Otherwise PLLVDD = PLLCOM)

2. DVDD1–DVDD2 = CLKVDD ± 0.30 V

To meet the rst condition, PLLVDD must be driven by the same power source as CLKVDD with each supply input independently decoupled with a 0.1 µF capacitor to its respective grounds. To meet the second condition, CLKVDD can share the power supply source as DVDD1–DVDD2, using the decoupling network shown in Figure 29 to isolate digital noise from the sensitive CLKVDD (and PLLVDD) supply. Alternatively, separate precision voltage regulators can be used to ensure that condition two is met.

In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection, placement and routing, and supply bypassing and grounding. Fig

ures 37 to 44 illustrate the recommended printed circuit board ground, power, and signal plane layouts that are implemented on the AD9772A evaluation board.

Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9772A features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. AVDD, CLKVDD, and PLLVDD must be powered from a clean analog supply and decoupled to their respective analog common (i.e., ACOM, CLKCOM, and PLLCOM) as close to the chip as physically possible. Similarly, DVDD1 and DVDD2, the digital supplies, should be decoupled to DCOM.

For those applications requiring a single 3.3 V supply for both the analog, digital, and phase-lock loop supply, a clean and/or CLKVD may be generated using the circuit

AVDD

shown in Figure 29. The circuit consists of a differential LC lter with separate power supply and return lines. Lower noise can be attained using low ESR-type electrolytic and tantalum capacitors.

Figure 29. Differential LC Filter for 3.3 V

Maintaining low noise on power supplies and ground is criti

cal to obtain optimum results from the AD9772A. If properly implemented, ground planes can perform a host of functions on high speed circuit boards, such as bypassing and shielding cur

rent transport. In mixed-signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane conned to the areas covering the analog signal traces, and the digital ground plane conned to areas covering the digital interconnects.

All analog ground pins of the DAC, reference, and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC. On the analog side, this includes the DAC output signal, reference signal, and the supply feeders.

The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct, and as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistors should be considered. The necessity and value of these resistors will be dependent upon the logic family used.

For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices’ Application Note AN-333.

REV. B

–21–

AD9772A

–23–

JTAG

OTHER AD6622s FOR INCREASED CHANNEL CAPACITY

AD9772A

PLLLOCK CLK

SUMMATION

SPORT RCF

CIC

FILTER

NCO QAM

SPORT RCF

CIC

FILTER

NCO

QAM

SPORT RCF

CIC

FILTER

NCO

QAM

SPORT RCF

CIC

FILTER

NCO

QAM

CLK

PORT

AD6622

FREQUENCY (MHz)

–40

–50

–100

0

AMPLITUDE (dBm)

–60

–70

–80

–90

5 10 15 20 3025

–30

–20

FREQUENCY (MHz)

–10

–110

0

AMPLITUDE (dBm)

–30

–50

–70

–90

5

10 15

20 25

–100

–80

–60

–40

–20

REV. B

AD9772A

APPLICATIONS

MULTICARRIER

The AD9772A’s wide dynamic range performance makes it well suited for next generation base station applications in which it reconstructs multiple modulated carriers over a designated frequency band. Cellular multicarrier and multimode radios are often referred to as software radios since the carrier tuning and modulation scheme is software programmable and performed digitally. The AD9772A is the recommended TxDAC in Analog Device SoftCell chipset, which comprises the AD6622, Quadrature Digital Upconverter IC, along with its companion Rx Digital Downconverter IC, the AD6624, and 14-bit, 65 MSPS ADC, the AD6644. Figure 30 shows a generic software radio Tx signal chain based on the AD9772A/AD6622.

Figure 31 shows a spectral plot of the AD9772A operating at

64.54 MSPS, reconstructing eight IS-136 modulated carriers spread over a 25 MHz band. For this particular test scenario, the AD9772A exhibited 74 dBc SFDR performance along with a carrier-to-noise ratio (CNR) of 73 dB. Figure 32 shows a spectral plot of the AD9772A operating at 52 MSPS, reconstructing four equal GSM carriers spread over a 15 MHz band. The SFDR and CNR (in 100 kHz BW) measured to be 76 dBc and 83.4 dB, respectively, along with a channel power of –13.5 dBFS. Note, the test vectors were generated using Rohde & Schwarz’s Win

IQSIM software.

Figure 30. Generic Multicarrier Signal Chain Using the AD6622 and AD9772A

Figure 31. Spectral Plot of AD9772A Reconstructing Eight IS-136 Modulated Carriers @ f PLLVDD = 0

= 64.54 MSPS,

DATA

Figure 32. Spectral Plot of AD9772A Reconstructing Four GSM Modulated Carriers @ f PLLVDD = 0

Although the above IS-136 and GSM spectral plots are representative of the AD9772A’s performance for a particular set of test conditions, the following recommendations are offered to maximize the performance and system integration of the AD9772A into multicarrier applications:

1. To achieve the highest possible CNR, the PLL clock multiplier should be disabled (i.e., PLLVDD to PLLCOM) and the AD9772A’s clock input driven with a low jitter/phase noise clock source at twice the input data rate. In this case, the divide-by-two clock appearing at PLLLOCK should serve as the master clock for the digital upconverter IC(s) such as the AD6622. PLLLOCK should be limited to a fanout of one.

2. The AD9772A achieves its optimum noise and distortion performance when congured for baseband operation along with a differential output and a full-scale current, I to approximately 20 mA.

3. Although the 2 interpolation lters frequency roll-off provides a maximum reconstruction bandwidth of 0.422  f the optimum adjacent image rejection (due to the interpolation process) is achieved (i.e., > 73 dBc) if the maximum channel assignment is kept below 0.400  f

4. To simplify the subsequent IF stages lter requirements (i.e., mixer image and LO rejection), it is often advantageous to offset the frequency band from dc to relax the transition band requirements of the IF lter.

5. Oversampling the frequency band often results in improved SFDR and CNR performance. This implies that the data input rate to the AD9772A is greater than f where f

PASSBAND

is the maximum bandwidth in which the AD9772A will be required to reconstruct and place carriers. The improved noise performance results in a reduction in the TxDAC’s noise spectral density due to the added process gain realized with oversampling. Also, higher oversampling ratios provide greater exibility in the frequency planning.

–22–

= 52 MSPS,

DATA

PASSBAND

.

OUTFS

/0.4

, set

DATA

REV. B

,

AD9772A

–30

CENTER 16.25MHz SPAN 6MHz600kHz

dBm

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

C11

C0 C0

Cu1 Cu1

FREQUENCY (MHz)

0

AMPLITUDE (dBm)

–30

–50

–70

–90

–100

–80

–60

–40

–20

100

200

300

400

A

OUT

(dBFS)

90

85

60

–14

SFDR (IN 25MHz WINDOW) (dBFS)

80

75

70

65

–12 –10 –8 –6 –2–4 0

55

50

325MHz

275MHz

75MHz

125MHz

BASEBAND SINGLE-CARRIER

The AD9772A is also well suited for wideband single-carrier applications such as WCDMA and multilevel QAM whose modulation scheme requires wide dynamic range from the reconstruction DAC to achieve the out-of-band spectral mask as well as the in-band CNR performance. Many of these applications strategically place the carrier frequency at one quarter of the DAC’s input data rate (i.e., f

/4) to simplify the digital modu-

DATA

lator design. Since this constitutes the rst xed IF frequency, the frequency tuning is accomplished at a later IF stage. To enhance the modulation accuracy as well as reduce the shape factor of the second IF SAW lter, many applications will often specify the pass band of the IF SAW lter to be greater than the channel bandwidth. The trade-off is that the TxDAC must now meet the particular application’s spectral mask requirements within the extended pass band of the second IF, which may include two or more adjacent channels.

Figure 33 shows a spectral plot of the AD9772A reconstructing a test vector similar to those encountered in WCDMA applications with the following exception. WCDMA applications prescribe a root raised cosine lter with an alpha = 0.22, which limits the theoretical ACPR of the TxDAC to about 70 dB. This particular test vector represents white noise that has been band-limited by a brick wall band-pass lter with the same pass band such that its maximum ACPR performance is theoretically 83 dB and its peak-to-rms ratio is 12.4 dB. As Figure 33 reveals, the AD9772A is capable of approximately 78 dB ACPR performance when one accounts for the additive noise/distortion contributed by the FSEA30 spectrum analyzer.

should disable the zeros-stufng operation. Also, to minimize the effects of the PLL clock multipliers phase noise as shown in Figure 9, an external low jitter/phase noise clock source equal to 4 f

is recommended.

DATA

Figure 34 shows the actual output spectrum of the AD9772A reconstructing a 16-QAM test vector with a symbol rate of 5 MSPS. The particular test vector was centered at f f

= 100 MSPS, and f

DATA

the pair of images appearing around f

= 400 MHz. For many applications,

DAC

will be more attractive

DATA

/4 with

since they have the attest pass band and highest signal power. Higher images can also be used with the understanding that these images will have reduced pass-band atness, dynamic range, and signal power, thus reducing the CNR and ACP performance. Fig

ure 35 shows a dual-tone SFDR amplitude sweep at the various IF images with f the two tones centered around f

= 100 MSPS and f

DATA

= 400 MHz and

DAC

/4. Note, since an IF lter is assumed to precede the AD9772A, the SFDR was measured over a 25 MHz window around the images occurring at 75 MHz, 125 MHz, 275 MHz, and 325 MHz.

Figure 33. AD9772A Achieves 78 dB ACPR Performance Re

constructing a WCDMA-Like Test Vector with f

65.536 MSPS and PLLVDD = 0

DIRECT IF

As discussed in the Digital Modes of Operation section, the AD9772A can be congured to transform digital data representing baseband signals into IF signals appearing at odd multiples of the input data rate (i.e., N  f is accomplished by conguring the MOD1 and MOD0 digital inputs high. Note, the maximum DAC update rate of 400 MSPS limits the data input rate in this mode to 100 MSPS when the zero-stufng operation is enabled (i.e., MOD1 high). Applications requiring higher IFs (i.e., 140 MHz) using higher data rates

REV. B

Figure 34. Spectral Plot of 16-QAM Signal in Direct IF Mode at f

=

DATA

where N = 1, 3, . . .). This

DATA

Figure 35. Dual-Tone Windowed SFDR vs. A f

= 100 MSPS

DATA

–23–

= 100 MSPS

DATA

OUT

@

AD9772A

–25–

FREQUENCY (MHz)

–10

–110

66

AMPLITUDE (dBm)

–30

–50

–70

–90

68 70 72 74

–80

–60

–40

–20

REV. B

Regardless of which image is selected for a given application, the adjacent images must be sufciently ltered. In most cases, a SAW lter providing differential inputs represents the optimum device for this purpose. For single-ended SAW lters, a balancedto-unbalanced RF transformer is recommended. The AD9772A’s high output impedance provides a certain amount of exibility in selecting the optimum resistive load, R

, as well as any match-

LOAD

ing network.

For many applications, the data update rate to the DAC (i.e., f

) must be some xed integer multiple of some system

DATA

clock (i.e., GSM – 13 MHz). Furthermore, these ap prefer to use standard IF frequencies which offer a large selec SAW lter choices of varying passbands (i.e., 70 MHz). These applications may still benet from the AD9772A’s capabilities when used in conjunction with a

direct IF mode

digital upconverter such as the AD6622. Since the AD6622 can digitally synthesize and tune up to four modulated carriers, it is possible to judiciously tune these carriers in a region which may fall within an IF lter’s pass band upon reconstruction by the AD9772A. Figure 36 shows an example in which four carriers were tuned around 18 MHz with a digital upconverter operating at 52 MSPS such that when reconstructed by the AD9772A in the IF mode, these carriers fall around a 70 MHz IF.

Figure 36. Spectral Plot of Four Carriers at 60 MHz IF with f

AD9772A EVALUATION BOARD

= 52 MSPS, PLLVDD = 0

DATA

The AD9772-EB is an evaluation board for the AD9772A Tx

DAC. Careful attention to layout and circuit design, combined with prototyping area, allows the user to easily and effectively evaluate the AD9772A in different modes of operation.

Referring to Figures 37 and 38, the AD9772A’s performance can be evaluated differentially or single-endedly using a transformer,

reference

plications

tion of

differential amplier, or directly coupled output. To evaluate the output differentially using the transformer, remove ers JP12 and JP13 and monitor the output at J6 (IOUT). To evaluate the output differentially, remove the transformer (T2) and install jumpers JP12 and JP13. The output of the amplier can be evaluated at J13 (AMPOUT). To evaluate the AD9772A single-endedly and directly coupled, remove the transformer and

jumpers (JP12 and JP13), and install resistors R16 or R17

with 0 W.

The digital data to the AD9772A comes across a ribbon cable which interfaces to a 40-pin IDC connector. Proper termination or voltage scaling can be accomplished by installing RN2 and/or RN3 SIP resistor networks. The

22 W DIP

resistor network, RN1, must be installed and helps reduce the digital data edge rates. A single-ended CLOCK input can be supplied via the ribbon cable by installing JP8 or more preferably via the SMA connector, J3 (CLOCK). If the CLOCK is supplied by J3, the AD9772A can installing jump

be congured for a differential clock interface by

ers JP1 and configur ing JP2, JP3, and JP9 for the DF position. To congure the AD9772A clock input for a single-ended clock interface, remove JP1 and congure JP2, JP3, and JP9 for the SE position.

The AD9772A’s PLL clock multiplier can be disabled by conguring jumper JP5 for the L position. In this case, the user must supply a clock input at twice (2) the data rate via J3 (CLOCK). The 1 clock is made available on SMA connector J1 (PLLL and should be used to trigger a pattern generator directly or via a programmable pulse generator. Note that PLLLOCK is capable of providing a 0 V to 0.85 V output into a

50 W load

. To enable the PLL clock multiplier, JP5 must be congured for the H position. In this case, the clock may be supplied via the ribbon cable (i.e., JP8 installed) or J3 (CLOCK). The divide-by-N ratio can be set by conguring JP6 (DIV0) and JP7 (DIV1).

The AD9772A can be congured for baseband or direct IF mode operation by conguring jumpers JP11 (MOD0) and JP10 (MOD1). For baseband operation, JP10 and JP11 should be con

gured in the L position. For direct IF operation, JP10 and JP11 should be congured in the H position. For direct IF operation without zero-stufng, JP11 should be congured in the H position while JP10 should be congured in the low position.

The AD9772A’s voltage reference can be enabled or disabled via JP4 (EXT REF IN). To enable the reference, congure JP in the INT position. A voltage of approximately 1.2 V will appear at the TP6 (REFIO) test point. To disable the internal reference, congure JP4 in the EXT position and drive TP6 with an external voltage reference. Lastly, the AD9772A can be placed in the SLEEP mode by driving the TP11 test point with logic level high input signal.

–24–

jump-

OCK),

REV. B

AD9772A

2 P1 1P1

116

107

9

8

125

134

143

152

161IN13

4 P1 3P1

IN12

6 P1 5P1

IN11

8 P1 7P1

IN10

10 P1 9P1

IN9

12 P1 11P1

IN8

14 P1 13P1

IN7

16 P1 15P1

IN6

6

7

8

5

4

3

2

1

MSB DB13

DB12

DB11

DB10

DB9

DB8

DB7

9

10

DB6

RN2

VALUE

RN1

VALUE

6

7

8

5

4

3

2

1

MSB

IN13

IN12

IN11

IN10

IN9

IN8

IN7

9

10

IN6

RN3

VALUE

18 P1 17P1

116

107

9

8

125

134

143

152

161IN5

20 P1 19P1

IN4

22 P1 21P1

IN3

24 P1 23P1

IN2

26 P1 25P1

IN1

28 P1 27P1

IN0

30 P1 29P1

32 P1 31P1

6

7

8

5

4

3

2

1

DB5

DB4

DB3

DB2

DB1

DB0

CLOCK

9

10

RESET

RN5

VALUE

RN4

VALUE

6

7

8

5

4

3

2

1

IN5

IN4

IN3

IN2

IN1

IN0

INCLOCK

9

10

INRESET

RN6

VALUE

LSB

34 P1 33P1

36 P1 35P1

38 P1 37P1

40 P1 39P1

INCLOCK

INRESET

L1

1

FBEAD 2

DVDD_IN

1

J7

C13 10F 10V

RED

DVDD

TP22

DGND

1

J8

BLK

TP23

RED

AVDD

TP24

C14 10F 10V

L2

1

FBEAD 2

AVDD_IN

1

J9

AGND

1

J10

BLK

TP25

RED

CLKVDD

TP26

L3

1

FBEAD 2

CLKVDD_IN

1

J11

C15 10F 10V

BLK

TP27

CLKGND

1

J12

c

–IN

+IN

U2

–V

+V

AD8055

R15

500

4

7

2

3

OUT

6 1

2

J13

AMPOUT

C18

0.1F

C17

0.1F

BLK TP19

RED TP20

+V

S

–V

S

R14

500

R12

500

R4

500

R11 50

R13 50

C16 100pF

JP13

AMP-B

JP12

AMP-A

IA

IB

REV. B

Figure 37. Drafting Schematic of Evaluation Board

–25–

AD9772A

–27–

36

34

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44 39 38 3743 42 41 40

PIN 1 IDENTIFIER

U1

AD9772A

MSB DB13

DB12 DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DVDD

C8

0.1F

C7

0.1F

TP14

TP15

RED

BLK

IA

IB

REFLO

C6

1F

C5

0.1F

AVDD

RED TP16

BLK

TP17

WHT

TP5

WHT

TP6

REFIO

FSADJ

C4

0.1F

R10

1.91k

R6 50

TP11

SLEEP WHT

REFLO

INT REF

A

B

1

2

3

JP4

EXT REF

AVDD

CLK–

CLK+

DIV0

DIV1

PLL-LOCK

LPF

35

33

R5

VAL

C1

VAL

PLLVDD

NOTE: SHIELD AROUND R5, C1 CONNECTED TO PLLVDD

c

C9 1F

C10

0.1F

CLKVDD

A

B

1

2

3

JP6

A

B

1

2

3

JP5

A

B

1

2

3

JP7

CLKVDD

REDTP7

RESET

TP10 WHT

DB3

DB2

DB1

LSB DB0

TP1

WHT

MOD0

c

A

B

1

2

3

JP11

H

L

H

L

A

B

1

2

3

JP10

DVDD

DGND

MOD1

TP2

WHT

C11

0.1F

C12 1F

DVDD

TP3

WHT

TP4

WHT

1

2

c

J1

TP28 WHT

CONNECT GNDs AS SHOWN UNDER USING BOTTOM SIGNAL LAYER

c

NOTE: LOCATE ALL DECOUPLING CAPS (C5 – C12) AS CLOSE AS POSSIBLE TO DUT, PREFERABLY UNDER DUT ON BOTTOM SIGNAL LAYER.

JP8

EDGE

CLOCK

A

B

1

2

3

JP3

SE

DF

CLKVDD

R2 1k

c

R3 1k

C19

0.1F

A

B

1

2

3

JP2

T1

1

2

3

S

SE

P

6

4

c

JP1

DF

1

2

c

CLOCK

J3

WHT

TP12

A

B

1

2

3

JP9

DF

SE

R1

50

c

T2

3

2

1

S

P

4

6

R17 VAL

R16 VAL

1

2

J6

IOUT

R8 50

C3 10pF

IA

R9 OPT

IB

C2 10pFR750

REV. B

Figure 38. Drafting Schematic of Evaluation Board (continued)

–26–

REV. B

AD9772A

Figure 39. Silkscreen Layer—Top

REV. B

Figure 40. Component Side PCB Layout (Layer 1)

–27–

AD9772A

–29–

REV. B

Figure 41. Ground Plane PCB Layout (Layer 2)

Figure 42. Power Plane PCB Layout (Layer 3)

–28–

REV. B

AD9772A

Figure 43. Solder Side PCB Layout (Layer 4)

REV. B

Figure 44. Silkscreen Layer—Bottom

–29–

AD9772A

–31–

TOP VIEW

(PINS DOWN)

1

12

13

25

24

36

37

48

0.27

0.22

0.17

0.50

BSC

7.00

BSC SQ

SEATING

PLANE

1.60 MAX

0.75

0.60

0.45

VIEW A

9.00 BSC SQ

PIN 1

0.20

0.09

1.45

1.40

1.35

0.08 MAX COPLANARITY

VIEW A

ROTATED 90 CCW

SEATING PLANE

10

6 2

7

3.5  0

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MS-026BBC

REV. B

OUTLINE DIMENSIONS

48-Lead Low Prole Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

–30–

REV. B

AD9772A

Revision History

Location Page

6/03—Data Sheet changed from REV. A to REV. B.

Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Change to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Change to DIGITAL FILTER SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ORERING GUIDE Updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Change to Figure 13a and 13b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Change to DIGITAL INPUTS/OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Change to SLEEP MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Change to Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Change to Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Change to POWER AND GROUND CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Change to Figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Update to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/02—Data Sheet changed from REV. 0 to REV. A.

Edits to DIGITAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Change to TPC 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Change to Figure 9 Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Change to Figure 13a and 13b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REV. B

–31–

C02253–0–6/03(B)

–32–

Datasheet AD9772A Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

DC SPECIFICATIONS

DYNAMIC SPECIFICATIONS

DIGITAL SPECIFICATIONS

DIGITAL FILTER SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

THERMAL CHARACTERISTIC

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Differential Nonlinearity (DNL)

Monotonicity

Offset Error

Gain Error

Output Compliance Range

Temperature Drift

Power Supply Rejection

Settling Time

Glitch Impulse

Spurious-Free Dynamic Range

Total Harmonic Distortion

Signal-to-Noise Ratio (SNR)

Pass Band

Stop-band Rejection

Group Delay

Impulse Response

Adjacent Channel Power Ratio (ACPR)

FUNCTIONAL DESCRIPTION

DIGITAL MODES OF OPERATION

2 Interpolation Filter Description

PLL CLOCK MULTIPLIER OPERATION

SYNCHRONIZATION OF CLK/DATA USING RESET WITH PLL DISABLED

DAC OPERATION

DAC TRANSFER FUNCTION

REFERENCE OPERATION

REFERENCE CONTROL AMPLIFIER

ANALOG OUTPUTS

DIGITAL INPUTS/OUTPUTS

APPLYING THE AD9772A OUTPUT CONFIGURATIONS

DIFFERENTIAL COUPLING USING A TRANSFORMER

DIFFERENTIAL COUPLING USING AN OP AMP

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

SINGLE-ENDED BUFFERED VOLTAGE OUTPUT

POWER AND GROUNDING CONSIDERATIONS

APPLICATIONS

MULTICARRIER

BASEBAND SINGLE-CARRIER

DIRECT IF

AD9772A EVALUATION BOARD

OUTLINE DIMENSIONS

Revision History