Datasheet AD9763 Datasheet (ANALOG DEVICES)

10-/12-/14-Bit, 125 MSPS

Dual TxDAC+ Digital-to-Analog Converters

Data Sheet

FEATURES

10-/12-/14-bit dual transmit digital-to-analog converters (DACs) 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control Dual-port or interleaved data On-chip 1.2 V reference 5 V or 3.3 V operation Power dissipation: 380 mW @ 5 V Power-down mode: 50 mW @ 5 V 48-lead LQFP

APPLICATIONS

Communications Base stations Digital synthesis Quadrature modulation 3D ultrasound

GENERAL DESCRIPTION

The AD9763/AD9765/AD9767 are dual-port, high speed, 2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates two high quality TxDAC+® cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP. The AD9763/ AD9765/AD9767 offer exceptional ac and dc performance while supporting update rates of up to 125 MSPS.

The AD9763/AD9765/AD9767 have been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs.

A mode control pin allows the AD9763/AD9765/AD9767 to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate.

The GAINCTRL pin allows two modes for setting the full-scale current (I independently using two external resistors, or I DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature.

) of the two DACs. I

OUTFS

for each DAC can be set

OUTFS

for both

OUTFS

AD9763/AD9765/AD9767

FUNCTIONAL BLOCK DIAGRAM

DCOM1/

DVDD1/

DCOM2

DVDD2

PORT1

WRT1/IQWRT

WRT2/IQSEL

PORT2

DIGITAL

INTERFACE

MODE

1

LATCH

AD9763/ AD9765/

AD9767

2

LATCH

Figure 1.

The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%.

The AD9763/AD9765/AD9767 are manufactured on an advanced, low cost CMOS process. They operate from a single supply of 3.3 V to 5 V and consume 380 mW of power.

PRODUCT HIGHLIGHTS

1. The AD9763/AD9765/AD9767 are members of a pin-

compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.

2. Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high

performance DACs for each part is optimized for low distortion performance and provides flexible transmission of I and Q information.

3. Matching. Gain matching is typically 0.1% of full scale, and

offset error is better than 0.02%.

4. Low Power. Complete CMOS dual DAC function operates on

380 mW from a 3.3 V to 5 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods.

5. On-Chip Voltage Reference. The AD9763/AD9765/AD9767

each include a 1.20 V temperature-compensated band gap voltage reference.

6. Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767

each feature a flexible dual-port interface, allowing dual or interleaved input data.

CLK1AVDD ACOM

1

DAC

REFERENCE

BIAS

GENERATOR

2

DAC

CLK2/IQ RESET

I

OUTA1

I

OUTB1

REFIO FSADJ1 FSADJ2 GAINCTRL

SLEEP

I

OUTA2

I

OUTB2

00617-001

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9763/AD9765/AD9767 Data Sheet

REVISION HISTORY

Revision History: AD9763/AD9765/AD9767

8/11—Rev. F to Rev. G

Changes to Gain Control Mode Section and Setting the Full-

Scale Current Section..................................................................... 22

Changes to DAC Transfer Function Section............................... 23

Changes to Power Supply Rejection Section............................... 29

6/09—Rev. E to Rev. F

Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91,

Deleted Original Figure 91 to Figure 94...................................... 34

1/08—Revision E: Initial Combined Version

Rev. G | Page 2 of 44

Revision History: AD9763

1/08—Rev. D to Rev. E

Combined with AD9765 and AD9767 Data Sheets.......Universal

Changes to Figure 1...........................................................................1

Changes to Applications Section .....................................................1

Changes to Timing Diagram Section .............................................7

Added Figure 4 and Figure 5............................................................9

Changes to Table 6.......................................................................... 10

Change to Typical Performance Characteristics Section

Conditions Statement .................................................................... 11

Added Figure 23 to Figure 56 ....................................................... 14

Added Note to Figure 58 ............................................................... 20

Changes to Functional Description Section ............................... 22

Changes to Figure 59 and Figure 60............................................. 22

Changes to Gain Control Mode Section ..................................... 22

Data Sheet AD9763/AD9765/AD9767

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section.......................................................22

Changes to DAC Transfer Section ................................................23

Change to Analog Outputs Section ..............................................24

Changes to Dual-Port Mode Timing............................................24

Changes to Interleaved Mode Timing Section ............................25

Added Figure 64 ..............................................................................25

Change to Differential Coupling Using a Transformer Section .....28

Changes to Power and Grounding Considerations Section............ 30

Added VDSL Example Applications Using the AD9765 and

AD9767 Section...............................................................................31

Added Figure 79 to Figure 82........................................................31

Changes to Figure 84 ......................................................................32

Changes to CDMA Section............................................................33

Changes to Figure 85 Caption .......................................................33

Changes to Figure 86 ......................................................................34

Changes to Figure 88 ......................................................................36

Changes to Ordering Guide...........................................................40

9/06—Rev. C to Rev. D

Updated Format.................................................................. Universal

Renumbered Figures.......................................................... Universal

Changes to Specifications Section...................................................3

Changes to Applications Section...................................................21

Updated Outline Dimensions........................................................32

Changes to Ordering Guide...........................................................32

10/01—Rev. B to Rev. C

Changes to Figure 29 ......................................................................21

2/00—Rev. A to Rev. B

12/99—Rev. 0 to Rev. A

Revision History: AD9765

1/08—Rev. C to Rev. E

Combined with AD9763 and AD9767 Data Sheets ...... Universal

Changes to Figure 1...........................................................................1

Changes to Applications Section.....................................................1

Changes to Timing Diagram Section .............................................7

Change to Absolute Maximum Ratings .........................................8

Added Figure 3 and Figure 5 ...........................................................9

Changes to Table 6 ..........................................................................10

Added Figure 6 to Figure 22..........................................................11

Added Figure 40 to Figure 56........................................................17

Added Note to Figure 58 ................................................................20

Changes to Functional Description Section................................22

Changes to Reference Operation Section ....................................22

Changes to Figure 59 and Figure 60 .............................................22

Changes to Gain Control Mode Section ......................................22

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section.......................................................22

Changes to DAC Transfer Section ................................................23

Rev. G | Page 3 of 44

Changes to Interleaved Mode Timing Section............................25

Added Figure 64..............................................................................25

Changes to Power and Grounding Considerations Section............ 30

Added Figure 80 and Figure 82 ..................................................... 31

Changes to Quadrature Amplitude Modulation (QAM)

Example Using the AD9763 Section.............................................32

Changes to Figure 83 and Figure 84 .............................................32

Changes to CDMA Section............................................................33

Changes to Figure 85 Caption .......................................................33

Changes to Figure 86 ......................................................................34

Changes to Figure 88 ......................................................................36

Changes to Ordering Guide...........................................................40

9/06—Rev. B to Rev. C

Updated Format ................................................................. Universal

Changes to Figure 2 .......................................................................... 5

Changes to Figure 3 .......................................................................... 7

Changes to Functional Description Section................................12

Changes to Figure 25 and Figure 26 .............................................15

Changes to Figure 28 and Figure 29 .............................................16

Changes to Power Dissipation Section......................................... 17

Changes to Power and Grounding Considerations Section...... 19

Changes to Figure 39 ......................................................................19

Changes to Figure 45 ......................................................................22

Changes to Evaluation Board Section ..........................................24

Changes to Figure 47 ......................................................................24

Updated Outline Dimensions........................................................30

Changes to Ordering Guide...........................................................30

2/00—Rev. A to Rev. B

12/99—Rev. 0 to Rev. A

8/99—Revision 0: Initial Version

Revision History: AD9767

1/08—Rev. C to Rev. E

Combined with AD9763 and AD9765 Data Sheets...... Universal

Changes to Figure 1 .......................................................................... 1

Changes to Features Section............................................................1

Changes to Applications Section..................................................... 1

Changes to Timing Diagram Section ............................................. 7

Change to Absolute Maximum Ratings ......................................... 8

Added Figure 3 and Figure 4 ...........................................................9

Changes to Table 6 ..........................................................................10

Added Figure 6 to Figure 39..........................................................11

Added Note to Figure 58 ................................................................20

Changes to Functional Description Section................................22

Changes to Reference Operation Section ....................................22

Changes to Figure 59 and Figure 60 .............................................22

Changes to Gain Control Mode Section ......................................22

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section ......................................................22

Changes to DAC Transfer Section ................................................23

AD9763/AD9765/AD9767 Data Sheet

Changes to Dual-Port Mode Timing........................................... 24

Changes to Interleaved Mode Timing Section ........................... 25

Added Figure 64.............................................................................. 25

Change to Differential Coupling Using a Transformer Section......28

Changes to Power and Grounding Considerations Section............ 30

Added Figure 79 and Figure 81..................................................... 31

Added to Quadrature Amplitude Modulation (QAM)

Example Using the AD9763 Section ............................................ 32

Added Figure 83 and Figure 84..................................................... 32

Changes to CDMA Section ........................................................... 33

Changes to Figure 85 Caption....................................................... 33

Changes to Figure 86...................................................................... 34

Changes to Figure 88...................................................................... 36

Changes to Ordering Guide.......................................................... 40

10/06—Rev. B to Rev. C

Updated Format.................................................................. Universal

Changes to Figure 2...........................................................................5

Changes to Figure 3...........................................................................7

Changes to Functional Description Section ............................... 12

Changes to Figure 25 and Figure 26............................................. 15

Changes to Figure 28 and Figure 29............................................. 16

Changes to Power Dissipation Section ........................................ 18

Changes to Figure 39...................................................................... 19

Changes to Power and Grounding Considerations Section ..... 19

Changes to Figure 45...................................................................... 22

Changes to Figure 47...................................................................... 24

Updated Outline Dimensions....................................................... 28

Changes to Ordering Guide.......................................................... 28

2/00—Rev. A to Rev. B

12/99—Rev. 0 to Rev. A

8/99—Revision 0: Initial Version

Rev. G | Page 4 of 44

Data Sheet AD9763/AD9765/AD9767

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 10 12 14 Bits DC ACCURACY1

Integral Linearity Error (INL) −1 ±0.1 +1 LSB

Differential Nonlinearity (DNL) LSB

ANALOG OUTPUT

Offset Error −0.02 +0.02 −0.02 +0.02 −0.02 +0.02 % of FSR Gain Error Without Internal Reference −2 ±0.25 +2 −2 ±0.25 +2 −2 ±0.25 +2 % of FSR Gain Error with Internal Reference −5 ±1 +5 −5 ±1 +5 −5 ±1 +5 % of FSR Gain Match −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 % of FSR

−0.14 +0.14 −0.14 +0.14 −0.14 +0.14 dB Full-Scale Output Current2 2.0 20.0 2.0 20.0 2.0 20.0 mA Output Compliance Range −1.0 +1.25 −1.0 +1.25 −1.0 +1.25 V Output Resistance 100 100 100 kΩ Output Capacitance 5 5 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 1.14 1.20 1.26 1.14 1.20 1.26 V Reference Output Current3 100 100 100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 0.1 1.25 0.1 1.25 V Reference Input Resistance 1 1 1 MΩ Small-Signal Bandwidth 0.5 0.5 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 0 0 ppm of FSR/°C Gain Drift Without Internal Reference ±50 ±50 ±50 ppm of FSR/°C Gain Drift with Internal Reference ±100 ±100 ±100 ppm of FSR/°C Reference Voltage Drift ±50 ±50 ±50 ppm/°C

POWER SUPPLY

Supply Voltages

Analog Supply Current (I Digital Supply Current (I Digital Supply Current (I Supply Current Sleep Mode (I Power Dissipation4 (5 V, I

Power Dissipation5 (5 V, I Power Dissipation6 (5 V, I Power Supply Rejection Ratio7—AVDD –0.4 +0.4 –0.4 +0.4 –0.4 +0.4 % of FSR/V Power Supply Rejection Ratio7—DVDD

OPERATING RANGE –40 +85 –40 +85 –40 +85 °C

1

Measured at I

2

Nominal full-scale current, I

3

An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4

Measured at f

5

Measured at f

6

Measured as unbuffered voltage output with I

7

±10% power supply variation.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

AD9763 AD9765 AD9767

= 20 mA, unless otherwise noted.

OUTFS

TA = 25°C −1.5 ±0.4 +1.5 −3.5 ±1.5 +3.5 LSB T

to T

MIN

−2.0 +2.0 −4.0 +4.0 LSB

MAX

TA = 25°C −0.5 ±0.07 +0.5 −0.75 ±0.3 +0.75 −2.5 ±1.0 +2.5 LSB T

to T

MIN

−1.0 +1.0 −3.0 +3.0 LSB

MAX

AVDD 3 5 5.5 3 5 5.5 3 5 5.5 V DVDD1, DVDD2 2.7 5 5.5 2.7 5 5.5 2.7 5 5.5 V

) 71 75 71 75 71 75 mA

AVDD

)4 5 7 5 7 5 7 mA

DVDD

)5 15 15 15 mA

DVDD

) 8 12.0 8 12.0 8 12.0 mA

AVDD

= 20 mA)

OUTFS

= 20 mA)

OUTFS

= 20 mA) 450 450 450 mW

OUTFS

380 410 380 410 380 410 mW 420 450 420 450 420 450 mW

–0.025 +0.025 –0.025 +0.025 –0.025 +0.025 % of FSR/V

, driving a virtual ground.

OUTA

= 25 MSPS and f

CLK

= 100 MSPS and f

CLK

, is 32 times the I

OUTFS

= 1.0 MHz.

OUT

= 1 MHz.

OUT

current.

REF

= 20 mA and R

OUTFS

= 50 Ω at I

LOAD

OUTA

and I

, f

= 100 MSPS, and f

OUTB

CLK

= 40 MHz.

OUT

Rev. G | Page 5 of 44

AD9763/AD9765/AD9767 Data Sheet

DYNAMIC SPECIFICATIONS

T

to T

MIN

doubly terminated, unless otherwise noted.

Table 2.

AD9763 AD9765 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f Output Settling Time (tST) to 0.1%1 35 35 35 ns Output Propagation Delay (tPD) 1 1 1 ns Glitch Impulse 5 5 5 pV-s Output Rise Time (10% to 90%)1 2.5 2.5 2.5 ns Output Fall Time (90% to 10%)1 2.5 2.5 2.5 ns Output Noise (I Output Noise (I

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

Spurious-Free Dynamic Range Within a Window

Total Harmonic Distortion

Multitone Power Ratio (Eight Tones at 110 kHz Spacing)

Channel Isolation

1

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

) 125 125 125 MSPS

CLK

= 20 mA) 50 50 50 pA/√Hz

OUTFS

= 2 mA) 30 30 30 pA/√Hz

OUTFS

f

= 100 MSPS, f

CLK

= 1.00 MHz

OUT

= 20 mA, differential transformer-coupled output, 50 Ω

OUTFS

0 dBFS Output 69 78 70 81 71 82 dBc –6 dBFS Output 74 77 77 dBc –12 dBFS Output 69 72 73 dBc –18 dBFS Output 61 70 70 dBc

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 100 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 100 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 65 MSPS, f

CLK

= 1.00 MHz 79 81 82 dBc

OUT

= 2.51 MHz 78 79 80 dBc

OUT

= 5.02 MHz 75 78 79 dBc

OUT

= 14.02 MHz 66 68 70 dBc

OUT

= 25 MHz 55 55 55 dBc

OUT

= 25 MHz 67 67 67 dBc

OUT

= 40 MHz 60 60 70 dBc

OUT

= 1.00 MHz; 2 MHz Span 78 85 80 90 82 91 dBc

OUT

= 5.02 MHz; 10 MHz Span 80 88 88 dBc

OUT

= 5.03 MHz; 10 MHz Span 82 88 88 dBc

OUT

= 5.04 MHz; 10 MHz Span 82 88 88 dBc

OUT

= 1.00 MHz −77 −69 −80 –70 −81 −71 dBc

OUT

= 2.00 MHz −77 −78 −79 dBc

OUT

= 4.00 MHz −74 −75 −83 dBc

OUT

= 10.00 MHz −72 −75 −80 dBc

OUT

= 2.00 MHz to 2.99 MHz

OUT

0 dBFS Output 76 80 80 dBc

−6 dBFS Output 74 79 79 dBc

−12 dBFS Output 71 77 78 dBc

−18 dBFS Output 67 75 76 dBc

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

= 10 MHz 85 85 85 dBc

OUT

= 40 MHz 77 77 77 dBc

OUT

Rev. G | Page 6 of 44

Data Sheet AD9763/AD9765/AD9767

DIGITAL SPECIFICATIONS

T

to T

MIN

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V 3.5 5 V Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V 2.1 3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V 0 1.3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (tS) 2.0 ns Input Hold Time (tH) 1.5 ns Latch Pulse Width (t

Timing Diagram

See Tab l e 3 and the DAC Timing section for more information about the timing specifications.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

, t

) 3.5 ns

LPW

CPW

DATA IN

= 20 mA, unless otherwise noted.

OUTFS

t

S

t

H

(WRT2) (WRT1/IQWRT)

(CLK2) (CLK1/IQCLK)

I

OUTA

OR

I

OUTB

t

LPW

t

CPW

t

PD

00617-002

Figure 2. Timing Diagram for Dual and Interleaved Modes

Rev. G | Page 7 of 44

AD9763/AD9765/AD9767 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4.

With

Parameter

AVDD ACOM −0.3 V to +6.5 V DVDD1, DVDD2 DCOM1/DCOM2 −0.3 V to +6.5 V ACOM DCOM1/DCOM2 −0.3 V to +0.3 V AVDD DVDD1/DVDD2 −6.5 V to +6.5 V MODE,

CLK1/IQCLK, CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL

Digital Inputs DCOM1/DCOM2

I

OUTA1/IOUTA2

I

REFIO, FSADJ1,

FSADJ2 GAINCTRL, SLEEP ACOM −0.3 V to AVDD + 0.3 V Junction

Temperature Storage

Temperature

Range Lead Temperature

(10 sec)

,

OUTB1/IOUTB2

Respect To Ra ting

DCOM1/DCOM2

ACOM −1.0 V to AVDD + 0.3 V

ACOM −0.3 V to AVDD + 0.3 V

150°C

−65°C to +150°C

300°C

−0.3 V to DVDD1/ DVDD2 + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θ

is specified for the worst-case conditions, that is, a device

JA

soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA Unit

48-Lead LQFP 91 °C/W

ESD CAUTION

Rev. G | Page 8 of 44

Data Sheet AD9763/AD9765/AD9767

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTA1

DB8P1

DB7P1

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

DB1P1

NC

1

2

3

4

5

6

7

8

9

10

11

12

DB9P1 (MSB)

DB0P1 (LSB)

NC = NO CONNECT

OUTA1

MODE

AVDD46I

48

47

PIN 1

13NC14NC15

OUTB1

I

45

44

(Not to Scale)

16

17

DVDD1

DCOM1

FSADJ143REFIO42GAINCTRL41FSADJ240I

AD9763

TOP VIEW

18

CLK1/IQCL K

WRT1/IQWRT

OUTB2

OUTA2

I

39

38

19

20

21

22

23

DVDD2

DCOM2

WRT2/IQSEL

CLK2/IQRESET

Figure 3. AD9763 Pin Configuration

ACOM37SLEEP

24

DB8P2

DB9P2 (MSB)

36

NC

35

NC

34

NC

33

NC

32

DB0P2 (LSB)

31

DB1P2

30

DB2P2

29

DB3P2

28

DB4P2

27

DB5P2

26

DB6P2

25

DB7P2

PIN 1

14

15

DB0P1 (LSB)

OUTB1

I

45

44

(Not to Scale)

16

17

DVDD1

DCOM1

FSADJ143REFIO42GAINCTRL41FSADJ240I

AD9767

TOP VIEW

18

CLK1/IQCL K

WRT1/IQWRT

MODE47AVDD46I

48

DB12P1

DB11P1

DB10P1

DB9P1

DB8P1

DB7P1

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

1

2

3

4

5

6

7

8

9

10

11

12

13

DB13P1 (MSB)

DB1P1

0617-003

Figure 5. AD9767 Pin Configuration

19

20

CLK2/IQRESET

OUTB2

OUTA2

I

ACOM37SLEEP

39

38

36

DB0P2 (LSB)

35

DB1P2

34

DB2P2

33

DB3P2

32

DB4P2

31

DB5P2

30

DB6P2

29

DB7P2

28

DB8P2

27

DB9P2

26

DB10P2

25

DB11P2

21

22

23

24

DVDD2

DCOM2

WRT2/IQSEL

DB12P2

DB13P2 (MSB)

0617-005

DB11P1 (MSB)

DB10P1

DB9P1

DB8P1

DB7P1

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

DB1P1

DB0P1 (LSB)

NC = NO CONNECT

OUTA1

47

PIN 1

AVDD46I

15

OUTB1

I

FSADJ143REFIO42GAINCTRL41FSADJ240I

45

44

AD9765

TOP VIEW

(Not to Scale)

16

17

18

19

MODE

48

1

2

3

4

5

6

7

8

9

10

11

12

13

NC14NC

DVDD1

DCOM1

CLK1/IQCL K

WRT1/IQWRT

CLK2/IQRESET

Figure 4. AD9765 Pin Configuration

OUTB2

OUTA2

I

ACOM37SLEEP

39

38

36

NC

35

NC

34

DB0P2 (LSB)

33

DB1P2

32

DB2P2

31

DB3P2

30

DB4P2

29

DB5P2

28

DB6P2

27

DB7P2

26

DB8P2

25

DB9P2

20

21

22

23

24

DVDD2

DCOM2

WRT2/IQSEL

DB10P2

DB11P2 (MSB)

0617-004

Rev. G

| Page 9 of 44

AD9763/AD9765/AD9767 Data Sheet

Table 6. Pin Function Descriptions

Pin No.

AD9763 AD9765 AD9767 Mnemonic Description

1 to 10 1 to 12 1 to 14 DBxP1 Data Bit Pins (Port 1) 11 to 14,

33 to 36

13, 14,

35, 36 15, 21 15, 21 15, 21 DCOM1, DCOM2 Digital Common 16, 22 16, 22 16, 22 DVDD1, DVDD2 Digital Supply Voltage 17 17 17 WRT1/IQWRT Input Write Signal for PORT 1 (IQWRT in Interleaving Mode) 18 18 18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode) 19 19 19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode) 20 20 20 WRT2/IQSEL Input Write Signal for PORT 2 (IQSEL in Interleaving Mode) 23 to 32 23 to 34 23 to 36 DBxP2 Data Bit Pins (Port 2) 37 37 37 SLEEP Power-Down Control Input 38 38 38 ACOM Analog Common 39, 40 39, 40 39, 40 I 41 41 41 FSADJ2 Full-Scale Current Output Adjust for DAC2 42 42 42 GAINCTRL Master/Slave Resistor Control Mode 43 43 43 REFIO Reference Input/Output 44 44 44 FSADJ1 Full-Scale Current Output Adjust for DAC1 45, 46 45, 46 45, 46 I 47 47 47 AVDD Analog Supply Voltage 48 48 48 MODE Mode Select (1 = dual port, 0 = interleaved)

N/A NC No Connect

, I

OUTA2

OUTB1

Port 2 Differential DAC Current Outputs

OUTB2

, I

Port 1 Differential DAC Current Outputs

OUTA1

Rev. G | Page 10 of 44

Data Sheet AD9763/AD9765/AD9767

TYPICAL PERFORMANCE CHARACTERISTICS

AD9763

AVDD = 3.3 V or 5 V, DVDD = 3.3 V, I unless otherwise noted.

90

80

f

= 5MSPS

CLK

f

= 25MSPS

70

SFDR (dBc)

60

50

1 10 100

CLK

f

= 65MSPS

CLK

f

OUT

Figure 6. SFDR vs. f

(MHz)

OUT

= 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist,

OUTFS

80

0dBFS

75

–6dBFS

f

OUT

(MHz)

OUT

@ 65 MSPS

@ 0 dBFS

f

= 125MSPS

CLK

70

–12dBFS

65

SFDR (dBc)

60

55

50

0 5 10 15 20 25 30 35

00617-006

Figure 9. SFDR vs. f

00617-009

80

0dBFS

75

SFDR (dBc)

70

65

0 0.5 1.0 1.5 2.0 2.5

80

75

70

SFDR (dBc)

65

–6dBFS

–12dBFS

f

(MHz)

OUT

Figure 7. SFDR vs. f

0dBFS

–12dBFS

@ 5 MSPS

OUT

–6dBFS

80

75

70

65

SFDR (dBc)

60

55

50

0 10203040506070

00617-007

80

75

70

65

SFDR (dBc)

60

55

0dBFS

–12dBFS

Figure 10. SFDR vs. f

I

= 20mA

OUTFS

I

OUTFS

f

= 5mA

–6dBFS

OUT

(MHz)

@ 125 MSPS

OUT

I

OUTFS

= 10mA

0617-010

60

02 1246810

Figure 8. SFDR vs. f

f

OUT

(MHz)

@ 25 MSPS

OUT

00617-008

Rev. G | Page 11 of 44

50

0 5 10 15 20 25 30 35

Figure 11. SFDR vs. f

OUT

f

OUT

and I

(MHz)

@ 65 MSPS and 0 dBFS

OUTFS

0617-011

AD9763/AD9765/AD9767 Data Sheet

85

80

75

70

SFDR (dBc)

65

60

55

–20 –16 –12 –8 –4 0

Figure 12. Single-Tone SFDR vs. A

85

80

75

70

SFDR (dBc)

65

60

55

–20 –16 –12 –8 –4 0

2MHz/10MSPS

Figure 13. Single-Tone SFDR vs. A

910kHz/10MSPS

2.27MHz/25M SPS

5.91MHz/65MSPS

(dBFS)

A

OUT

1MHz/5MSPS

13MHz/65MSP S

(dBFS)

A

OUT

11.37MHz/125M SPS

@ f

OUT

5MHz/25MSPS

25MHz/125MSPS

@ f

OUT

= f

CLK

/11

/5

0617-012

00617-013

70

I

= 20mA

OUTFS

65

I

= 10mA

OUTFS

SINAD (dBc)

60

I

= 5mA

OUTFS

55

20 40 60 80 100 120 140

Figure 15. SINAD vs. f

0.25

0.20

0.15

0.10

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

–0.25

0 200 400 600 800 1000

CLK

f

CLK

and I

(MSPS)

@ f

OUTFS

CODE

= 5 MHz and 0 dBFS

OUT

Figure 16. Typical INL

00617-015

0617-016

80

3.38MHz/3. 36MHz @ 25MSPS

75

70

65

SFDR (dBc)

60

55

6.75MHz/7. 25MHz @ 65MSPS

–20 –16 –12 –8 –4 0

Figure 14. Dual-Tone SFDR vs. A

0.965MHz/1.035MHz @ 7MSPS

16.9MHz/18. 1MHz @ 125MSPS

(dBFS)

A

OUT

@ f

OUT

= f

CLK

0.30

0.25

0.20

0.15

0.10

DNL (LSB)

0.05

0

–0.05

–0.10

0 200 40 0 600 800 1000

00617-014

/7

Figure 17. Typical DNL

CODE

00617-017

Rev. G | Page 12 of 44

Data Sheet AD9763/AD9765/AD9767

85

f

= 1MHz

80

75

70

65

SFDR (dBc)

60

55

50

45

–60 –40 –20 0 20 40 60 80 100

Figure 18. SFDR vs. Temperature @ f

OUT

f

= 10MHz

OUT

f

= 25MHz

OUT

f

= 40MHz

OUT

f

= 60MHz

OUT

TEMPERATURE (° C)

CLK

= 125 MSPS, 0 dBFS

00617-018

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

0 1020304

Figure 21. Dual-Tone SFDR @ f

FREQUENCY (MHz )

CLK

= 125 MSPS

0

00617-021

0.05

0.03

OFFSET ERROR

0

OFFSET ERROR (%FS)

–0.03

–0.05

–40 –20 0 20 40 60 80

GAIN ERROR

TEMPERATURE (° C)

Figure 19. Gain and Offset Error vs. Temperature @ f

10

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

0 1020304

Figure 20. Single-Tone SFDR @ f

FREQUENCY (MHz)

CLK

= 125 MSPS

CLK

= 125 MSPS

1.0

0.5

0

GAIN ERROR (%FS)

–0.5

–1.0

0

00617-020

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

0 1020304

00617-019

Figure 22. Four-Tone SFDR @ f

FREQUENCY (MHz)

CLK

= 125 MSPS

0

00617-022

Rev. G | Page 13 of 44

AD9763/AD9765/AD9767 Data Sheet

AD9765

AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, I Nyquist, unless otherwise noted.

90

f

= 5MSPS

CLK

f

= 25MSPS

CLK

80

f

= 65MSPS

@ 0 dBFS

OUT

CLK

70

SFDR (dBc)

60

f

CLK

50

110

f

(MHz)

OUT

Figure 23. SFDR vs. f

= 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to

OUTFS

85

= 125MSPS

SFDR (dBc)

100

0617-023

80

75

70

65

60

55

50

0330252015105

0dBFS

–6dBFS

–12dBFS

f

OUT

Figure 26. SFDR vs. f

(MHz)

@ 65 MSPS

OUT

5

0617-026

95

90

85

SFDR (dBc)

80

75

1.00 2.252.001.751.501.25

90

85

80

75

SFDR (dBc)

70

–6dBFS

Figure 24. SFDR vs. f

–6dBFS

0dBFS

f

OUT

(MHz)

OUT

–12dBFS

@ 5 MSPS

–12dBFS

85

80

75

70

65

SFDR (dBc)

60

55

50

07605040302010

0617-024

85

80

75

70

65

SFDR (dBc)

60

0dBFS

–12dBFS

Figure 27. SFDR vs. f

I

OUTFS

= 5mA

I

OUTFS

= 10mA

f

OUT

(MHz)

@ 125 MSPS

OUT

= 20mA

I

OUTFS

–6dBFS

0

0617-027

65

60

01108642

f

OUT

Figure 25. SFDR vs. f

(MHz)

@ 25 MSPS

OUT

55

2

0617-025

50

03252015105

Figure 28. SFDR vs. f

OUT

and I

Rev. G | Page 14 of 44

f

(MHz)

OUT

@ 65 MSPS and 0 dBFS

OUTFS

0

0617-028

Data Sheet AD9763/AD9765/AD9767

90

85

80

2.27MHz/25MS PS

0.91MHz/10MSPS

75

I

= 20mA

OUTFS

70

I

OUTFS

= 10mA

75

SFDR (dBc)

70

65

60

–20 0–5–10–15

Figure 29. Single-Tone SFDR vs. A

90

85

5MHz/25MSPS

80

75

70

SFDR (dBc)

65

60

55

–20 0–5–10–15

2MHz/10MSPS

13MHz/65MSP S

Figure 30. Single-Tone SFDR vs. A

11.37MHz/125M SPS

5.91MHz/65MSPS

A

(dBFS)

OUT

1MHz/5MSPS

25MHz/125MSPS

A

(dBFS)

OUT

@ f

OUT

= f

65

SINAD (dBc)

60

I

= 5mA

OUTFS

55

20 140120100806040

f

(MSPS)

00617-029

/11

CLK

00617-030

/5

CLK

Figure 32. SINAD vs. f

0.6

0.5

0.4

0.3

0.2

0.1

INL (LSB)

0

–0.1

–0.2

–0.3

–0.4

0 40001000 2000 3000

CLK

and I

OUTFS

CODE

@ f

OUT

Figure 33. Typical INL

= 5 MHz and 0 dBFS

0617-032

00617-033

80

3.38MHz/3. 36MHz@25MSPS

75

70

SFDR (dBc)

65

60

55

–20 0–5–10–15

0.965MHz/1. 035MHz@7MSPS

16.9MHz/18. 1MHz@125MSPS

Figure 31. Dual-Tone SFDR vs. A

6.75MHz/7. 25MHz@65MSPS

A

(dBFS)

OUT

@ f

= f

OUT

0.05

0

–0.05

–0.10

–0.15

DNL (LS B)

–0.20

–0.25

–0.30

–0.35

0 4000350030002500200015001000500

00617-031

/7

CLK

Figure 34. Typical DNL

CODE

00617-034

Rev. G | Page 15 of 44

AD9763/AD9765/AD9767 Data Sheet

85

80

75

70

65

SFDR (dBc)

60

55

50

45

–60 –40 –20 0 20 40 60 80 100

f

= 1MHz

OUT

f

= 10MHz

OUT

f

= 25MHz

OUT

f

= 40MHz

OUT

f

= 60MHz

OUT

TEMPERATURE ( °C)

Figure 35. SFDR vs. Temperature @ 125 MSPS, 0 dBFS

00617-035

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

04302010

FREQUENCY (MHz )

Figure 38. Dual-Tone SFDR @ f

= 125 MSPS

CLK

0

00617-038

0.05

0.03

OFFSET ERROR

0

OFFSET ERROR (%FS)

–0.03

–0.05

–40–200 20406080

GAIN ERROR

TEMPERATURE ( °C)

Figure 36. Gain and Offset Error vs. Temperature @ f

10

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

04302010

Figure 37. Single-Tone SFDR @ f

FREQUENCY (MHz )

CLK

= 125 MSPS

CLK

1.0

0.5

0

–0.5

–1.0

GAIN ERROR (%FS)

00617-036

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

04302010

Figure 39. Four-Tone SFDR @ f

0

00617-037

FREQUENCY (MHz )

CLK

= 125 MSPS

0

00617-039

Rev. G | Page 16 of 44

Data Sheet AD9763/AD9765/AD9767

AD9767

AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, I Nyquist, unless otherwise noted.

90

f

= 5MSPS

CLK

f

= 25MSPS

CLK

80

f

= 125MSPS

CLK

70

SFDR (dBc)

60

f

= 65MSPS

CLK

50

110

f

(MHz)

OUT

Figure 40. SFDR vs. f

@ 0 dBFS

OUT

= 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to

OUTFS

85

SFDR (dBc)

100

0617-040

80

75

70

65

60

55

50

0330252015105

0dBFS

–6dBFS

Figure 43. SFDR vs. f

f

OUT

(MHz)

@ 65 MSPS

OUT

–12dBFS

5

0617-043

90

85

SFDR (dBc)

80

75

90

85

80

75

SFDR (dBc)

70

65

022.01.51.00.5

0dBFS

–12dBFS

f

OUT

Figure 41. SFDR vs. f

0dBFS

–6dBFS

(MHz)

OUT

–6dBFS

@ 5 MSPS

–12dBFS

85

80

75

70

65

SFDR (dBc)

60

55

.5

0617-041

50

07605040302010

0dBFS

–12dBFS

Figure 44. SFDR vs. f

90

85

80

75

70

SFDR (dBc)

65

60

55

I

OUTFS

= 5mA

I

OUTFS

= 20mA

–6dBFS

f

(MHz)

OUT

= 10mA

@ 125 MSPS

OUT

0

0617-044

60

01108642

f

OUT

Figure 42. SFDR vs. f

(MHz)

@ 25 MSPS

OUT

2

0617-042

50

0330252015105

Figure 45. SFDR vs. f

OUT

and I

Rev. G | Page 17 of 44

f

(MHz)

OUT

@ 65 MSPS and 0 dBFS

OUTFS

5

0617-045

AD9763/AD9765/AD9767 Data Sheet

90

85

80

75

SFDR (dBc)

70

65

60

–20 0–5–10–15

2.27MHz/25MSPS

5.91MHz/65MS PS

Figure 46. Single-Tone SFDR vs. A

910kHz/10MSPS

11.37MHz/125MSPS

A

(dBFS)

OUT

@ f

OUT

= f

00617-046

/11

CLK

75

70

65

SINAD (dBc)

60

55

20 140120100806040

Figure 49. SINAD vs. f

CLK

I

OUTFS

I

OUTFS

I

OUTFS

f

and I

CLK

= 20mA

= 10mA

= 5mA

(MSPS)

OUTFS

@ f

= 5 MHz and 0 dBFS

OUT

0617-049

90

85

2MHz/10MSPS

80

75

70

SFDR (dBc)

65

60

55

50

–20 0–5–10–15

5MHz/25MSPS

Figure 47. Single-Tone SFDR vs. A

85

80

3.38MHz/3. 63MHz@25MSPS

75

70

65

SFDR (dBc)

60

55

50

–25 –20 0–5–10–15

Figure 48. Dual-Tone SFDR vs. A

1MHz/5MSPS

13MHz/65MSP S

25MHz/125MSPS

A

(dBFS)

OUT

@ f

= f

OUT

0.965MHz/1. 035MHz@7MSPS

16.9MHz/18. 1MHz@125MSPS

6.75MHz/7. 25MHz@65MSPS

A

(dBFS)

OUT

@ f

= f

OUT

2.5

2.0

1.5

1.0

0.5

INL (LSB)

0

–0.5

–1.0

–1.5

0 160004000 8000 12000

00617-047

/5

CLK

/7

CLK

Figure 50. Typical INL

0.4

0.2

0

–0.2

–0.4

–0.6

DNL (LS B)

–0.8

–1.0

–1.2

–1.4

0 1000800600400200

00617-048

Figure 51. Typical DNL

CODE

00617-050

00617-051

Rev. G | Page 18 of 44

Data Sheet AD9763/AD9765/AD9767

85

80

75

70

65

SFDR (dBc)

60

55

50

45

–60 –40 –20 0 20 40 60 80 100

f

= 1MHz

OUT

f

= 10MHz

OUT

f

= 25MHz

OUT

f

= 40MHz

OUT

f

= 60MHz

OUT

TEMPERATURE ( °C)

Figure 52. SFDR vs. Temperature @ 125 MSPS, 0 dBFS

00617-052

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

04302010

FREQUENCY (MHz )

Figure 55. Dual-Tone SFDR @ f

= 125 MSPS

CLK

0

00617-055

0.05

0.03

OFFSET ERROR

0

OFFSET ERROR (%FS)

–0.03

–0.05

–40–200 20406080

GAIN ERROR

TEMPERATURE ( °C)

Figure 53. Gain and Offset Error vs. Temperature @ f

10

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

04302010

Figure 54. Single-Tone SFDR @ f

FREQUENCY (MHz )

= 125 MSPS

CLK

= 125 MSPS

CLK

1.0

0.5

0

–0.5

–1.0

GAIN ERROR (%FS)

00617-053

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

04302010

Figure 56. Four-Tone SFDR @ f

0

00617-054

FREQUENCY (MHz )

CLK

= 125 MSPS

0

00617-056

Rev. G | Page 19 of 44

AD9763/AD9765/AD9767 Data Sheet

TERMINOLOGY

Linearity Error (Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

Offset error is the deviation of the output current from the ideal of zero. For I For I

OUTB

, 0 mA output is expected when the inputs are all 0s.

OUTA

, 0 mA output is expected when all inputs are set to 1s.

Gain Error

Gain error is the difference between the actual and ideal output spans. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance.

Temp e ra t ur e Dr if t

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

MAX

. For offset and gain drift, the drift is reported in part per million (ppm) of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius (ppm/°C).

Power Supply Rejection (PSR)

PSR is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.

Settling Time

Settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in picovolts per second (pV-s).

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).

Rev. G | Page 20 of 44

Data Sheet AD9763/AD9765/AD9767

V

THEORY OF OPERATION

5

AVDD

DIVIDER

CHANNEL 1 LATCH

PORT 1 PORT 2

DIGITAL

DATA

TEKTRONIX

AWG2021

w/OPTION 4

R

1

SET

2kΩ

0.1µF

R

SET

DVDD1/DVDD2

DCOM1/DCOM2

RETIMED CLO CK OUTPUT*

2

2kΩ

LECROY 9210

GENERATOR

FSADJ1

REFIO

FSADJ2

1.2V REF

GAINCTRL

PULSE

WRT1/

IQWRT

50Ω

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

AD9763/ AD9765/ AD9767

Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767,

Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2

5

AVDD

R

1

SET

2kΩ

1

I

REF

2

I

REF

0.1µF

R

SET

2kΩ

2

FSADJ1

REFIO

FSADJ2

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

DIVIDER

AD9763/

WRT1/ IQWRT

AD9765/ AD9767

CHANNEL 1 LATCH CHANNEL 2 LATCH

PORT 1 PORT 2

DIGITAL DATA INPUTS

1.2V REF

GAINCTRL

NOTES

1. IN THIS CONFIGURAT ION, THE 22nF CAPACITOR AND 256Ω RESISTOR ARE NO T REQUIRED BECAUSE R

Figure 58. Simplified Block Diagram

FUNCTIONAL DESCRIPTION

Figure 58 shows a simplified block diagram of the AD9763/ AD9765/AD9767. The AD9763/AD9765/AD9767 consist of two DACs, each one with its own independent digital control logic and full-scale output current control. Each DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (I

The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th MSB current source. The remaining LSB is a binary weighted fraction of the middle bit current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances the dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of each DAC (that is, >100 k).

OUTFS

).

CLK1/IQCL K CLK2/IQRESET

CLK

DAC1

LATCH

DAC2

LATCH

MULTIPLEXING LOGIC

CHANNEL 2 LATCH

*AWG2021 CLOCK RET IMED SUCH THAT DIGITAL DATA TRANSITI ONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.

CLK1/IQCLK CLK2/IQRESET

CLK

DAC1

LATCH

DAC2

LATCH

MULTIPLEXING LOGIC

of an

Rev. G | Page 21 of 44

SEGMENTED

SWITCHES FOR

DAC1

SEGMENTED

SWITCHES FOR

DAC2

SEGMENTED

SWITCHES F OR

DAC1

SEGMENTED

SWITCHES FOR

DAC2

All of these current sources are switched to one of the two output nodes (that is, I current switches. The switches are based on a new architecture that drastically improves distortion performance. This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches.

The analog and digital sections of the AD9763/AD9765/AD9767 have separate power supply inputs (that is, AVDD and DVDD1/ DVDD2) that can operate independently at 3.3 V or 5 V. The digital section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V band gap voltage reference, and two reference control amplifiers.

WRT2/ IQSEL

SLEEP

LSB

SWITCH

LSB

SWITCH

DCOM1/

DCOM2

SLEEP

LSB

SWITCH

LSB

SWITCH

DCOM1/ DCOM2

SET

DVDD1/

DVDD2

DVDD1/

DVDD2

= 2kΩ.

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

MODE

ACOM

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

MODE

OUTA

50Ω 50Ω

5V

V

OUT

5V

or I

OUTB

Mini-Circuits

T1-1T

= V

DIFF

V

OUT

2B

R

2B

L

50Ω

OUT

2A

R 50Ω

A – V

2A

L

V

TO HP3589A OR EQUIVALENT SPECTRUM/ NETWORK ANALYZER

B

OUT

V

OUT

1B

OUT

R

1B

L

50Ω

1A

R 50Ω

L

) via the PMOS differential

00617-057

1A

00617-058

AD9763/AD9765/AD9767 Data Sheet

The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from 2 mA to 20 mA via an external network connected to the full scale adjust (FSADJ) pin. The external network, in combination with both the reference control amplifier and voltage reference (V

) sets the reference current I

REFIO

, which is replicated to the

REF

segmented current sources with the proper scaling factor. The full-scale current (I

OUTFS

) is 32 × I

REF

.

REFERENCE OPERATION

The AD9763/AD9765/AD9767 contain an internal 1.20 V band gap reference. This can easily be overridden by a low noise external reference with no effect on performance. REFIO serves as either an input or output, depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 µF capacitor. The internal reference voltage is present at REFIO. If the voltage at REFIO is used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 59.

CURRENT

SOURCE

ARRAY

AVDDGAINCTRL

CURRENT

SOURCE

ARRAY

AVDDGAINCTRL

ACOM

0617-060

OPTIONAL

EXTERNAL

REFERENCE

ADDITIONAL

EXTERNAL

LOAD

BUFFER

0.1µF

I

REF

1.2V REF

REFIO

FSADJ1/

256Ω

FSADJ2

SET

22nF

R

AD9763/ AD9765/

AD9767

REFERENCE

SECTION

Figure 59. Internal Reference Configuration

An external reference can be applied to REFIO as shown in Figure 60. The external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. The 0.1 µF compensation capacitor is not required because the internal reference is overridden and the relatively high input impedance of REFIO minimizes any loading of the external reference.

AD9763/ AD9765/

AVDD

EXTERNAL

REFERENCE

R

1.2V REF

REFIO

FSADJ1/

256Ω

I

REF

SET

FSADJ2

22nF

AD9767

REFERENCE

SECTION

Figure 60. External Reference Configuration Gain Control Mode

00617-059

GAIN CONTROL MODE

The AD9763/AD9765/AD9767 has two gain control modes, independent and master/slave. If the GAINCTRL terminal is low (connected to ground), the full-scale currents of DAC1 and DAC2 are set separately using two different R

resistors. One resistor

SET

is connected to the FSADJ1 terminal, and the other resistor is connected to the FSADJ2 terminal. This is independent mode. If the GAINCTRL terminal is set high (connected to AVDD), the full-scale currents of DAC1 and DAC2 are set to the same value using one R

resistor. In master/slave mode, full-scale current

SET

for both DAC1 and DAC2 is set via the FSADJ1 terminal.

SETTING THE FULL-SCALE CURRENT

Both of the DACs in the AD9763/AD9765/AD9767 contain a control amplifier that is used to regulate the full-scale output current (I converter, as shown in Figure 59, so that its current output (I is determined by the ratio of the V R

.

SET

I

REF

The DAC full-scale current, I larger than the reference current, I

I

OUTFS

The control amplifier allows a wide (10:1) adjustment span of I

from 2 mA to 20 mA by setting I

OUTFS

625 µA. The wide adjustment range of I benefits. The first relates directly to the power dissipation of the AD9763/AD9765/AD9767, which is proportional to I the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes.

To ensure that the AD9763/AD9765/AD9767 performs properly, connect a 22 nF capacitor and 256  resistor network (shown in Figure 59 and Figure 60) from the FSADJ1 terminal to ground and from the FSADJ2 terminal to ground.

). The control amplifier is configured as a V-I

OUTFS

and an external resistor,

REFIO

= V

REFIO/RSET

= 32 × I

REF

, is an output current 32 times

OUTFS

.

REF

between 62.5 µA and

REF

provides several

OUTFS

REF

(refer to

)

Rev. G | Page 22 of 44

Data Sheet AD9763/AD9765/AD9767

DAC TRANSFER FUNCTION

Both DACs in the AD9763/AD9765/AD9767 provide complementary current outputs, I full-scale current output (I

and I

OUTA

) when all bits are high (that is,

OUTFS

DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/ AD9767, respectively), while I

OUTB

provides no current. The current output appearing at I I

is a function of both the input code and I

OUTB

AD9763, AD9765, and AD9767, respectively, can be expressed as

I

= (DAC CODE/1024) × I

OUTA

I

= (DAC CODE/4096) × I

OUTA

I

= (DAC CODE/16,384) × I

OUTA

I

for the AD9763, AD9765, and AD9767, respectively, can be

OUTB

expressed as

I

= ((1023 − DAC CODE)/1024) × I

OUTB

= ((4095 − DAC CODE)/4096) × I

I

OUTB

I

= ((16,383 − DAC CODE)/16,384) × I

OUTB

where DAC CODE = 0 to 1024, 0 to 4095, or 0 to 16,384 (decimal representation).

I

is a function of the reference current (I

OUTFS

set by a reference voltage (V

) and an external resistor (R

REFIO

It can be expressed as

I

where I

= 32 × I

OUTFS

is set as discussed in the Setting the Full-Scale

REF

(3)

REF

Current section.

The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, I should be directly connected to matching resistive loads (R that are tied to the analog common (ACOM). Note that R can represent the equivalent load resistance seen by I as is the case in a doubly terminated 50  or 75  cable. The singleended voltage output appearing at the I

= I

× R

V

OUTA

OUTB

= I

OUTA

OUTB

× R

(5)

LOAD

(6)

LOAD

Note that the full-scale value of V exceed the specified output compliance range to maintain the specified distortion and linearity performance.

= (I

V

DIFF

OUTA

− I

OUTB

) × R

LOAD

Equation 7 highlights some of the advantages of operating the AD9763/AD9765/AD9767 differentially. First, the differential operation helps cancel common-mode error sources associated with I

OUTA

and I

such as noise, distortion, and dc offsets.

OUTB

Second, the differential code-dependent current and subsequent voltage, V output (that is, V

, is twice the value of the single-ended voltage

DIFF

OUTA

or V

), thus providing twice the signal

OUTB

power to the load.

. I

OUTB

provides a near

OUTA

, the complementary output,

and

OUTA

. I

OUTA

and I

or I

OUTA

nodes is

for the

SET

OUTB

LOAD

,

OUTB

OUTFS

(1)

OUTFS

(2)

OUTFS

). This is nominally

REF

OUTA

and I

OUTA

and V

OUTB

must not

(7)

).

)

The gain drift temperature performance for a single-ended (V

OUTA

and V

) or differential output (V

OUTB

DIFF

) of the AD9763/AD9765/AD9767 can be enhanced by selecting temperature tracking resistors for R

LOAD

and R

due to their

SET

ratiometric relationship.

ANALOG OUTPUTS

The complementary current outputs, I DAC can be configured for single-ended or differential operation. I single-ended voltage outputs, V resistor (R The differential voltage (V

and I

OUTA

) as described in Equation 5 through Equation 7.

LOAD

can be converted into complementary

OUTB

OUTA

) existing between V

DIFF

can be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9763/AD9765/AD9767 is optimum and specified using a differential transformer-coupled output in which the voltage swing at I

OUTA

and I

is limited to ±0.5 V. If a single-ended

OUTB

unipolar output is desired, select IOUTA.

The distortion and noise performance of the AD9763/AD9765/ AD9767 can be enhanced when it is configured for differential operation. The common-mode error sources of both I I

can be significantly reduced by the common-mode rejection

OUTB

of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise.

Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load, assuming no source termination. Because the output currents of I

OUTA

and I

OUTB

become additive when processed differentially. A properly selected transformer allows the AD9763/AD9765/AD9767 to provide the required power and voltage levels to different loads.

The output impedance of I

OUTA

and I equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 k in parallel with 5 pF. It is also slightly dependent on the output voltage (that is, V

and V

OUTA

maintaining I

) due to the nature of a PMOS device. As a result,

OUTB

OUTA

and/or I

at a virtual ground via an I-V

OUTB

op amp configuration results in the optimum dc linearity. Note that the INL/DNL specifications for the AD9763/AD9765/AD9767 are measured with I

maintained at a virtual ground via an op amp.

OUTA

and V

and I

OUTB

, in each

OUTB

, via a load

and V

OUTA

and

are complementary, they

is determined by the

OUTB

Rev. G | Page 23 of 44

AD9763/AD9765/AD9767 Data Sheet

W

I

OUTA

and I

also have a negative and positive voltage

OUTB

compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of −1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9763/AD9765/AD9767.

The positive output compliance range is slightly dependent on the full-scale output current, I

OUTFS

. When I

is decreased

OUTFS

from 20 mA to 2 mA, the positive output compliance range degrades slightly from its nominal 1.25 V to 1.00 V. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at I

OUTA

and I

OUTB

does not exceed 0.5 V. Applications requiring the AD9763/ AD9765/AD9767 output (that is, V output compliance range must size R

and/or V

OUTA

LOAD

OUTB

accordingly. Operation

) to extend its

beyond this compliance range adversely affects the linearity performance of the AD9763/AD9765/AD9767 and subsequently degrades its distortion performance.

DIGITAL INPUTS

The digital inputs of the AD9763/AD9765/AD9767 consist of two independent channels. For the dual-port mode, each DAC has its own dedicated 10-/12-/14-bit data port: WRT line and CLK line. In the interleaved timing mode, the function of the digital control pins changes as described in the Interleaved Mode Timing section. The 10-/12-/14-bit parallel data inputs follow straight binary coding, where the most significant bits (MSBs) are DB9P1 and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765, and DB13P1 and DB13P2 for the AD9767, and the least significant bits (LSBs) are DB0P1 and DB0P2 for all three parts. I a full-scale output current when all data bits are at Logic 1. I

produces

OUTA

OUTB

produces a complementary output with the full-scale current split between the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered master/slave latch. The DAC outputs are updated following either the rising edge or every other rising edge of the clock, depending on whether dual or interleaved mode is used. The DAC outputs are designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock.

DAC TIMING

The AD9763/AD9765/AD9767 can operate in two timing modes, dual and interleaved, which are described in the following sections. The block diagram in Figure 61 represents the latch architecture in the interleaved timing mode.

INTERLEAVED

DATA IN, PORT 1

IQWRT

IQSEL

IQCLK

IQRESET

Figure 61. Latch Structure in Interleaved Mode

Dual-Port Mode Timing

When the MODE pin is at Logic 1, the AD9763/AD9765/AD9767 operates in dual-port mode (refer to Figure 57). The AD9763/ AD9765/AD9767 functions as two distinct DACs. Each DAC has its own completely independent digital input and control lines.

The AD9763/AD9765/AD9767 features a double-buffered data path. Data enters the device through the channel input latches. This data is then transferred to the DAC latch in each signal path. After the data is loaded into the DAC latch, the analog output settles to its new value.

For general consideration, the WRT lines control the channel input latches, and the CLK lines control the DAC latches. Both sets of latches are updated on the rising edge of their respective control signals.

The rising edge of CLK must occur before or simultaneously with the rising edge of WRT. If the rising edge of CLK occurs after the rising edge of WRT, a minimum delay of 2 ns must be maintained from the rising edge of WRT to the rising edge of CLK.

Timing specifications for dual-port mode are shown in Figure 62 and Figure 63.

DATA IN

RT1/W RT2

CLK1/CLK2

I

OUTA

OR

I

OUTB

DATA IN

RT1/WRT2

CLK1/CLK2

D1 D2 D3 D4 D5

I

OUTA

OR

I

OUTB

PORT 1

INPUT

LATCH

PORT 2

INPUT

LATCH

÷2

t

DAC1 LATCH

DAC1

DAC2 LATCH

DAC2

S

t

H

t

PD

Figure 62. Dual-Port Mode Timing

XX

D1

D2

Figure 63. Dual-Port Mode Timing

DEINTERLEAVED DATA OUT

LPW

CPW

D3

D4

00617-063

00617-061

00617-062

Rev. G | Page 24 of 44

Data Sheet AD9763/AD9765/AD9767

Interleaved Mode Timing

When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767 operate in interleaved mode (refer to Figure 61). In addition, WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2 functions as IQSEL, and CLK2 functions as IQRESET.

Data enters the device on the rising edge of IQWRT. The logic level of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper operation, IQSEL must change state only when IQWRT and IQCLK are low.

When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the next rising edge on IQCLK updates both DAC latches with the data present at their inputs. In the interleaved mode, IQCLK is divided by 2 internally. Following this first rising edge, the DAC latches are only updated on every other rising edge of IQCLK. In this way, IQRESET can be used to synchronize the routing of the data to the DACs.

Similar to the order of CLK and WRT in dual-port mode, IQCLK must occur before or simultaneously with IQWRT.

Timing specifications for interleaved mode are shown in Figure 64 and Figure 66.

The digital inputs are CMOS compatible with logic thresholds, V

THRESHOLD

, set to approximately half the digital positive supply

(DVDDx), or

V

THRESHOLD

DATA IN

IQSEL

IQWRT

IQCLK

I

OUTA

I

OUTB

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

= DVDDx/2(±20%)

t

S

t

*

H

500 ps

OR

Figure 64. 5 V or 3.3 V Interleaved Mode Timing

t

PD

t

H

500 ps

t

LPW

00617-064

At 5 V it is permissible to drive IQWRT and IQCLK together as shown in Figure 65, but at 3.3 V the interleaved data transfer is not reliable.

t

S

DATA IN

IQSEL

t

*

IQWRT

IQCLK

I

OUTA

OR

I

OUTB

*APPLIES T O FALLI NG EDGE OF I QCLK/IQ WRT AND IQSEL ONLY.

H

t

H

t

LPW

t

PD

00617-065

Figure 65. 5 V Only Interleaved Mode Timing

INTERLEAVED

IQWRT

IQRESET

DAC OUTPUT

PORT 1

DAC OUTPUT

PORT 2

xx D1 D2 D3 D4 D5

DATA

IQSEL

IQCLK

xx

D1

D2

D3

D4

00617-066

Figure 66. Interleaved Mode Timing

The internal digital circuitry of the AD9763/AD9765/AD9767 is capable of operating at a digital supply of 3.3 V or 5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD1/DVDD2 is set to accommodate the maximum high level voltage (V

) of the TTL drivers. A DVDD1/DVDD2

OH(MAX)

of 3.3 V typically ensures proper compatibility with bipolar TTL logic families. Figure 67 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar, with the exception that it contains an active pull-down circuit, thus ensuring that the AD9763/AD9765/AD9767 remains enabled if this input is left disconnected.

DVDD1

DIGITAL

INPUT

00617-067

Figure 67. Equivalent Digital Input

Rev. G | Page 25 of 44

AD9763/AD9765/AD9767 Data Sheet

Because the AD9763/AD9765/AD9767 is capable of being clocked up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9763/AD9765/AD9767 with reduced logic swings and a corresponding digital supply (DVDD1/DVDD2) results in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9763/AD9765/AD9767 as well as its required minimum and maximum input logic level thresholds.

Digital signal paths should be kept short, and run lengths should be matched to avoid propagation delay mismatch. The insertion of a low value (that is, 20  to 100 ) resistor network between the AD9763/AD9765/AD9767 digital inputs and driver outputs can be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. For longer board traces and high data update rates, stripline techniques with proper impedance and termination resistors should be considered to maintain “clean” digital inputs.

The external clock driver circuitry provides the AD9763/AD9765/ AD9767 with a low-jitter clock input meeting the minimum and maximum logic levels while providing fast edges. Fast clock edges help minimize jitter manifesting itself as phase noise on a reconstructed waveform. Therefore, the clock input should be driven by the fastest logic family suitable for the application.

Note that the clock input can also be driven via a sine wave, which is centered around the digital threshold (that is, DVDDx/2) and meets the minimum and maximum logic threshold. This typically results in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. In addition, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered, because it affects the effective clock duty cycle and, subsequently, cuts into the required data setup and hold times.

Input Clock and Data Timing Relationship

SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9763/AD9765/AD9767 are rising edge triggered and therefore exhibit SNR sensitivity when the data transition is close to this edge. The goal when applying the AD9763/AD9765/AD9767 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 68 shows the relationship of SNR to clock placement with different sample rates. Note that at the lower sample rates, much more tolerance is allowed in clock placement; much more care must be taken at higher rates.

80

AD9763 AD9765 AD9767

70

60

50

40

SNR (dBc)

30

20

10

0

–4 –3 –2 –1 0 1 2 3 4

Figure 68. SNR vs. Clock Placement @ f

TIME OF DATA CHANGE RELATI VE TO

RISING CLOCK EDGE (ns)

= 20 MHz and f

OUT

= 125 MSPS

CLK

00617-068

SLEEP MODE OPERATION

The AD9763/AD9765/AD9767 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 3.3 V to 5 V and over the full operating temperature range. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital input also contains an active pull-down circuit that ensures the AD9763/AD9765/AD9767 remains enabled if this input is left disconnected. The AD9763/AD9765/AD9767 require less than 50 ns to power down and approximately 5 s to power back up.

POWER DISSIPATION

The power dissipation (PD) of the AD9763/AD9765/AD9767 is dependent on several factors, including

• the power supply voltages (AVDD and DVDD1/DVDD2)

• the full-scale current output (I

• the update rate (f

CLK

)

• the reconstructed digital input waveform

The power dissipation is directly proportional to the analog supply current (I

is directly proportional to I

I

AVD D

and is insensitive to f

Conversely, I the f

, and the digital supply (DVDD1/DVDD2). Figure 70

CLK

and Figure 71 show I output ratios (f

) and the digital supply current (I

AVD D

.

CLK

is dependent on the digital input waveform,

DVDD

as a function of full-scale sine wave

DVDD

) for various update rates with DVDD1 =

OUT/fCLK

DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively. Note that I

is reduced by more than a factor of 2 when

DVDD

DVDD1/DVDD2 is reduced from 5 V to 3.3 V.

)

OUTFS

as shown in Figure 69,

OUTFS,

DVDD

).

Rev. G | Page 26 of 44

Data Sheet AD9763/AD9765/AD9767

(mA)

AVDD

I

80

70

90

50

40

30

20

10

0252015105

Figure 69. I

I

OUTFS

AVDD

vs. I

OUTFS

00617-069

(mA)

DVDD

I

18

16

14

12

10

8

6

4

2

0

000.40.30.20. 1

Figure 71. I

125MSPS

100MSPS

65MSPS

25MSPS

5MSPS

RATIO (

f

/

f

)

OUT

CLK

vs. Ratio @ DVDD1 = DVDD2 = 3.3 V

DVDD

.5

0617-071

35

30

25

20

(mA)

15

DVDD

I

10

5

0

000.40.30.20. 1

Figure 70. I

125MSPS

100MSPS

65MSPS

25MSPS

5MSPS

RATIO (

f

/

f

)

OUT

CLK

vs. Ratio @ DVDD1 = DVDD2 = 5 V

DVDD

.5

0617-070

Rev. G | Page 27 of 44

AD9763/AD9765/AD9767 Data Sheet

Ω

APPLYING THE AD9763/AD9765/AD9767

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configurations for the AD9763/AD9765/AD9767, with I

set to a nominal

OUTFS

20 mA, unless otherwise noted. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if I sized load resistor (R

OUTA

and/or I

LOAD

is connected to an appropriately

OUTB

) referred to as ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier can be configured as an I-V converter, thus converting I

or I

OUTA

tion provides the best dc linearity because I maintained at a virtual ground. Note that I better performance than I

into a negative unipolar voltage. This configura-

OUTB

or I

OUTB

OUTA

.

OUTB

provides slightly

is

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used as shown in Figure 72 to perform a differential-to-single-ended signal conversion. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the pass band of the transformer. An RF transformer such as the Mini-Circuits® T1-1T provides excellent rejection of common-mode distortion (that is, even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios can also be used for impedance matching purposes. Note that the transformer provides ac coupling only.

Mini-Circuits

OPTIONAL R

DIFF

T1-1T

R

LOAD

00617-072

I

OUTA

AD9763/ AD9765/ AD9767

I

OUTB

Figure 72. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path

for both I at I

OUTA

around ACOM and must be maintained with the output compliance range of the AD9763/AD9765/AD9767 to achieve the specified performance. A differential resistor (R inserted in applications where the output of the transformer is connected to the load (R or cable. R ratio and provides the proper source termination that results in a low VSWR. Approximately half the signal power will be dissipated across R

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used as shown in Figure 73 to perform a differential-to-single-ended conversion. The AD9763/AD9765/ AD9767 is configured with two equal load resistors (R 25  each. The differential voltage developed across I I

is converted to a single-ended signal via the differential

OUTB

op amp configuration. An optional capacitor can be installed across I The addition of this capacitor often enhances the op amp’s distortion performance by preventing the DAC’s high-slewing output from overloading the op amp’s input.

The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate from a dual supply because its output is approximately ±1.0 V. Select a high speed amplifier capable of preserving the differential performance of the AD9763/AD9765/AD9767 while meeting other system level objectives (that is, cost or power). Consider the op amp’s differential gain, gain setting resistor values, and full-scale output swing capabilities when optimizing this circuit.

The differential circuit shown in Figure 74 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9763/AD9765/AD9767 and the op amp, is used to level shift the differential output of the AD9763/AD9765/AD9767 to midsupply (that is, AVDD/2). The AD8055 is a suitable op amp for this application.

and I

OUTA

and I

OUTB

is determined by the transformer’s impedance

DIFF

.

DIFF

and I

OUTA

I

OUTA

AD9763/ AD9765/ AD9767

I

OUTB

Figure 73. DC Differential Coupling Using an Op Amp

. The complementary voltages appearing

OUTB

(that is, V

, forming a real pole in a low-pass filter.

OUTB

and V

OUTA

) via a passive reconstruction filter

LOAD

C

OPT

25Ω25Ω

) swing symmetrically

OUTB

225Ω

AD8047

500Ω

DIFF

500

) can be

LOAD

OUTA

) of

and

0617-073

Rev. G | Page 28 of 44

Data Sheet AD9763/AD9765/AD9767

A

I

OUTA

AD9763/ AD9765/ AD9767

I

OUTB

C

25Ω

225Ω

OPT

25Ω

500Ω

AD8055

1kΩ

AVDD

0617-074

Figure 74. Single-Supply DC Differential-Coupled Circuit

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

Figure 75 shows the AD9763/AD9765/AD9767 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50  cable, because the nominal fullscale current (I R

of 25 . In this case, R

LOAD

resistance seen by I can be connected directly to ACOM or via a matching R Different values of I

) of 20 mA flows through the equivalent

OUTFS

represents the equivalent load

LOAD

or I

OUTA

OUTFS

. The unused output (I

OUTB

and R

can be selected as long as the

LOAD

OUTA

LOAD

or I

.

OUTB

positive compliance range is adhered to. One additional consideration in this mode is the INL (see the Analog Outputs section). For optimum INL performance, the single-ended, buffered voltage output configuration is suggested.

I

= 20m

OUTFS

I

OUTA

AD9763/ AD9765/ AD9767

I

OUTB

50Ω

25Ω

Figure 75. 0 V to 0.5 V Unbuffered Voltage Output

V

OUTA

= 0V TO 0. 5V

50Ω

00617-075

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION

Figure 76 shows a buffered single-ended output configuration in which the U1 op amp performs an I-V conversion on the AD9763/AD9765/AD9767 output current. U1 maintains I (or I

) at a virtual ground, thus minimizing the nonlinear

OUTB

output impedance effect on the INL performance of the DAC, as described in the Analog Outputs section. Although this singleended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by the slewing capabilities of U1. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of R

and I

FB

OUTFS

full-scale output within U1’s voltage output swing capabilities by scaling I performance may result with a reduced I

and/or RFB. An improvement in ac distortion

OUTFS

because the signal

OUTFS

current U1 has to sink will be subsequently reduced.

OUTA

. Set the

C

OPT

R

FB

200Ω

I

= 10mA

OUTFS

I

OUTA

AD9763/ AD9765/ AD9767

I

OUTB

200Ω

U1

V

= I

OUTFS

× R

FB

00617-076

OUT

Figure 76. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS

Power Supply Rejection

Many applications seek high speed and high performance under less than ideal operating conditions. In these applications, the

)

implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. Figure 92 to Figure 93 illustrate recommended printed circuit board ground, power, and signal plane layouts that are implemented on the AD9763/AD9765/AD9767 evaluation board.

One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the power supply rejection ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC’s full-scale current, I

. AC noise on the dc supplies

OUTFS

is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise occurs over the spectrum of tens of kilohertz to several megahertz. The PSRR vs. frequency of the AD9763/AD9765/AD9767 AVDD supply over this frequency range is shown in Figure 77.

90

85

80

PSRR (dB)

75

70

0.20.30.40.50.60.70.80.91.01.1

FREQUENCY (MHz)

00617-077

Figure 77. AVDD Power Supply Rejection Ratio vs. Frequency

Rev. G | Page 29 of 44

AD9763/AD9765/AD9767 Data Sheet

Note that the data in Figure 77 is given in terms of current out vs. voltage in. Noise on the analog power supply has the effect of modulating the internal current sources and therefore the output current. The voltage noise on AVDD, therefore, is added in a nonlinear manner to the desired I

. PSRR is very code

OUT

dependent, thus producing mixing effects that can modulate low frequency power supply noise to higher frequencies. Worstcase PSRR for either one of the differential DAC outputs occurs when the full-scale current is directed toward that output. As a result, the PSRR measurement in Figure 77 represents a worstcase condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured.

An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity’s sake, all of this noise is concentrated at 250 kHz (that is, ignore harmonics). To calculate how much of this undesired noise will appear as current noise superimposed on the DAC full-scale current, I Figure 77 at 250 kHz. To calculate the PSRR for a given R

, one must determine the PSRR in decibels using

OUTFS

LOAD

, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 77 by the scaling factor 20 × log(R For example, if R

is 50 , the PSRR is reduced by 34 dB (that

LOAD

).

is, the PSRR of the DAC at 250 kHz, which is 85 dB in Figure 77, becomes 51 dB V

OUT/VIN

).

Proper grounding and decoupling are primary objectives in any high speed, high resolution system. The AD9763/AD9765/AD9767 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, decouple the analog supply (AVDD) to the analog common (ACOM) as close to the chip as physically possible. Similarly, decouple the digital supply (DVDD1/DVDD2) to the digital common (DCOM1/DCOM2) as close to the chip as possible.

For those applications that require a single 5 V or 3.3 V supply for both the analog and digital supplies, a clean analog supply can be generated using the circuit shown in Figure 78. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low-ESR type electrolytic and tantalum capacitors.

FERRITE

TTL/CMOS

LOGIC

CIRCUITS

5V

POWER SUPPLY

Figure 78. Differential LC Filter for Single 5 V and 3.3 V Applications

BEADS

ELECTROLYTIC

10µF

100µF 0.1µF

TO 22µF

TANTALUM

CERAMIC

AVDD

ACOM

00617-078

Rev. G | Page 30 of 44

Data Sheet AD9763/AD9765/AD9767

–

APPLICATIONS INFORMATION

VDSL EXAMPLE APPLICATIONS USING THE AD9765 AND AD9767

Very high frequency digital subscriber line (VDSL) technology is growing rapidly in applications requiring data transfer over relatively short distances. By using quadrature amplitude modulation (QAM) and transmitting the data in discrete multiple tones (DMT), high data rates can be achieved.

As with other multitone applications, each VDSL tone is capable of transmitting a given number of bits, depending on the signal-to-noise ratio (SNR) in a narrow band around that tone. For a typical VDSL application, the tones are evenly spaced over the range of several kHz to 10 MHz. At the high frequency end of this range, performance is generally limited by cable characteristics and environmental factors such as external interferers. Performance at the lower frequencies is much more dependent on the performance of the components in the signal chain. In addition to in-band noise, intermodulation from other tones can also potentially interfere with the data recovery for a given tone. The two graphs in Figure 79 and Figure 81 represent a 500-tone missing bin test vector, with frequencies evenly spaced from 400 Hz to 10 MHz. This test is very commonly done to determine if distortion limits the number of bits that can be transmitted in a tone. The test vector has a series of missing tones around 750 kHz, which is represented in Figure 79, and a series of missing tones around 5 MHz, which is represented in Figure 81. In both cases, the spurious-free dynamic range (SFDR) between the transmitted tones and the empty bins is greater than 60 dB.

20

–30

–40

–50

–60

–70

(dBm)

–80

–90

–100

–110

–120

0.665 0.8250.8050.7850.7650.7450.7250.7050.685

Figure 79. AD9765 Notch in Missing Bin at 750 kHz Is Down >60 dB

FREQUENCY (MHz)

(Peak Amplitude = 0 dBm)

00617-079

20

–30

–40

–50

–60

–70

(dBm)

–80

–90

–100

–110

–120

0.665 0.8250.8050.7850.7650.7450.7250.7050.685

FREQUENCY (MHz)

Figure 80. AD9767 Notch in Missing Bin at 750 kHz Is Down >60 dB

(Peak Amplitude = 0 dBm)

30

–40

–50

–60

–70

(dBm)

–80

–90

–100

–110

–120

4.85 4.90 4.95 5.00 5.05 5.10 5.15

FREQUENCY (MHz )

Figure 81. AD9765 Notch in Missing Bin at 5 MHz Is Down >60 dB

(Peak Amplitude = 0 dBm)

20

–40

–60

(dBm)

–80

–100

–120

4.85 4.90 4.95 5.00 5.05 5.10 5.15

FREQUENCY (MHz )

Figure 82. AD9767 Notch in Missing Bin at 5 MHz Is Down >60 dB

(Peak Amplitude = 0 dBm)

00617-080

00617-081

00617-082

Rev. G | Page 31 of 44

AD9763/AD9765/AD9767 Data Sheet

A

QUADRATURE AMPLITUDE MODULATION (QAM) EXAMPLE USING THE AD9763

QAM is one of the most widely used digital modulation schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum (that is, CDMA) based systems. A QAM signal is a carrier frequency that is modulated in both amplitude (that is, AM modulation) and phase (that is, PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90° phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90° phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency.

A common and traditional implementation of a QAM modulator is shown in Figure 83. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filters shape and limit each component’s spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate, or at a multiple of the QAM symbol rate if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase

between the two baseband channels. A quadrature mixer modulates the I and Q components with the in-phase and quadrature carrier frequency and then sums the two outputs to provide the QAM signal.

10

DAC

DSP

OR

ASIC

CARRIER

FREQUENCY

10

DAC

NYQUIS T FILTERS

0°

Σ

90°

QUADRATURE

MODULATOR

TO MIXER

00617-083

Figure 83. Typical Analog QAM Architecture

In this implementation, it is much more difficult to maintain proper gain and phase matching between the I and Q channels. The circuit implementation shown in Figure 84 helps improve the matching between the I and Q channels, and it shows a path for upconversion using the AD8346 quadrature modulator. The AD9763 provides both I and Q DACs a common reference that improves the gain matching and stability. R

can be used to

CAL

compensate for any mismatch in gain between the two channels. The mismatch can be attributed to the mismatch between R and R

, the effective load resistance of each channel, and/or

SET2

SET1

the voltage offset of the control amplifier in each DAC. The differential voltage outputs of both DACs in the AD9763 are fed into the respective differential inputs of the AD8346 via matching networks.

VDD

DCOM1/

DVDD1/

DCOM2

TEKTRONIX

AWG2021

WITH

OPTION 4

WRT1/IQWRT

CLK1/IQCL K

WRT2/IQSEL

SLEEP FSADJ1 F SADJ2MODE REFIO

NOTES

1. DAC FULL-S CALE OUTPUT CURRENT = I

2. RA, RB, AND RL ARE T HIN FILM RESISTOR NE TWORKS WITH 0.1% M ATCHING, 1% ACCURACY AVAI LABLE FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.

DVDD2

DIGITAL INTERFACE

PORT Q PORT I

256Ω

22nF

I DAC

LATCH

Q DAC

LATCH

2kΩ

20kΩ

AD9763/ AD9765/

AD9767

256Ω

22nF

OUTFS

ACOM

.

Figure 84. Baseband QAM Implementation Using an AD9763 and an AD8346

AVDD

I

DAC

Q

DAC

2kΩ

20kΩ

I

OUT

A

CA

B

A

CA

B

0.1µF

RL

LA

CB

LA

RL

LA

CB

LA

DIFFERENTIAL RLC FILT ER

RL = 200Ω RA = 2500Ω RB = 500Ω RP = 200Ω CA = 280pF CB = 45pF LA = 10µH

= 11mA

I

OUTFS

AVDD = 5.0V VCM = 1.2V

RA RA

RB

RA

RB

C

FILTER

RB

RLRL

VDIFF = 1.82V p-p

RA

0.1µF

BBIP

BBIN

BBQP

BBQN

AD976x

0 TO I

VPBF

OUTFS

PHASE

SPLITTER

AD8346

V

ROHDE & SCHWARZ

SPECTRUM ANALYZ ER

VOUT

+

LOIP

LOIN

ROHDE & SCHWARZ

SIGNAL G ENERATOR

AVDD

RL

RB

DAC

FSEA30B

OR EQUIVALENT

RA

AD8346

V

MOD

00617-084

Rev. G | Page 32 of 44

Data Sheet AD9763/AD9765/AD9767

–

I and Q digital data can be fed into the AD9763 in two ways. In dual-port mode, the digital I information drives one input port, and the digital Q information drives the other input port. If no interpolation filter precedes the DAC, the symbol rate is the rate at which the system clock drives the CLK and WRT pins on the AD9763. In interleaved mode, the digital input stream at Port 1 contains the I and the Q information in alternating digital words. Using IQSEL and IQRESET, the AD9763 can be synchronized to the I and Q data streams. The internal timing of the AD9763 routes the selected I and Q data to the correct DAC output. In interleaved mode, if no interpolation filter precedes the AD9763, the symbol rate is half that of the system clock driving the digital data stream and the IQWRT and IQCLK pins on the AD9763.

CDMA

Code division multiple access (CDMA) is an air transmit/receive scheme in which the signal in the transmit path is modulated with a pseudorandom digital code (sometimes referred to as the spreading code). The effect of this is to spread the transmitted signal across a wide spectrum. Similar to a discrete multitone (DMT) waveform, a CDMA waveform containing multiple subscribers can be characterized as having a high peak to average ratio (that is, crest factor), thus demanding highly linear components in the transmit signal path. The bandwidth of the spectrum is defined by the CDMA standard being used, and in operation it is implemented by using a spreading code with particular characteristics.

Distortion in the transmit path can lead to power being transmitted out of the defined band. The ratio of power transmitted in-band to out-of-band is often referred to as adjacent channel power (ACP). This is a regulatory issue due to the possibility of interference with other signals being transmitted by air. Regulatory bodies define a spectral mask outside of the transmit band, and the ACP must fall under this mask. If distortion in the transmit path causes the ACP to be above the spectral mask, filtering or different component selection is needed to meet the mask requirements.

Figure 85 shows the results of using the AD9763/AD9765/ AD9767 with the AD8346 to reconstruct a wideband CDMA signal centered at 2.4 GHz. The baseband signal is sampled at 65 MSPS and has a chip rate of 8 MHz.

30

–40

–50

–60

==

–70

–80

(dB)

–90

–100

–110

c11

–120

–130

CENTER 2.4GHz

Figure 85. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS, Recreated at

2.4 GHz, Adjacent Channel Power >60 dBm

c11

C0

FREQUENCY

cu1

C0

cu1

SPAN 30MHz3MHz

00617-085

Rev. G | Page 33 of 44

AD9763/AD9765/AD9767 Data Sheet

EVALUATION BOARD

GENERAL DESCRIPTION

The AD9763/AD9765/AD9767-EBZ is an evaluation board for the AD9763/AD9765/AD9767 10-/12-/14-bit dual DAC. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9763/AD9765/AD9767 in any application where a high resolution, high speed conversion is required.

SCHEMATICS

RED

DVDDIN 3

TB1

1

L1

DCASE

VAL VOLT

DVDD AVDD

BLKBLKBLK

This board allows the user the flexibility to operate the AD9763/ AD9765/AD9767 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single-ended and differential outputs. The digital inputs can be used in dual-port or interleaved mode and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. When operating the AD9763/AD9765/AD9767, best performance is obtained by running the digital supply (DVDD1/DVDD2) at

3.3 V and the analog supply (AVDD) at 5 V.

RED

AVDDIN

TB1

L2

BEADBEAD

DCASE

C10C9

VAL VOLT

BLKBLKBLK

TB1

2

INP31

INP32

INP33

INP34

INP35

INP36

INCK2

BLK

1

RCO M

22 22

R1

INP23

R2

3

4

5

6

7

8

9

10

INP24

R3

INP25

R4

INP26

R5

INP27

R6

INP28

R7

INP29

R8

INP30

R9

DGND

10

1

RCO M

R1

22

3

4

5

6

7

8

9

RP10RP15

INP9

R2

INP10

R3

INP11

R4

INP12

R5

INP13

R6

INP14

R7

R8

INCK1

R9

TB1

4

BLK

AGND

10

1

2

3

4

5

6

7

8

9

RCO M

22

RP16

R1

R2

R3

R4

R5

R6

R7

R8

R9

00617-086

1

RCO M

22

R1

2

3

4

5

6

7

8

9

10

RP9

INP1

R2

INP2

R3

INP3

R4

INP4

R5

INP5

R6

INP6

R7

INP7

R8

INP8

R9

Figure 86. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (1)

Rev. G | Page 34 of 44

Data Sheet AD9763/AD9765/AD9767

9

712

Q

Q_

DVDD;16

DGND;8

CLR

PRE

U6

C8

CC0805CC0805

C7

10

.01UF

.1UF

DVDD

1

B

C

4

2

A

3

SW1

JP2

C34

.01UF

CC0805

C33

.1UF

DVDD

CC0805

DCLKIN2

+IN

7

14

CLK

J

K

13

11

SN74F112

5

Q

Q_

DVDD;16

DGND;8

A

CLR

U6

PRE

15

K

CLK

J

3126

SN74F112

3

C

2

B

1

SW2

DVDD

JP1

10

OUT

U2

11

SO16

OUT

DS90LV048B

U2

-IN

+IN

8

5

14

SO16

DS90LV048B

-IN

6

SO16

OUT

DS90LV048B

U2

+IN

-IN

3

4

CLK2

CLK1

WRT1

WRT2

SLEEP

/2 CLOCK DIVIDER

DVDD

12

13

VCC

GND

SO16

U2

DS90LV048B

EN

DVDD

VAL

R30

RC0603

EN

9

16

00617-091

JP9

JP16

JP5

DCLKIN1

15

OUT

U2

+IN

1

1K

RC0603RC0603

R19

1K

R16

DVDD

RC0603

1KR17 R18 1K

RC0603

.1

CC0805

.1

CC0805

C18

C19

1234

T3

T1-1TCUP

5

6

DVDD

JP17

SO16

DS90LV048B

-IN

2

RC0603

JP14

R63 50

JP13

WHT

DGND;3,4,5

SMA200UP

S1

RT1IN

IQWRT

JP4

JP3

R4

5050

RC0805

R3

50

RC0805

R2

50

RC0805

R1

RC0805

WHT

DGND;3,4,5

SMA200UP

S2

1QCLK

CLK1IN

WHT

S3

CLK2IN

DGND;3,4,5

RESET

WHT

DGND;3,4,5

SMA200UP

S4

RT2IN

IQSEL

50

R13

RC0805

WHT

SLEEP

Figure 87. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (2)

Rev. G | Page 35 of 44

AD9763/AD9765/AD9767 Data Sheet

A

O2N

O2P

C24

L6 DNP

LC0805

DNPL5

LC0805

PNDPND

CC0805CC0805

C23

R23 51

RC0603

JP19

RC0603 RC0603

R22 DNP51R21

C31

DNP

CC0603

MODULATED O UTPUT

AGND2;3,4,5

SMAEDGE

RC0603

LOCAL OSC INPUT

RC0603

J1

2

AGND2;3,4,5

SMAEDGE

J2

2

VDD2

BCASE

2

AVDD2

RC0603

R20 50

0R27

R29 0

C28

.1UF

C27

100PF

C29

CC0603CC0603

.1UF

CC0603

15

16

QBBP

AGND2;17

IBBP

2

1

QBBN

IBBN

9

10

13

14

11712

G2

G3

G4A

G4B

VPS2

VOUT

U3

AD834 9

RC0603

G1A

G1B

3

4

5

ENBL

LOIN

LOIP

VPS1

8

6

C20 10UF 10V

2

C30

2

C26

100PF

100PFC25

CC0603 CC0603

CC0603

100PF

2

R28 1K

JP18

ETC1-1-13

SP

1

T4

AVDD2

TP6

RED

AGND2

TP5

BLK

43

5

O1N

O1P

DNP

JP20

R25 51

51R26

RC0603

C32

DNP

CC0603

DNPR24

RC0603

DNPL4

LC0805

L3 DNP

LC0805

DNP

CC0805CC0805

12C22C

Figure 88. Modulator on AD9763/AD9765/AD9767 Evaluation Board

2

JP21

JP22

2

00617-092

Rev. G | Page 36 of 44

Data Sheet AD9763/AD9765/AD9767

00617-093

470470

RC0603

R49R50

RC0603

DUTP1

DUTP5

DUTP4

DUTP3

DUTP2

DUTP9

DUTP8

DUTP7

DUTP6

DUTP13

DUTP14

DUTP12

DUTP11

DUTP10

DCLKIN1

470470

RC0603

R51 R33

RC0603

470 470

RC0603

R53 R52

RC0603

470 470

RC0603

R55R56

RC0603

470

RC0603

R57 R54

RC0603

R58

470470

RC0603

R59

RC0603

R60

470 470

RC0603

470

R61

RC0603

R62

470

RC0603

152

134

116

9

10

RP5

161

143

125

10

RP5

152

10

RP5

RP6

8

107

10

RP5

RP6

116

134

10

RP6

10

RP6

314

116

10

RP6

10

RP6

512

98

10

RP6

INP1

INP3

INP2

INP4

INP5

INP6

INP7

9

3

1

P1

87

65

4

2

14 13

12 11

10

Figure 89. Digital Input Signaling (1)

INP8

INP9

INP10

INP11

INP12

19

RIBBON RA

24 23

22 21

20

18 17

16 15

INP13

INP14

INCK1

710

RP6

10

SPARES

29

32 31

30

28 27

26 25

39

HDR040RA

40

38 37

36 35

34 33

Rev. G | Page 37 of 44

AD9763/AD9765/AD9767 Data Sheet

00617-087

470

RC0603

470

R41 R42

RC0603

DUTP23

DUTP24

DUTP25

DUTP29

DUTP27

DUTP26

DUTP28

DUTP33

DUTP31

DUTP30

DUTP32

DUTP34

DUTP35

DUTP36

DCLKIN2

470470

RC0603

R43 R40

RC0603

470 470

RC0603

R45 R44

RC0603

470 470

RC0603

R39R38

RC0603

470

RC0603

R47 R46

RC0603

R37

470470

RC0603

R36

RC0603

R48

470 470

RC0603

470

R35R34

RC0603

470

RC0603

116

INP23

10

RP7

INP24

152

10

RP7

INP25

RP7

314

134

10

RP7

INP26

512

INP27

10

RP7

10

710

116

10

RP7

INP28

INP29

INP30

98

10

RP710152

INP31

RP8

116

RP8

INP32

314

INP33

10

RP8

INP34

134

10

RP8

512

INP35

10

RP8

116

10

RP8

INP36

1

3

56789

1112

1314

1516

1718

19

2122

10

RIBBON RA

20

P2

2

4

Figure 90. Digital Input Signaling (2)

Rev. G | Page 38 of 44

98

10

RP8

INCK2

710

RP8

10

SPARES

2324

2526

2728

29

3132

3334

3536

3738

39

HDR040RA

30

HDR040RA

40

Data Sheet AD9763/AD9765/AD9767

OUT1

SMA200UP

AGND;3,4,5

S6

WHT

REFIO

C14

.1UF

CC0805

WHT

6

5

T5

T1-1TCUP

BL1

1234

VAL

R11

RC07CUP

R6

RC0805

5050

C5

CC0805

R5

RC0805

BL2

RC0805

R14 256

R15 256

RC0805

1.92KR10

22NF

R9 1.92K

C16

WHT

CC0805

C17

10PF

BL3

T6

JP10

RC0805

34

WHT

50

R8

RC0805

10PF

C6

CC0805

50

R7

RC0805

OUT2

SMA200UP

AGND;3,4,5

S11

WHT

6

5

BL4

T1-1TCUP

1

2

VAL

R12

RC07CUP

AVDD

00617-088

RC0805

R31 10

JP23

CC0805

C4

10PF

O1P

O1N

JP6 JP7

31

BA

2

JP15

ACOM

AVDD

DVDD

C3

.1UF

BA

JP8

2

13

MODE

DVDD

47

48

AVDD

MODE

44

4146404539

43

42

IA1

IB1

REFIO

ACOM1

FSADJ1

FSADJ2

C15

CC0805

10PF

RC0805

10R32

.1UF

C13C11 C12

O2N

O2P

JP24

JP12 JP11

SLEEP

DUTP35

DUTP36

36

38

37

IB2

IA2

ACOM

DB0P2

DB1P2

SLEEP

DUTP31

DUTP32

DUTP33

DUTP34

32

DB2P2

DB3P2

DB4P2

DB5P2

DUTP27

DUTP28

DUTP29

DUTP30

DUTP25

DUTP26

27

DB6P2

DB7P2

DB8P2

DB9P2

DB10P2

DB11P2

.01UF

CC0805

CC0805 CC0805

VAL

U1

AD9763/65/67

.01UF

C2C1

CLK1

DVDD1

CLK2

WRT1

WRT2

18

19

17

20

DB12P2

DB13P2MSB

DCOM2

DVDD2

23

22

DB10P1

DB11P1

DB12P1

DB13P1MSB

VAL

CC0805 CC0805 CC0805

DB8P1

DB9P1

4263252241

DB4P1

DB5P1

DB6P1

DB7P1

9318307296285

DB0P1

DB1P1

DB2P1

DB3P1

DCOM1

14

13351234113310

152116

CLK2

CLK1

WRT2

DUTP5

DUTP6

DUTP7

DUTP8

DUTP1

DUTP2

DUTP3

DUTP4

DUTP9

DUTP10

DUTP11

DUTP12

DUTP13

WRT1

DUTP14

DUTP23

DUTP24

Figure 91. Device Under Test/Analog Output Signal Conditioning

Rev. G | Page 39 of 44

AD9763/AD9765/AD9767 Data Sheet

EVALUATION BOARD LAYOUT

00617-089

Figure 92. Assembly, Top Side

Rev. G | Page 40 of 44

Data Sheet AD9763/AD9765/AD9767

00617-090

Figure 93. Assembly, Bottom Side

Rev. G | Page 41 of 44

AD9763/AD9765/AD9767 Data Sheet

OUTLINE DIMENSIONS

9.20

1

12

0.50

BSC

48

13

9.00 SQ

8.80

PIN 1

TOP VIEW

(PINS DO WN)

37

36

7.20

7.00 SQ

6.80

25

24

0.27

0.22

0.17

051706-A

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.75

0.60

0.45

0.20

0.09 7°

3.5° 0°

0.08 COPLANARIT Y

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

1.60 MAX

VIEW A

LEAD PITCH

Figure 94. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9763ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9763ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9763-EBZ Evaluation Board AD9765AST –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765ASTRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9765-EBZ Evaluation Board AD9767ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9767ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD9767-EBZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. G | Page 42 of 44

Data Sheet AD9763/AD9765/AD9767

NOTES

Rev. G | Page 43 of 44

AD9763/AD9765/AD9767 Data Sheet

NOTES

Rev. G | Page 44 of 44

Datasheet AD9763 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

Revision History: AD9763/AD9765/AD9767

Revision History: AD9763

Revision History: AD9765

Revision History: AD9767

SPECIFICATIONS

DC SPECIFICATIONS

DYNAMIC SPECIFICATIONS

DIGITAL SPECIFICATIONS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

AD9763

AD9765

AD9767

TERMINOLOGY

THEORY OF OPERATION

FUNCTIONAL DESCRIPTION

REFERENCE OPERATION

GAIN CONTROL MODE

SETTING THE FULL-SCALE CURRENT

DAC TRANSFER FUNCTION

ANALOG OUTPUTS

DIGITAL INPUTS

DAC TIMING

Dual-Port Mode Timing

Interleaved Mode Timing

Input Clock and Data Timing Relationship

SLEEP MODE OPERATION

POWER DISSIPATION

APPLYING THE AD9763/AD9765/AD9767

OUTPUT CONFIGURATIONS

DIFFERENTIAL COUPLING USING A TRANSFORMER

DIFFERENTIAL COUPLING USING AN OP AMP

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION

POWER AND GROUNDING CONSIDERATIONS

Power Supply Rejection

APPLICATIONS INFORMATION

VDSL EXAMPLE APPLICATIONS USING THE AD9765 AND AD9767

QUADRATURE AMPLITUDE MODULATION (QAM) EXAMPLE USING THE AD9763

CDMA

EVALUATION BOARD

GENERAL DESCRIPTION

SCHEMATICS

EVALUATION BOARD LAYOUT

OUTLINE DIMENSIONS

ORDERING GUIDE