Page 1
12-Bit, 125 MSPS High Performance
a
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 79 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Basestations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9752 is a 12-bit resolution, wideband, second generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog-converters (DACs). The TxDAC
which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options,
small outline package and pinout, thus providing an upward or
downward component selection path based on performance,
resolution and cost. The AD9752 offers exceptional ac and dc
performance while supporting update rates up to 125 MSPS.
The AD9752’s flexible single-supply operating range of 4.5 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 65 mW, without a significant degradation in
performance, by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 20 mW.
The AD9752 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V to +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and
5703519. Other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
family,
TxDAC® D/A Converter
AD9752*
FUNCTIONAL BLOCK DIAGRAM
+5V
R
SET
CLOCK
0.1mF
+5V
REFLO
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
DIGITAL DATA INPUTS (DB11–DB0)
150pF
SEGMENTED
SWITCHES
LATCHES
The AD9752 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support singleended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9752 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9752 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9752 may operate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9752 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9752 is a member of the wideband TxDAC product
family that provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and
cost. The entire family of TxDACs is available in industry
standard pinouts.
2. Manufactured on a CMOS process, the AD9752 uses a
proprietary switching technique that enhances dynamic
performance beyond that previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +2.7 V to +5 V CMOS logic families. The AD9752 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 4.5 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9752 to operate at reduced power levels.
5. The current output(s) of the AD9752 can be easily configured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
CURRENT
SOURCE
ARRAY
LSB
SWITCHES
AVDD ACOM
AD9752
ICOMP
IOUTA
IOUTB
0.1mF
Page 2
AD9752–SPECIFICATIONS
DC SPECIFICATIONS
(T
to T
MIN
, AVDD = +5 V, DVDD = +5 V, I
MAX
= 20 mA, unless otherwise noted)
OUTFS
Parameter Min Typ Max Units
RESOLUTION 12 Bits
DC ACCURACY
1
Integral Linearity Error (INL)
T
= +25°C –1.5 ±0.5 +1.5 LSB
A
to T
T
MIN
MAX
–2.0 +2.0 LSB
Differential Nonlinearity (DNL)
T
= +25°C –0.75 ±0.25 +0.75 LSB
A
T
MIN
to T
MAX
–1.0 +1.0 LSB
ANALOG OUTPUT
Offset Error –0.02 +0.02 % of FSR
Gain Error
Gain Error
Full-Scale Output Current
(Without Internal Reference) –2 ±0.5 +2 % of FSR
(With Internal Reference) –5 ±1.5 +5 % of FSR
2
2.0 20.0 mA
Output Compliance Range –1.0 1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current
3
100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 MΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift
Gain Drift
(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
AVDD 4.5 5.0 5.5 V
DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
5
(5 V, I
Power Supply Rejection Ratio
4
)
AVDD
5
)
DVDD
OUTFS
6
)
AVDD
= 20 mA) 185 220 mW
7
—AVDD –0.4 +0.4 % of FSR/V
34 39 mA
35mA
48mA
Power Supply Rejection Ratio7—DVDD –0.025 +0.025 % of FSR/V
OPERATING RANGE –40 +85 °C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
Use an external buffer amplifier to drive any external load.
4
Requires +5 V supply.
5
Measured at f
6
Logic level for SLEEP pin must be referenced to AVDD. Min VIH = 3.5 V.
7
±5% Power supply variation.
Specifications subject to change without notice.
= 25 MSPS and I
CLOCK
, is 32 × the I
OUTFS
current.
REF
= static full scale (20 mA).
OUT
–2–
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Page 3
AD9752
(T
to T
, AVDD = +5 V, DVDD = +5 V, I
MAX
DYNAMIC SPECIFICATIONS
MIN
50 ⍀ Doubly Terminated, unless otherwise noted)
Parameter Min Typ Max Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t
) (to 0.1%)
ST
)1ns
PD
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I
= 20 mA) 50 pA/√Hz
OUTFS
= 2 mA) 30 pA/√Hz
OUTFS
) 125 MSPS
CLOCK
1
1
1
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
= 25 MSPS; f
CLOCK
= 1.00 MHz
OUT
0 dBFS Output
= +25°C 75 84 dBc
T
A
–6 dBFS Output 76 dBc
–12 dBFS Output 81 dBc
= 50 MSPS; f
f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
= 50 MSPS; f
f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 100 MSPS; f
CLOCK
= 100 MSPS; f
f
CLOCK
f
= 100 MSPS; f
CLOCK
= 100 MSPS; f
f
CLOCK
= 1.00 MHz 81 dBc
OUT
= 2.51 MHz 81 dBc
OUT
= 5.02 MHz 76 dBc
OUT
= 14.02 MHz 62 dBc
OUT
= 20.2 MHz 60 dBc
OUT
= 2.5 MHz 78 dBc
OUT
= 5 MHz 76 dBc
OUT
= 20 MHz 63 dBc
OUT
= 40 MHz 55 dBc
OUT
Spurious-Free Dynamic Range within a Window
f
= 25 MSPS; f
CLOCK
= 50 MSPS; f
f
CLOCK
f
= 100 MSPS; f
CLOCK
= 1.00 MHz 84 93 dBc
OUT
= 5.02 MHz; 2 MHz Span 86 dBc
OUT
= 5.04 MHz; 4 MHz Span 86 dBc
OUT
Total Harmonic Distortion
= 25 MSPS; f
f
CLOCK
T
= +25°C –82 –74 dBc
A
f
= 50 MHz; f
CLOCK
= 100 MHz; f
f
CLOCK
= 1.00 MHz
OUT
= 2.00 MHz –76 dBc
OUT
= 2.00 MHz –76 dBc
OUT
Multitone Power Ratio (8 Tones at 110 kHz Spacing)
f
= 20 MSPS; f
CLOCK
= 2.00 MHz to 2.99 MHz
OUT
0 dBFS Output 81 dBc
–6 dBFS Output 81 dBc
–12 dBFS Output 85 dBc
–18 dBFS Output 86 dBc
NOTES
1
Measured single ended into 50 Ω load.
Specifications subject to change without notice.
= 20 mA, Differential Transformer Coupled Output,
OUTFS
35 ns
2.5 ns
2.5 ns
REV. 0 –3–
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AD9752
WARNING!
ESD SENSITIVE DEVICE
DIGITAL SPECIFICATIONS
(T
to T
MIN
, AVDD = +5 V, DVDD = +5 V, I
MAX
= 20 mA, unless otherwise noted)
OUTFS
Parameter Min Typ Max Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V
1
1
3.5 5 V
0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t
NOTES
1
When DVDD = +5 V and Logic 1 voltage ≈3.5 V and Logic 0 voltage ≈1.3 V. IVDD can increase by up to 10 mA, depending on f
Specifications subject to change without notice.
) 2.0 ns
S
) 1.5 ns
H
) 3.5 ns
LPW
.
CLOCK
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
H
t
LPW
t
ST
0.1%
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Units
AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
ICOMP ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
Model Range Description Options*
AD9752AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9752ARU –40°C to +85°C 28-Lead TSSOP RU-28
AD9752-EB Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
θ
= 71.4°C/W
JA
= 23°C/W
θ
JC
28-Lead TSSOP
θ
= 97.9°C/W
JA
= 14.0°C/W
θ
JC
ORDERING GUIDE
Temperature Package Package
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9752 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
Page 5
AD9752
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9752
NC = NO CONNECT
(MSB) DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
CLOCK
DVDD
DCOM
NC
AVDD
ICOMP
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Pin No. Name Description
1 DB11 Most Significant Data Bit (MSB).
2–11 DB10–DB1 Data Bits 1–10.
12 DB0 Least Significant Data Bit (LSB).
13, 14,
19, 25 NC No Internal Connection.
15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated
if not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 NC No Connect.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.
REV. 0
–5–
Page 6
AD9752
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported
in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing multiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
DVDD
DCOM
R
SET
2kV
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
0.1mF
+5V
50V
+5V
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
CLOCK
OUTPUT
150pF
SEGMENTED SWITCHES
FOR DB11–DB3
LATCHES
DIGITAL
DATA
TEKTRONIX
AWG-2021
W/OPTION 4
AVDD ACOM
PMOS
CURRENT SOURCE
ARRAY
LSB
SWITCHES
AD9752
Figure 2. Basic AC Characterization Test Setup
ICOMP
IOUTA
IOUTB
50V
0.1mF
MINI-CIRCUITS
100V
50V
20pF
20pF
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
T1-1T
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
–6–
REV. 0
Page 7
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, I
= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)
OUTFS
AD9752
90
25MSPS
80
70
SFDR – dB
60
50
40
0
65MSPS
1 100
f
OUT
Figure 3. SFDR vs. f
90
80
70
60
SFDR – dBc
50
–6dBFS
0dBFS
50MSPS
– MHz
OUT
125MSPS
10
@ 0 dBFS
–12dBFS
90
80
70
SFDR – dB
60
50
40
0
–12dBFS
46810
214
f
OUT
Figure 4. SFDR vs. f
90
80
70
60
SFDR – dB
50
–6dBFS
0dBFS
–12dBFS
– MHz
@ 25 MSPS
OUT
–6dBFS
0dBFS
90
80
70
60
SFDR – dBc
50
40
12
05 25
Figure 5. SFDR vs. f
90
80
70
SFDR – dBc
60
20mA FS
0dBFS
5mA FS
–6dBFS
–12dBFS
10
f
OUT
10mA FS
15 20
– MHz
@ 50 MSPS
OUT
40
0
10 15 25
530
f
OUT
Figure 6. SFDR vs. f
90
2.27MHz@25MSPS
80
70
60
SFDR – dB
50
40
–30 –25
11.36MHz@125MSPS
–20 –15 –5
A
OUT
20
– MHz
@ 65 MSPS
OUT
4.55MHz@50MSPS
5.91MHz@65MSPS
–10
– dBFS
Figure 9. Single-Tone SFDR vs. A
@ f
OUT
= f
CLOCK
/11
0
OUT
40
0
10 60
20 30 50
f
OUT
Figure 7. SFDR vs. f
90
80
5MHz@25MSPS
70
SFDR – dB
60
50
25MHz@125MSPS
40
–30 –25
–20 –15 –5
A
OUT
– MHz
OUT
– dBFS
10MHz@50MSPS
40
@ 125 MSPS
13MHz@65MSPS
–10
Figure 10. Single-Tone SFDR vs.
A
@ f
OUT
OUT
= f
CLOCK
/5
50
0
212
Figure 8. SFDR vs. f
@ 25 MSPS and 0 dBFS
80
70
5mA FS
SNR – dB
60
50
0
0
20 120
Figure 11. SNR vs. f
@ f
= 2 MHz and 0 dBFS
OUT
– MHz
OUT
– MSPS
CLOCK
8
and I
20mA FS
80
and I
OUTFS
OUTFS
46 10
f
OUT
10mA FS
40 60 100
f
CLOCK
REV. 0
–7–
Page 8
AD9752
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
ERROR – LSB
–0.1
–0.2
–0.3
–0.4
0
1000 2000 3000
CODE
Figure 12. Typical INL
0
–10
–20
–30
–40
–50
–60
–70
SIGNAL AMPLITUDE – dBm
–80
–90
–100
0
10 20 30
f
– MHz
OUT
f
CLK
f
OUT1
f
OUT2
A
OUT
SFDR = 68.4dBc
40 50
Figure 15. Dual-Tone SFDR
= 125MSPS
= 13.5MHz
= 14.5MHz
= 0dBFS
4000
60
0.1
0.0
–0.1
–0.2
ERROR – LSB
–0.3
–0.4
–0.5
0
1000 2000 3000
CODE
Figure 13. Typical DNL
0
f
–10
–20
–30
–40
–50
–60
–70
SIGNAL AMPLITUDE – dBm
–80
–90
–100
0
5.0 10.0 15.0
CLK
f
OUT1
f
OUT2
f
OUT3
f
OUT4
SFDR = 69dBc
AMPLITUDE = 0dBFS
f
– MHz
OUT
Figure 16. Four-Tone SFDR
= 65MSPS
= 6.25MHz
= 6.75MHz
= 7.25MHz
= 7.75MHz
20.0 25.0
4000
30.0
90
f
= 4MHz
80
70
SFDR – dBc
60
50
–55 95–30 –5 20
TEMPERATURE – 8C
OUT
f
= 10MHz
OUT
f
= 29MHz
OUT
f
= 40MHz
OUT
45 70
Figure 14. SFDR vs. Temperature @
125 MSPS, 0 dBFS
–8–
REV. 0
Page 9
+5V
AD9752
0.1mF
V
REFIO
R
CLOCK
SET
2kV
I
REF
+5V
REFLO
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
150pF
CURRENT SOURCE
SEGMENTED SWITCHES
FOR DB11–DB3
LATCHES
DIGITAL DATA INPUTS (DB11–DB0)
Figure 17. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Figure 17 shows a simplified block diagram of the AD9752.
The AD9752 consists of a large PMOS current source array that
is capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted fractions of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on a new
architecture that drastically improves distortion performance.
This new switch architecture reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.
The analog and digital sections of the AD9752 have separate
power supply inputs (i.e., AVDD and DVDD). The digital
section, which is capable of operating up to a 125 MSPS clock
rate and over a +2.7 V to +5.5 V operating range, consists of
edge-triggered latches and segment decoding logic circuitry.
The analog section, which can operate over a +4.5 V to +5.5 V
range, includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, R
both the reference control amplifier and voltage reference V
sets the reference current I
. The external resistor, in combination with
SET
, which is mirrored over to the
REF
REFIO
,
segmented current sources with the proper scaling factor. The
full-scale current, I
, is thirty-two times the value of I
OUTFS
REF
.
DAC TRANSFER FUNCTION
The AD9752 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
I
, when all bits are high (i.e., DAC CODE = 4095) while
OUTFS
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function
of both the input code and I
IOUTA = (DAC CODE/4096) × I
and can be expressed as:
OUTFS
OUTFS
(1)
AVDD
PMOS
ARRAY
SWITCHES
ACOM
AD9752
0.1mF
ICOMP
V
= V
LSB
IOUTA
IOUTB
I
OUTB
I
OUTA
DIFF
V
R
50V
OUTB
LOAD
OUTA
– V
OUTB
V
R
50V
OUTA
LOAD
IOUTB = (4095 – DAC CODE)/4096 × I
OUTFS
(2)
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, I
current I
V
REFIO
I
where I
, which is nominally set by a reference voltage
REF
and external resistor R
= 32 × I
OUTFS
REF
= V
REF
REFIO/RSET
is a function of the reference
OUTFS
. It can be expressed as:
SET
(3)
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
R
LOAD
, which are tied to analog common, ACOM. Note,
LOAD
may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply :
V
= IOUTA × R
OUTA
V
= IOUTB × R
OUTB
Note the full-scale value of V
LOAD
LOAD
OUTA
and V
should not exceed
OUTB
(5)
(6)
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, V
, appearing across IOUTA and
DIFF
IOUTB is:
V
= (IOUTA – IOUTB) × R
DIFF
Substituting the values of I
OUTA
, I
LOAD
OUTB
, and I
REF
; V
DIFF
(7)
can be
expressed as:
V
= {(2 DAC CODE – 4095)/4096} ×
DIFF
(32 R
LOAD/RSET
) × V
REFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9752 differentially. First, the differential operation will help cancel common-mode error sources associated
with I
OUTA
and I
such as noise, distortion and dc offsets.
OUTB
Second, the differential code dependent current and subsequent
voltage, V
output (i.e., V
, is twice the value of the single-ended voltage
DIFF
OUTA
or V
), thus providing twice the signal
OUTB
power to the load.
Note, the gain drift temperature performance for a single-ended
(V
OUTA
and V
) or differential output (V
OUTB
) of the AD9752
DIFF
can be enhanced by selecting temperature tracking resistors for
R
LOAD
and R
due to their ratiometric relationship as shown
SET
in Equation 8.
REV. 0
–9–
Page 10
AD9752
REFERENCE OPERATION
The AD9752 contains an internal 1.20 V bandgap reference
that can easily be disabled and overridden by an external reference. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 18, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1 µF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.
+5V
AVDD
CURRENT
SOURCE
ARRAY
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
0.1mF
2kV
+1.2V REF
REFIO
FS ADJ
AD9752
REFLO
150pF
Figure 18. Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 19. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1 µF compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the
external reference.
AVDD
AVDD
EXTERNAL
REF
REFLO
+1.2V REF
V
REFIO
R
I
SET
REF
V
REFIO/RSET
REFIO
FS ADJ
=
AD9752
150pF
CURRENT
SOURCE
ARRAY
REFERENCE
CONTROL
AMPLIFIER
AVDD
REFERENCE CONTROL AMPLIFIER
The AD9752 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, I
OUTFS
.
The control amplifier is configured as a V-I converter as shown
in Figure 19, such that its current output, I
the ratio of the V
in Equation 4. I
and an external resistor, R
REFIO
is copied over to the segmented current
REF
sources with the proper scaling factor to set I
, is determined by
REF
SET
OUTFS
, as stated
as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
I
over a 2 mA to 20 mA range by setting IREF between
OUTFS
62.5 µA and 625 µA. The wide adjustment span of I
OUTFS
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9752, which is
proportional to I
(refer to the Power Dissipation section).
OUTFS
The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 0.5 MHz. The output of the control amplifier is
internally compensated via a 150 pF capacitor that limits the
control amplifier small-signal bandwidth and reduces its
output impedance. Since the –3 dB bandwidth corresponds to
the dominant pole, and hence the time constant, the settling
time of the control amplifier to a stepped reference input response can be approximated. In this case, the time constant can
be approximated to be 320 ns.
There are two methods in which I
. The first method is suitable for a single-supply system in
R
SET
can be varied for a fixed
REF
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing I
to be varied for a fixed R
REF
. Since the
SET
input impedance of REFIO is approximately 1 MΩ, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 20 using the AD7524 and an external 1.2 V reference,
the AD1580.
Figure 19. External Reference Configuration
AVDD
1.2V
AD1580
R
OUT1
OUT2
AGND
FB
AD7524
V
DD
V
DB7–DB0
Figure 20. Single-Supply Gain Control Circuit
REF
0.1V TO 1.2V
R
SET
–10–
I
REF
V
REF/RSET
AVDD
REFLO
+1.2V REF
REFIO
FS ADJ
=
AD9752
150pF
AVDD
CURRENT
SOURCE
ARRAY
REV. 0
Page 11
AD9752
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and I
varied by an external voltage, V
, applied to R
GC
via an ampli-
SET
REF
is
fier. An example of this method is shown in Figure 21, in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
GC
, is
referenced to ACOM and should not exceed 1.2 V. The value
of R
SET
is such that I
REFMAX
and I
do not exceed 62.5 µA
REFMIN
and 625 µA, respectively. The associated equations in Figure 21
can be used to determine the value of R
REFLO
+1.2V REF
REFIO
I
REF
I
= (1.2–VGC)/R
REF
WITH V
FS ADJ
AD9752
< V
GC
SET
REFIO
1mF
V
R
SET
GC
.
SET
150pF
AND 62.5mA # I
AVDD
AVDD
CURRENT
SOURCE
ARRAY
# 625A
REF
Figure 21. Dual-Supply Gain Control Circuit
ANALOG OUTPUTS
The AD9752 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, V
V
, via a load resistor, R
OUTB
, as described in the DAC
LOAD
OUTA
and
Transfer Function section by Equations 5 through 8. The
differential voltage, V
, existing between V
DIFF
OUTA
and V
OUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 22 shows the equivalent analog output circuit of the
AD9752 consisting of a parallel combination of PMOS differential current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS
switches and is typically 100 kΩ in parallel with 5 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., V
OUTA
and V
OUTB
)
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, I
. Although the output impedance’s
OUTFS
signal dependency can be a source of dc nonlinearity and ac linearity (i.e., distortion), its effects can be limited if certain precautions are noted.
AVDD
IOUTBIOUTA
R
LOAD
R
LOAD
Figure 22. Equivalent Analog Output
IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9752.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.25 V for an I
= 20 mA to 1.00 V for an I
OUTFS
. It degrades slightly from its
OUTFS
OUTFS
=
2 mA. Operation beyond the positive compliance range will
induce clipping of the output signal which severely degrades
the AD9752’s linearity and distortion performance.
For applications requiring the optimum dc linearity, IOUTA
and/or IOUTB should be maintained at a virtual ground via an
I-V op amp configuration. Maintaining IOUTA and/or IOUTB
at a virtual ground keeps the output impedance of the AD9752
fixed, significantly reducing its effect on linearity. However,
it does not necessarily lead to the optimum distortion performance due to limitations of the I-V op amp. Note that the
INL/DNL specifications for the AD9752 are measured in
this manner using IOUTA. In addition, these dc linearity
specifications remain virtually unaffected over the specified
power supply range of 4.5 V to 5.5 V.
Operating the AD9752 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends
from –1.0 V to +1.25 V, optimum distortion performance is
achieved when the maximum full-scale signal at IOUTA and
IOUTB does not exceed approximately 0.5 V. A properly selected transformer with a grounded center-tap will allow the
AD9752 to provide the required power and voltage levels to
different loads while maintaining reduced voltage swings at
IOUTA and IOUTB. DC-coupled applications requiring a
differential or single-ended output configuration should size
accordingly. Refer to Applying the AD9752 section for
R
LOAD
examples of various output configurations.
The most significant improvement in the AD9752’s distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both
IOUTA and IOUTB can be substantially reduced by the
common-mode rejection of a transformer or differential amplifier. These common-mode error sources include evenorder distortion products and noise. The enhancement in
distortion performance becomes more significant as the reconstructed waveform’s frequency content increases and/or its
amplitude decreases.
The distortion and noise performance of the AD9752 is also
slightly dependent on the analog and digital supply as well as the
full-scale current setting, I
. Operating the analog supply at
OUTFS
5.0 V ensures maximum headroom for its internal PMOS current
sources and differential switches leading to improved distortion
performance. Although I
20 mA, selecting an I
OUTFS
can be set between 2 mA and
OUTFS
of 20 mA will provide the best distortion and noise performance also shown in Figure 8. The
noise performance of the AD9752 is affected by the digital supply (DVDD), output frequency, and increases with increasing
clock rate as shown in Figure 11. Operating the AD9752 with
low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise.
REV. 0
–11–
Page 12
AD9752
In summary, the AD9752 achieves the optimum distortion and
noise performance under the following conditions:
(1) Differential Operation.
(2) Positive voltage swing at IOUTA and IOUTB limited to
+0.5 V.
(3) I
set to 20 mA.
OUTFS
(4) Analog Supply (AVDD) set at 5.0 V.
(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-
priate logic levels.
Note that the ac performance of the AD9752 is characterized
under the above mentioned operating conditions.
DIGITAL INPUTS
The AD9752’s digital input consists of 12 data input pins and a
clock input pin. The 12-bit parallel data inputs follow standard
positive binary coding where DB11 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met;
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
V
THRESHOLD
set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD/2 (±20%)
The internal digital circuitry of the AD9752 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V
. A DVDD of 3 V to 3.3 V will typically ensure
OH(MAX)
proper compatibility with most TTL logic families. Figure 23
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9752 remains enabled if this input is left disconnected.
data interface circuitry should be specified to meet the minimum setup and hold times of the AD9752 as well as its required min/max input logic level thresholds. Typically, the
selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20 Ω to 100 Ω) between the
AD9752 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. For longer run lengths and high data
update rates, strip line techniques with proper termination resistors should be considered to maintain “clean” digital inputs. Also,
operating the AD9752 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feedthrough.
The external clock driver circuitry should provide the AD9752
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note, the clock input could also be driven via a sine wave, which is
centered around the digital threshold (i.e., DVDD/2), and meets
the min/max logic threshold. This will typically result in a slight
degradation in the phase noise, which becomes more noticeable
at higher sampling rates and output frequencies. Also, at higher
sampling rates, the 20% tolerance of the digital logic threshold
should be considered since it will affect the effective clock duty
cycle and subsequently cut into the required data setup and
hold times.
INPUT CLOCK/DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9752 is positive edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9752 is to
make the data transitions shortly after the positive clock edge.
This becomes more important as the sample rate increases. Figure
24 shows the relationship of SNR to clock placement with different sample rates and different frequencies out. Note that at
the lower sample rates, much more tolerance is allowed in clock
placement, while at higher rates, much more care must be taken.
68
64
FS = 65MSPS
60
DVDD
DIGITAL
INPUT
Figure 23. Equivalent Digital Input
Since the AD9752 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
–12–
56
52
SNR – dB
48
44
40
–8 10–6 –4 –2 0 2 4 6 8
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE – ns
FS = 125MSPS
Figure 24. SNR vs. Clock Placement @ f
= 10 MHz
OUT
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Page 13
AD9752
SLEEP MODE OPERATION
The AD9752 has a power-down function which turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level “1” to the SLEEP pin. This digital input also contains an active pull-down circuit that ensures the AD9752 remains enabled if this input is left disconnected. The AD9752
takes less than 50 ns to power down and approximately 5 µs to
power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9752 is dependent on
several factors which include: (1) AVDD and DVDD, the
power supply voltages; (2) I
(3) f
, the update rate; (4) and the reconstructed digital
CLOCK
, the full-scale current output;
OUTFS
input waveform. The power dissipation is directly proportional
to the analog supply current, I
. I
rent, I
DVDD
is directly proportional to I
AVDD
Figure 25 and is insensitive to f
Conversely, I
form, f
CLOCK
show I
DVDD
(f
OUT/fCLOCK
is dependent on both the digital input wave-
DVDD
, and digital supply DVDD. Figures 26 and 27
as a function of full-scale sine wave output ratios
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note, how I
, and the digital supply cur-
AVDD
CLOCK
.
is reduced by more
DVDD
as shown in
OUTFS
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
35
30
25
– mA
20
AVDD
I
15
10
5
2204 6 8 1012141618
Figure 25. I
18
16
14
12
10
– mA
8
DVDD
I
6
4
2
0
0.01 10.1
Figure 26. I
I
– mA
OUTFS
vs. I
AVDD
RATIO (f
CLOCK/fOUT
vs. Ratio @ DVDD = 5 V
DVDD
OUTFS
)
125MSPS
100MSPS
50MSPS
25MSPS
5MSPS
8
6
– mA
4
DVDD
I
2
0
0.01 10.1
Figure 27. I
RATIO (f
vs. Ratio @ DVDD = 3 V
DVDD
CLOCK/fOUT
125MSPS
100MSPS
50MSPS
25MSPS
5MSPS
)
APPLYING THE AD9752
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations for the AD9752. Unless otherwise noted, it is assumed
that I
is set to a nominal 20 mA. For applications requir-
OUTFS
ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain and/or level shifting.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, R
, referred to ACOM. This con-
LOAD
figuration may be more suitable for a single-supply system
requiring a dc coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter thus
converting IOUTA or IOUTB into a negative unipolar voltage.
This configuration provides the best dc linearity since IOUTA
or IOUTB is maintained at a virtual ground. Note, IOUTA
provides slightly better performance than IOUTB.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 28. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only.
REV. 0
–13–
Page 14
AD9752
MINI-CIRCUITS
IOUTA
AD9752
IOUTB
T1-1T
OPTIONAL R
DIFF
R
LOAD
Figure 28. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., V
OUTA
and V
OUTB
)
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9752. A
differential resistor, R
, may be inserted in applications in
DIFF
which the output of the transformer is connected to the load,
, via a passive reconstruction filter or cable. R
R
LOAD
DIFF
is determined by the transformer’s impedance ratio and provides the
proper source termination which results in a low VSWR. Note
that approximately half the signal power will be dissipated across
.
R
DIFF
DIFFERENTIAL USING AN OP AMP
An op amp can also be used to perform a differential to singleended conversion as shown in Figure 29. The AD9752 is configured with two equal load resistors, R
, of 25 Ω. The
LOAD
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB forming a real pole in a low-pass filter.
The addition of this capacitor also enhances the op amps distortion performance by preventing the DACs high slewing output
from overloading the op amp’s input.
500V
AD9752
IOUTA
IOUTB
C
OPT
225V
225V
25V25V
AD8055
500V
Figure 29. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential op amp circuit is configured to provide some additional
signal gain. The op amp must operate off of a dual supply since
its output is approximately ±1.0 V. A high speed amplifier such
as the AD8055 or AD9632 capable of preserving the differential
performance of the AD9752 while meeting other system level
objectives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 30 provides the necessary level-shifting required in a single supply system. In this
case, AVDD which is the positive analog supply for both the
AD9752 and the op amp is also used to level-shift the differential output of the AD9752 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
500V
AD9752
IOUTA
IOUTB
C
OPT
225V
1kV
AD8041
1kV
AVDD
225V
25V25V
Figure 30. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 31 shows the AD9752 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50 Ω cable since the nominal full-scale current, I
20 mA flows through the equivalent R
case, R
represents the equivalent load resistance seen by
LOAD
of 25 Ω. In this
LOAD
OUTFS
, of
IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
Different values of I
OUTFS
and R
can be selected as long as
LOAD
LOAD
.
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL) as
discussed in the ANALOG OUTPUT section of this data sheet.
For optimum INL performance, the single-ended, buffered
voltage output configuration is suggested.
AD9752
IOUTA
IOUTB
I
OUTFS
= 20mA
25V
50V
V
OUTA
= 0 TO +0.5V
50V
Figure 31. 0 V to +0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 32 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9752
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC’s INL performance as discussed in the ANALOG
OUTPUT section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the
product of R
and I
FB
within U1’s voltage output swing capabilities by scaling I
. The full-scale output should be set
OUTFS
OUTFS
and/or RFB. An improvement in ac distortion performance may
result with a reduced I
since the signal current U1 will be
OUTFS
required to sink will be subsequently reduced.
–14–
REV. 0
Page 15
AD9752
C
OPT
R
FB
200V
U1
V
= I
OUTFS
3 R
FB
OUT
AD9752
IOUTA
IOUTB
I
OUTFS
= 10mA
200V
Figure 32. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these circuits, the implementation and construction of the printed circuit board design
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 42-47 illustrate the recommended printed
circuit board ground, power and signal plane layouts which are
implemented on the AD9752 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution
(i.e., AVDD, DVDD). This is referred to as Power Supply
Rejection Ratio (PSRR). For dc variations of the power supply,
the resulting performance of the DAC directly corresponds to a
gain error associated with the DAC’s full-scale current, I
OUTFS
.
AC noise on the dc supplies is common in applications where
the power distribution is generated by a switching power supply.
Typically, switching power supply noise will occur over the
spectrum from tens of kHz to several MHz. PSRR vs. frequency
of the AD9752 AVDD supply, over this frequency range, is
given in Figure 33.
90
frequency power supply noise to higher frequencies. Worst case
PSRR for either one of the differential DAC outputs will occur
when the full-scale current is directed towards that output. As a
result, the PSRR measurement in Figure 33 represents a worst
case condition in which the digital inputs remain static and the
full scale output current of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and for
simplicity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise super imposed on the DAC’s
full-scale current, I
, one must determine the PSRR in dB
OUTFS
using Figure 33 at 250 kHz. To calculate the PSRR for a given
R
, such that the units of PSRR are converted from A/V to
LOAD
V/V, adjust the curve in Figure 33 by the scaling factor 20 × Log
). For instance, if R
(R
LOAD
is 50 Ω, the PSRR is reduced
LOAD
by 34 dB (i.e., PSRR of the DAC at 1 MHz which is 74 dB in
Figure 33 becomes 40 dB V
OUT/VIN
).
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9752 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close as physically as possible.
For those applications that require a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 34. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
100mF
ELECT.
10-22mF
TANT.
0.1mF
CER.
AVDD
ACOM
80
PSRR – dB
70
60
0.5 0.75
FREQUENCY – MHz
1.00.26
Figure 33. Power Supply Rejection Ratio of AD9752
Note that the units in Figure 33 are given in units of (amps out)/
(volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output
current. The voltage noise on the dc power, therefore, will be
added in a nonlinear manner to the desired I
. Due to the
OUT
relative different sizes of these switches, PSRR is very code dependent. This can produce a mixing effect which can modulate low
REV. 0
–15–
+5V OR +3V
POWER SUPPLY
Figure 34. Differential LC Filter for Single +5 V or +3 V
Applications
Maintaining low noise on power supplies and ground is critical
to obtaining optimum results from the AD9752. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.
All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8
to 1/4 inch wide underneath or within 1/2 inch of the DAC to
Page 16
AD9752
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some “free” capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, strip line techniques with proper termination resistor
should be considered. The necessity and value of this resistor
will be dependent upon the logic family used.
For a more detailed discussion of the implementation and
construction of high speed, mixed signal printed circuit boards,
refer to Analog Devices’ application notes AN-280 and
AN-333.
–30
–40
–50
–60
–70
AMPLITUDE – dBm
–80
–90
–100
600k
800k
FREQUENCY – Hz
1M
Figure 35a. Notch in Missing Bin at 750 kHz is Down
>60 dB. (Peak Amplitude + 0 dBm).
–30
–40
–50
–60
–70
–80
AMPLITUDE – dBm
–90
–100
–110
4.85
5
FREQUENCY – MHz
5.15
Figure 35b. Notch in Missing Bin at 5 MHz is Down
>60 dB. (Peak Amplitude + 0 dBm).
APPLICATIONS
VDSL Applications Using the AD9752
Very High Frequency Digital Subscriber Line (VDSL) technology is growing rapidly in applications requiring data transfer
over relatively short distances. By using QAM modulation and
transmitting the data in multiple discrete tones, high data rates
can be achieved.
As with other multitone applications, each VDSL tone is capable of transmitting a given number of bits, depending on the
signal-to-noise ratio (SNR) in a narrow band around that tone.
The tones are evenly spaced over the range of several kHz to
10 MHz. At the high frequency end of this range, performance
is generally limited by cable characteristics and environmental
factors, such as external interferers. Performance at the lower
frequencies is much more dependent on the performance of the
components in the signal chain. In addition to in-band noise,
intermodulation from other tones can also potentially interfere
with the recovery of data for a given tone. The two graphs in
Figure 35 represent a 500 tone missing bin test vector, with
frequencies evenly spaced from 400 Hz to 10 MHz. This test is
very commonly done to determine if distortion will limit the
number of bits which can be transmitted in a tone. The test
vector has a series of missing tones around 750 kHz, which is
represented in Figure 35a and a series of missing tones around
5 MHz which is represented in Figure 35b. In both cases, the
spurious free range between the transmitted tones and the empty
bins is greater than 60 dB.
Using the AD9752 for Quadrature Amplitude Modulation
(QAM)
QAM is one of the most widely used digital modulation
schemes in digital communication systems. This modulation
technique can be found in FDM as well as spreadspectrum (i.e.,
CDMA) based systems. A QAM signal is a carrier frequency
that is modulated in both amplitude (i.e., AM modulation) and
phase (i.e., PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a
90° phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90° phase
shift with respect to the I component. The I and Q components
are then summed to provide a QAM signal at the specified carrier frequency.
A common and traditional implementation of a QAM modulator is shown in Figure 36. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components, respectively. Each component is
then typically applied to a Nyquist filter before being applied to
a quadrature mixer. The matching Nyquist filters shape and
limit each component’s spectral envelope while minimizing
intersymbol interference. The DAC is typically updated at the
QAM symbol rate or possibly a multiple of it if an interpolating
filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog
filter, which can be a significant contributor to mismatches in
gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with in-phase
and quadrature phase carrier frequency and then sums the two
outputs to provide the QAM signal.
–16–
REV. 0
Page 17
AD9752
12
AD9752
DSP
OR
ASIC
12
AD9752
CARRIER
FREQUENCY
NYQUIST
FILTERS
0
S
90
QUADRATURE
MODULATOR
TO
MIXER
Figure 36. Typical Analog QAM Architecture
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 37 helps improve
upon the matching and temperature stability characteristics
between the I and Q channels, as well as showing a path for upconversion using the AD8346 quadrature modulator. Using a
single voltage reference derived from U1 to set the gain for both
the I and Q channels will improve the gain matching and stability. R
can be used to compensate for any mismatch in gain
CAL
between the two channels. This mismatch may be attributed to
the mismatch between R
SET1
and R
, effective load resistance
SET2
of each channel, and/or the voltage offset of the control amplifier in each DAC. The differential voltage outputs of U1 and U2
are fed into the respective differential inputs of the AD8346 via
matching networks.
Using the same matching techniques described above, Figure 38
shows an example of the AD9752 used in a W-CDMA transmitter application using the AD6122 CDMA 3 V transmitter IF
subsystem. The AD6122 has functions, such as external gain
control and low distortion characteristics, needed for the superior Adjacent Channel Power (ACP) requirements of W-CDMA.
CDMA
Carrier Division Multiple Access, or CDMA, is an air transmit/
receive scheme where the signal in the transmit path is modulated with a pseudorandom digital code (sometimes referred to
as the spreading code). The effect of this is to spread the transmitted signal across a wide spectrum. Similar to a DMT waveform, a CDMA waveform containing multiple subscribers can
be characterized as having a high peak to average ratio (i.e.,
crest factor), thus demanding highly linear components in the
transmit signal path. The bandwidth of the spectrum is defined
by the CDMA standard being used, and in operation is implemented by using a spreading code with particular characteristics.
Distortion in the transmit path can lead to power being transmitted out of the defined band. The ratio of power transmitted
in-band to out-of-band is often referred to as Adjacent Channel
Power (ACP). This is a regulatory issue due to the possibility of
interference with other signals being transmitted by air. Regulatory bodies define a spectral mask outside of the transmit band,
and the ACP must fall under this mask. If distortion in the
transmit path cause the ACP to be above the spectral mask,
then filtering, or different component selection is needed to
meet the mask requirements.
REFIO
FSADJ
R
SET1
2kV
I DATA
INPUT
CLK
Q DATA
INPUT
0.1mF
+5V
1.82V
500V
FILTER
500V
500mV p-p WITH
634V
500V
V
CM
500V500V
=1.2V
0.1mF
BBIP
BBIN
BBQP
BBQN
VPBF
PHASE
SPLITTER
AD8346
REFLO
AD9752
(“I DAC”)
LATCHES
LATCHES
AD9752
(“Q DAC”)
REFIO
R
SET2
1.9kV
DVDD
AVDD
FSADJ
U1
DAC
REFLO
U2
DAC
R
CAL
220V
ACOM
SLEEP
IOUTA
IOUTB
AVDD
QOUTA
QOUTB
DCOM
AVDD
100W
500V
500V
C
FILTER
500V
100V
100V
C
100V
NOTE: 500V RESISTOR NETWORK - OHMTEK ORN5000D
100V RESISTOR NETWORK - TOMC1603-100D
Figure 37. Baseband QAM Implementation Using Two AD9752s
+
VOUT
LOIP
LOIN
REV. 0
–17–
Page 18
AD9752
+3V
REFIO
FSADJ
R
SET1
2kV
I DATA
INPUT
CLK
Q DATA
INPUT
0.1mF
REFLO
AD9752
(“I DAC”)
LATCHES
LATCHES
AD9752
(“Q DAC”)
REFIO
500V
500V
CONTROL
634V
LOIPP
LOIPN
GAIN
TXOPP
TXOPN
500V
IIPP
IIPN
IIQP
IIQN
REFIN
VGAIN
42
SPLITTER
TEMPERATURE
COMPENSATION
GAIN
CONTROL
SCALE
FACTOR
R
SET2
1.9kV
DVDD
FSADJ
DAC
DAC
R
CAL
220V
ACOM
U1
REFLOAVDD
U2
SLEEP
IOUTA
IOUTB
AVDD
QOUTA
QOUTB
DCOM
AVDD
100W
100V
C
100V
500V
FILTER
500V
500V
500V
500V
100V
Figure 38. CDMA Transmit Application Using AD9752
AD6122
PHASE
V
CC
V
CC
Figure 39 shows the AD9752 reconstructing a wideband, or
W-CDMA test vector with a bandwidth of 5 MHz, centered at
15.625 MHz and being sampled at 62.5 MSPS. ACP for the given
test vector is measured at 70 dB.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
CENTER 16.384MHz SPAN 14.096MHz1.4096MHz
CO COCL1 CU1
Figure 39. CDMA Signal, Sampled at 65 MSPS, Adjacent
Channel Power >70 dBm
It is also possible to generate a QAM signal completely in the
digital domain via a DSP or ASIC, in which case only a single
DAC of sufficient resolution and performance is required to
reconstruct the QAM signal. Also available from several vendors
are Digital ASICs which implement other digital modulation
schemes such as PSK and FSK. This digital implementation has
the benefit of generating perfectly matched I and Q components
in terms of gain and phase, which is essential in maintaining
optimum performance in a communication system. In this implementation, the reconstruction DAC must be operating at a
sufficiently high clock rate to accommodate the highest specified
QAM carrier frequency. Figure 40 shows a block diagram of
such an implementation using the AD9752.
I DATA
Q DATA
CARRIER
FREQUENCY
12
12
12
STEL-1130
QAM
12
SIN
STEL-1177
NCO
12
50V
TO
MIXER
LPF
AD9752
12
COS
CLOCK
50V
Figure 40. Digital QAM Architecture
AD9752 EVALUATION BOARD
General Description
The AD9752-EB is an evaluation board for the AD9752 12-bit
D/A converter. Careful attention to layout and circuit design
combined with a prototyping area allow the user to easily and
effectively evaluate the AD9752 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9752
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators, with the
on-board option to add a resistor network for proper load
termination. Provisions are also made to operate the AD9752
with either the internal or external reference, or to exercise the
power-down feature.
Refer to the application note AN-420 for a thorough description
and operating instructions for the AD9752 evaluation board.
–18–
REV. 0
Page 19
AVCC
AVEE
AGND
AVDD
DGND
DVDD
AD9752
TP13
A
B
2
1
3
JP3
TP8
C9
0.1mF
A
AVDD
C8
0.1mF
C7
1mF
3
2
CLK
JP1
1
AB
R15
49.9V
TP1
J1
EXTCLK
A
DVDD
C6
10mF
TP7
B6
A
C5
10mF
TP6
B5
TP5
TP19
TP18
B4
B3
B2
B1
TP4
TP2
TP3
A
C4
10mF
DVDD
C3
10mF
R7
R3
R5
R1
U1
1
1
16 PINDIP
1
1
2827262524
DVDD
CLOCK
AD975x
DB13
DB12
123456789
10
98765432
10
98765432
16151413121110
RES PK
1234567
C19C1C2
10
98765432
10
98765432
13579
P1
246
OUT 2
OUT 1
TP10 TP9
TP11
AVDD
ACOM
REFIO
FS ADJ
COMP1
DB5
DB4
DB3
DB2
1011121314
16 PINDIP
15
16
SLEEP
REFLO
DB1
DB0
RES PK
25
2729313335
1615141312
12345
C30
23222120191817
NC
AVDD
DCOM
IOUTA
IOUTB
COMP2
DB11
DB10
DB9
DB8
DB7
DB6
9
8
C25
C26
C27
C28
C29
11131517192123
8
101214161820222426283032343638
C10
0.1mF
AVDD
TP14
R16
2kV
JP4
C11
0.1mF
1
2
3JP2
AVDD
A
A
CT1
C31
C32
C33
C34
37
A A A
J2
PDIN
R17
49.9V
TP12
1
DVDD
R8
1098765432
1
R4
1098765432
11
10
6
7
C35
C36
39
40
1098765432
98765432
10
1
DVDD
R6
1
R2
AVCC
R18
C17
0.1mF
AVCC
U6
R42
1kV
6
VOUT
U7
GND
REF43
VIN
2
C16
AVCC
C18
J6
C22
1mF
A
C21
0.1mF
6
7
U4
3
1kV
JP8
A
JP7A
JP7B
R12
JP6A
J7
C12
OUT1
J3
A
7
3
R43
4
1mF
0.1mF
R37
AD8047
2
B
B
B
OPEN
T1
4
22pF
R20
49.9V
6
AD8047
CW
5kV
A
A
A
49.9V
4
R10
A
0
C20
3
2
1kV
A A
AVEE
4
A
A
A
A
5
R14
JP5
R45
C14
J5
EXTREFIN
R36
1kV
JP6B
1
A
0
123
C15
0.1mF
A
A
R46
1kV
1kV
1mF
R44
50V
A
A
C24
1mF
A
C23
0.1mF
AVEE
R35
1kV
A
B
A
JP9
R9
1kV
R13
OPEN
A
A
6
C13
22pF
OUT2
R38
49.9V
J4
A A
REV. 0
Figure 41. Evaluation Board Schematic
–19–
Page 20
AD9752
Figure 42. Silkscreen Layer—Top
Figure 43. Component Side PCB Layout (Layer 1)
–20–
REV. 0
Page 21
AD9752
Figure 44. Ground Plane PCB Layout (Layer 2)
REV. 0
Figure 45. Power Plane PCB Layout (Layer 3)
–21–
Page 22
AD9752
Figure 46. Solder Side PCB Layout (Layer 4)
Figure 47. Silkscreen Layer—Bottom
–22–
REV. 0
Page 23
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead, 300 Mil SOIC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
AD9752
0.0118 (0.30)
0.0040 (0.10)
0.177 (4.50)
0.169 (4.30)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
28
1
PIN 1
28
1
PIN 1
0.0500
(1.27)
BSC
0.386 (9.80)
0.378 (9.60)
0.0256 (0.65)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
28-Lead TSSOP
(RU-28)
15
14
0.0118 (0.30)
0.0075 (0.19)
15
0.2992 (7.60)
0.2914 (7.40)
14
0.1043 (2.65)
0.0926 (2.35)
0.0125 (0.32)
0.0091 (0.23)
0.256 (6.50)
0.246 (6.25)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.4193 (10.65)
0.3937 (10.00)
0.0291 (0.74)
0.0098 (0.25)
0.0500 (1.27)
88
0.0157 (0.40)
08
88
08
C3332–8–1/99
3 458
0.028 (0.70)
0.020 (0.50)
REV. 0
PRINTED IN U.S.A.
–23–
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