Datasheet AD9748 Datasheet (ANALOG DEVICES)

8-Bit, 210 MSPS TxDAC® D/A Converter

FEATURES

High performance member of pin-compatible

TxDAC product family

Linearity

0.1 LSB DNL

0.1 LSB INL
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.20 V reference
CMOS-compatible digital interface
32-lead LFCSP
Edge-triggered latches
Fast settling: 11 ns to 0.1% full-scale

GENERAL DESCRIPTION

The AD97481 is an 8-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path of
communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based on
performance, resolution, and cost. The AD9748 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.

The AD9748’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.

AD9748

APPLICATIONS

Communications
Direct digital synthesis (DSS)
Instrumentation

FUNCTIONAL BLOCK DIAGRAM

3.3V

150pF

SEGMENTED

SWITCHES

Figure 1.

LATCHES

R

SET

CLK+

CLK–

0.1μF
REFIO

FS ADJ

DVDD

3.3V

DCOM

3.3V CLKVDD
CLKCOM

SLEEP

1.2V REF

DIGITAL DATA INPUTS (DB7–DB0)

Edge-triggered input latches and a 1.2 V temperature­compensated band gap reference have been integrated to
provide a complete monolithic DAC solution. The digital inputs
support 3 V CMOS logic families.

PRODUCT HIGHLIGHTS

1. 32-lead LFCSP.

2. The AD9748 is the 8-bit member of the pin-compatible

TxDAC family, which offers excellent INL and DNL
performance.

3. Differential or single-ended clock input (LVPECL or

CMOS), supports 210 MSPS conversion rate.

4. Data input supports twos complement or straight binary

data coding.

5. Low power: Complete CMOS DAC function operates on

135 mW from a 2.7 V to 3.6 V single supply. The DAC full­scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.

6. On-chip voltage reference: The AD9748 includes a 1.2 V

temperature-compensated band gap voltage reference.

1

Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.

AVDD ACOM

CURRENT

SOURCE

ARRAY

LSB

SWITCHES

AD9748

IOUTA

IOUTB

MODE
CMODE

03211-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD9748

TABLE OF CONTENTS

Features .............................................................................................. 1

Applying the AD9748 ................................................................ 15

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

Dynamic Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Te r mi n ol o g y ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

Functional Description ..................................................................11

Reference Operation ..................................................................11

Reference Control Amplifier .................................................... 11

DAC Transfer Function ............................................................. 12

Analog Outputs........................................................................... 12

Digital Inputs ..............................................................................13

Clock Input.................................................................................. 13

DAC Timing................................................................................ 14

Power Dissipation....................................................................... 14

Differential Coupling Using a Transformer............................... 15

Differential Coupling Using an Op Amp................................ 16

Single-Ended, Unbuffered Voltage Output............................. 16

Single-Ended, Buffered Voltage Output Configuration........ 16

Power and Grounding Considerations, Power Supply

Rejection...................................................................................... 17

Evaluation Board ............................................................................ 18

General Description................................................................... 18

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

12/05—Rev. 0 to Rev. A

Updated Format.................................................................. Universal

Changes to General Description and Product Highlights...........1

Changes to Table 1.............................................................................3

Changes to Table 2.............................................................................4

Changes to Table 4.............................................................................6

Inserted Figure 7; Renumbered Sequentially.................................9

Changes to Figure 8 and Figure 9....................................................9

Changes to Functional Description, Reference Operation, and

Reference Control Amplifier Sections......................................... 11

Inserted Figure 16; Renumbered Sequentially ........................... 11

Changes to DAC Transfer Function Section............................... 12

Changes to Digital Inputs Section................................................ 13

Changes to Figure 22, Figure 23, and Figure 24......................... 14

Changes to Figure 25...................................................................... 15

Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 16

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

2/03—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD9748

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 8 Bits
DC ACCURACY1

Integral Linearity Error (INL) ±0.25 ±0.1 +0.25 LSB
Differential Nonlinearity (DNL) ±0.25 ±0.1 +0.25 LSB

ANALOG OUTPUT

Offset Error −0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Full-Scale Output Current2 2.0 20.0 mA
Output Compliance Range −1.0 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 7 kΩ
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation5 145 mW
Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V
Power Supply Rejection Ratio—DVDD

OPERATING RANGE −40 +85 °C

1

Measured at IOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4

Measured at f

5

Measured as unbuffered voltage output with I

6

±5% power supply variation.

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V

) 33 36 mA

AVDD

)4 8 9 mA

DVDD

) 5 7 mA

CLKVDD

) 5 6 mA

4

= 100 MSPS and f

CLOCK

AVDD

, is 32 times the I

OUTFS

OUT

= 1 MHz.

6

current.

REF

= 20 mA, 50 Ω R

OUTFS

at IOUTA and IOUTB, f

LOAD

135 145 mW

−0.04 +0.04 % of FSR/V

= 100 MSPS, and f

CLOCK

= 40 MHz.

OUT

Rev. A | Page 3 of 24

AD9748

DYNAMIC SPECIFICATIONS

T

to T

MIN

terminated, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f

Output Settling Time (tST) (to 0.1%)1 11 ns

Output Propagation Delay (tPD) 1 ns

Glitch Impulse 5 pV-s

Output Rise Time (10% to 90%)

Output Fall Time (10% to 90%)

Output Noise (I

Output Noise (I
AC LINEARITY

Signal-to-Noise and Distortion Ratio

Total Harmonic Distortion

Spurious-Free Dynamic Range to Nyquist

1

Measured single-ended into 50 Ω load.

2

Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

= 20 mA, differential transformer coupled output, 50 Ω doubly

OUTFS

) 210 MSPS

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 165 MSPS; f

CLOCK

f

= 165 MSPS; f

CLOCK

f

= 210 MSPS; f

CLOCK

f

= 210 MSPS; f

CLOCK

f

= 25 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 165 MSPS; f

CLOCK

f

= 210 MSPS; f

CLOCK

f

= 25 MSPS; f

CLOCK

1

1

= 20 mA)2 50 pA/√Hz

OUTFS

OUTFS

= 2 mA)

2

= 5 MHz 50 dB

OUT

= 19 MHz 48 dB

OUT

= 5 MHz 50 dB

OUT

= 39 MHz 46 dB

OUT

= 5 MHz 50 dB

OUT

= 49 MHz 47 dB

OUT

= 9 MHz 50 dB

OUT

= 68 MHz 46 dB

OUT

= 1 MHz −72 −61 dBc

OUT

= 12.5 MHz −65 dBc

OUT

= 25 MHz −60 dBc

OUT

= 41.3 MHz −58 dBc

OUT

= 68 MHz −65 dBc

OUT

= 1 MHz

OUT

2.5 ns

2.5 ns

30 pA/√Hz

0 dBFS Output 61 72 dBc

f

= 65 MSPS; f

CLOCK

f

= 65 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 165 MSPS; f

CLOCK

f

= 165 MSPS; f

CLOCK

f

= 210 MSPS; f

CLOCK

f

= 210 MSPS; f

CLOCK

= 5 MHz 69 dBc

OUT

= 19 MHz 65 dBc

OUT

= 5 MHz 68 dBc

OUT

= 39 MHz 62 dBc

OUT

= 5 MHz 68 dBc

OUT

= 49 MHz 54 dBc

OUT

= 5 MHz 67 dBc

OUT

= 68 MHz 60 dBc

OUT

Rev. A | Page 4 of 24

AD9748

DIGITAL SPECIFICATIONS

T

to T

MIN

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 μA
Logic 0 Current −10 +10 μA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (t

CLK INPUTS1

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

1

Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

) 1.5 ns

LPW

= 20 mA, unless otherwise noted.

OUTFS

DB0–DB7

CLOCK

IOUTA

OR

IOUTB

t

S

t

PD

0.1%

t

H

t

LPW

t

ST

0.1%

03211-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

AD9748

ABSOLUTE MAXIMUM RATINGS

Table 4.

With
Respect

Parameter

AVDD ACOM −0.3 +3.9 V
DVDD DCOM −0.3 +3.9 V
CLKVDD CLKCOM −0.3 +3.9 V
ACOM DCOM −0.3 +0.3 V
ACOM CLKCOM −0.3 +0.3 V
DCOM CLKCOM −0.3 +0.3 V
AVDD DVDD −3.9 +3.9 V
AVDD CLKVDD −3.9 +3.9 V
DVDD CLKVDD −3.9 +3.9 V
CLK+, CLK−, SLEEP DCOM −0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V
REFIO, FS ADJ ACOM −0.3 AVDD + 0.3 V
CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature

Range
Lead Temperature

(10 sec)

to

−65 +150 °C

300 °C

Min Max Unit

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may effect
device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance

32-Lead LFCSP

= 32.5°C/W

θ

JA

1

Thermal impedance measurements were taken on a 4-layer board in still air,

in accordance with EIA/JESD51-7.

1

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 24

AD9748

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

B6
D

DB2

DB3

31

32

DB7 (MSB)

DB4

DB5

DCOM

SLEEP

29

28

27

26

30

25

1DB1

PIN 1

2(LSB) DB0

INDICATOR

3DVDD
4NC
5NC
6NC
7NC
8NC

AD9748

TOP VIEW

(Not to Scale)

9

10

M

NC

DCO

NC = NO CONNECT

11

12

13

14

CLK–

CLK+

CLKVDD

CLKCOM

15

CMODE

16

MODE

24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD

03211-003

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

27 DB7 (MSB) Most Significant Data Bit (MSB).
28 to 32, 1 DB6 to DB1 Data Bits 6 to 1.
2 DB0 (LSB) Least Significant Data Bit (LSB).
3 DVDD Digital Supply Voltage (3.3 V).
4 to 9 NC No Internal Connection.
10, 26 DCOM Digital Common.
11 CLKVDD Clock Supply Voltage (3.3 V).
12 CLK+ Differential Clock Input.
13 CLK− Differential Clock Input.
14 CLKCOM Clock Common.
15 CMODE

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float

CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).
16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
17, 18 AVDD Analog Supply Voltage (3.3 V).
19, 22 ACOM Analog Common.
20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 REFIO Reference Input/Output. Requires 0.1 μF capacitor to ACOM.
24 FS ADJ Full-Scale Current Output Adjust.
25 SLEEP

Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated

if not used.

Rev. A | Page 7 of 24

AD9748

TERMINOLOGY

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output increases or remains constant
as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Tem p er at u re Dr i ft

Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T

MIN

or T

. For offset

MAX

and gain drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.

3.3V

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.

Total Harmonic Distortion (THD)

T

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.

*AWG2021 CLOCK
RETIMED SO THAT
THE DIGITAL DATA
TRANSITIONS ON
FALLING EDGE OF
50% DUTY CYCLE
CLOCK.

DVDD

DCOM

RETIMED

CLOCK

OUTPUT*

R

SET

50Ω

LECROY 9210

PULSE GENERATOR

0.1μF

3.3V

CLK+

CLK–

3.3V

1.2V REF

REFIO
FS ADJ

DVDD

DCOM

CLKVDD
CLKCOM

SLEEP

CLOCK

OUTPUT

150pF

SEGMENTED

SWITCHES

LATCHES

DIGITAL DATA INPUTS (DB7–DB0)

DIGITAL

DATA

TEKTRONIX AWG-2021

WITH OPTION 4

AVDD ACOM

CURRENT

SOURCE

ARRAY

LSB

SWITCHES

AD9748

IOUTA

IOUTB

MODE

CMODE

50Ω

Figure 4. Basic AC Characterization Test Setup (SOIC/TSSOP Packages)

Rev. A | Page 8 of 24

20pF

50Ω

100Ω

20pF

MINI-CIRCUITS

T1-1T

ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER

03211-004

AD9748

TYPICAL PERFORMANCE CHARACTERISTICS

55

50

10mA

40

SINAD (dB)

45

35

30

1 10 100

Figure 5. SINAD vs. I

5mA

2.5mA

f

OUT

@ 100 MSPS (Single-Ended Output)

OUTFS

20mA

(MHz)

55

50

10mA

20mA

03211-005

80

75

70

65

60

55

SINAD/THD (dB)

50

45

40

1 10 100

SINAD@50MSPS

SINAD@100MSPS

Figure 8. SINAD/THD vs. f

SINAD@165MSPS

SINAD@210MSPS

f

(MHz)

OUT

(Single-Ended Output)

OUT

THD@50MSPS

THD@100MSPS

THD@165MSPS

THD@210MSPS

80

75

70

THD@165MSPS

THD@210MSPS

03211-039

5mA

40

SINAD (dB)

45

35

30

1 10 100

Figure 6. SINAD vs. I

f

(MHz)

OUT

@ 165 MSPS (Single-Ended Output)

OUTFS

2.5mA

55

20mA

50

40

SINAD (dB)

45

35

30

1 10 100

Figure 7. SINAD vs. I

2.5mA

f

(MHz)

OUT

@ 210 MSPS (Single-Ended Output)

OUTFS

5mA

10mA

03211-006

03211-038

65

60

55

SINAD/THD (dB)

50

45

40

1 10 100

Figure 9. SINAD/THD vs. f

THD@50MSPS

SINAD@50MSPS

SINAD@100MSPS

THD@100MSPS

SINAD@165MSPS

SINAD@210MSPS

f

(MHz)

OUT

(Differential Output)

OUT

0

f

= 25MSPS

CLOCK

–10

f

= 7.81MHz

OUT

SFDR = 65.0dBc

–20

AMPLITUDE = 0dBFS

–30

–40

–50

–60

MAGNITUDE (dBm)

–70

–80

–90

–100

02 4 6 81012

FREQUENCY (MHz)

Figure 10. Single-Tone Spectral Plot @ 25 MSPS (Single-Ended Output)

03211-040

03211-009

Rev. A | Page 9 of 24

AD9748

0

–10

–20

–30

–40

–50

–60

MAGNITUDE (dBm)

–70

–80

–90

–100

0 102030405060

FREQUENCY (MHz)

Figure 11. Single-Tone Spectral Plot @ 125 MSPS (Single-Ended Output)

0

f

= 165MSPS

CLOCK

–10

f

= 49MHz

OUT

SFDR = 50.1dBc

–20

AMPLITUDE = 0dBFS

–30

–40

–50

–60

MAGNITUDE (dBm)

–70

–80

–90

–100

010203040 706050 80

FREQUENCY (MHz)

Figure 12. Single-Tone Spectral Plot @ 165 MSPS (Single-Ended Output)

f

= 125MSPS

CLOCK

f

= 27MHz

OUT

SFDR = 56.2dBc
AMPLITUDE = 0dBFS

50mV/DIV

03211-010

5ns/DIV

03211-012

Figure 13. Step Response (Single-Ended Output)

0

f

= 210MSPS

CLOCK

–10

f

= 68MHz

OUT

SFDR = 50dBc

–20

AMPLIT UDE = 0dBFS

–30

–40

–50

–60

MAGNITUDE (dBm)

–70

–80

–90

–100

0 10.5 105

03211-011

FREQUENCY (MHz)

03211-043

Figure 14. Single-Tone Spectral Plot @ 210 MSPS (Single-Ended Output)

R

SET

CLK+
CLK–

0.1μF

3.3V

3.3V

1.2V REF

REFIO
FS ADJ

DVDD

DCOM

CLKVDD
CLKCOM

SLEEP

3.3V

150pF

AVDD ACOM

CURRENT

SOURCE

ARRAY

SEGMENTED

SWITCHES

LSB

SWITCHES

LATCHES

DIGITAL DATA INPUTS (DB7–DB0)

Figure 15. Simplified Block Diagram

Rev. A | Page 10 of 24

AD9748

V

IOUTA

IOUTB

MODE
CMODE

DIFF

= V

OUTA

R

LOAD

50Ω

= V

OUTB

R
50Ω

LOAD

03211-013

AD9748

A

V

FUNCTIONAL DESCRIPTION

Figure 15 shows a simplified block diagram of the AD9748. The
AD9748 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I

). The array is divided into 31 equal currents that

OUTFS

make up the five most significant bits (MSBs). The next three
bits consist of seven equal current sources whose value is ⅛ of
an MSB current source. Implementing the lower bits with
current sources, instead of an R-2R ladder, enhances its
dynamic performance for multitone or low amplitude signals
and helps maintain the DAC’s high output impedance (that is,
>100 kΩ).

All of these current sources are switched to one or the other of
the two output nodes (that is, IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.

The analog and digital sections of the AD9748 have separate
power supply inputs (that is, AVDD and DVDD) that can
operate independently over a 2.7 V to 3.6 V range. The digital
section, which is capable of operating at a rate of up to 210 MSPS,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.2 V band gap voltage
reference, and a reference control amplifier.

current of less than 100 nA should be used. An example of the
use of the internal reference is shown in

AVDD

84µA

7k

REFLO

Figure 16. Equivalent Circuit of Internal Reference

OPTIONAL

EXTERNAL

REF BUFFER

1.2V REF

2kΩ

REFIO

FS ADJ

AD9748

DDITIONAL

LOAD

0.1μF

Figure 17. Internal Reference Configuration

REFLO

Figure 17.

REFIO

03211-044

150pF

3.3V

AVDD

CURRENT

SOURCE

ARRAY

An external reference can be applied to REFIO, as shown in
Figure 18. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 μF
compensation capacitor is not required because the internal
reference is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.

3.3

03211-045

The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R

, connected to the full-scale adjust (FS ADJ)

SET

pin. The external resistor, in combination with both the reference
control amplifier and voltage reference, V
current, I

, which is replicated to the segmented current

REF

, sets the reference

REFIO

sources with the proper scaling factor. The full-scale current,
I

, is 32 times I

OUTFS

REF

.

REFERENCE OPERATION

The AD9748 contains an internal 1.2 V band gap reference. The
internal reference cannot be disabled but can be easily overridden
by an external reference with no effect on performance.
shows an equivalent circuit of the band gap reference. REFIO
serves as either an output or an input depending on whether the
internal or an external reference is used. To use the internal
reference, simply decouple the REFIO pin to ACOM with a

0.1 μF capacitor and connect REFLO to ACOM via a resistance
less than 5 Ω. The internal reference voltage are present at
REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, than an external buffer amplifier with an input bias

Figure 16

Rev. A | Page 11 of 24

REFLO

1.2V REF

REFIO

FS ADJ

AD9748

Figure 18. External Reference Configuration

150pF

REFERENCE CONTROL AMPLIFI ER

AVD D

CURRENT

SOURCE

ARRAY

03211-046

REFERENCE CONTROL AMPLIFIER

The AD9748 contains a control amplifier that is used to regulate
the full-scale output current, I
configured as a V-I converter, as shown in
current output, I
an external resistor, R

, is determined by the ratio of the V

REF

, as stated in Equation 4. I

SET

to the segmented current sources with the proper scale factor to
set I

, as stated in Equation 3.

OUTFS

. The control amplifier is

OUTFS

Figure 17, so that its

REFIO

is copied

REF

and

AD9748

The control amplifier allows a wide (10:1) adjustment span of

over a 2 mA to 20 mA range by setting I

I

OUTFS

μA and 625 μA. The wide adjustment span of I

between 62.5

REF

provides

OUTFS

several benefits. The first relates directly to the power
dissipation of the AD9748, which is proportional to I
the

Power Dissipation section). The second relates to a 20 dB

OUTFS

(see

adjustment, which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.

DAC TRANSFER FUNCTION

The AD9748 provides complementary current outputs, IOUTA
and IOUTB. IOUTA provides a near full-scale current output,
I

, when all bits are high (that is, DAC CODE = 255), while

OUTFS

IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and I

IOUTA = (DAC CODE/256) × I

IOUTB = (255 − DAC CODE)/256 × I

where DAC CODE = 0 to 255 (that is, decimal representation).

As mentioned previously, I
current I
V

REFIO

, which is nominally set by a reference voltage,

REF

, and external resistor, R

I

OUTFS

= 32 × I

(3)

REF

where

I

REF

= V

REFIO/RSET

(4)

The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, then IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
that R

, that are tied to analog common, ACOM. Note

LOAD

can represent the equivalent load resistance seen by

LOAD

IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply

= IOUTA × R

V

OUTA

V

= IOUTB × R

OUTB

Note that the full-scale value of V
exceed the specified output compliance range to maintain
specified distortion and linearity performance.

= (IOUTA − IOUTB) × R

V

DIFF

and can be expressed as:

OUTFS

(1)

OUTFS

(2)

OUTFS

is a function of the reference

OUTFS

. It can be expressed as:

SET

(5)

LOAD

(6)

LOAD

and V

OUTA

(7)

LOAD

should not

OUTB

Substituting the values of IOUTA, IOUTB, I
expressed as:

= {(2 × DAC CODE − 255)/256}

V

DIFF

(32 × R

LOAD/RSET

) × V

(8)

REFIO

Equation 7 and Equation 8 highlight some of the advantages of
operating the AD9748 differentially. First, the differential
operation helps cancel common-mode error sources associated
with IOUTA and IOUTB, such as noise, distortion, and dc
offsets. Second, the differential code dependent current and
subsequent voltage, V
voltage output (that is, V

, is twice the value of the single-ended

DIFF

OUTA

or V

), thus providing twice the

OUTB

signal power to the load.

Note that the gain drift temperature performance for a single­ended (V

OUTA

and V

OUTB

) or differential output (VB
AD9748 can be enhanced by selecting temperature tracking
resistors for R

LOAD

and R

due to their ratiometric relationship,

SET

as shown in Equation 8.

ANALOG OUTPUTS

The complementary current outputs in each DAC, IOUTA,
and IOUTB can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, V
via a load resistor, R
Function

section by Equation 5 through Equation 8. The
differential voltage, V
also be converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance
of the AD9748 is optimum and specified using a differential
transformer-coupled output in which the voltage swing at
IOUTA and IOUTB is limited to ±0.5 V.

The distortion and noise performance of the AD9748 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases and/or its amplitude decreases. This is due
to the first-order cancellation of various dynamic common­mode distortion mechanisms, digital feedthrough, and noise.

Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when
processed differentially. A properly selected transformer allows
the AD9748 to provide the required power and voltage levels to
different loads.

, as described in the DAC Transfer

LOAD

, existing between V

DIFF

, and V

REF

OUTA

DIFF

OUTA

and V

DIFF

) of the

and V

OUTB

can be

OUTB

, can

,

Rev. A | Page 12 of 24

AD9748

The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, V

OUTA

and V

) due to the nature of a PMOS

OUTB

device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD9748 are measured with IOUTA maintained at a virtual
ground via an op amp.

IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit can result in a breakdown
of the output stage and affect the reliability of the AD9748.

The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.2 V for an I

OUTFS

. It degrades slightly from its

OUTFS

= 20 mA to 1 V for an I

OUTFS

= 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.

DIGITAL INPUTS

The AD9748 digital section consists of eight input bit channels
and a clock input. The 8-bit parallel data inputs follow standard
positive binary coding, where DB7 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.

DVDD

CLOCK INPUT

A configurable clock input allows for one single-ended and two
differential modes. The mode selection is controlled by the
CMODE input, as summarized in
to CLKCOM selects the single-ended clock input. In this mode,
the CLK+ input is driven with rail-to-rail swings and the CLK−
input is left floating. If CMODE is connected to CLKVDD, then
the differential receiver mode is selected. In this mode, both
inputs are high impedance. The final mode is selected by
floating CMODE. This mode is also differential, but internal
terminations for positive emitter-coupled logic (PECL) are
activated. There is no significant performance difference
between any of the three clock input modes.

Table 6. Clock Mode Selection

CMODE Pin Clock Input Mode

CLKCOM Single-ended
CLKVDD Differential
Float PECL

In the single-ended input mode, the CLK+ pin must be driven
with rail-to-rail CMOS levels. The quality of the DAC output is
directly related to the clock quality, and jitter is a key concern.
Any noise or jitter in the clock translates directly into the DAC
output. Optimal performance is achieved if the clock input has
a sharp rising edge, because the DAC latches are positive edge
triggered.

In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave,
because the high gain bandwidth of the differential inputs
convert the sine wave into a single-ended square wave
internally.

Tabl e 6. Connecting CMODE

DIGITAL

INPUT

03211-016

Figure 19. Equivalent Digital Input

The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these
transition edges can affect digital feedthrough and distortion
performance. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.

Rev. A | Page 13 of 24

The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 20. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.

CLK+

CLK–

50Ω 50Ω

V

= 1.3V NOM

TT

Figure 20. Clock Termination in PECL Mode

AD9748

CLOCK
RECEIVER

TO DAC CORE

03211-017

AD9748

DAC TIMING

Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9748 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9748 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases.

Figure 21 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.

80

75

70

65

60

55

SFDR (dB)

50

45

40

35

30

02 64 8 10 12

CLOCK PLACEMENT (ns)

Figure 21. SFDR vs. Clock Placement @ f

= 165 MSPS)

(f

CLOCK

20MHz SFDR

50MHz SFDR

= 20 MHz and 50 MHz

OUT

03211-018

Sleep Mode Operation

The AD9748 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9748 remains enabled if this
input is left disconnected. The AD9748 takes less than 50 ns to
power down and approximately 5 μs to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9748 is dependent on
several factors that include the:

• Power supply voltages (AVDD, CLKVDD, and DVDD)

• Full-scale current output (I

• Update rate (f

CLOCK

)

• Reconstructed digital input waveform

The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f

, and the digital supply current, I

AVD D

OUTFS

.

CLOCK

)

OUTFS

. I

DVDD

AVD D

, as shown in Figure 22, and is

Conversely, I
waveform, f
as a function of full-scale sine wave output ratios (f
for various update rates with DVDD = 3.3 V.

35

30

25

(mA)

20

AVDD

I

15

10

0

2

20

18

16

14

12

(mA)

10

DVDD

I

8

6

4

2

0

0.01 10.1

11

10

9

8

7

6

(mA)

5

CLKVDD

I

4

3

2

1

0

0 15010050 200 250

is dependent on both the digital input

DVDD

, and digital supply DVDD. Figure 23 shows I

CLOCK

OUT/fCLOCK

4 6 8 101214161820

Figure 23. I

Figure 24. I

I

(mA)

OUTFS

Figure 22. I

RATIO (f

DVDD

CLKVDD

vs. I

AVDD

210MSPS

165MSPS

125MSPS

65MSPS

OUT/fCLOCK

vs. Ratio @ DVDD = 3.3 V

DIFF

PECL

SE

f

(MSPS)

CLOCK

vs. f

and Clock Mode

CLOCK

OUTFS

)

DVDD

)

03211-019

03211-041

03211-042

Rev. A | Page 14 of 24

AD9748

APPLYING THE AD9748

Output Configurations

The following sections illustrate some typical output
configurations for the AD9748. Unless otherwise noted, it is
assumed that I
requiring the optimum dynamic performance, a differential
output configuration is suggested. A differential output
configuration can consist of either an RF transformer or a
differential op amp configuration. The transformer configuration
provides the optimum high frequency performance and is
recommended for any application that allows ac coupling. The
differential op amp configuration is suitable for applications
requiring dc coupling, bipolar output, signal gain, and/or
level shifting within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, R
can be more suitable for a single-supply system requiring a dc­coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus
converting IOUTA or IOUTB into a negative unipolar voltage.
This configuration provides the best dc linearity because
IOUTA or IOUTB is maintained at a virtual ground.

is set to a nominal 20 mA. For applications

OUTFS

, referred to ACOM. This configuration

LOAD

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to­single-ended signal conversion, as shown in
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral
content lies within the transformer’s pass band. An RF transformer,
such as the Mini-Circuits® T1–1T, provides excellent rejection of
common-mode distortion (that is, even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios can also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.

MINI-CIRCUI TS

IOUTA

AD9748

IOUTB

Figure 25. Differential Output Using a Transformer

T1-1T

OPTIONAL R

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (that is, V
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9748. A
differential resistor, R

, can be inserted in applications where

DIFF

the output of the transformer is connected to the load, R
via a passive reconstruction filter or cable. R
by the transformer’s impedance ratio and provides the proper
source termination that results in a low VSWR. Note that
approximately half the signal power is dissipated across R

Figure 25. A

DIFF

OUTA

DIFF

R

LOAD

03211-022

and V

OUTB

)

B

LOAD

,

is determined

.

DIFF

Rev. A | Page 15 of 24

AD9748

Ω

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-single­ended conversion, as shown in
configured with two equal load resistors, R
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.

AD9748

IOUTA

IOUTB

Figure 26. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate off a dual
supply because its output is approximately ±1 V. A high speed
amplifier capable of preserving the differential performance
of the AD9748 while meeting other system level objectives (that
is, cost or power) should be selected. The op amp’s differential
gain, gain setting resistor values, and full-scale output swing
capabilities should all be considered when optimizing this circuit.

The differential circuit shown in
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9748 and the op amp, is also used to level shift the
differential output of the AD9748 to midsupply (that is,
AVDD/2). The AD8041 is a suitable op amp for this application.

AD9748

IOUTA

IOUTB

C

OPT

Figure 27. Single-Supply DC Differential Coupled Circuit

Figure 26. The AD9748 is

LOAD

225Ω

225Ω

C

OPT

25Ω25Ω

500Ω

Figure 27 provides the

225Ω

225Ω

1kΩ25Ω25Ω

, of 25 Ω. The

500Ω

AD8047

500

AD8041

1kΩ

AVD D

03211-023

03211-024

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

Figure 28 shows the AD9748 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly
terminated 50 Ω cable because the nominal full-scale current,
I

, of 20 mA flows through the equivalent R

OUTFS

In this case, R

represents the equivalent load resistance seen

LOAD

of 25 Ω.

LOAD

by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
Different values of I

OUTFS

and R

can be selected as long as

LOAD

LOAD

.

the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL),
discussed in the

Analog Outputs section. For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.

I

= 20mA

AD9748

IOUTA

IOUTB

OUTFS

50Ω

25Ω

V

OUTA

=0VTO0.5V

50Ω

Figure 28. 0 V to 0.5 V Unbuffered Voltage Output

03211-025

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION

Figure 29 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9748 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the
Analog Outputs section. Although this single-ended
configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates can be limited by U1’s slew rate capabilities. U1
provides a negative unipolar output voltage, and its full-scale
output voltage is simply the product of R
scale output should be set within U1’s voltage output swing
capabilities by scaling I

and/or RFB. An improvement in ac

OUTFS

distortion performance can result with a reduced I
U1 is required to sink less signal current.

I

=10mA

AD9748

IOUTA

IOUTB

OUTFS

200Ω

Figure 29. Unipolar Buffered Voltage Output

C

R

200Ω

U1

OPT

FB

FB

and I

OUTFS

V

OUT

OUTFS

. The full-

because

= I

× R

OUTFS

FB

03211-026

Rev. A | Page 16 of 24

AD9748

POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION

Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF techniques
must be used for device selection, placement, and routing as
well as power supply bypassing and grounding to ensure
optimum performance.
recommended printed circuit board ground, power, and signal
plane layouts implemented on the AD9748 evaluation board.

One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, I
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9748 AVDD supply over this frequency range is shown in
Figure 30.

85

80

75

70

65

60

PSRR (dB)

55

50

45

40

24

Figure 30. Power Supply Rejection Ratio (PSRR)

Figure 35 to Figure 38 illustrate the

. AC noise on the dc supplies

OUTFS

FREQUENCY (MHz)

1268100

03211-027

Note that the ratio in Figure 30 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, is added in a nonlinear
manner to the desired IOUT. Due to the relative different size of
these switches, the PSRR is very code dependent. This can produce
a mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs occurs when the full-scale current
is directed toward that output. As a result, the PSRR measurement
in

Figure 30 represents a worst-case condition in which the
digital inputs remain static and the full-scale output current of
20 mA is directed to the DAC output being measured.

The following illustrates the effect of supply noise on the analog
supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake (ignoring harmonics), all of this noise is concentrated at
250 kHz. To calculate how much of this undesired noise appears as
current noise superimposed on the DAC’s full-scale current,
I

, users must determine the PSRR in dB using Figure 30 at

OUTFS

250 kHz. To calculate the PSRR for a given R

, such that the

LOAD

units of PSRR are converted from A/V to V/V, adjust the curve
in

Figure 30 by the scaling factor 20 Ω log (R
if R

is 50 Ω, then the PSRR is reduced by 34 dB (that is,

LOAD

PSRR of the DAC at 250 kHz, which is 85 dB in
becomes 51 dB V

OUT/VIN

).

). For instance,

LOAD

Figure 30,

Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9748 features separate analog and digital supplies and
ground pins to optimize the management of analog and digital
ground currents in a system. In general, AVDD, the analog
supply, should be decoupled to ACOM, the analog common,
as close to the chip as physically possible. Similarly, DVDD, the
digital supply, should be decoupled to DCOM as close to the
chip as physically possible.

For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply can be
generated using the circuit shown in

Figure 31. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.

FERRITE

TTL/CMOS

LOGIC

CIRCUITS

BEADS

100μF
ELECT.

10μF–22μF
TANT.

0.1μF
CER.

AVDD

ACOM

3.3V

POWER SUPPLY

Figure 31. Differential LC Filter for Single 3.3 V Applications

Rev. A | Page 17 of 24

03211-028

AD9748

EVALUATION BOARD

GENERAL DESCRIPTION

The AD9748 evaluation boards allow for easy setup and testing
of the product in the LFCSP package. Careful attention to layout
and circuit design, combined with a prototyping area, allows the
user to evaluate the AD9748 easily and effectively in any
application where high resolution, high speed conversion is
required.

This board allows the user the flexibility to operate the AD9748
in various configurations. Possible output configurations
include transformer coupled, resistor terminated, and single
and differential outputs. The digital inputs are designed to be
driven from various word generators, with the on-board option
to add a resistor network for proper load termination. Provisions
are also made to exercise the power-down feature of the
AD9748 and select the clock and data modes.

Rev. A | Page 18 of 24

AD9748

TB1 1

TB1 2

TB3 1

TB3 2

TB4 1

TB4 2

C3

0.1μF

C7

0.1μF

C9

0.1μF

L1

L2

L3

BLK

BLK

BLK

BEAD

TP2

BEAD

TP4

BEAD

TP6

C2
10μF

6.3V

C4
10μF

6.3V

C5
10μF

6.3V

RED

RED

RED

TP12

TP13

TP5

C10

0.1μF

C6

0.1μF

C8

0.1μF

CVDD

DVDD

AVDD

2
4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38
40

1
3

5

7

9

11

13

15

17

19

21

23

25

27

29

31
33

35

HEADER STRAIGHT UP MALE NO SHROUD

37
39

J1

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

JP3

CKEXTX

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

CKEXTX

R3
100Ω

R21
100Ω

R4
100Ω

R24
100Ω

100Ω

R25
100Ω

100Ω

R26
100Ω

100Ω

100Ω

R27
100Ω

100Ω

R28
100Ω

100Ω

1 RP3

2 RP3

3 RP3

4 RP3

5 RP3

6 RP3

7 RP3

8 RP3

1 RP4

2 RP4

3 RP4

4 RP4

5 RP4

6 RP4
7 RP4

8 RP4

22Ω 16

22Ω 15

22Ω 14

22Ω 13

22Ω 12

22Ω 11

22Ω 10

22Ω 9

22Ω 16

22Ω 15

22Ω 14

22Ω 13

22Ω 12

22Ω 11
22Ω 10

22Ω 9

R20

R19

R18

R17

R16

R15

Figure 32. Evaluation Board Schematic—Power Supply and Digital Inputs

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CKEXT

03211-029

Rev. A | Page 19 of 24

AD9748

A

V

CMODE

TP7

WHT

MODE

DB7

DB6

DVDD

DB5

DB4

DB3

DB2

DB1

DB0

CVDD

CLK

CLKB

1

2

3

4
5

6

7

8

9

10

11

12
13

14

15

16

R30
10Ω

DB7

DB6

DVDD

DB5

DB4

DB3

DB2

DB1

DB0

DCOM

CVDD

CLK

CLKB

CCOM

CMODE

MODE

AD9748LFCSP

DD

SLEEP

TP11
WHT

R29

32

DB8

DB9

DB10

DB11

DB12

DB13

DCOM1

SLEEP

FS ADJ

REFIO

U1

ACOM

ACOM1

AVDD

AVDD1

CVDD

JP1 0.1%

DB8

31

DB9

30

DB10

29

DB11

28

DB12

27

DB13

26
25

24
23

22

21

IA

20

IB

19

18

17

10kΩ

AVDD

TP3

WHT

C11

0.1μF

C17

TP1

WHT

R1
2kΩ

0.1μF

DVDD CVDD

C19

C19

0.1μF

R11
50Ω

DNP
C13

JP8

DNP
C12

3

2

1

R10

50Ω

T1

T1 – 1T

JP9

4

5

6

IOUT

S3

AGND: 3, 4, 5

C32

0.1μF

03211-030

Figure 33. Evaluation Board Schematic—Output Signal Conditioning

C20
10μF
16V

CVDD

R6
50Ω

C35

0.1μF

S5
AGND: 3, 4, 5

03211-031

CLKB

CKEXT

CLK

JP2

7

U4

2

AGND: 5

CVDD: 8

CVDD

R5
120Ω

3

1

6

U4

4

AGND: 5
CVDD: 8

R2
120Ω

Figure 34. Evaluation Board Schematic—Clock Input

C34

0.1μF

Rev. A | Page 20 of 24

AD9748

03211-032

Figure 35. Evaluation Board Layout—Primary Side

Figure 36. Evaluation Board Layout—Secondary Side

Rev. A | Page 21 of 24

03211-033

AD9748

03211-034

Figure 37. Evaluation Board Layout—Ground Plane

Figure 38. Evaluation Board Layout—Power Plane

Rev. A | Page 22 of 24

03211-035

AD9748

03211-036

Figure 39. Evaluation Board Layout Assembly—Primary Side

Figure 40. Evaluation Board Layout Assembly—Secondary Side

Rev. A | Page 23 of 24

03211-037

AD9748

OUTLINE DIMENSIONS

0.60 MAX

25

24

EXPOSED

PAD

(BOTTOM VIEW)

17

16

32

1

8

9

3.50 REF

PIN 1
INDICATOR

3.25

3.10 SQ

2.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 41. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9748ACP −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9748ACPRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9748ACPZ
AD9748ACPZRL7
AD9748ACP-PCB Evaluation Board

1

Z = Pb-free part.

1

1

−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2

−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03211–0–12/05(A)

Rev. A | Page 24 of 24