Datasheet AD9748 Datasheet (Analog Devices)

8-Bit, 165 MSPS

TxDAC® D/A Converter

FEATURES
High Performance Member of Pin Compatible

TxDAC Product Family

Linearity:

0.1 LSB DNL

0.1 LSB INL
Twos Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
SINAD @ 5 MHz Output: 50 dB
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.20 V Reference
CMOS Compatible Digital Interface
32-Lead LFCSP
Edge-Triggered Latches
Fast Settling: 11 ns to 0.1% Full Scale

APPLICATIONS
Communications
Direct Digital Synthesis (DDS)
Instrumentation

GENERAL DESCRIPTION

The AD9748 is an 8-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica­tion systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or
downward component selection path based on performance,
resolution, and cost. The AD9748 offers exceptional ac and
dc performance while supporting update rates up to 165 MSPS.

The AD9748’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can be
further reduced to a mere 60 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce spuri­ous components and enhance dynamic performance. Edge-triggered

AD9748

*

FUNCTIONAL BLOCK DIAGRAM

3.3V

AVDD ACOM

CURRENT

SOURCE

ARRAY

LSB

SWITCHES

AD9748

IOUTA

IOUTB

MODE
CMODE

R

SET

CLK
CLK

0.1F

3.3V

3.3V

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLKVDD
CLKCOM

SLEEP DIGITAL DATA INPUTS (DB7–DB0)

150pF

SEGMENTED

SWITCHES

LATCHES

input latches and a 1.2 V temperature compensated band gap
reference have been integrated to provide a complete monolithic
DAC solution. The digital inputs support 3 V CMOS logic families.

PRODUCT HIGHLIGHTS

1. 32-lead LFCSP package.

2. The AD9748 is the 8-bit member of the pin compatible TxDAC
family, which offers excellent INL and DNL performance.

3. Differential or single-ended clock input (LVPECL or CMOS),
supports 165 MSPS conversion rate.

4. Data input supports twos complement or straight binary data
coding.

5. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.

6. On-chip voltage reference: The AD9748 includes a 1.2 V
temperature-compensated band gap voltage reference.

*Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD9748–SPECIFICATIONS

DC SPECIFICATIONS

(T

MIN to TMAX,

AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

= 20 mA, unless otherwise noted.)

OUTFS

Parameter Min Typ Max Unit

RESOLUTION 8 Bits

DC ACCURACY

1

Integral Linearity Error (INL) ± 0.25 ± 0.1 ± 0.25 LSB
Differential Nonlinearity (DNL) ± 0.25 ± 0.1 ± 0.25 LSB

ANALOG OUTPUT

Offset Error –0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Gain Error (With Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Full-Scale Output Current

2

2.0 20.0 mA

Output Compliance Range –1.0 +1.25 V
Output Resistance 100 kW
Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 1 MW
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/∞C
Gain Drift (Without Internal Reference) ± 50 ppm of FSR/∞C
Gain Drift (With Internal Reference) ± 100 ppm of FSR/∞C
Reference Voltage Drift ± 50 ppm/∞C

POWER SUPPLY

Supply Voltages

AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V

CLKVDD 2.7 3.3 3.6 V
Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation

4

5

Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD

)3336mA

AVDD

4

)

DVDD

CLKDVDD

AVDD

)57mA

)56mA

89 mA

135 145 mW

6

6

–1+1% of FSR/V
–0.04 +0.04 % of FSR/V

145 mW

OPERATING RANGE –40 +85 ∞C

NOTES

1

Measured at IOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

An external buffer amplifier with an input bias current <100 nA should be used to drive any external load.

4

Measured at f

5

Measured as unbuffered voltage output with I

6

± 5% power supply variation.

Specifications subject to change without notice.

= 100 MSPS and f

CLOCK

, is 32 times the I

OUTFS

OUT

REF

= 1 MHz.

= 20 mA and 50 W R

OUTFS

current.

at IOUTA and IOUTB, f

LOAD

= 100 MSPS and f

CLOCK

= 40 MHz.

OUT

REV. 0–2–

AD9748

(T

to T

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

Single-Ended Output, 50  Doubly Terminated, unless otherwise noted.)

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I

OUTFS

OUTFS

= 20 mA)
= 2 mA)

2

CLOCK

1

1

2

) 165 MSPS

1

11 ns

2.5 ns

2.5 ns
50 pA/÷Hz
30 pA/÷Hz

AC LINEARITY

Signal-to-Noise and Distortion Ratio

= 50 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 100 MSPS; f

f

CLOCK

f

= 100 MSPS; f

CLOCK

= 165 MSPS; f

f

CLOCK

= 165 MSPS; f

f

CLOCK

= 5 MHz 50 dB

OUT

= 19 MHz 47 dB

OUT

= 5 MHz 50 dB

OUT

= 39 MHz 46 dB

OUT

= 5 MHz 50 dB

OUT

= 49 MHz 47 dB

OUT

Total Harmonic Distortion

= 25 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

f

= 100 MSPS; f

CLOCK

= 165 MSPS; f

f

CLOCK

= 1 MHz –72 –61 dBc

OUT

= 12.5 MHz –65 dBc

OUT

= 25 MHz –60 dBc

OUT

= 41.3 MHz –58 dBc

OUT

Spurious-Free Dynamic Range to Nyquist

= 25 MSPS; f

f

CLOCK

= 1 MHz

OUT

0 dBFS Output 61 72 dBc
f
f
f
f
f
f

NOTES

1

Measured single-ended into 50 W load.

2

Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.

Specifications subject to change without notice.

= 65 MSPS; f

CLOCK

= 65 MSPS; f

CLOCK

= 100 MSPS; f

CLOCK

= 100 MSPS; f

CLOCK

= 165 MSPS; f

CLOCK

= 165 MSPS; f

CLOCK

= 5 MHz 69 dBc

OUT

= 19 MHz 65 dBc

OUT

= 5 MHz 68 dBc

OUT

= 39 MHz 62 dBc

OUT

= 5 MHz 68 dBc

OUT

= 49 MHz 54 dBc

OUT

= 20 mA, Differential

OUTFS

DIGITAL SPECIFICATIONS

(T

to T

MIN

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.)

OUTFS

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current –10 +10 mA
Logic 0 Current –10 +10 mA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t

) 2.0 ns

S

) 1.5 ns

H

) 1.5 ns

LPW

CLK INPUTS*

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

*Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.

Specifications subject to change without notice.

REV. 0

–3–

AD9748

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Unit

AVDD ACOM –0.3 +3.9 V
DVDD DCOM –0.3 +3.9 V
CLKVDD CLKCOM –0.3 +3.9 V
ACOM DCOM –0.3 +0.3 V
ACOM CLKCOM –0.3 +0.3 V
DCOM CLKCOM –0.3 +0.3 V
AVDD DVDD –3.9 +3.9 V
AVDD CLKVDD –3.9 +3.9 V
DVDD CLKVDD –3.9 +3.9 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
REFIO, REFLO, FSADJ ACOM –0.3 AVDD + 0.3 V
CLK+, CLK–, CMODE CLKCOM –0.3 CLKVDD + 0.3 V
Junction Temperature 150 ∞C
Storage Temperature –65 +150 ∞C
Lead Temperature (10 sec) 300 ∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.

DB0–DB11

CLOCK

IOUTA

OR

IOUTB

t

S

t

PD

0.1%

t

H

t

LPW

t

ST

0.1%

Figure 1. Timing Diagram

ORDERING GUIDE

Temperature Package Package

Model Range Description Options*

AD9748ACP –40∞C to +85∞C 32-Lead LFCSP CP-32
AD9748ACP-PCB Evaluation Board

*CP = Lead Frame Chip Scale Package

THERMAL CHARACTERISTICS
Thermal Resistance

32-Lead LFCSP

= 32.5∞C/W

␪

JA

Thermal impedance measurements were taken on a 4-layer board
in still air, in accordance with EIA/JESD51-7.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9748 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–4–

PIN CONFIGURATION

32 DB2

31 DB3

30 DB4

29 DB5

27 DB7 (MSB)

26 DCOM

25 SLEEP

28 DB6

AD9748

DB1 1

(LSB) DB0 2

DVDD 3

NC 4
NC 5
NC 6
NC 7
NC 8

PIN 1
INDICATOR

AD9748

TOP VIEW

NC 9

CLK 12

CLK 13

DCOM 10

CLKVDD 11

NC = NO CONNECT

MODE 16

CMODE 15

CLKCOM 14

24 FSADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

27 DB7 Most Significant Data Bit (MSB)

28–32, 1 DB6–DB1 Data Bits 6–1

2 DB0 Least Significant Data Bit (LSB)

3 DVDD Digital Supply Voltage (3.3 V)

4–9NCNo Internal Connection

10, 26 DCOM Digital Common

11 CLKVDD Clock Supply Voltage (3.3 V)

12 CLK+ Differential Clock Input

13 CLK– Differential Clock Input

14 CLKCOM Clock Common

15 CMODE

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–).
Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).

16 MODE Selects Input Data Format. Connect to CLKCOM for straight binary, CLKVDD for twos complement.

17, 18 AVDD Analog Supply Voltage (3.3 V)

19, 22 ACOM Analog Common

20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.

21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.

23 REFIO Reference Input/Output. Requires 0.1 mF capacitor to ACOM.

24 FSADJ Full-Scale Current Output Adjust

25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated

if not used.

REV. 0

–5–

AD9748

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is called
the offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set to
1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (25∞C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale range
(FSR) per ∞C. For reference drift, the drift is reported in ppm per ∞C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies are
varied from nominal to minimum and maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the start
of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic compo­nents to the rms value of the measured input signal. It is expressed
as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious free dynamic range containing multiple carrier tones
of equal amplitude. It is measured as the difference between the
rms amplitude of a carrier tone to the peak spurious signal in
the region of a removed tone.

*AWG2021 CLOCK

RETIMED SO THAT
THE DIGITAL DATA
TRANSITIONS ON
FALLING EDGE OF
50% DUTY CYCLE
CLOCK.

DVDD

DCOM

RETIMED
CLOCK
OUTPUT*

PULSE GENERATOR

R

SET

50

LECROY 9210

0.1F

3.3V

CLK

CLK

3.3V

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLKVDD
CLKCOM

SLEEP DIGITAL DATA INPUTS (DB7–DB0)

CLOCK

OUTPUT

150pF

SEGMENTED

SWITCHES

TEKTRONIX AWG-2021

WITH OPTION 4

Figure 2. Basic AC Characterization Test Setup

CURRENT

LATCHES

DIGITAL

DATA

3.3V

AVDD ACOM

SOURCE

ARRAY

LSB

SWITCHES

AD9748

IOUTA

IOUTB

MODE

CMODE

50

20pF

50

100

20pF

MINI-CIRCUITS

T1–1T

ROHDE &
SCHWARZ
FSEA30
SPECTRUM
ANALYZER

REV. 0–6–

Typical Performance Characteristics–AD9748

55

50

45

40

SINAD – dB

35

30

110100

TPC 1. SINAD vs. I

10mA

5mA

2.5mA

f

– MHz

OUT

OUTFS

(Single-Ended Output)

80

75

70

65

60

55

SINAD/THD – dB

50

45

40

1

TPC 4. SINAD/THD vs. f

THD@165MSPS

THD@50MSPS

THD@100MSPS

SINAD@165MSPS

SINAD@50MSPS

SINAD@100MSPS

10 100

f

– MHz

OUT

OUT

Output)

20mA

@ 100 MSPS

(Differential

55

50

5mA

45

40

SINAD – dB

35

30

110100

TPC 2. SINAD vs. I

f

OUT

10mA

2.5mA

– MHz

@ 165 MSPS

OUTFS

20mA

(Single-Ended Output)

0

f

= 25MSPS

CLOCK

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE – dBm

–80

–90

–100

f

= 7.81MHz

OUT

SFDR = 65.0dBc
AMPLITUDE = 0dBFS

246810 12

0

FREQUENCY – MHz

TPC 5. Single-Tone Spectral Plot @
25 MSPS (Single-Ended Output)

80

75

70

65

60

55

SINAD@50MSPS

SINAD/THD – dB

50

45

SINAD@165MSPS

40

1

THD@165MSPS

TPC 3. SINAD/THD vs. f

THD@50MSPS

THD@100MSPS

SINAD@100MSPS

10 100

f

– MHz

OUT

(Single-

OUT

Ended Output)

0

–10

–20

–30

–40

–50

–60

MAGNITUDE – dBm

–70

–80

–90

–100

01020304050

f

= 125MSPS

CLOCK

f

= 27MHz

OUT

SFDR = 56.2dBc
AMPLITUDE = 0dBFS

FREQUENCY – MHz

TPC 6. Single-Tone Spectral Plot@
125 MSPS (Single-Ended Output)

60

0

f

= 165MSPS

CLOCK

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE – dBm

–80

–90

–100

f

= 49MHz

OUT

SFDR = 50.1dBc
AMPLITUDE = 0dBFS

0

20 3010 40 50 60 70 80

FREQUENCY – MHz

TPC 7. Single-Tone Spectral Plot

@ 165 MSPS (Single-Ended

Output)

REV. 0

50mV/DIV

5ns/DIV

TPC 8. Step Response (Single-Ended
Output)

–7–

AD9748

R

SET

CLK
CLK

0.1F

3.3V

3.3V

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLKVDD
CLKCOM

SLEEP DIGITAL DATA INPUTS (DB7–DB0)

150pF

SEGMENTED

SWITCHES

Figure 3. Simplified Block Diagram

CURRENT

LATCHES

3.3V

AVDD ACOM

SOURCE

ARRAY

LSB

SWITCHES

AD9748

V

DIFF

IOUTA

IOUTB

MODE
CMODE

= V

OUTA

R
50

– V

LOAD

OUTB

R
50

LOAD

FUNCTIONAL DESCRIPTION

Figure 3 shows a simplified block diagram of the AD9748. The
AD9748 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I

). The array is divided into 31 equal currents

OUTFS

that make up the 5 most significant bits (MSBs). The next
3 bits consist of 7 equal current sources whose

value is 1/8th of
an MSB current source. Implementing the lower bits with cur­rent sources, instead of an R-2R ladder, enhances its dynamic
performance for multitone or low amplitude signals and helps
maintain the DAC’s high output impedance (i.e., >100 kW).

All of these current sources are switched to one or the other of the
two output nodes (i.e., IOUTA or IOUTB) via PMOS differen­tial current switches. The switches are based on the architecture
that was pioneered in the AD9764 family, with further refine­ments to reduce distortion contributed by the switching transient.
This switch architecture also reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.

The analog and digital sections of the AD9748 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 165 MSPS, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.2 V band gap voltage refer­ence, and a reference control amplifier.

The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R

, connected to the full-scale adjust (FSADJ)

SET

pin. The external resistor, in combination with both the refer­ence control amplifier and voltage reference, V
reference current I

, which is replicated to the segmented

REF

REFIO

, sets the

current sources with the proper scaling factor. The full-scale
current, I

, is 32 times I

OUTFS

REF

.

REFERENCE OPERATION

The AD9748 contains an internal 1.2 V band gap reference,
which can be easily overridden by an external reference with no
effect on performance. When using the internal reference, simply
decouple the REFIO pin to ACOM with a 0.1 mF capacitor.
The internal reference voltage will be present at REFIO. If the
voltage at REFIO is to be used anywhere else in the circuit, an
external buffer amplifier with an input bias current of less than
100 nA should be used. An example of the use of the internal
reference is given in Figure 4.

3.3V

AVDD

CURRENT

SOURCE

ARRAY

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

0.1F

2k

150pF

+1.2V REF

REFIO

FS ADJ

AD9748

Figure 4. Internal Reference Configuration

An external reference can be applied to REFIO as shown in
Figure 5. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 mF
compensation capacitor is not required since the internal refer­ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.

3.3V

AVDD

EXTERNAL

REF

150pF

+1.2V REF

V

REFIO

R

I

SET

REF

V

REFIO/RSET

REFIO

FS ADJ

=

AD9748

REFERENCE
CONTROL
AMPLIFIER

AVDD

CURRENT

SOURCE

ARRAY

Figure 5. External Reference Configuration

REV. 0–8–

AD9748

REFERENCE CONTROL AMPLIFIER

The AD9748 contains a control amplifier that is used to regulate
the full-scale output current, I

. The control amplifier is

OUTFS

configured as a V-I converter, as shown in Figure 4, so that its
current output, I
and an external resistor, R

, is determined by the ratio of the V

REF

, as stated in Equation 4. I

SET

REFIO

is

REF

copied to the segmented current sources with the proper scale
factor to set I

as stated in Equation 3.

OUTFS

The control amplifier allows a wide (10:1) adjustment span
of I

62.5 mA and 625 mA. The wide adjustment span of I

over a 2 mA to 20 mA range by setting I

OUTFS

between

REF

OUTFS

pro­vides several benefits. The first relates directly to the power
dissipation of the AD9748, which is proportional to I

OUTFS

(refer
to the Power Dissipation section). The second relates to the 20 dB
adjustment, which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.

DAC TRANSFER FUNCTION

Both DACs in the AD9748 provide complementary current outputs,
IOUTA and IOUTB. IOUTA will provide a near full-scale cur­rent output, I

, when all bits are high (i.e., DAC CODE = 255)

OUTFS

while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a func­tion of both the input code and I

IOUTA DAC CODE I

IOUTB DAC CODE I

=¥(/)256

=¥( – )/255 256

and can be expressed as:

OUTFS

OUTFS

OUTFS

(1)

(2)

where DAC CODE = 0 to 255 (i.e., decimal representation).

As mentioned previously, I
current I
and external resistor, R

, which is nominally set by a reference voltage, V

REF

SET

II

=¥32

OUTFS REF

is a function of the reference

OUTFS

. It can be expressed as:

REFIO

,

(3)

where

IV R

= /

REF REFIO SET

(4)

The two current outputs will typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and
IOUTB should be directly connected to matching resistive loads,

, that are tied to analog common, ACOM. Note, R

R

LOAD

LOAD

may represent the equivalent load resistance seen by IOUTA or
IOUTB as would be the case in a doubly terminated 50 W or
75 W cable. The single-ended voltage output appearing at the
IOUTA and IOUTB nodes is simply:

V IOUTA R

=¥

OUTA LOAD

V IOUTB R

=¥

OUTB LOAD

Note that the full-scale value of V

OUTA

and V

should not

OUTB

(5)

(6)

exceed the specified output compliance range to maintain speci­fied distortion and linearity performance.

DIFF

(7)

can

V IOUTA IOUTB R

=¥( – )

DIFF LOAD

Substituting the values of IOUTA, IOUTB, I

REF

, and V

be expressed as:

VDACCODE

=¥

( – )/

2 255 256

{}

DIFF

RR V

¥

32

()

LOAD SET REFIO

¥

/

(8)

These last two equations highlight some of the advantages of
operating the AD9748 differentially. First, the differential opera­tion will help cancel common-mode error sources associated
with IOUTA and IOUTB, such as noise, distortion, and dc offsets.
Second, the differential code dependent current and subsequent
voltage, V
output (i.e., V

, is twice the value of the single-ended voltage

DIFF

OUTA

or V

), thus providing twice the signal

OUTB

power to the load.

Note that the gain drift temperature performance for a single­ended (V

OUTA

and V

) or differential output (V

OUTB

DIFF

) of the
AD9748 can be enhanced by selecting temperature tracking
resistors for R

LOAD

and R

due to their ratiometric relationship

SET

as shown in Equation 8.

ANALOG OUTPUTS

The complementary current outputs in each DAC, IOUTA, and
IOUTB,

may be configured for single-ended or differential opera­tion. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, V
R

, as described in the DAC Transfer Function section by

LOAD

OUTA

and V

Equations 5 through 8. The differential voltage, V
between V

OUTA

and V

, can also be converted to a single-

OUTB

, via a load resistor,

OUTB

, existing

DIFF

ended voltage via a transformer or differential amplifier configuration.
The ac performance of the AD9748 is optimum and specified
using a differential transformer coupled output in which the
voltage swing at IOUTA and IOUTB is limited to ± 0.5 V.

The distortion and noise performance of the AD9748 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi­cant as the frequency content of the reconstructed waveform
increases and/or its amplitude decreases. This is due to the first
order cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise.

Performing a differential-to-single-ended conversion via a trans­former also provides the ability to deliver twice the reconstructed
signal power to the load (assuming no source termination). Since
the output currents of IOUTA and IOUTB are comple

mentary,
they become additive when processed differentially. A properly
selected transformer will allow the AD9748 to provide the required
power and voltage levels to different loads.

The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associ­ated with the current sources and is typically 100 kW in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., V

OUTA

and V

) due to the nature of a PMOS device.

OUTB

As a result, maintaining IOUTA and/or IOUTB at a virtual
ground via an I-V op amp configuration will result in the optimum
dc linearity. Note that the INL/DNL specifications for the AD9748
are measured with IOUTA maintained at a virtual ground via
an op amp.

IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9748.

REV. 0

–9–

AD9748

The positive output compliance range is slightly dependent on the
full-scale output current, I
nal 1.2 V for an I

= 20 mA to 1.0 V for an I

OUTFS

. It degrades slightly from its nomi-

OUTFS

OUTFS

= 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale signal
at IOUTA and IOUTB does not exceed 0.5 V.

DIGITAL INPUTS

The AD9748 digital section consists of 8 input bit channels and
a clock input. The 8-bit parallel data inputs follow standard posi­tive binary coding, where DB7 is the most significant bit (MSB)
and DB0 is the least significant bit (LSB).

IOUTA produces a full­scale output current when all data bits are at Logic 1. IOUTB
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.

DVDD

DIGITAL

INPUT

Figure 6. Equivalent Digital Input

The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
165 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.

CLOCK INPUT

A configurable clock input allows for one single-ended and two
differential modes. The mode selection is controlled by the
CMODE input, as summarized in Table I. Connecting CMODE
to CLKCOM selects the single-ended clock input. In this mode,
the CLK+ input is driven with rail-to-rail swings and the CLK–
input is left floating. If CMODE is connected to CLKVDD, the
differential receiver mode is selected. In this mode both inputs are
high impedance. The final mode is selected by floating CMODE.
This mode is also differential, but internal terminations for
positive emitter-coupled logic (PECL) are activated. There is no
significant performance difference between any of the three clock
input modes.

Table I. Clock Mode Selection

CMODE Pin Clock Input Mode

CLKCOM Single-Ended
CLKVDD Differential
Float PECL

In the single-ended clock input mode, the CLK+ pin must be
driven to rail-to-rail CMOS levels. The quality of the DAC output
is directly related to the clock quality, and jitter is a key concern.
Any noise or jitter in the clock will translate directly into the DAC

output. Optimal performance will be achieved if the CLOCK
input has a sharp rising edge, since the DAC latches are positive
edge triggered.

In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK– inputs can vary from 0.75 V to 2.25 V,
and the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave, since
the high gain-bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.

The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 7. These termination resistors are untrimmed and the
absolute resistance can vary up to ± 20%. However, matching
between the resistors should be generally better than ± 1%.

CLK+

CLK–

50 50

= 1.3V NOM

V

TT

AD9748

CLOCK
RECEIVER

TO DAC CORE

Figure 7. Clock Termination in PECL Mode

DAC TIMING
Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the relation­ship between the position of the clock edges and the time at
which the input data changes. The AD9748 is rising edge trig­gered, and so exhibits dynamic performance sensitivity when the
data transition is close to this edge. In general, the goal when
applying the AD9748 is to make the data transition close to the
falling clock edge. This becomes more important as the sample
rate increases. Figure 8 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement, while
at higher rates, more care must be taken.

80

75

70

65

60

55

SFDR – dB

50

45

40

35

30

246810 120

CLOCK PLACEMENT – ns

Figure 8. SFDR vs. Clock Placement @ f
and 50 MHz (f

= 165 MSPS)

CLOCK

20MHz SFDR

50MHz SFDR

OUT

= 20 MHz

REV. 0–10–

AD9748

Sleep Mode Operation

The AD9748 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over
the specified supply range of 2.7 V to 3.6 V and temperature
range. This mode can be activated by applying a logic level 1 to
the SLEEP pin. The SLEEP pin logic threshold is equal to

0.5 ⫻ AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9748 remains enabled if this
input is left disconnected. The AD9748 takes less than 50 ns to
power down and approximately 5 ms to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9748 is dependent on
several factors that include the:

∑

Power supply voltages (AVDD, CLKVDD, and DVDD)

∑

Full-scale current output I

∑

Update rate f

∑

Reconstructed digital input waveform

CLOCK

OUTFS

The power dissipation is directly proportional to the analog supply
current, I
directly proportional to I
sitive to f
digital input waveform, f
Figure 10 shows I
ratios (f

, and the digital supply current, I

AVDD

. Conversely, I

CLOCK

OUT/fCLOCK

35

30

25

– mA

20

AVD D

I

15

10

5

2

4681012 14 16 18 20

DVDD

) for various update rates with DVDD = 3.3 V.

Figure 9. I

, as shown in Figure 9, and is insen-

OUTFS

CLOCK

is dependent on both the

DVDD

, and digital supply DVDD.

as a function of full-scale sine wave output

I

– mA

OUTFS

AVDD

vs. I

OUTFS

DVDD

. I

AVDD

is

10

9

8

7

6

– mA

5

CLKVDD

4

I

3

2

1

0

30 60 90 120 150 1800

Figure 11. I

PECL

CLKVDD

vs. f

f

CLK

CLOCK

DIFF

SE

and Clock Mode

APPLYING THE AD9748
Output Configurations

The following sections illustrate some typical output configura­tions for the AD9748. Unless otherwise noted, it is assumed that

is set to a nominal 20 mA. For applications requiring the

I

OUTFS

optimum dynamic performance, a differential output configura­tion is suggested. A differential output configuration may consist of
either an RF transformer or a differential op amp configuration. The
transformer configuration provides the optimum high frequency
performance and is recommended for any application that allows
ac coupling. The differential op amp configuration is suitable for
applications requiring dc coupling, a bipolar output, signal gain,
and/or level shifting within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, R

, referred to ACOM. This configura-

LOAD

tion may be more suitable for a single-supply system requiring a
dc-coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This con­figuration provides the best dc linearity since IOUTA or IOUTB
is maintained at a virtual ground.

REV. 0

16

14

12

10

– mA

8

DVDD

I

6

4

2

0

0.01 0.1

Figure 10. I

RATIO –

vs. Ratio @ DVDD = 3.3 V

DVDD

165MSPS

125MSPS

65MSPS

f

OUT

/

f

CLOCK

1.0

–11–

AD9748

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-single­ended signal conversion, as shown in Figure 12. A differentially
coupled transformer output provides the optimum distortion
performance for output signals whose spectral content lies within
the transformer’s pass band. An RF transformer, such as the
Mini-Circuits T1–1T, provides excellent rejection of common­mode distortion (i.e., even-order harmonics) and noise over a
wide frequency range. It also provides electrical isolation and the
ability to deliver twice the power to the load. Transformers with
different impedance ratios may also be used for impedance match­ing purposes. Note that the transformer provides ac coupling only.

MINI-CIRCUITS

IOUTA

AD9748

IOUTB

T1–1T

OPTIONAL R

DIFF

R

LOAD

Figure 12. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., V

OUTA

and V

OUTB

) swing
symmetrically around ACOM and should be maintained with
the specified output compliance range of the AD9748. A differ­ential resistor, R
output of the transformer is connected to the load, R
passive reconstruction filter or cable. R

, may be inserted in applications where the

DIFF

is determined by the

DIFF

LOAD

, via a

transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately
half the signal power will be dissipated across R

DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-

single­ended conversion as shown in Figure 13. The AD9748 is
configured with two equal load resistors, R

, of 25 W. The

LOAD

differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter.
The addition of this capacitor also enhances the op amp’s
distortion performance by preventing the DACs high slewing
output from overloading the op amp’s input.

500

AD9748

IOUTA

IOUTB

C

OPT

225

225

2525

AD8047

500

Figure 13. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differen­tial op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off a dual
supply since its output is approximately ± 1.0 V. A high speed
amplifier capable of preserving the differential performance of the

AD9748 while meeting other system level objectives (e.g., cost,
or power) should be selected. The op amp’s differential gain, its
gain setting resistor values, and full-scale output swing capabili­ties should all be considered when optimizing this circuit.

The differential circuit shown in Figure 14 provides the neces­sary level shifting required in a single-supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9748 and the op amp, is also used to level shift the differ­ential output of the AD9748 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.

500

AD9748

IOUTA

IOUTB

C

OPT

225

1k

AD8041

1k

AVDD

225

2525

Figure 14. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 15 shows the AD9748 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly termi­nated 50 W cable, since the nominal full-scale current, I
of 20 mA flows through the equivalent R
case, R

represents the equivalent load resistance seen by

LOAD

of 25 W. In this

LOAD

OUTFS

,

IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
Different values of I

OUTFS

and R

can be selected as long as

LOAD

LOAD

.

the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL),
discussed in the Analog Output section of this data sheet. For
optimum INL performance, the single-ended, buffered voltage
output configuration is suggested.

AD9748

IOUTA

IOUTB

I

OUTFS

= 20mA

25

50

V

OUTA

= 0V TO 0.5V

50

Figure 15. 0 V to 0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION

Figure 16 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9748
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, minimizing the nonlinear output impedance effect on the
DAC’s INL performance, as discussed in the Analog Output sec­tion. Although this single-ended configuration typically provides
the best dc linearity performance, its ac distortion performance at
higher DAC update rates may be limited by U1’s slew rate capa­bilities. U1 provides a negative unipolar output voltage and its
full-scale output voltage is simply the product of R

FB

and I

OUTFS

.
The full-scale output should be set within U1’s voltage output
swing capabilities by scaling I
in ac distortion performance may result with a reduced I

and/or RFB. An improvement

OUTFS

OUTFS

since U1 will be required to sink less signal current.

REV. 0–12–

AD9748

C

OPT

R

FB

200

U1

V

= I

OUTFS

 R

FB

OUT

AD9748

IOUTA

IOUTB

I

= 10mA

OUTFS

22

21

200

Figure 16. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION

Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF techniques
must be used for device selection, placement, and routing as well
as power supply bypassing and grounding to ensure optimum
performance. Figures 22 to 25 illustrate the recommended
printed circuit board ground, power, and signal plane layouts
implemented on the AD9748 evaluation board.

One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise super­imposed on the analog or digital dc power distribution. This is
referred to as the power supply rejection ratio. For dc variations
of the power supply, the resulting performance of the DAC
directly corresponds to a gain error associated with the DAC’s
full-scale current, I

. AC noise on the dc supplies is common

OUTFS

in applications where the power distribution is generated by a
switching power supply. Typically, switching power supply noise
will occur over the spectrum from tens of kHz to several MHz.
The PSRR versus frequency of the AD9748 AVDD supply over
this frequency range is shown in Figure 17.

85

80

75

70

65

60

PSRR – dB

55

50

45

40

24 810

FREQUENCY – MHz

1260

Figure 17. Power Supply Rejection Ratio

Note that ratio in Figure 17 is calculated amps out/volts in.
Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The volt­age noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative size of these
switches, PSRR is very code dependent. This can produce a
mixing effect that can modulate low-frequency power supply

noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs will occur when the full-scale
current is directed toward that output. As a result, the PSRR
measurement in Figure 17 represents a worst-case condition in
which the digital inputs remain static and the full-scale output
current of 20 mA is directed to the DAC output being measured.

An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplic­ity sake (i.e., ignore harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC’s full-scale
current, I
Figure 17 at 250 kHz. To calculate the PSRR for a given R

, one must determine the PSRR in dB using

OUTFS

LOAD

,
such that the units of PSRR are converted from A/V to V/V, adjust
the curve in Figure 17 by the scaling factor 20 ⫻ log(R
For instance, if R

is 50 W, the PSRR is reduced by 34 dB

LOAD

LOAD

).

(i.e., PSRR of the DAC at 250 kHz which is 85 dB in Figure 17
becomes 51 dB V

OUT/VIN

).

Proper grounding and decoupling should be a primary objective
in any high-speed, high resolution system. The AD9748 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physically
possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close to the chip as physically possible.

For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 18. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.

FERRITE

BEADS

TTL/CMOS

LOGIC

CIRCUITS

3.3V

POWER SUPPLY

100F
ELECT.

10F–22F
TANT.

0.1F
CER.

AVDD

ACOM

Figure 18. Differential LC Filter for Single 3.3 V Applications

EVALUATION BOARD
General Description

The AD9748 evaluation board allows for easy set up and testing
of the product in the 32-lead LFCSP package. Careful attention
to layout and circuit design, combined with a prototyping area,
allows the user to evaluate the AD9748 easily and effectively in
any application that requires high resolution, high speed conversion.

This board allows the user the flexibility to operate the AD9748
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single and differ­ential outputs. The digital inputs are designed to be driven from
various word generators, with the on-board option to add a
resistor network for proper load termination. Provisions are also
made to exercise the power-down feature of the AD9748 and
select the clock and data modes.

REV. 0

–13–

AD9748

X

TB1 1

TB1 2

TB3 1

TB3 2

TB4 1

TB4 2

C3

0.1F

C7

0.1F

C9

0.1F

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

CKEXTX

L1

BLK

L2

BLK

L3

BLK

R3
100

BEAD

TP2

BEAD

TP4

BEAD

TP6

R4
100

C2
10F

6.3V

C4
10F

6.3V

C5
10F

6.3V

R15
100

RED

RED

RED

TP12

TP13

TP5

R16
100

C10

0.1F

C6

0.1F

C8

0.1F

R17
100

CVDD

DVDD

AVDD

R18
100

R19
100

R20
100

1 RP3

2 RP3

3 RP3

4 RP3

5 RP3

6 RP3

7 RP3

8 RP3

1 RP4

2 RP4

3 RP4

4 RP4

5 RP4

6 RP4
7 RP4

8 RP4

2
4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38
40

22 16

22 15

22 14

22 13

22 12

22 11

22 10

22 9

22 16

22 15

22 14

22 13

22 12

22 11
22 10

22 9

1
3

5

7

9

11

13

15

17

19

21

23

25

27

29

31
33

35

HEADER STRAIGHT UP MALE NO SHROUD

37
39

J1

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

JP3

CKEXT

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CKEXT

R21
100

R24
100

R25
100

R26
100

R27
100

R28
100

Figure 19. Evaluation Board Schematic: Power Supply and Digital Inputs

REV. 0–14–

AD9748

CMODE

TP7

WHT

MODE

DB7

DB6

DVDD

DB5

DB4

DB3

DB2

DB1

DB0

CVDD

CLK

CLKB

10

11
12

13

14

15

16

1

2

3

4

5

6

7

8

9

DB7

DB6

DVDD
DB5

DB4

DB3

DB2

DB1

DB0

DCOM

CVDD

CLK

CLKB

CCOM

CMODE

MODE

R30
10k

DB10
DB11

DB12

DB13

DCOM1

SLEEP

FSADJ

REFIO

U1

ACOM

ACOM1

AVDD

AVDD1

AD9744LFCSP

CVDD

JP1

DB8

DB9

SLEEP

TP11
WHT

R29

32

DB8

31

DB9

30

DB10

29

DB11

28

DB12

27

DB13

26

25

24

23

22

21

IA

20

IB

19

18

17

AVDD

10k

TP3

WHT

C11

0.1F

TP1

WHT

R1
2k

0.1%

C17

0.1F

DVDD CVDDAVDD

DNP
C13

3

2

1

DNP
C12

R11
50

R10
50

JP8

T1

T1–1T

JP9

C19

0.1F

C32

0.1F

IOUT

4

5

6

S3
AGND: 3, 4, 5

CLKB

CKEXT

CLK

Figure 20. Evaluation Board Schematic: Output Signal Conditioning

C20
10F
16V

CVDD

R6
50

C35

0.1F

JP2

7

3

U4

4

AGND: 5
CVDD: 8

U4

AGND: 5
CVDD: 8

1

2

CVDD

R5
120

6

C34

0.1F

R2
120

Figure 21. Evaluation Board Schematic: Clock Input

S5
AGND: 3, 4, 5

REV. 0

–15–

AD9748

Figure 22. Evaluation Board Layout: Primary Side

Figure 23. Evaluation Board Layout: Secondary Side

REV. 0–16–

AD9748

Figure 24. Evaluation Board Layout: Ground Plane

REV. 0

Figure 25. Evaluation Board Layout: Power Plane

–17–

AD9748

Figure 26. Evaluation Board Layout: Assembly—Primary Side

Figure 27. Evaluation Board Layout: Assembly—Secondary Side

REV. 0–18–

OUTLINE DIMENSIONS

32-Lead, Lead Frame Chip Scale Package (LFCSP)

(CP-32)

Dimensions shown in millimeters

AD9748

PIN 1

INDICATOR

1.00

0.90

0.80

12 MAX

SEATING
PLANE

5.00

BSC SQ

0.30

0.23

0.18

4.75

BSC SQ

0.25 REF

TOP

VIEW

0.70 MAX

0.65 NOM

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

25

24

17

16

0.60 MAX

BOTTOM

VIEW

3.50
REF

PIN 1

32

9

INDICATOR

1

3.25
SQ

3.10

2.95

8

REV. 0

–19–

C03211–0–2/03(0)

–20–

PRINTED IN U.S.A.