Datasheet AD9744 Datasheet (Analog Devices)

14-Bit, 165 MSPS

TxDAC

®

D/A Converter

FEATURES
High Performance Member of Pin Compatible

TxDAC Product Family
Excellent Spurious-Free Dynamic Range Performance
SFDR to Nyquist:

83 dBc @ 5 MHz Output

80 dBc @ 10 MHz Output

73 dBc @ 20 MHz Output
SNR @ 5 MHz Output, 125 MSPS: 77 dB
Twos Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.2 V Reference
CMOS Compatible Digital Interface
28-Lead SOIC, 28-Lead TSSOP, and 32-Lead LFCSP

Packages
Edge-Triggered Latches

APPLICATIONS
Wideband Communication Transmit Channel:

Direct IF

Base Stations

Wireless Local Loop

Digital Radio Link

Direct Digital Synthesis (DDS)

Instrumentation

R

SET

CLOCK

FUNCTIONAL BLOCK DIAGRAM

0.1F

3.3V

REFLO

+1.2V REF
REFIO

FS ADJ

DVDD

DCOM

CLOCK

DIGITAL DATA INPUTS (DB13–DB0)

SLEEP

150pF

SEGMENTED

SWITCHES

LATCHES

CURRENT

SOURCE

ARRAY

SWITCHES

AD9744

3.3V

AVDD

ACOM

AD9744

LSB

IOUTA

IOUTB

*

MODE

GENERAL DESCRIPTION

The AD9744 is a 14-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communi­cation systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or down­ward component selection path based on performance, resolution,
and cost. The AD9744 offers exceptional ac and dc performance
while supporting update rates up to 165 MSPS.

The AD9744’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also,
a power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architec­ture is combined with a proprietary switching technique to
reduce spurious components and enhance dynamic performance.

*Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

Edge-triggered input latches and a 1.2 V temperature compen­sated band gap reference have been integrated to provide a
complete monolithic DAC solution. The digital inputs support
3V CMOS logic families.

PRODUCT HIGHLIGHTS

1. The AD9744 is the 14-bit member of the pin compatible
TxDAC family, which offers excellent INL and DNL
performance.

2. Data input supports twos complement or straight binary
data coding.

3. High speed, single-ended CMOS clock input supports
165 MSPS conversion rate.

4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.

5. On-chip voltage reference: The AD9744 includes a 1.2 V
temperature compensated band gap voltage reference.

6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead
LFCSP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD9744–SPECIFICATIONS

(T

to T

DC SPECIFICATIONS

MIN

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

Parameter Min Typ Max Unit

RESOLUTION 14 Bits

DC ACCURACY

1

Integral Linearity Error (INL) –5 ± 0.8 +5 LSB
Differential Nonlinearity (DNL) –3 ± 0.5 +3 LSB

ANALOG OUTPUT

Offset Error –0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Gain Error (With Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Full-Scale Output Current

2

220mA

Output Compliance Range –1 +1.25 V
Output Resistance 100 kW
Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance (Ext. Reference) 1 MW
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/∞C
Gain Drift (Without Internal Reference) ± 50 ppm of FSR/∞C
Gain Drift (With Internal Reference) ± 100 ppm of FSR/∞C
Reference Voltage Drift ± 50 ppm/∞C

POWER SUPPLY

Supply Voltages

AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V

CLKVDD 2.7 3.3 3.6 V
Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation

4

5

Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD

)3336mA

AVDD

4

)

DVDD

)56mA

CLKVDD

)56mA

AVDD

6

6

–1 +1 % of FSR/V
–0.04 +0.04 % of FSR/V

OPERATING RANGE –40 +85 ∞C

NOTES

1

Measured at IOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4

Measured at f

5

Measured as unbuffered voltage output with I

6

± 5% power supply variation.

Specifications subject to change without notice.

= 25 MSPS and f

CLOCK

, is 32 times the I

OUTFS

OUT

= 1 MHz.

OUTFS

current.

REF

= 20 mA and 50 W R

at IOUTA and IOUTB, f

LOAD

CLOCK

= 20 mA, unless otherwise noted.)

OUTFS

100 nA

89mA

135 145 mW
145 mW

= 100 MSPS and f

= 40 MHz.

OUT

REV. A–2–

AD9744

(T

to T

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

transformer coupled output, 50  doubly terminated, unless otherwise noted.)

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I
Noise Spectral Density

OUTFS

OUTFS

= 20 mA)
= 2 mA)

3

2

) 165 MSPS

CLOCK

1

1

1

2

11 ns

2.5 ns

2.5 ns
50 pA/÷Hz
30 pA/÷Hz
–155 dBm/Hz

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

= 25 MSPS; f

f

CLOCK

= 1.00 MHz

OUT

0 dBFS Output 77 90 dBc
–6 dBFS Output 87 dBc
–12 dBFS Output 82 dBc
–18 dBFS Output 82 dBc

= 65 MSPS; f

f

CLOCK

f

= 65 MSPS; f

CLOCK

= 65 MSPS; f

f

CLOCK

= 65 MSPS; f

f

CLOCK

f

= 65 MSPS; f

CLOCK

= 165 MSPS; f

f

CLOCK

= 165 MSPS; f

f

CLOCK

= 1.00 MHz 85 dBc

OUT

= 2.51 MHz 84 dBc

OUT

= 10 MHz 80 dBc

OUT

= 15 MHz 75 dBc

OUT

= 25 MHz 74 dBc

OUT

= 21 MHz 73 dBc

OUT

= 41 MHz 60 dBc

OUT

Spurious-Free Dynamic Range within a Window

= 25 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

f

= 65 MSPS; f

CLOCK

= 125 MSPS; f

f

CLOCK

= 1.00 MHz; 2 MHz Span 84 90 dBc

OUT

= 5.02 MHz; 2 MHz Span 90 dBc

OUT

= 5.03 MHz; 2.5 MHz Span 87 dBc

OUT

= 5.04 MHz; 4 MHz Span 87 dBc

OUT

Total Harmonic Distortion

= 25 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 65 MSPS; f

f

CLOCK

f

= 125 MSPS; f

CLOCK

= 1.00 MHz –86 –77 dBc

OUT

= 2.00 MHz –77 dBc

OUT

= 2.00 MHz –77 dBc

OUT

= 2.00 MHz –77 dBc

OUT

Signal-to-Noise Ratio

= 65 MSPS; f

f

CLOCK

f

= 65 MSPS; f

CLOCK

= 125 MSPS; f

f

CLOCK

= 125 MSPS; f

f

CLOCK

f

= 165 MSPS; f

CLOCK

= 165 MSPS; f

f

CLOCK

= 5 MHz; I

OUT

= 5 MHz; I

OUT

= 5 MHz; I

OUT

= 5 MHz; I

OUT

= 5 MHz; I

OUT

= 5 MHz; I

OUT

= 20 mA 82 dB

OUTFS

= 5 mA 88 dB

OUTFS

= 20 mA 77 dB

OUTFS

= 5 mA 78 dB

OUTFS

= 20 mA 70 dB

OUTFS

= 5 mA 70 dB

OUTFS

Multitone Power Ratio (8 Tones at 400 kHz Spacing)

= 78 MSPS; f

f

CLOCK

= 15.0 MHz to 18.2 MHz

OUT

0 dBFS Output 66 dBc
–6 dBFS Output 68 dBc
–12 dBFS Output 62 dBc
–18 dBFS Output 61 dBc

NOTES

1

Measured single-ended into 50 W load.

2

Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.

3

Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.

Specifications subject to change without notice.

= 20 mA, differential

OUTFS

REV. A

–3–

AD9744

DIGITAL SPECIFICATIONS

(T

to T

MIN

, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I

MAX

= 20 mA, unless otherwise noted.)

OUTFS

Parameter Min Typ Max Unit

DIGITAL INPUTS

1

Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current –10 +10 mA
Logic 0 Current –10 +10 mA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t

CLK INPUTS

2

) 2.0 ns

S

) 1.5 ns

H

) 1.5 ns

LPW

Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V

NOTES

1

Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.

2

Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.

Specifications subject to change without notice.

DB0–DB13

CLOCK

IOUTA

OR

IOUTB

t

S

t

PD

0.1%

t

H

t

LPW

t

ST

0.1%

Figure 1. Timing Diagram

REV. A–4–

AD9744

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Unit

AVDD ACOM –0.3 +3.9 V

DVDD DCOM –0.3 +3.9 V

CLKVDD CLKCOM –0.3 +3.9 V

ACOM DCOM –0.3 +0.3 V

ACOM CLKCOM –0.3 +0.3 V

DCOM CLKCOM –0.3 +0.3 V

AVDD DVDD –3.9 +3.9 V

AVDD CLKVDD –3.9 +3.9 V

DVDD CLKVDD –3.9 +3.9 V

CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V

Digital Inputs, MODE DCOM –0.3 DVDD + 0.3 V

IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V

REFIO, REFLO, FS ADJ ACOM –0.3 AVDD + 0.3 V

CLK+, CLK–, CMODE CLKCOM –0.3 CLKVDD + 0.3 V

Junction Temperature 150 ∞C

Storage Temperature –65 +150 ∞C

Lead Temperature (10 sec) 300 ∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.

THERMAL CHARACTERISTICS* Thermal Resistance

28-Lead 300-Mil SOIC

␪

= 55.9∞C/W

JA

28-Lead TSSOP

= 67.7∞C/W

␪

JA

32-Lead LFCSP

= 32.5∞C/W

␪

JA

*Thermal impedance measurements were taken on a 4-layer board in still air,

in accordance with EIA/JESD51-7.

ORDERING GUIDE

Model Temperature Range Package Description Package Options*

AD9744AR –40∞C to +85∞C 28-Lead 300-Mil SOIC R-28
AD9744ARRL –40∞C to +85∞C 28-Lead 300-Mil SOIC R-28
AD9744ARU –40∞C to +85∞C 28-Lead TSSOP RU-28
AD9744ARURL7 –40∞C to +85∞C 28-Lead TSSOP RU-28
AD9744ACP –40∞C to +85∞C 32-Lead LFCSP CP-32
AD9744ACPRL7 –40∞C to +85∞C 32-Lead LFCSP CP-32
AD9744-EB Evaluation Board (SOIC)
AD9744ACP-PCB Evaluation Board (LFCSP)

*R = Small Outline IC; RU = Thin Shrink Small Outline Package; CP = Lead Frame Chip Scale Package

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD9744 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

REV. A

–5–

AD9744

28-Lead SOIC and TSSOP

PIN CONFIGURATION

32-Lead LFCSP

(MSB) DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

(LSB ) DB0

1

2

3

4

5

AD9744

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

13

14

NC = NO CONNECT

28

CLOCK

27

DVDD

26

DCOM

25

MODE

AVDD

24

23

RESERVED

22

IOUTA

21

IOUTB

20

ACOM

19

NC

FS ADJ

18

REFIO

17

REFLO

16

SLEEP

15

DB7 1
DB6 2

DVDD 3

DB5 4
DB4 5
DB3 6
DB2 7
DB1 8

32 DB8

31 DB9

30 DB10

29 DB11

28 DB12

PIN 1
INDICATOR

AD9744

TOP VIEW

CLK 12

CLK 13

DCOM 10

CLKVDD 11

(LSB) DB0 9

NC = NO CONNECT

27 DB13 (MSB)

26 DCOM

25 SLEEP

24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD

MODE 16

CMODE 15

CLKCOM 14

PIN FUNCTION DESCRIPTIONS

SOIC/TSSOP LFCSP
Pin No. Pin No. Mnemonic Description

127DB13 Most Significant Data Bit (MSB).
2–13 28–32, 1, 2, 4–8 DB12–DB1 Data Bits 12–1.
14 9 DB0 Least Significant Data Bit (LSB).
15 25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit;

it may be left unterminated if not used.

16 N/A REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to

disable internal reference.

17 23 REFIO Reference Input/Output. Serves as reference input when internal reference disabled

(i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal
reference activated (i.e., tie REFLO to ACOM). Requires 0.1 mF capacitor to

ACOM when internal reference activated.
18 24 FS ADJ Full-Scale Current Output Adjust.
19 N/A NC No Internal Connection.
20 19, 22 ACOM Analog Common.
21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 N/A RESERVED Reserved. Do Not Connect to Common or Supply.
24 17, 18 AVDD Analog Supply Voltage (3.3 V).
25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for

twos complement.
N/A 15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver

(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.

Float for PECL receiver (terminations on-chip).
26 10, 26 DCOM Digital Common.
27 3 DVDD Digital Supply Voltage (3.3 V).
28 N/A CLOCK Clock Input. Data latched on positive edge of clock.
N/A 12 CLK+ Differential Clock Input.
N/A 13 CLK– Differential Clock Input.
N/A 11 CLKVDD Clock Supply Voltage (3.3 V).
N/A 14 CLKCOM Clock Common.

REV. A–6–

AD9744

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (25∞C) value to the value at either T

MIN

or T

MAX

. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per ∞C. For reference drift, the drift is reported in
ppm per ∞C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic compo­nents to the rms value of the measured input signal. It is expressed
as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference between
the rms amplitude of a carrier tone to the peak spurious signal
in the region of a removed tone.

DVDD

DCOM

R

SET

2k

RETIMED

CLOCK

OUTPUT*

LECROY 9210

PULSE GENERATOR

3.3V

0.1F

3.3V

50

+1.2V REF

REFIO

FS ADJ

DVDD

DCOM

CLOCK

SLEEP

REFLO

SEGMENTED SWITCHES

FOR DB13–DB5

CLOCK

OUTPUT

150pF

LATCHES

DIGITAL

DATA

TEKTRONIX AWG-2021

WITH OPTION 4

AVDD ACOM

PMOS

CURRENT SOURCE

ARRAY

LSB

SWITCHES

AD9744

IOUTA

IOUTB

MODE

50

50

*AWG2021 CLOCK RETIMED
SO THAT THE DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

Figure 2. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages)

MINI-CIRCUITS

T1-1T

RHODE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER

REV. A

–7–

AD9744–Typical Performance Characteristics

95

90

85

80

65MSPS

75

70

65

SFDR (dBc)

60

55

50

45

125MSPS (LFCSP)

110

TPC 1. SFDR vs. f

90

85

80

75

70

65

60

SFDR (dBc)

–12dBFS

65

55

50

45

0102030

TPC 4. SFDR vs. f

125MSPS

165MSPS

f

(MHz)

OUT

OUT

–6dBFS (LFCSP)

0dBFS

–6dBFS

(MHz)

f

OUT

@ 165 MSPS

OUT

165MSPS (LFCSP)

@ 0 dBFS

100

–12dBFS (LFCSP)

0dBFS (LFCSP)

40 50 60

95

90

85

80

75

70

65

SFDR (dBc)

60

55

50

45

05 2510 15 20

TPC 2. SFDR vs. f

95

90

20mA

85

80

75

70

65

SFDR (dBc)

60

55

50

45

05 2510 15 20

TPC 5. SFDR vs. f

f

f

OUT

OUT

0dBFS

(MHz)

OUT

(MHz)

OUT

–6dBFS

@ 65 MSPS

and I

@ 65 MSPS and 0 dBFS

–12dBFS

10mA

5mA

OUTFS

95

90

85

80

75

70

65

SFDR (dBc)

60

55

50

45

05 4510 15 35

TPC 3. SFDR vs. f

95

90

85

80

75

70

65

SFDR (dBc)

60

55

50

45

–6dBFS

(MHz)

f

OUT

@ 125 MSPS

OUT

65MSPS

165MSPS

A

(dBFS)

OUT

–12dBFS

0dBFS

403020 25

125MSPS

TPC 6. Single-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/11

0–5–25 –10–15–20

OUT

95

90

85

80

75

70

65

SFDR (dBc)

60

55

50

45

–25 –20 –15 –10

65MSPS

125MSPS

165MSPS (LFCSP)

125MSPS (LFCSP)

A

(dBFS)

OUT

165MSPS

–5 0

TPC 7. Single-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/5

OUT

80

75

70

65

SNR (dB)

60

55

50

5mA SOIC

25 45 65 85

TPC 8. SNR vs. f
@ f

= 5 MHz and 0 dBFS

OUT

20mA SOIC

10mA LFCSP

105 125 145 165

(MSPS)

f

CLOCK

CLOCK

20mA LFCSP

10mA SOIC

5mA LFCSP

and I

OUTFS

95

65MSPS (8.3,10.3)

90

85

80

75

70

125MSPS (16.9, 18.9)

65

SFDR (dBc)

60

55

50

45

165MSPS (22.6, 24.6)

78MSPS (10.1, 12.1)

A

(dBFS)

OUT

TPC 9. Dual-Tone IMD vs. A
@ f

OUT

= f

CLOCK

/7

0–5–25 –10–15–20

OUT

REV. A–8–

AD9744

1.5

1.0

0.5

0

ERROR (LSB)

–0.5

–1.0

–1.5

4096 8192 12288 16384

0

CODE

TPC 10. Typical INL

0

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE (dBm)

–80

–90

–100

16 2611 16 21

f

CLOCK

f

= 15.0MHz

OUT

SFDR = 79dBc
AMPLITUDE = 0dBFS

FREQUENCY (MHz)

TPC 13. Single-Tone SFDR

= 78MSPS

1.0

0.8

0.6

0.4

0.2

0

–0.2

ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 4096

8192 12288 16384

CODE

TPC 11. Typical DNL

95

90

85

80

75

70

65

SFDR (dBc)

34MHz

60

55

50

45

–40 –20 6002040

4MHz

19MHz

49MHz

TEMPERATURE (C)

TPC 12. SFDR vs. Temperature

80

@ 165 MSPS, 0 dBFS

0

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE (dBm)

–80

–90

31

36

–100

16 2611 16 21

f

= 78MSPS

CLOCK

f

= 15.0MHz

OUT1

f

= 15.4MHz

OUT2

SFDR = 77dBc
AMPLITUDE = 0dBFS

FREQUENCY (MHz)

31

36

TPC 14. Dual-Tone SFDR

0

–10

–20

–30

–40

–50

–60

–70

MAGNITUDE (dBm)

–80

–90

–100

16 2611 16 21

f
f
f
f
f

SFDR = 75dBc
AMPLITUDE = 0dBFS

FREQUENCY (MHz)

TPC 15. Four-Tone SFDR

CLOCK

OUT1

OUT2

OUT3

OUT4

= 78MSPS

= 15.0MHz

= 15.4MHz

= 15.8MHz

= 16.2MHz

31

36

–20

–30

–40

–50

–60

–70

–80

–90

MAGNITUDE (dBm)

C12

–100

–110

–120

CENTER 33.22MHz

C12

C0

C11

C11

3MHz SPAN 30MHz

C0

CU1

TPC 16. Two-Carrier UMTS
Spectrum (ACLR = 64 dB)

–39.01dBm

29.38000000MHz

CH PWR –19.26dBm

ACP UP –64.98dB
ACP L OW +0.55dB
ALT1 UP –66.26dB

ALT1 LOW –64.23dB

CU1

CU2

CU2

REV. A

–9–

AD9744

150pF

+1.2V REF

AVDDREFLO

CURRENT

SOURCE

ARRAY

3.3V

REFIO

FS ADJ

R

SET

AD9744

EXTERNAL

REF

I

REF

=

V

REFIO/RSET

AVDD

REFERENCE
CONTROL
AMPLIFIER

V

REFIO

3.3V

0.1F

V

REFIO

R

CLOCK

SET

2k

I

REF

3.3V

REFIO

FS ADJ

DVDD

DCOM

CLOCK

SLEEP

REFLO

+1.2V REF

SEGMENTED SWITCHES

150pF

CURRENT SOURCE

FOR DB13–DB5

LATCHES

DIGITAL DATA INPUTS (DB13–DB0)

Figure 3. Simplified Block Diagram (SOIC/TSSOP Packages)

FUNCTIONAL DESCRIPTION

Figure 3 shows a simplified block diagram of the AD9744. The
AD9744 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I

). The array is divided into 31 equal currents

OUTFS

that make up the five most significant bits (MSBs). The next
four bits, or middle bits, consist of 15 equal current sources
whose value is 1/16th of an MSB current source. The remaining
LSBs are binary weighted fractions of the middle bits current
sources. Implementing the middle and lower bits with current
sources, instead of an R-2R ladder, enhances its dynamic per­formance for multitone or low amplitude signals and helps
maintain the DAC’s high output impedance (i.e., >100 kW).

All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces vari­ous timing errors and provides matching complementary drive
signals to the inputs of the differential current switches.

The analog and digital sections of the AD9744 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 165 MSPS, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the asso­ciated differential switches, a 1.2 V band gap voltage reference,
and a reference control amplifier.

The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R

, connected to the full-scale adjust (FS ADJ)

SET

pin. The external resistor, in combination with both the refer­ence control amplifier and voltage reference V
reference current I

, which is replicated to the segmented

REF

REFIO

, sets the

current sources with the proper scaling factor. The full-scale
current, I

, is 32 times I

OUTFS

REF

.

AVDD ACOM

AD9744

PMOS

ARRAY

SWITCHES

LSB

IOUTA

IOUTB

MODE

IOUTB



IOUTA

V

= V

OUTB

LOAD

OUTA

– V

V

R
50

OUTB

OUTA

LOAD

DIFF

V

R

50

REFERENCE OPERATION

The AD9744 contains an internal 1.2 V band gap reference. The
internal reference can be disabled by raising REFLO to AVDD.
It can also be easily overridden by an external reference with no
effect on performance. REFIO serves as either an input or an
output depending on whether the internal or an external reference
is used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1 mF capacitor and connect REFLO to
ACOM via a resistance less than 5 W. The internal reference volt­age will be present at REFIO. If the voltage at REFIO is to be
used anywhere else in the circuit, an external buffer amplifier with
an input bias current of less than 100 nA should be used. An
example of the use of the internal reference is shown in Figure 4.

3.3V

AVDD

CURRENT

SOURCE

ARRAY

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

0.1F

2k

+1.2V REF

REFIO

FS ADJ

AD9744

REFLO

150pF

Figure 4. Internal Reference Configuration

An external reference can be applied to REFIO, as shown in
Figure 5. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 mF
compensation capacitor is not required since the internal refer­ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.

Figure 5. External Reference Configuration

REV. A–10–

AD9744

REFERENCE CONTROL AMPLIFIER

The AD9744 contains a control amplifier that is used to regu­late the full-scale output current, I

. The control amplifier

OUTFS

is configured as a V-I converter, as shown in Figure 4, so that its
current output, I
and an external resistor, R

, is determined by the ratio of the V

REF

, as stated in Equation 4. I

SET

REFIO

REF

is
copied to the segmented current sources with the proper scale
factor to set I

as stated in Equation 3.

OUTFS,

The control amplifier allows a wide (10:1) adjustment span of
I

over a 2 mA to 20 mA range by setting I

OUTFS

62.5 mA and 625 mA. The wide adjustment span of I

between

REF

OUTFS

pro­vides several benefits. The first relates directly to the power
dissipation of the AD9744, which is proportional to I

OUTFS

(refer to the Power Dissipation section). The second relates to
the 20 dB adjustment, which is useful for system gain control
purposes.

The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.

DAC TRANSFER FUNCTION

Both DACs in the AD9744 provide complementary current
outputs, IOUTA and IOUTB. IOUTA provides a near full­scale current output, I

, when all bits are high (i.e., DAC

OUTFS

CODE = 16383), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA
and IOUTB is a function of both the input code and I

OUTFS

and

can be expressed as

IOUTA DAC CODE I

IOUTB DAC CODE I

=

()

=

()

¥/ 16384

OUTFS

¥16383 16384–/

OUTFS

(1)

(2)

where DAC CODE = 0 to 16383 (i.e., decimal representation).

As mentioned previously, I
current I

V

REFIO

, which is nominally set by a reference voltage,

REF

, and external resistor, R

II

=¥32

OUTFS REF

is a function of the reference

OUTFS

. It can be expressed as

SET

(3)

where

IV R

= /

REF REFIO SET

(4)

The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
that R

, that are tied to analog common, ACOM. Note

LOAD

may represent the equivalent load resistance seen by

LOAD

IOUTA or IOUTB as would be the case in a doubly terminated
50 W or 75 W cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply

V IOUTA R

=¥

OUTA LOAD

V IOUTB R

=¥

OUTB LOAD

Note that the full-scale value of V

OUTA

and V

should not

OUTB

(5)

(6)

exceed the specified output compliance range to maintain speci­fied distortion and linearity performance.

V IOUTA IOUTB R

=

()

DIFF LOAD

¥–

(7)

Substituting the values of IOUTA, IOUTB, I

REF

, and V

DIFF

can

be expressed as

V DAC CODE

DIFF

32

()

2 16383 16384

=¥

()

{}

¥

/

RRV

LOAD SET REFIO

–/

(8)

¥

Equations 7 and 8 highlight some of the advantages of operating
the AD9744 differentially. First, the differential operation helps
cancel common-mode error sources associated with IOUTA and
IOUTB, such as noise, distortion, and dc offsets. Second, the
differential code dependent current and subsequent voltage, V
is twice the value of the single-ended voltage output (i.e., V
or V

), thus providing twice the signal power to the load.

OUTB

DIFF

OUTA

,

Note that the gain drift temperature performance for a single­ended (V

OUTA

and V

) or differential output (V

OUTB

DIFF

) of the
AD9744 can be enhanced by selecting temperature tracking
resistors for R

LOAD

and R

due to their ratiometric relation-

SET

ship, as shown in Equation 8.

ANALOG OUTPUTS

The complementary current outputs in each DAC, IOUTA,
and IOUTB may be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into comple­mentary single-ended voltage outputs, V
load resistor, R

, as described in the DAC Transfer Func-

LOAD

OUTA

and V

OUTB

, via a

tion section by Equations 5 through 8. The differential voltage,

, existing between V

V

DIFF

OUTA

and V

, can also be con-

OUTB

verted to a single-ended voltage via a transformer or differential
amplifier configuration. The ac performance of the AD9744 is
optimum and specified using a differential transformer-coupled
output in which the voltage swing at IOUTA and IOUTB is
limited to ± 0.5 V.

The distortion and noise performance of the AD9744 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi­cant as the frequency content of the reconstructed waveform
increases and/or its amplitude decreases. This is due to the first
order cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise.

Performing a differential-to-single-ended conversion via a trans­former also provides the ability to deliver twice the reconstructed
signal power to the load (assuming no source termination).
Since the output currents of IOUTA and IOUTB are comple­mentary, they become additive when processed differentially. A
properly selected transformer will allow the AD9744 to provide
the required power and voltage levels to different loads.

The output impedance of IOUTA and IOUTB is determined by
the equivalent parallel combination of the PMOS switches asso­ciated with the current sources and is typically 100 kW in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., V

OUTA

and V

) due to the nature of a PMOS device.

OUTB

As a result, maintaining IOUTA and/or IOUTB at a virtual
ground via an I-V op amp configuration will result in the opti­mum dc linearity. Note that the INL/DNL specifications for the
AD9744 are measured with IOUTA maintained at a virtual
ground via an op amp.

REV. A

–11–

AD9744

IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9744.

The positive output compliance range is slightly dependent on the
full-scale output current, I
nominal 1.2 V for an I

OUTFS

. It degrades slightly from its

OUTFS

= 20 mA to 1 V for an I

OUTFS

=
2 mA. The optimum distortion performance for a single­ended or differential output is achieved when the maximum
full-scale signal at IOUTA and IOUTB does not exceed 0.5 V.

DIGITAL INPUTS

The AD9744 digital section consists of 14 input bit channels
and a clock input. The 14-bit parallel data inputs follow stan­dard positive binary coding, where DB13 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.

DVDD

DIGITAL

INPUT

Figure 6. Equivalent Digital Input

The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
165 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.

LFCSP Package

A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes. The
mode selection is controlled by the CMODE input, as summa­rized in Table I. Connecting CMODE to CLKCOM selects the
single-ended clock input. In this mode, the CLK+ input is driven
with rail-to-rail swings and the CLK– input is left floating. If
CMODE is connected to CLKVDD, the differential receiver
mode is selected. In this mode, both inputs are high impedance.
The final mode is selected by floating CMODE. This mode is
also differential, but internal terminations for positive emitter­coupled logic (PECL) are activated. There is no significant
performance difference among any of the three clock input modes.

Table I. Clock Mode Selection

CMODE Pin Clock Input Mode

CLKCOM Single-Ended
CLKVDD Differential
Float PECL

The single-ended input mode operates in the same way as the
CLOCK input in the 28-lead packages, as described previously.

In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK– inputs can vary from 0.75 V to 2.25 V,
and the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.

The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 7. These termination resistors are untrimmed and can
vary up to ± 20%. However, matching between the resistors
should generally be better than ±1%

CLK+

CLK–

50⍀ 50⍀

AD9744

CLOCK
RECEIVER

TO DAC CORE

CLOCK INPUT
SOIC/TSSOP Packages

The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock qual­ity, and jitter is a key concern. Any noise or jitter in the clock
will translate directly into the DAC output. Optimal perfor­mance will be achieved if the CLOCK input has a sharp rising
edge, since the DAC latches are positive edge triggered.

V

= 1.3V NOM

TT

Figure 7. Clock Termination in PECL Mode

DAC TIMING
Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the relation­ship between the position of the clock edges and the time at

REV. A–12–

AD9744

50 100 150

0

1

2

3

4

5

6

7

8

9

10

f

CLOCK

(MSPS)

I

CLKVDD

(

mA)

2000

DIFF

PECL

SE

which the input data changes. The AD9744 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when apply­ing the AD9744 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 8 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement, while
at higher rates, more care must be taken.

75

70

65

60

55

dB

50

45

40

50MHz SFDR

35

–3 –2 2–1 0 1

Figure 8. SFDR vs. Clock Placement @ f

20MHz SFDR

ns

50MHz SFDR

= 20 MHz

OUT

3

and 50 MHz

Sleep Mode Operation

The AD9744 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and tempera­ture range. This mode can be activated by applying a logic level
1 to the SLEEP pin. The SLEEP pin logic threshold is equal to

0.5 ¥ AVDD. This digital input also contains an active pull­down circuit that ensures that the AD9744 remains enabled if
this input is left disconnected. The AD9744 takes less than
50 ns to power down and approximately 5 ms to power back up.

35

30

25

(mA)

20

AVD D

I

15

10

0

2

4681012 14 16 18 20

Figure 9. I

16

14

12

10

(mA)

8

DVDD

I

6

4

2

0

0.01 10.1

Figure 10. I

RATIO (

vs. Ratio @ DVDD = 3.3 V

DVDD

I

(mA)

OUTFS

vs. I

AVDD

165MSPS

125MSPS

65MSPS

f

OUT

/

f

CLOCK

OUTFS

)

POWER DISSIPATION

The power dissipation, PD, of the AD9744 is dependent on
several factors that include:

∑ The power supply voltages (AVDD, CLKVDD, and DVDD)
∑ The full-scale current output I
∑ The update rate f

CLOCK

OUTFS

∑ The reconstructed digital input waveform

The power dissipation is directly proportional to the analog
supply current, I

is directly proportional to I

I

AVDD

and is insensitive to f
both the digital input waveform, f
DVDD. Figure 10 shows I
wave output ratios (f
DVDD = 3.3 V.

REV. A

, and the digital supply current, I

AVDD

CLOCK

OUT/fCLOCK

. Conversely, I

as a function of full-scale sine

DVDD

) for various update rates with

, as shown in Figure 9,

OUTFS

CLOCK

is dependent on

DVDD

, and digital supply

DVDD

.

–13–

Figure 11. I

CLKVDD

vs. f

and Clock Mode

CLOCK

AD9744

APPLYING THE AD9744
Output Configurations

The following sections illustrate some typical output configura­tions for the AD9744. Unless otherwise noted, it is assumed
that I

is set to a nominal 20 mA. For applications requir-

OUTFS

ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti­mum high frequency performance and is recommended for any
application that allows ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling,
a bipolar output, signal gain, and/or level shifting within the
bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, R

, referred to ACOM. This configura-

LOAD

tion may be more suitable for a single-supply system requiring a
dc-coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus convert­ing IOUTA or IOUTB into a negative unipolar voltage. This
configuration provides the best dc linearity since IOUTA or
IOUTB is maintained at a virtual ground.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-single­ended signal conversion, as shown in Figure 12. A differentially
coupled transformer output provides the optimum distortion
performance for output signals whose spectral content lies within
the transformer’s pass band. An RF transformer, such as the
Mini-Circuits T1–1T, provides excellent rejection of common­mode distortion (i.e., even-order harmonics) and noise over a
wide frequency range. It also provides electrical isolation and the
ability to deliver twice the power to the load. Transformers with
different impedance ratios may also be used for impedance match­ing purposes. Note that the transformer provides ac coupling only.

MINI-CIRCUITS

IOUTA

AD9744

IOUTB

22

21

T1-1T

OPTIONAL R

DIFF

R

LOAD

Figure 12. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., V

OUTA

and V

OUTB

)
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9744. A
differential resistor, R
the output of the transformer is connected to the load, R
via a passive reconstruction filter or cable. R

, may be inserted in applications where

DIFF

is determined

DIFF

LOAD

,

by the transformer’s impedance ratio and provides the proper
source termination that results in a low VSWR. Note that approxi­mately half the signal power will be dissipated across R

DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-single­ended conversion, as shown in Figure 13. The AD9744 is
configured with two equal load resistors, R

, of 25 W. The

LOAD

differential voltage developed across IOUTA and IOUTB is conver­ted to a single-ended signal via the differential op amp configuration.
An optional capacitor can be installed across IOUTA and IOUTB,
forming a real pole in a low-pass filter. The addition of this
capacitor also enhances the op amp’s distortion performance by
preventing the DAC’s high slewing output from overloading the
op amp’s input.

500

AD9744

IOUTA

IOUTB

22

21

C

OPT

225

225

2525

AD8047

500

Figure 13. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ­ential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off a dual
supply since its output is approximately ± 1 V. A high speed
amplifier capable of preserving the differential performance of the
AD9744 while meeting other system level objectives (e.g., cost
or power) should be selected. The op amp’s differential gain, gain
setting resistor values, and full-scale output swing capabilities
should all be considered when optimizing this circuit.

The differential circuit shown in Figure 14 provides the neces­sary level shifting required in a single-supply system. In this case,
AVDD, which is the positive analog supply for both the AD9744
and the op amp, is also used to level-shift the differential output
of the AD9744 to midsupply (i.e., AVDD/2). The AD8041 is a
suitable op amp for this application.

500

AD9744

IOUTA

IOUTB

22

21

C

OPT

225

1k

AD8041

1k

AVDD

225

2525

Figure 14. Single Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 15 shows the AD9744 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly termi­nated 50 W cable since the nominal full-scale current, I
20 mA flows through the equivalent R

represents the equivalent load resistance seen by IOUTA

R

LOAD

of 25 W. In this case,

LOAD

OUTFS

, of

or IOUTB. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching R

LOAD

. Different

REV. A–14–

AD9744

FREQUENCY (MHz)

85

40

1260

PSRR (dB)

80

75

70

65

60

55

50

24 810

45

values of I

OUTFS

and R

can be selected as long as the positive

LOAD

compliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL), discussed in the
Analog Output section. For optimum INL performance, the
single-ended, buffered voltage output configuration is suggested.

AD9744

IOUTA

IOUTB

I

= 20mA

OUTFS

22

50

21

25

V

OUTA

= 0V TO 0.5V

50

Figure 15. 0 V to 0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION

Figure 16 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9744
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, minimizing the nonlinear output impedance effect on
the DAC’s INL performance as described in the Analog Output
section. Although this single-ended configuration typically provides
the best dc linearity performance, its ac distortion performance
at higher DAC update rates may be limited by U1’s slew rate
capabilities. U1 provides a negative unipolar output voltage, and
its full-scale output voltage is simply the product of R
I

. The full-scale output should be set within U1’s voltage

OUTFS

output swing capabilities by scaling I

and/or RFB. An

OUTFS

FB

and

improvement in ac distortion performance may result with a
reduced I

since the signal current U1 will be required to

OUTFS

sink less signal current.

C

OPT

R

FB

200

U1

V

= I

OUTFS

 R

FB

OUT

AD9744

IOUTA

IOUTB

I

= 10mA

OUTFS

22

21

200

Figure 16. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION

Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit board
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum per­formance. Figures 21 to 24 illustrate the recommended printed
circuit board ground, power, and signal plane layouts implemented
on the AD9744 evaluation board.

One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.

REV. A

–15–

This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated
with the DAC’s full-scale current, I

. AC noise on the dc

OUTFS

supplies is common in applications where the power distribution
is generated by a switching power supply. Typically, switching
power supply noise will occur over the spectrum from tens of
kHz to several MHz. The PSRR versus frequency of the AD9744
AVDD supply over this frequency range is shown in Figure 17.

Figure 17. Power Supply Rejection Ratio (PSRR)

Note that the ratio in Figure 17 is calculated as amps out/volts in.
Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative different size
of these switches, the PSRR is very code dependent. This can
produce a mixing effect that can modulate low frequency power
supply noise to higher frequencies. Worst-case PSRR for either
one of the differential DAC outputs will occur when the full-scale
current is directed toward that output. As a result, the PSRR
measurement in Figure 17 represents a worst-case condition in
which the digital inputs remain static and the full-scale output
current of 20 mA is directed to the DAC output being measured.

An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switch­ing frequency of 250 kHz produces 10 mV of noise and, for
simplicity’s sake (ignoring harmonics), all of this noise is con­centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise superimposed on the DAC’s
full-scale current, I

, one must determine the PSRR in dB

OUTFS

using Figure 17 at 250 kHz. To calculate the PSRR for a given

, such that the units of PSRR are converted from A/V to

R

LOAD

V/V, adjust the curve in Figure 17 by the scaling factor 20 ¥ log

). For instance, if R

(R

LOAD

is 50 W, the PSRR is reduced by

LOAD

34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 17, becomes 51 dB V

OUT/VIN

).

Proper grounding and decoupling should be a primary objec­tive in any high speed, high resolution system. The AD9744
features separate analog and digital supplies and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, AVDD, the analog supply, should be
decoupled to ACOM, the analog common, as close to the chip

AD9744

as physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close to the chip as physically possible.

For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 18. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.

FERRITE

BEADS

TTL/CMOS

LOGIC

CIRCUITS

100F
ELECT.

10F–22F
TANT.

0.1F
CER.

AVDD

ACOM

3.3V

POWER SUPPLY

Figure 18. Differential LC Filter for Single 3.3 V Applications

J1

21

4

3
65
87

10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39

RIBBON

JP3

DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X

CKEXTX

DB13X
DB12X
DB11X
DB10X

DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X

CKEXTX

DCOM

2R13R24R35R46R57R68R79

1

EVALUATION BOARD
General Description

The TxDAC family evaluation boards allow for easy setup and
testing of any TxDAC product in the SOIC and LFCSP
packages. Careful attention to layout and circuit design, com­bined with a prototyping area, allows the user to evaluate the
AD9744 easily and effectively in any application where high
resolution, high speed conversion is required.

This board allows the user the flexibility to operate the AD9744
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single and differ­ential outputs. The digital inputs are designed to be driven from
various word generators, with the on-board option to add a
resistor network for proper load termination. Provisions are also
made to operate the AD9744 with either the internal or external
reference or to exercise the power-down feature.

RP5

R9

R8

OPT

10

RP3 22

RP3 22

RP3 22

3

RP3 22

4

RP3 22

5

RP3 22

6

RP3 22

7

RP3 22

8

RP4 22

1

RP4 22

2

RP4 22

3

RP4 22

4

RP4 22

5

RP4 22

6

RP4 22

7

RP4 22

8

DCOM

1

161

152

14

13

12

11

10

9

16

15

14

13

12

11

10

9

2R13R24R35R46R57R68R79

RP1

R9

R8

OPT

10

DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0

CKEXT

TB1 1

TB1 2

TB1 3

TB1 4

C7

0.1F

C9

0.1F

L2 BEAD

BLK

TP4

L3 BEAD

BLK

TP6

+

+

C4
10F
25V

C5
10F
25V

RED

RED

TP2

TP5

C6

0.1F

C8

0.1F

DVD D

BLK BLK

AV DD

BLK BLK

TP7

TP10

TP8

TP9

1

DCOM

2

3

5

6

9

4

R3

R1

R2

8

7

10

RP6

R7

R5

R4

R9

R8

R6

OPT

1

DCOM

2

3

R1

R2

Figure 19. SOIC Evaluation Board—Power Supply and Digital Inputs

5

6

9

4

R3

8

7

10

RP2

R7

R5

R4

R9

R8

R6

OPT

REV. A–16–

AD9744

AV DD

DVD D

CKEXT

DB13
DB12
DB11
DB10

DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0

AV DD

CLOCK

DVD D

AV DD

R3
10k



CUT

UNDER DUT

JP6

R5
OPT

TP1
WHT

REF

R1
2k



DVD D

R4
50

TP3
WHT

C11

0.1F



CLOCK

AV DD

S5

C1

0.1F

R2
10k

DVD D



JP2

MODE

C2

0.1F

JP10

IOUTA

OPT

S1

1

S2

R6

1

IX

IOUTB

IY

A

B

2

2

AB
JP11

C13

OPT

OPT

C12

3

R11

50



JP8

T1

T1-1T

JP9

4

5

6

3

2

1

R10
50



3

IOUT

S3

C14

+

+

1

2

3

4

5

6

7

8

9

10
11
12
13
14

10F
16V

C15
10F
16V

DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0

1

EXT

C16

0.1F

C18

0.1F

AD9744

2

AB
JP5

REF

JP4

RESERVED

U1

3

INT

C17

0.1F

C19

0.1F

CLOCK

DVD D
DCOM
MODE

AV DD

IOUTA
IOUTB
ACOM

NC

FS ADJ

REFIO

REFLO
SLEEP

SLEEP

TP11
WHT

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Figure 20. SOIC Evaluation Board—Output Signal Conditioning

REV. A

–17–

AD9744

Figure 21. SOIC Evaluation Board–Primary Side

Figure 22. SOIC Evaluation Board—Secondary Side

REV. A–18–

AD9744

Figure 23. SOIC Evaluation Board–Ground Plane

REV. A

Figure 24. SOIC Evaluation Board—Power Plane

–19–

AD9744

Figure 25. SOIC Evaluation Board Assembly—Primary Side

Figure 26. SOIC Evaluation Board Assembly—Secondary Side

REV. A–20–

AD9744

X

TB1 1

TB1 2

TB3 1

TB3 2

TB4 1

TB4 2

C3

0.1F

C7

0.1F

C9

0.1F

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

CKEXTX

L1

BLK

L2

BLK

L3

BLK

R3
100

BEAD

TP2

BEAD

TP4

BEAD

TP6

R4
100

C2
10F

6.3V

C4
10F

6.3V

C5
10F

6.3V

R15
100

RED

RED

RED

TP12

TP13

TP5

R16
100

C10

0.1F

C6

0.1F

C8

0.1F

R17
100

CVDD

DVDD

AVDD

R18
100

R19
100

R20
100

1 RP3

2 RP3

3 RP3

4 RP3

5 RP3

6 RP3

7 RP3

8 RP3

1 RP4

2 RP4

3 RP4

4 RP4

5 RP4

6 RP4
7 RP4

8 RP4

2
4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38
40

22 16

22 15

22 14

22 13

22 12

22 11

22 10

22 9

22 16

22 15

22 14

22 13

22 12

22 11
22 10

22 9

1
3

5

7

9

11

13

15

17

19

21

23

25

27

29

31
33

35

HEADER STRAIGHT UP MALE NO SHROUD

37
39

J1

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

JP3

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CKEXT

CKEXT

REV. A

R21

R24

R25

R26

R27

100

100

100

100

100

R28
100

Figure 27. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs

–21–

AD9744

CMODE

TP7

WHT

MODE

DB7

DB6

DVDD

DB5

DB4

DB3

DB2

DB1

DB0

CVDD

CLK

CLKB

10

11
12

13

14

15

16

1

2

3

4

5

6

7

8

9

DB7

DB6

DVDD
DB5

DB4

DB3

DB2

DB1

DB0

DCOM

CVDD

CLK

CLKB

CCOM

CMODE

MODE

R30
10k⍀

DB10
DB11

DB12

DB13

DCOM1

SLEEP

FS ADJ

REFIO

U1

ACOM

ACOM1

AVDD

AVDD1

AD9744LFCSP

CVDD

JP1

DB8

DB9

SLEEP

TP11
WHT

R29

32

DB8

31

DB9

30

DB10

29

DB11

28

DB12

27

DB13

26

25

24

23

22

21

IA

20

IB

19

18

17

AVDD

10k⍀

TP3

WHT

C11

0.1␮F

TP1

WHT

R1
2k⍀

0.1%

C17

0.1␮F

DVDD CVDDAVDD

DNP
C13

DNP
C12

C19

0.1␮F

R11
50⍀

JP8

3

2

1

T1–1T

JP9

R10
50⍀

4

T1

5

6

IOUT

S3
AGND: 3, 4, 5

C32

0.1␮F

Figure 28. LFCSP Evaluation Board Schematic—Output Signal Conditioning

C20
10␮F
16V

CVDD

CLKB

CKEXT

CLK

JP2

7

3

U4

4

AGND: 5
CVDD: 8

U4

AGND: 5
CVDD: 8

6

1

2

CVDD

R5
120⍀

C34

0.1␮F

R2
120⍀

Figure 29. LFCSP Evaluation Board Schematic—Clock Input

R6
50⍀

C35

0.1␮F

S5
AGND: 3, 4, 5

REV. A–22–

AD9744

Figure 30. LFCSP Evaluation Board Layout—Primary Side

REV. A

Figure 31. LFCSP Evaluation Board Layout—Secondary Side

–23–

AD9744

Figure 32. LFCSP Evaluation Board Layout—Ground Plane

Figure 33. LFCSP Evaluation Board Layout—Power Plane

REV. A–24–

AD9744

Figure 34. LFCSP Evaluation Board Layout Assembly—Primary Side

REV. A

Figure 35. LFCSP Evaluation Board Layout Assembly—Secondary Side

–25–

AD9744

OUTLINE DIMENSIONS

28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

9.80

9.70

9.60

28

PIN 1

0.15

0.05

COPLANARITY

0.10

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AE

15

141

SEATING
PLANE

1.20

MAX

4.50

4.40

4.30

0.20

0.09

6.40 BSC

28-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-28)

Dimensions shown in millimeters and (inches)

18.10 (0.7126)

17.70 (0.6969)

28 15

1

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

1.27 (0.0500)

COMPLIANT TO JEDEC STANDARDS MS-013AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

0.51 (0.0201)

0.33 (0.0130)

14

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.32 (0.0126)

0.23 (0.0091)

8
0

0.75 (0.0295)

0.25 (0.0098)

8
0

0.75

0.60

0.45

1.27 (0.0500)

0.40 (0.0157)

 45

PIN 1

INDICATOR

32-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-32)

Dimensions shown in millimeters

1.00

0.90

0.80

12 MAX

SEATING
PLANE

5.00

BSC SQ

0.30

0.23

0.18

4.75

BSC SQ

0.20 REF

TOP

VIEW

1.00 MAX

0.65 NOM

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50
BSC

0.50

0.40

0.30

0.08

25

24

17

16

0.60 MAX

BOTTOM

VIEW

3.50
REF

PIN 1

32

INDICATOR

1

3.25

3.10

SQ

2.95

8

9

REV. A–26–

AD9744

Revision History

Location Page

5/03—Data Sheet changed from REV. 0 to REV. A.

Added 32-Lead LFCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Edits to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Replaced TPCs 1, 4, 7, and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edits to FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Added CLOCK INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Added new Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to DAC TIMING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to Sleep Mode Operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Edits to POWER DISSIPATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Renumbered Figures 8–26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Added Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Added Figures 27–35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

REV. A

–27–

C02913–0–5/03(A)

–28–