Datasheet AD9743 Datasheet (ANALOG DEVICES)

Dual 8-/10-/12-/14-/16-Bit

250 MSPS Digital-to-Analog Converters

AD9741/AD9743/AD9745/AD9746/AD9747

FEATURES

High dynamic range, dual DACs Low noise and intermodulation distortion Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits useable outputs

beyond Nyquist frequency

LVCMOS inputs with dual-port or optional interleaved

single-port operation

Differential analog current outputs are programmable from

8.6 mA to 31.7 mA full scale

Auxiliary 10-bit current DACs with source/sink capability for

external offset nulling Internal 1.2 V precision reference voltage source Operates from 1.8 V and 3.3 V supplies 315 mW power dissipation Small footprint, Pb-free, 72-Lead LFCSP

APPLICATIONS

Wireless infrastructure:

WCDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications:

LMDS/MMDS, point-to-point Instrumentation:

RF signal generators, arbitrary waveform generators

GENERAL DESCRIPTION

The AD9741/AD9743/AD9745/AD9746/AD9747 are pincompatible, high dynamic range, dual digital-to-analog converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions and sample rates of up to 250 MSPS. The devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators, such as the ADL5370.

A proprietary, dynamic output architecture permits synthesis of analog outputs even above Nyquist by shifting energy away from the fundamental and into the image frequency.

Full programmability is provided through a serial peripheral interface (SPI) port. In addition, some pin-programmable features are offered for those applications without a controller.

PRODUCT HIGHLIGHTS

1. Low noise and intermodulation distortion (IMD) enables

high quality synthesis of wideband signals.

2. Proprietary switching output for enhanced dynamic

performance.

3. Programmable current outputs and dual auxiliary DACs

provide flexibility and system enhancements.

FUNCTIONAL BLOCK DIAGRAM

CLKP

CLKN

PID<15:0>

CMOS

INTERFACE

P2D<15:0>

SERIAL

PERIPHERAL

INTERFACE

SDO

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

INTERFACE L OGIC

CSB

SDIO

SCLK

INTERNAL

REFERENCE

AND BIAS

REFIO

10

FSADJ

Figure 1.

16-BIT

DAC1

16-BIT

DAC2

GAIN

DAC

GAIN

DAC

OFFSET

DAC

OFFSET

DAC

IOUT1P

IOUT1N

IOUT2P

IOUT2N

AUX1P

AUX1N

AUX2P

AUX2N

06569-001

AD9741/AD9743/AD9745/AD9746/AD9747

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

sample rate, unless otherwise noted.

Table 1. AD9741, AD9743, and AD9745

Parameter

RESOLUTION 8 10 12 Bits ACCURACY

Differential Nonlinearity (DNL) ±0.03 ±0.05 ±0.13 LSB Integral Nonlinearity (INL) ±0.05 ±0.10 ±0.25 LSB

MAIN DAC OUTPUTS

Offset Error ±0.001 ±0.001 ±0.001 %FSR Offset Error Temperature Coefficient 1.0 1.0 1.0 ppm/°C Gain Error ±2.0 ±2.0 ±2.0 %FSR Gain Error Temperature Coefficient 100 100 100 ppm/°C Gain Matching (DAC1 to DAC2) ±1.0 ±1.0 ±1.0 %FSR Full-Scale Output Current 8.6 31.7 8.6 31.7 8.6 31.7 mA Output Compliance Voltage −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V Output Resistance 10 10 10 MΩ

AUXILIARY DAC OUTPUTS

Resolution 10 10 10 Bits Full-Scale Output Current −2.0 +2.0 −2.0 +2.0 −2.0 +2.0 mA Output Compliance Voltage Range—Sink Current 0.8 1.6 0.8 1.6 0.8 1.6 V Output Compliance Voltage Range—Source Current 0 1.6 0 1.6 0 1.6 V Output Resistance 1 1 1 MΩ Monotonicity 10 10 10 Bits

REFERENCE INPUT/OUTPUT

Output Voltage 1.2 1.2 1.2 V Output Voltage Temperature Coefficient 10 10 10 ppm/°C External Input Voltage Range 1.15 1.3 1.15 1.3 1.15 1.3 V Input or Output Resistance 5 5 5 kΩ

POWER SUPPLY VOLTAGES

AVDD33, DVDD33 3.13 3.47 3.13 3.47 3.13 3.47 V CVDD18, DVDD18 1.70 1.90 1.70 1.90 1.70 1.90 V

POWER SUPPLY CURRENTS

I

AVDD33

I

DVDD33

I

CVDD18

I

DVDD18

POWER DISSIPATION

f

DAC

DAC Outputs Disabled 115 115 120 mW Full Device Power-Down 3 3 3 mW

OPERATING TEMPERATURE −40 +85 −40 +85 −40 +85 °C

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum

MAX

AD9741 AD9743 AD9745

Min Typ Max Min Typ Max Min Typ Max

Unit

56 60 56 60 56 60 mA 10 14 10 14 11 15 mA 18 22 18 22 18 22 mA 28 32 29 33 30 34 mA

= 250 MSPS, f

= 20 MHz 300 345 300 345 305 350 mW

OUT

Rev. 0 | Page 3 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

T

to T

MIN

sample rate, unless otherwise noted. The AD9745 is repeated in

Table 2. AD9745, AD9746, and AD9747

Parameter

RESOLUTION 12 14 16 Bits ACCURACY

Differential Nonlinearity (DNL) ±0.13 ±0.5 ±2.0 LSB Integral Nonlinearity (INL) ±0.25 ±1.0 ±4.0 LSB

MAIN DAC OUTPUTS

Offset Error ±0.001 ±0.001 ±0.001 %FSR Offset Error Temperature Coefficient 0.1 0.1 0.1 ppm/°C Gain Error ±2.0 ±2.0 ±2.0 %FSR Gain Error Temperature Coefficient 100 100 100 ppm/°C Gain Matching (DAC1 to DAC2) ±1.0 ±1.0 ±1.0 %FSR Full-Scale Output Current 8.6 31.7 8.6 31.7 8.6 31.7 mA Output Compliance Voltage −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V Output Resistance 10 10 10 MΩ

AUXILIARY DAC OUTPUTS

Resolution 10 10 10 Bits Full-Scale Output Current −2.0 +2.0 −2.0 +2.0 −2.0 +2.0 mA Output Compliance Voltage Range—Sink Current 0.8 1.6 0.8 1.6 0.8 1.6 V Output Compliance Voltage Range—Source Current 0 1.6 0 1.6 0 1.6 V Output Resistance 1 1 1 MΩ Monotonicity 10 10 10 Bits

REFERENCE INPUT/OUTPUT

Output Voltage 1.2 1.2 1.2 V Output Voltage Temperature Coefficient 10 10 10 ppm/°C External Input Voltage Range 1.15 1.3 1.15 1.3 1.15 1.3 V Input or Output Resistance 5 5 5 kΩ

POWER SUPPLY VOLTAGES

AVDD33, DVDD33 3.13 3.47 3.13 3.47 3.13 3.47 V CVDD18, DVDD18 1.70 1.90 1.70 1.90 1.70 1.90 V

POWER SUPPLY CURRENTS

I

AVDD33

I

DVDD33

I

CVDD18

I

DVDD18

POWER DISSIPATION

f

DAC

DAC Outputs Disabled 120 125 125 mW Full Device Power-Down 3 3 3 mW

OPERATING TEMPERATURE −40 +85 −40 +85 −40 +85 °C

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum

MAX

Tabl e 2 so the user can compare it with all other parts.

AD9745 AD9746 AD9747

Min Typ Max Min Typ Max Min Typ Max

Unit

56 60 56 60 56 60 mA 11 15 12 16 12 16 mA 18 22 18 22 18 22 mA 30 34 31 35 32 36 mA

= 250 MSPS, f

= 20 MHz 305 350 310 355 310 355 mW

OUT

Rev. 0 | Page 4 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

AC SPECIFICATIONS

T

to T

MIN

sample rate, unless otherwise noted.

Table 3. AD9741, AD9743, and AD9745

Parameter

SPURIOUS FREE DYNAMIC RANGE (SFDR)

f

DAC

f

DAC

f

DAC

INTERMODULATION DISTORTION (IMD)

f

DAC

f

DAC

f

DAC

CROSSTALK

f

DAC

f

DAC

f

DAC

ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE

CARRIER WCDMA

f

DAC

f

DAC

f

DAC

NOISE SPECTRAL DENSITY (NSD)

f

DAC

f

DAC

f

DAC

1

Mix Mode.

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum

MAX

AD9741 AD9743 AD9745

Min Typ Max Min Typ Max Min Typ Max

= 250 MSPS, f = 250 MSPS, f = 250 MSPS, f

= 20 MHz 70 80 82 dBc

OUT

= 70 MHz 70 70 70 dBc

OUT

= 180 MHz

OUT

= 20 MHz 80 80 86 dBc

OUT

= 70 MHz 80 80 80 dBc

OUT

= 180 MHz

OUT

= 20 MHz 80 80 80 dBc

OUT

= 70 MHz 80 80 80 dBc

OUT

= 180 MHz

OUT

1

64 64 66 dBc

72 72 74 dBc

80 80 80 dBc

= 245.76 MSPS, f = 245.76 MSPS, f = 245.76 MSPS, f

= 15.36 MHz 54 66 76 dBc

OUT

= 61.44 MHz 54 66 76 dBc

OUT

= 184.32 MHz

OUT

= 15.36 MHz −132 −144 −155 dBm/Hz

OUT

= 61.44 MHz −132 −144 −155 dBm/Hz

OUT

= 184.32 MHz

OUT

1

54 64 72 dBc

−135 −147 −155 dBm/Hz

Unit

Rev. 0 | Page 5 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

T

to T

MIN

sample rate, unless otherwise noted. The AD9745 is repeated in Table 4 so the user can compare it with all other parts.

Table 4. AD9745, AD9746, and AD9747

Parameter

SPURIOUS FREE DYNAMIC RANGE (SFDR)

f

DAC

f

DAC

f

DAC

INTERMODULATION DISTORTION (IMD)

f

DAC

f

DAC

f

DAC

CROSSTALK

f

DAC

f

DAC

f

DAC

ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE

CARRIER WCDMA

f

DAC

f

DAC

f

DAC

NOISE SPECTRAL DENSITY (NSD)

f

DAC

f

DAC

f

DAC

1

Mix Mode.

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum

MAX

AD9745 AD9746 AD9747

Min Typ Max Min Typ Max Min Typ Max

= 250 MSPS, f = 250 MSPS, f = 250 MSPS, f

= 20 MHz 82 82 82 dBc

OUT

= 70 MHz 70 70 70 dBc

OUT

= 180 MHz1 66 66 66 dBc

OUT

= 20 MHz 86 86 86 dBc

OUT

= 70 MHz 80 80 80 dBc

OUT

= 180 MHz1 74 74 74 dBc

OUT

= 20 MHz 80 80 80 dBc

OUT

= 70 MHz 80 80 80 dBc

OUT

= 180 MHz1 80 80 80 dBc

OUT

= 245.76 MSPS, f = 245.76 MSPS, f = 245.76 MSPS, f

= 15.36 MHz 76 78 82 dBc

OUT

= 61.44 MHz 76 78 80 dBc

OUT

= 184.32 MHz1 72 74 74 dBc

OUT

= 15.36 MHz −155 −163 −165 dBm/Hz

OUT

= 61.44 MHz −155 −160 −162 dBm/Hz

OUT

= 184.32 MHz1 −155 −158 −160 dBm/Hz

OUT

Unit

Rev. 0 | Page 6 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

DIGITAL AND TIMING SPECIFICATIONS

T

to T

MIN

sample rate, unless otherwise noted.

Table 5. AD9741/AD9743/AD9745/AD9746/AD9747

Parameter Min Typ Max Unit

DAC CLOCK INPUTS (CLKP, CLKN)

Differential Peak-to-Peak Voltage 400 800 1600 mV Single-Ended Peak-to-Peak Voltage 800 mV Common-Mode Voltage 300 400 500 mV Input Current 1 μA Input Frequency 250 MHz

DATA CLOCK OUTPUT (DCO)

Output Voltage High 2.4 V Output Voltage Low 0.4 V Output Current 10 mA DAC Clock to Data Clock Output Delay (t

DATA PORT INPUTS

Input Voltage High 2.0 V Input Voltage Low 0.8 V Input Current 1 μA Data to DAC Clock Setup Time (t Data to DAC Clock Hold Time (t DAC Clock to Analog Output Data Latency (Dual-Port Mode) 7 Cycles Data or IQSEL Input to DAC Clock Setup Time (t Data or IQSEL Input to DAC Clock Hold Time (t DAC Clock to Analog Output Data Latency (Single-Port Mode) 8 Cycles

SERIAL PERIPHERAL INTERFACE

SCLK Frequency (f SCLK Pulse Width High (t SCLK Pulse Width Low (t CSB to SCLK Setup Time (tS) 1 ns CSB to SCLK Hold Time (tH) 0 ns SDIO to SCLK Setup Time (tDS) 1 ns SDIO to SCLK Hold Time (tDH) 0 ns SCLK to SDIO/SDO Data Valid Time (tDV) 1 ns RESET Pulse Width High 10 ns

WAKE-UP TIME AND OUTPUT LATENCY

From DAC Outputs Disabled 200 μs From Full Device Power-Down 1200 μs DAC Clock to Analog Output Latency (Dual-Port Mode) 7 Cycles DAC Clock to Analog Output Latency (Single-Port Mode) 8 Cycles

, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum

MAX

) 2.0 2.2 2.8 ns

DCO

Dual-Port Mode) 400 ps

DBS

Dual-Port Mode) 1200 ps

DBH

Single-Port Mode) 400 ps

DBS

Single-Port Mode) 1200 ps

DBH

) 40 MHz

SCLK

) 10 ns

PWH

) 10 ns

PWL

Rev. 0 | Page 7 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

ABSOLUTE MAXIMUM RATINGS

Table 6.

With

Parameter

AVDD33, DVDD33 AVSS DVSS

DVDD18, CVDD18 AVSS DVSS

AVSS DVSS CVSS −0.3 V to +0.3 V DVSS AVSS CVSS −0.3 V to +0.3 V CVSS AVSS DVSS −0.3 V to +0.3 V REFIO AVSS −0.3 V to AVDD33 + 0.3 V IOUT1P, IOUT1N, IOUT2P,

IOUT2P, AUX1P, AUX1N, AUX2P, AUX2N

P1D15 to P1D0, P2D15 to P2D0

CLKP, CLKN CVSS −0.3 V to CVDD18 + 0.3 V RESET, CSB, SCLK, SDIO, SDO DVSS –0.3 V to DVDD33 + 0.3 V Junction Temperature 125°C Storage Temperature −65°C to +150°C

Respect to

CVSS

AVSS −1.0 V to AVDD33 + 0.3 V

DVSS −0.3 V to DVDD33 + 0.3 V

Rating

−0.3 V to +3.6 V

−0.3 V to +1.98 V

THERMAL RESISTANCE

Thermal resistance tested using JEDEC standard 4-layer thermal test board with no airflow.

Table 7.

Package Type θJA Unit

CP-72-1 (Exposed Pad Soldered to PCB) 25 °C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 8 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVDD33

AVSS

IOUT1P

IOUT1N

AVSS

AUX1P

AUX1N

AVSS

AUX2N

AUX2P

AVSS

IOUT2N

IOUT2P

AVSS

AVDD33

REFIO

7271706968676665646362616059585756

55

CVDD18

DVDD18

NC = NO CONNECT

CVSS CLKP CLKN CVSS

DVSS

P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17NC 18NC

PIN 1 INDICATOR

(TOP VIEW)

192021222324252627282930313233

NCNCNCNCNC

NC

DCO

AD9741

NC

DVSS

DVDD33

FSADJ

54

RESET

53

CSB

52

SCLK

51

SDIO

50

SDO

49

DVSS

48

DVDD18

47

NC

46

NC

45

NC

44

NC

43

NC

42

NC

41

NC

40

NC

39

P2D0

38

P2D1

37

34

35P2D3

36P2D2

NC

P2D7

P2D6

P2D5

IQSEL

P2D4

06569-006

Figure 2. AD9741 Pin Configuration

Table 8. AD 9741 Pin Function Descriptions

Pin No. Mnemonic Description

1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 16 P1D<7:0> Port 1 Data Bit Inputs. 17 to 24, 26, 30, 39 to 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 38 P2D<7:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS

Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance.

Rev. 0 | Page 9 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

AVDD33

AVSS

IOUT1P

IOUT1N

AVSS

AUX1P

AUX1N

AVSS

AUX2N

AUX2P

AVSS

IOUT2N

IOUT2P

AVSS

AVDD33

REFIO

7271706968676665646362616059585756

55

CVDD18

DVDD18

NC = NO CONNECT

CVSS CLKP CLKN CVSS

DVSS

P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17P1D1 18P1D0

PIN 1 INDICATOR

(TOP VIEW)

192021222324252627282930313233

NCNCNCNCNC

NC

DCO

AD9743

NC

DVSS

DVDD33

FSADJ

54

RESET

53

CSB

52

SCLK

51

SDIO

50

SDO

49

DVSS

48

DVDD18

47

NC

46

NC

45

NC

44

NC

43

NC

42

NC

41

P2D0

40

P2D1

39

P2D2

38

P2D3

37

34

35P2D5

36P2D4

NC

P2D9

P2D8

P2D7

IQSEL

P2D6

06569-005

Figure 3. AD9743 Pin Configuration

Table 9. AD 9743 Pin Function Descriptions

Pin No. Mnemonic Description

1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 18 P1D<9:0> Port 1 Data Bit Inputs. 19 to 24, 26, 30, 41 to 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 40 P2D<9:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS

Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance.

Rev. 0 | Page 10 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

AVDD33

AVSS

IOUT1P

IOUT1N

AVSS

AUX1P

AUX1N

AVSS

AUX2N

AUX2P

AVSS

IOUT2N

IOUT2P

AVSS

AVDD33

REFIO

7271706968676665646362616059585756

55

CVDD18

DVDD18

NC = NO CONNECT

CVSS CLKP CLKN CVSS

DVSS

P1D11 P1D10

P1D9 P1D8 P1D7 P1D6 P1D5 P1D4

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17P1D3 18P1D2

PIN 1 INDICATOR

(TOP VIEW)

192021222324252627282930313233

NCNCNC

NC

P1D1

P1D0

DCO

AD9745

NC

DVSS

DVDD33

FSADJ

54

RESET

53

CSB

52

SCLK

51

SDIO

50

SDO

49

DVSS

48

DVDD18

47

NC

46

NC

45

NC

44

NC

43

P2D0

42

P2D1

41

P2D2

40

P2D3

39

P2D4

38

P2D5

37

34

35P2D7

36P2D6

NC

P2D9

IQSEL

P2D8

P2D11

P2D10

06569-004

Figure 4. AD9745 Pin Configuration

Table 10. AD9745 Pin Function Descriptions

Pin No. Mnemonic Description

1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 20 P1D<11:0> Port 1 Data Bit Inputs. 21 to 24, 26, 30, 43 to 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 42 P2D<11:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS

Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance.

Rev. 0 | Page 11 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

AVDD33

AVSS

IOUT1P

IOUT1N

AVSS

AUX1P

AUX1N

AVSS

AUX2N

AUX2P

AVSS

IOUT2N

IOUT2P

AVSS

AVDD33

REFIO

7271706968676665646362616059585756

55

CVDD18

DVDD18

NC = NO CONNECT

CVSS CLKP CLKN CVSS

DVSS

P1D13 P1D12 P1D11 P1D10

P1D9 P1D8 P1D7 P1D6

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17P1D5 18P1D4

PIN 1 INDICATOR

(TOP VIEW)

192021222324252627282930313233

NC

P1D3

P1D2

DCO

P1D1

P1D0

AD9746

NC

DVSS

DVDD33

FSADJ

54

RESET

53

CSB

52

SCLK

51

SDIO

50

SDO

49

DVSS

48

DVDD18

47

NC

46

NC

45

P2D0

44

P2D1

43

P2D2

42

P2D3

41

P2D4

40

P2D5

39

P2D6

38

P2D7

37

34

35P2D9

36P2D8

NC

IQSEL

P2D11

P2D13

P2D12

P2D10

06569-003

Figure 5. AD9746 Pin Configuration

Table 11. AD9746 Pin Function Descriptions

Pin No. Mnemonic Description

1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 22 P1D<13:0> Port 1 Data Bit Inputs. 23, 24, 26, 30, 45, 46 NC No Connect. 25 DCO Data Clock Output. Use to clock data source. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 44 P2D<13:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output True. Sources full-scale current when input data bits are all 1. 60 IOUT2N DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS

Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance.

Rev. 0 | Page 12 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

AVD D33

AVS S

IOUT1P

IOUT1N

AVS S

AUX1P

AUX1N

AVS S

AUX2N

AUX2P

AVS S

IOUT2N

IOUT2P

AVS S

AVD D33

7271706968676665646362616059585756

REFIO

55

CVDD18

DVDD18

NC = NO CONNECT

CVSS CLKP CLKN CVSS

DVSS

P1D15 P1D14 P1D13 P1D12 P1D11 P1D10

P1D9 P1D8

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17P1D7 18P1D6

PIN 1 INDICATOR

(TOP VIEW)

192021222324252627282930313233

P1D5

P1D4

DCO

P1D3

P1D2

P1D1

P1D0

AD9747

NC

DVDD33

DVSS

FSADJ

54

RESET

53

CSB

52

SCLK

51

SDIO

50

SDO

49

DVSS

48

DVDD18

47

P2D0

46

P2D1

45

P2D2

44

P2D3

43

P2D4

42

P2D5

41

P2D6

40

P2D7

39

P2D8

38

P2D9

37

34

35P2D11

36P2D10

NC

IQSEL

P2D15

P2D14

P2D13

P2D12

06569-002

Figure 6. AD9747 Pin Configuration

Table 12. AD9747 Pin Function Descriptions

Pin No. Mnemonic Description

1, 6 CVDD18 Clock Supply Voltage (1.8 V). 2, 5 CVSS Clock Supply Common (0 V). 3 CLKP Differential DAC Clock Input. 4 CLKN Complementary Differential DAC Clock Input. 7, 28, 48 DVSS Digital Supply Common (0 V). 8, 47 DVDD18 Digital Core Supply Voltage (1.8 V). 9 to 24 P1D<15:0> Port 1 Data Bit Inputs. 25 DCO Data Clock Output. Use to clock data source. 26, 30 NC No Connect. 27 DVDD33 Digital I/O Supply Voltage (3.3 V). 29 IQSEL I/Q Framing Signal for Single-Port Mode Operation. 31 to 46 P2D<15:0> Port 2 Data Bit Inputs. 49 SDO Serial Peripheral Interface Data Output. 50 SDIO Serial Peripheral Interface Data Input and Optional Data Output. 51 SCLK Serial Peripheral Interface Clock Input. 52 CSB Serial Peripheral Interface Chip Select Input. Active low. 53 RESET Hardware Reset. Active high. 54 FSADJ Full-Scale Current Output Adjust. Connect a 10 kΩ resistor to AVSS. 55 REFIO Reference Input/Output. Connect a 0.1 μF capacitor to AVSS. 56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V). 58, 61, 64, 67, 70 AVSS Analog Supply Common (0 V). 59 IOUT2P DAC2 Current Output. Sources full-scale current when input data bits are all 1. 60 IOUT2N Complementary DAC2 Current Output. Sources full-scale current when data bits are all 0. 62 AUX2P Auxiliary DAC2 Default Current Output Pin. 63 AUX2N Auxiliary DAC2 Optional Output Pin. Enable through SPI. 65 AUX1N Auxiliary DAC1 Optional Output Pin. Enable through SPI. 66 AUX1P Auxiliary DAC1 Default Current Output Pin. 68 IOUT1N Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. 69 IOUT1P DAC1 Current Output. Sources full-scale current when data bits are all 1. EPAD AVSS

Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance.

Rev. 0 | Page 13 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

–

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

80

70

SFDR (dBc)

60

50

40

0 20406080100120

Figure 7. AD9747 SFDR vs. f

100

90

80

70

SFDR (dBc)

60

50

125MSPS

f

OUT

250MSPS

(MHz)

, Normal Mode

OUT

90

80

70

IMD (dBc)

60

50

40

0 20406080100120

06569-007

125MSPS

Figure 10. AD9747 IMD vs. f

100

90

80

70

IMD (dBc)

60

50

250MSPS

f

(MHz)

OUT

, Normal Mode

OUT

06569-010

40

125 250

90

85

80

75

ACLR (dB c)

70

65

60

0 250

Figure 9. AD9747 ACLR vs. f

150 175 200 225

f

OUT

Figure 8. AD9747 SFDR vs. f

NORMAL MODE

50 100 150 200

f

OUT

, Single Carrier WCDMA, 245.76 MSPS

OUT

(MHz)

, Mix Mode, 250 MSPS

OUT

MIX MODE

(MHz)

40

125 250

06569-008

152

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–166

–168

02

06569-009

Figure 12. AD9747 NSD vs. f

150 175 200 225

f

OUT

Figure 11. AD9747 IMD vs. f

NORMAL MODE

50 100 150 200

f

OUT

, Single Carrier WCDMA, 245.76 MSPS

OUT

(MHz)

, Mix Mode, 250 MSPS

OUT

MIX MODE

(MHz)

06569-011

50

06569-012

Rev. 0 | Page 14 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

100

90

80

70

SFDR (dBc)

60

50

40

0 20 40 60 80 100 120

20mAFS

10mAFS

30mAFS

f

(MHz)

OUT

Figure 13. AD9747 SFDR vs. Analog Output, 250 MSPS

100

90

80

70

SFDR (dBc)

60

0dBFS

–3dBFS

–6dBFS

90

80

70

IMD (dBc)

60

50

40

0 20406080100120

f

(MHz)

06569-036

OUT

10mAFS

20mAFS

30mAFS

06569-039

Figure 16. AD9747 IMD vs. Analog Output, 250 MSPS

100

90

80

70

IMD (dBc)

60

–3dBFS

0dBFS

–6dBFS

50

40

0 20 40 60 80 100 120

f

(MHz)

IN

Figure 14. AD9747 SFDR vs. Digital Input, 250 MSPS

90

85

80

75

SFDR (dBc)

70

RANGE OF POSSIBLE SFDR PERFORMANCE IS DEPENDENT ON

65

INPUT DATA TIMING RELATIVE TO THE DAC CLOCK. SEE INPUT DATA TIMING SECTION.

60

10 20 30 40 50 60 70 80 90 100 110

f

(MHz)

OUT

Figure 15. AD9747 SFDR vs. f

Over Input Data Timing

OUT

50

40

0 20406080100120

f

(MHz)

06569-037

IN

06569-040

Figure 17. AD9747 IMD vs. Digital Input, 250 MSPS

90

85

80

75

IMD (dBc)

70

RANGE OF IMD PERFORMANCE IS ESSENTIALLY INDEPENDENT OF

65

INPUT DATA TI MING RELAT IVE TO THE DAC CLOCK. SEE INPUT DATA TIMI NG SECT ION.

60

20 30 40 50 60 70 80 90 100 11010

f

(MHz)

06569-038

Figure 18. AD9747 IMD vs. f

OUT

Over Input Data Timing

OUT

06569-041

Rev. 0 | Page 15 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

–

1

130

0

–1

NORMAL MODE

–2

(dBm)

OUT

A

–3

–4

–5

25 75 125 175 22550 100 150 2000 250

f

(MHz)

OUT

Figure 19. Nominal Power in the Fundamental, I

85

80

75

MIX MODE

= 20 mA

FS

06569-042

–135

–140

–145

–150

NSD (dBm/Hz)

–155

–160

–165

AD9747AD9746AD9745AD9743AD9741

Figure 21. NSD vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS, f

= 61.44 MHz

f

CARRIER

06569-044

CARRIER

70

65

ACLR (dBc)

60

55

50

AD9747AD9746AD9745AD9743AD9741

Figure 20. ACLR vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS,

= 61.44 MHz

f

CARRIER

06569-043

Rev. 0 | Page 16 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

TERMINOLOGY

Integral Nonlinearity (INL)

The maximum deviation of the actual analog output from the ideal output, as determined by a straight line drawn from zero scale to full scale.

Differential Nonlinearity (DNL)

A measure of the maximum deviation in analog output associated with any single value change in the digital input code relative to an ideal LSB.

Monotonicity

A DAC is monotonic if the analog output increases or remains constant in response to an increase in the digital input.

Offset Error

The deviation of the output current from the ideal zero-scale current. For differential outputs, 0 mA is expected at I all inputs are low, and 0 mA is expected at I

when all inputs

OUTN

OUTP

when

are high.

Gain Error

The deviation of the output current from the ideal full-scale current. Actual full-scale output current is determined by subtracting the output (when all inputs are low) from the output (when all inputs are high).

Output Compliance Range

The range of allowable voltage seen by the analog output of a current output DAC. Operation beyond the compliance limits may cause output stage saturation and/or a breakdown resulting in nonlinear performance.

Tem p er at u re Dr i ft

Temperature drift is specified as the maximum change in a parameter from ambient temperature (25°C) to either T or T

and is typically reported as ppm/°C.

MAX

MIN

Spurious-Free Dynamic Range (SFDR)

The difference in decibels between the peak amplitude of a test tone and the peak amplitude of the largest spurious signal over the specified bandwidth.

Intermodulation Distortion (IMD)

The difference in decibels between the maximum peak amplitude of two test tones and the maximum peak amplitude of the distortion products created from the sum or difference of integer multiples of the test tones.

Adjacent Channel Leakage Ratio (ACLR)

The ratio between the measured power of a wideband signal within a channel relative to the measured power in an empty adjacent channel.

Noise Spectral Density (NSD)

The measured noise power over a 1 Hz bandwidth seen at the analog output.

Rev. 0 | Page 17 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

THEORY OF OPERATION

The AD9741/AD9743/AD9745/AD9746/AD9747 combine many features to make them very attractive for wired and wireless communications systems. The dual DAC architecture facilitates easy interfacing to common quadrature modulators when designing single sideband transmitters. In addition, the speed and performance of the devices allow wider bandwidths and more carriers to be synthesized than in previously available products.

All features and options are software programmable through the SPI port.

SERIAL PERIPHERAL INTERFACE

SDO

SDIO

SCLK

CSB

AD9747

SPI

PORT

Figure 22. SPI Port

6569-013

The SPI port is a flexible, synchronous serial communications port allowing easy interfacing to many industry-standard microcontrollers and microprocessors. The port is compatible with most synchronous transfer formats including both the

Motorola SPI and Intel

® SSR protocols.

The interface allows read and write access to all registers that configure the AD9741/AD9743/AD9745/AD9746/AD9747. Single or multiple byte transfers are supported as well as MSBfirst or LSB-first transfer formats. Serial data input/output can be accomplished through a single bidirectional pin (SDIO) or through two unidirectional pins (SDIO/SDO).

The serial port configuration is controlled by Register 0x00, Bits<7:6>. It is important to note that any change made to the serial port configuration occurs immediately upon writing to the last bit of this byte. Therefore, it is possible with a multibyte transfer to write to this register and change the configuration in the middle of a communication cycle. Care must be taken to compensate for the new configuration within the remaining bytes of the current communication cycle.

Use of a single-byte transfer when changing the serial port configuration is recommended to prevent unexpected device behavior.

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to any communication cycle with the AD9741/AD9743/AD9745/AD9746/AD9747: Phase 1 and Phase 2. Phase 1 is the instruction cycle, which writes an instruction byte into the device. This byte provides the serial port controller with information regarding Phase 2 of the communication cycle: the data transfer cycle.

The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data

transfer, and a reference register address for the first byte of the data transfer. A logic high on the CSB pin followed by a logic low resets the SPI port to its initial state and defines the start of the instruction cycle. From this point, the next eight rising SCLK edges define the eight bits of the instruction byte for the current communication cycle.

The remaining SCLK edges are for Phase 2 of the communication cycle, which is the data transfer between the serial port controller and the system controller. Phase 2 can be a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Using multibyte transfers is usually preferred although single-byte data transfers are useful to reduce CPU overhead or when only a single register access is required.

All serial port data is transferred to and from the device in synchronization with the SCLK pin. Input data is always latched on the rising edge of SCLK whereas output data is always valid after the falling edge of SCLK. Register contents change immediately upon writing to the last bit of each transfer byte.

When synchronization is lost, the device has the ability to asynchronously terminate an I/O operation whenever the CSB pin is taken to logic high. Any unwritten register content data is lost if the I/O operation is aborted. Taking CSB low then resets the serial port controller and restarts the communication cycle.

INSTRUCTION BYTE

The instruction byte contains the information shown in the following bit map.

MSB B7 B6 B5 B4 B3 B2 B1 B0

R/W N1 N0 A4 A3 A2 A1 A0

Bit 7, R/W, determines whether a read or a write data transfer occurs after the instruction byte write. Logic high indicates a read operation. Logic 0 indicates a write operation.

Bits<6:5>, N1 and N0, determine the number of bytes to be transferred during the data transfer cycle. The bits decode as shown in

Table 13. Byte Transfer Count

N1 N0 Description

0 0 Transfer one byte 0 1 Transfer two bytes 1 0 Transfer three bytes 1 1 Transfer four bytes

Bits<4:0>, A4, A3, A2, A1, and A0, determine which register is accessed during the data transfer of the communications cycle. For multibyte transfers, this address is a starting or ending address depending on the current data transfer mode. For MSBfirst format, the specified address is an ending address or the most significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated

Tabl e 1 3 .

LSB

Rev. 0 | Page 18 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

internally by the serial port controller by decrementing from the specified address. For LSB-first format, the specified address is a beginning address or the least significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated internally by the serial port controller by incrementing from the specified address.

MSB/LSB TRANSFERS

The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by Register 0x00, Bit 6. The default is Logic 0, which is MSB-first format.

When using MSB-first format (LSBFIRST = 0), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes are loaded into sequentially lower address locations. In MSB-first mode, the serial port internal address generator decrements for each byte of the multibyte data transfer.

When using LSB-first format (LSBFIRST = 1), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes are loaded into sequentially higher address locations. In LSB-first mode, the serial port internal address generator increments for each byte of the multibyte data transfer.

Use of a single-byte transfer when changing the serial port data format is recommended to prevent unexpected device behavior.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

Chip Select Bar (CSB)

Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. CSB must stay low during the entire communication cycle. Incomplete data transfers are aborted anytime the CSB pin goes high. SDO and SDIO pins go to a high impedance state when this input is high.

Serial Clock (SCLK)

The serial clock pin is used to synchronize data to and from the device and to run the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK.

Serial Data I/O (SDIO)

Data is always written into the device on this pin. However, SDIO can also function as a bidirectional data output line.

The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, which configures the SDIO pin as unidirectional.

Serial Data Out (SDO)

Data is read from this pin for protocols that use separate lines for transmitting and receiving data. The configuration of this pin is controlled by Register 0x00, Bit 7. If this bit is set to a Logic 1, the SDO pin does not output data and is set to a high impedance state.

INSTRUCTIO N CYCLE DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

R/W N1 N0 A4 A3 A2 A1 A0 D7 D6ND5

D7 D6ND5

N

D00D10D20D3

0

D00D10D20D3

0

Figure 23. Serial Register Interface—MSB First

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

A0 A1 A2 A3 A4 N0 N1 R/W D00D10D2

D00D10D2

0

D7ND6ND5ND4

N

D7ND6ND5ND4

N

Figure 24. Serial Register Interface Timing—LSB First

t

PWH

t

–1

f

SCLK

t

PWL

DH

INSTRUCTIO N BIT 6INSTRUCTIO N BIT 7

CSB

SCLK

SDIO

t

S

t

DS

Figure 25. Timing Diagram for SPI Register Write

CSB

SCLK

t

DV

SDIO

SDO

Figure 26. Timing Diagram for SPI Register Read

DATA BIT N – 1DATA BIT N

06569-014

6569-015

06569-016

06569-017

Rev. 0 | Page 19 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

SPI REGISTER MAP

Reading any register returns previously written values for all defined register bits, unless otherwise noted. Change serial port configuration or execute software reset in single byte instruction only to avoid unexpected device behavior.

Table 14.

Register Name Address Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPI Control 0x00 0x00 SDIODIR LSBFIRST SWRESET Data Control 0x02 0x00 DATTYPE ONEPORT Power Down 0x03 0x00 PD_DCO PD_AUX2 PD_AUX1 PD_BIAS PC_CLK PD_DAC2 PD_DAC1 DAC Mode Select 0x0A 0x00 DAC1MOD<1:0> DAC2MOD<1:0> DAC1 Gain LSB 0x0B 0xF9 DAC1FSC<7:0> DAC1 Gain MSB 0x0C 0x01 DAC1FSC<9:8> AUX DAC1 LSB 0x0D 0x00 AUXDAC1<7:0> AUX DAC1 MSB 0x0E 0x00 AUX1PIN AUX1DIR AUXDAC1<9:8> DAC2 Gain LSB 0x0F 0xF9 DAC2FSC<7:0> DAC2 Gain MSB 0x10 0x01 DAC2FSC<9:8> AUX DAC2 LSB 0x11 0x00 AUXDAC2<7:0> AUX DAC2 MSB 0x12 0x00 AUX2PIN AUX2DIR AUXDAC2<9:8>

INVDCO

Rev. 0 | Page 20 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

SPI REGISTER DESCRIPTIONS

Table 15.

Register Address Bit Name Description

SPI Control 0x00

Data Control 0x02

Power Down 0x03

DAC Mode Select 0x0A

DAC1 Gain

AUX DAC1

DAC2 Gain

AUX DAC2

0x0B 7:0 DAC1FSC<7:0> DAC1 full-scale 10-bit adjustment word 0x0C

0x0D 7:0 AUXDAC1<7:0> Auxiliary DAC1 10-bit output current adjustment word 0x0E

0x0F 7:0 DAC2FSC<7:0> DAC2 full-scale 10-bit adjustment word 0x10

0x11 7:0 AUXDAC2<7:0> Auxiliary DAC2 10-bit output current adjustment word 0x12 1:0 AUXDAC2<9:8> 0x03FF, sets output current magnitude to 2.0 mA 0x0200, sets output current to 1.0 mA 0x0000, sets output current to 0.0 mA 7 AUX2PIN 0, AUX2P output pin is active 1, AUX2N output pin is active 6 AUX2DIR 0, configures AUX2 DAC output to source current 1, configures AUX2 DAC output to sink current

7 SDIODIR 0, operate SPI in 4-wire mode, SDIO pin operates as an input only 1, operate SPI in 3-wire mode, SDIO pin operates as a bidirectional I/O line 6 LSBFIRST 0, LSBFIRST off, SPI serial data mode is MSB to LSB 1, LSBFIRST on, SPI serial data mode is LSB to MSB 5 SWRESET 0, resume normal operation following software RESET 1, software RESET; loads default values to all registers (except Register 0x00) 7 DATTYPE 0, DAC input data is twos complement binary format 1, DAC input data is unsigned binary format 6 ONEPORT 0, normal two port input mode 1, optional single port input mode, interleaved data received on Port 1 only 4 INVDCO 1, inverts data clock output signal 7 PD_DCO 1, power down data clock output 5 PD_AUX2 1, power down AUX2 DAC 4 PD_AUX1 1, power down AUX1 DAC 3 PD_BIAS 1, power down reference voltage bias circuit 2 PD_CLK 1, power down DAC clock input circuit 1 PD_DAC2 1, power down DAC2 analog output 0 PD_DAC1 1, power down DAC1 analog output 3:2 DAC1MOD<1:0> 00, selects normal mode, DAC1 01, selects mix mode, DAC1 10, selects return-to-zero mode, DAC1 1:0 DAC2MOD<1:0> 00, selects normal mode, DAC2 01, selects mix mode, DAC2 10, selects return-to-zero mode, DAC2

1:0 DAC1FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA 0x01F9, sets full-scale current to the nominal value of 20.0 mA 0x0000, sets full-scale current to the minimum value of 8.64 mA

1:0 AUXDAC1<9:8> 0x03FF, sets output current magnitude to 2.0 mA 0x0200, sets output current magnitude to 1.0 mA 0x0000, sets output current magnitude to 0.0 mA 7 AUX1PIN 0, AUX1P output pin is active 1, AUX1N output pin is active 6 AUX1DIR 0, configures AUX1 DAC output to source current 1, configures AUX1 DAC output to sink current

1:0 DAC2FSC<9:8> 0x03FF, sets full-scale current to the maximum value of 31.66 mA 0x01F9, sets full-scale current to the nominal value of 20.0 mA 0x0000, sets full-scale current to the minimum value of 8.64 mA

Rev. 0 | Page 21 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

DIGITAL INPUTS AND OUTPUTS

The AD9741/AD9743/AD9745/AD9746/AD9747 can operate in two data input modes: dual-port mode and single-port mode. For the default dual-port mode (ONEPORT = 0), each DAC receives data from a dedicated input port. In single-port mode (ONEPORT = 1), however, both DACs receive data from Port 1. In single-port mode, DAC1 and DAC2 data is interleaved and the IQSEL input is used to steer data to the correct DAC.

In single-port mode, when the IQSEL input is high, Port 1 data is delivered to DAC1 and when IQSEL is low, Port 1 data is delivered to DAC2. The IQSEL input should always coincide and be time-aligned with the other data bus signals. In singleport mode, minimum setup and hold times apply to the IQSEL input as well as to the input data signals. In dual-port mode, the IQSEL input is ignored.

In dual-port mode, the data must be delivered at the sample rate (up to 250 MSPS). In single-port mode, data must be delivered at twice the sample rate. Because the data inputs function only up to 250 MSPS, it is only practical to operate the DAC clock at up to 125 MHz in single-port mode.

In both dual-port and single-port modes, a data clock output (DCO) signal is available as a fixed time base with which to stimulate data from an FPGA. This output signal always operates at the sample rate. It may be inverted by asserting the INVDCO bit.

INPUT DATA TIMING

With most DACs, signal-to-noise ratio (SNR) is a function of the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9741/ AD9743/AD9745/AD9746/AD9747 are rising edge triggered and thus exhibit greater SNR sensitivity when the data transition is close to this edge.

The specified minimum setup and hold times define a window of time, within each data period, where the data is sampled correctly. Generally, users should position data to arrive relative to the DAC clock and well beyond the minimum setup and minimum hold times. This becomes increasingly more important at increasingly higher sample rates.

DUAL-PORT MODE TIMING

The timing diagram for the dual-port mode is shown in Figure 27.

CLKP/CLKN

DCO

P1D<15:0>

P2D<15:0>

Figure 27. Data Interface Timing, Dual-Port Mode

t

DCO

t

DBH

DBS

I1 I2 I3 I4

Q1 Q2 Q3 Q4

06569-018

In Figure 27, data samples for DAC1 are labeled Ix and data samples for DAC2 are labeled Qx. Note that the differential DAC clock input is shown in a logical sense (CLKP/CLKN). The data clock output is labeled DCO.

Setup and hold times are referenced to the positive transition of the DAC clock. Data should arrive at the input pins such that the minimum setup and hold times are met. Note that the data clock output has a fixed time delay from the DAC clock and may be a more convenient signal to use to confirm timing.

SINGLE-PORT MODE TIMING

The single-port mode timing diagram is shown in Figure 28.

CLKP/CLKN

DCO

P1D<15:0>

IQSEL

t

DBS

Figure 28. Data Interface Timing, Single-Port Mode

t

DCO

t

DBH

I1 Q1 I2 Q2

In single-port mode, data for both DACs is received on the Port 1 input bus. Ix and Qx data samples are interleaved and arrive twice as fast as in dual-port mode. Accompanying the data is the IQSEL input signal, which steers incoming data to its respective DAC. When IQSEL is high, data is steered to DAC1 and when IQSEL is low, data is steered to DAC2. IQSEL should coincide as well as be time-aligned with incoming data.

SPI PORT, RESET, AND PIN MODE

In general, when the AD9741/AD9743/AD9745/AD9746/ AD9747 are powered up, an active high pulse applied to the RESET pin should follow. This insures the default state of all control register bits. In addition, once the RESET pin goes low, the SPI port can be activated, so CSB should be held high.

For applications without a controller, the AD9741/AD9743/ AD9745/AD9746/AD9747 also support pin mode operation, which allows some functional options to be pin, selected without the use of the SPI port. Pin mode is enabled anytime the RESET pin is held high. In pin mode, the four SPI port pins take on secondary functions, as shown in Table 16.

Table 16. SPI Pin Functions (Pin Mode)

Pin Name Pin Mode Description

SCLK

SDIO

CSB

SDO

ONEPORT (Register 0x02, Bit 6), bit value (1/0) equals pin state (high/low)

DATTYPE (Register 0x02, Bit 7), bit value (1/0) equals pin state (high/low)

Enable Mix Mode, if CSB is high, Register 0x0A is set to 0x05 putting both DAC1 and DAC2 into mix mode

Enable full power-down, if SDO is high, Register 0x03 is set to 0xFF

06569-019

Rev. 0 | Page 22 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

F

T

F

V

2

0

F

In pin mode, all register bits are reset to their default values with the exception of those that are controlled by the SPI pins.

Note also that the RESET pin should be allowed to float and must be pulled low. Connect an external 10 kΩ resistor to DVSS. This avoids unexpected behavior in noisy environments.

DRIVING THE DAC CLOCK INPUT

The DAC clock input requires a low jitter drive signal. It is a PMOS differential pair powered from the CVDD18 supply. Each pin can safely swing up to 800 mV p-p at a commonmode voltage of about 400 mV. Though these levels are not directly LVDS-compatible, CLKP and CLKN can be driven by an ac-coupled, dc-offset LVDS signal, as shown in

LVDS_P_IN CLKP

LVDS_N_IN CLKN

0.1µ

50Ω

V

50Ω

0.1µF

CM

Figure 29. LVDS DAC Clock Drive Circuit

Using a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through an LVDS translator and then ac-coupled as described previously, or alternatively, it can be transformer-coupled and clamped, as shown in

TL OR CMOS

CLK INPUT

0.1µ

Figure 30. TTL or CMOS DAC Clock Drive Circuit

50Ω

If a sine wave signal is available, it can be transformer-coupled directly to the DAC clock inputs, as shown in

SINE WAVE

INPUT

Figure 31. Sine Wave DAC Clock Drive Circuit

50Ω

CLKP

CLKN

V

CM

= 400mV

The 400 mV common-mode bias voltage can be derived from the CVDD18 supply through a simple divider network, as shown in

Figure 32.

1kΩ

87Ω

CM

CVDD18

0.1µF 1nF

CVSS

Figure 32. DAC Clock VCM Circuit

= 400mV

Figure 30.

BAV99ZXCT HIGH SPEED DUAL DIODE

= 400mV

V

CM

Figure 31.

= 400mV

Figure 29.

06569-021

CLKP

CLKN

06569-022

06569-034

06569-023

It is important to use CVDD18 and CVSS for any clock bias circuit as noise that is coupled onto the clock from another power supply is multiplied by the DAC input signal and degrades performance.

FULL-SCALE CURRENT GENERATION

The full-scale currents on DAC1 and DAC2 are functions of the current drawn through an external resistor connected to the FSADJ pin (Pin 54). The required value for this resistor is 10 kΩ. An internal amplifier sets the current through the resistor to force a voltage equal to the band gap voltage of 1.2 V. This develops a reference current in the resistor of 120 μA.

AD9747

1.2V BANDGAP

REFIO

.1µ

FSADJ

10kΩ

Figure 33. Reference Circuitry

REFIO (Pin 55) should be bypassed to ground with a 0.1 μF capacitor. The band gap voltage is present on this pin and can be buffered for use in external circuitry. The typical output impedance is near 5 kΩ. If desired, an external reference can be connected to REFIO to overdrive the internal reference.

Internal current mirrors provide a means for adjusting the DAC full-scale currents. The gain for DAC1 and DAC2 can be adjusted independently by writing to the DAC1FSC<9:0> and DAC2FSC<9:0> register bits. The default value of 0x01F9 for the DAC gain registers gives an I

V 1.2

⎛

FS n

10,000

72

⎜ ⎝

The full-scale output current range is 8.6 mA to 31.7 mA for register values 0x000 to 0x3FF.

35

30

25

20

(mA)

FS

I

15

10

5

0 256 512 768 1024

Figure 34. I

DAC1 GAIN

CURRENT

SCALING

DAC2 GAIN

of 20 mA, where IFS equals

FS

3

⎛

×+×= FSCDACI

⎜

16

⎝

DAC GAIN CODE

vs. DAC Gain Code

FS

DAC1

DAC FULL SCAL E REFERENCE CU RRENT

DAC2

⎞

⎟

⎟ ⎠

⎠

06569-025

06569-024

Rev. 0 | Page 23 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

DAC TRANSFER FUNCTION

Each DAC output of the AD9741/AD9743/AD9745/AD9746/ AD9747 drives complementary current outputs I I

provides a near full-scale current output (IFS) when all bits

OUTP

and I

OUTN

are high. For example,

DAC CODE = 2

N

− 1

where: N = 8-/10-/12-/14-/16-bits (for AD9741/AD9743/AD9745/ AD9746/AD9747 respectively), and I

The current output appearing at I both the input code and I

= (DAC DATA/2N) × IFS (1)

I

OUTP

= ((2N − 1) − DAC DATA)/2N × IFS (2)

I

OUTN

where DAC DATA = 0 to 2

OUTP

and can be expressed as

FS

N

− 1 (decimal representation).

provides no current.

OUTN

and I

is a function of

OUTN

The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, I should be connected to matching resistive loads (R

OUTP

LOAD

and I

OUTN

) that are tied to analog common (AVSS). The single-ended voltage output appearing at the I

= I

OUTP

OUTN

× R

V

OUTP

OUTN

and I

OUTP

(3)

LOAD

(4)

LOAD

OUTN

pins is

Note that to achieve the maximum output compliance of 1 V at the nominal 20 mA output current, R Also note that the full-scale value of V

must be set to 50 Ω.

LOAD

and V

OUTP

OUTN

should not exceed the specified output compliance range to maintain specified distortion and linearity performance.

There are two distinct advantages to operating the AD9741/ AD9743/AD9745/AD9746/AD9747 differentially. First, differential operation helps cancel common-mode error sources associated with I

OUTP

and I

, such as noise, distortion, and

OUTN

dc offsets. Second, the differential code dependent current and subsequent output voltage (V single-ended voltage output (V

) is twice the value of the

DIFF

OUTP

or V

), providing 2×

OUTN

signal power to the load.

V

= (I

– I

DIFF

OUTP

OUTN

) × R

(5)

LOAD

ANALOG MODES OF OPERATION

The AD9741/AD9743/AD9745/AD9746/AD9747 utilize a proprietary quad-switch architecture that lowers the distortion of the DAC output by eliminating a code dependent glitch that occurs with conventional dual-switch architectures. But whereas this architecture eliminates the code dependent glitches, it creates a constant glitch at a rate of 2 × f

. For communications

DAC

.

systems and other applications requiring good frequency domain performance, this is seldom problematic.

The quad-switch architecture also supports two additional modes of operation; mix mode and return-to-zero (RZ) mode. The waveforms of these two modes are shown in Figure 35. In mix mode, the output is inverted every other half clock cycle. This effectively chops the DAC output at the sample rate. This chopping has the effect of frequency shifting the sinc roll-off from dc to f

. Additionally, there is a second subtle effect on

DAC

the output spectrum. The shifted spectrum is shaped by a second sinc function with a first null at 2 × f

. The reason for this

DAC

shaping is that the data is not continuously varying at twice the clock rate, but is simply repeated.

In RZ mode, the output is set to midscale on every other half clock cycle. The output is similar to the DAC output in normal mode except that the output pulses are half the width and half the area. Because the output pulses have half the width, the sinc function is scaled in frequency by 2 and has a first null at

. Because the area of the pulses is half that of the pulses

2 × f

DAC

in normal mode, the output power is half the normal mode output power.

D9D8D7D6D5D4D3D2D

INPUT DATA

4-SWITCH

DAC OUTPUT

(

f

MIX MODE)

S

4-SWITCH

DAC OUTPUT

(RETURN TO

ZERO MODE)

1

DAC CLK

Figure 35. Mix Mode and RZ Mode DAC Waveforms

D

10

t

The functions that shape the output spectrums for normal mode, mix mode, and RZ mode, are shown in Figure 36. Switching between the modes reshapes the sinc roll off inherent at the DAC output. This ability to change modes in the AD9741/ AD9743/AD9745/D9746/AD9747 makes the parts suitable for direct IF applications. The user can place a carrier anywhere in the first three Nyquist zones depending on the operating mode selected. The performance and maximum amplitude in all three zones are impacted by this sinc roll off depending on where the carrier is placed, as shown in Figure 36.

6569-026

Rev. 0 | Page 24 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

A

0

MIX

NORMAL

RZ

F

S

06569-027

–10

–20

T(f) (dB)

–30

–40

0.5 1.5 2

Figure 36. Transfer Function for Each Analog Operating Mode

AUXILIARY DACS

Two auxiliary DACs are provided on the AD9741/AD9743/ AD9745/AD9746/AD9747. A functional diagram is shown in

Figure 37. The auxiliary DACs are current output devices with two output pins, AUXP and AUXN. The active pin can be programmed to either source or sink current. When either sinking or sourcing, the full-scale current magnitude is 2 mA. The available compliance range at the auxiliary DAC outputs depends on whether the output is configured to a sink or source current. When sourcing current, the compliance voltage is 0 V to 1.6 V, but when sinking current, the output compliance voltage reduces to 0.8 V to 1.6 V. Either output can be used, but only one output of the auxiliary DAC (P or N) is active at any time. The inactive pin is always in a high impedance state (>100 kΩ).

0m

TO

2mA

V

BIAS

0mA

TO

2mA

SINK

OR

SOURCE

POSITIVE

OR

NEGATI VE

Figure 37. Auxiliary DAC Functional Diagram

In a single side band transmitter application, the combination of the input referred dc offset voltage of the quadrature modulator and the DAC output offset voltage can result in local oscillator (LO) feedthrough at the modulator output, which degrades system performance. The auxiliary DACs can be used to remove the dc offset and the resulting LO feedthrough. The circuit configuration for using the auxiliary DACs for performing dc offset correction depends on the details of the DAC and modulator interface. An example of a dc-coupled configuration with low-pass filtering is outlined in the

Power Dissipation

section.

AUXP

AUXN

06569-035

QUADRATURE

MODULATOR V+

AD9747

DAC1 OR

DAC2

25Ω TO 50Ω

AUX

DAC1 OR

DAC2

OPTIONAL

PASSIVE

FILTERING

QUAD MOD I OR Q INPUTS

25Ω TO 50Ω

06569-029

Figure 38. DAC DC Coupled to Quadrature Modulator with Passive DC Shift

POWER DISSIPATION

Figure 39 shows the power dissipation and current draw of the AD9741/AD9743/AD9745/AD9746/AD9747. It shows that the devices have a quiescent power dissipation of about 190 mW. Most of this comes from the AVDD33 supply. Total power dissipation increases about 50% as the clock rate is increased to the maximum clock rate of 250 MHz.

350

310

f

= NYQUIST

OUT

270

(mW)

TOTAL

230

P

190

150

0 50 100 150 200 250

25 75 125 175 225

f

DAC

Figure 39. AD9747 Power Dissipation vs. f

15

12

9

(mA)

6

DVDD33

I

3

0

0 50 100 150 200 250

25 75 125 175 225

AD9747

f

DAC

(MHz)

Figure 40. DVDD33 Current vs. f

(MHz)

f

OUT

AD9741

= DC

DAC

06569-030

06569-031

DAC

Rev. 0 | Page 25 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

30

24

18

(mA)

12

DVDD18

I

AD9747

AD9741

Figure 43 shows the power consumption for each power supply domain as well as the total power consumption. Individual bars within each group display the power in full active mode (blue) vs. power for five increasing levels of power-down.

350

FULL ACTIVE DCO OFF AUX OF F

300

DAC OFF CLK OFF BIAS OFF

250

6

0

0 50 100 150 200 250

25 75 125 175 225

Figure 41. DVDD18 Current vs. f

15

13

11

(mA)

9

CVDD18

I

7

5

0 50 100 150 200 250

25 75 125 175 225

Figure 42. CVDD18 Current vs. f

f

(MHz)

DAC

f

(MHz)

DAC

200

(mW)

150

DISS

P

06569-032

100

50

0

AVDD33 DVDD18 CV DD18 DVDD33 TOT PWR

06569-045

Figure 43. Power Dissipation vs. Power-Down Mode

The overall power consumption is dominated by AVDD33 and significant power savings can be achieved simply by disabling the DAC outputs. Also, disabling the DAC outputs is a significant way to conserve power and still maintain a fast wake-up time. Full power-down disables all circuitry for minimum power consumption. Note, however, that even in full powerdown, there is a small power draw (25 mW) due to incoming data activity. To lower power consumption to near zero, all incoming data activity must be halted.

06569-033

Rev. 0 | Page 26 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

C

OUTLINE DIMENSIONS

0.60

0.42

0.24

55

54

(BOTTOM VIEW)

EXPOSED

PAD

72

1

PIN 1 INDICATOR

4.70

BSC SQ

INDI

PIN 1

ATOR

10.00

BSC SQ

TOP VIEW

9.75

BSC SQ

0.60

0.42

0.24

0.50 BSC

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.30

0.23

0.18 COMPLIANT TO JEDEC S TANDARDS MO-220-VNND-4

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

37

36

8.50 REF

18

19

EXPOSED PAD MUST BE SOLDERED TO PCB AND CONNECT ED TO AVSS.

111507-A

Figure 44. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

10 mm × 10 mm, Very Thin Quad

(CP-72-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9741BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9741BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9743BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9743BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9745BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9745BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9746BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9746BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9747BCPZ1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9747BCPZRL1 −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1 AD9741-EBZ1 Evaluation Board AD9743-EBZ1 Evaluation Board AD9745-EBZ1 Evaluation Board AD9746-EBZ1 Evaluation Board AD9747-EBZ1 Evaluation Board

1

Z = RoHS Compliant Part.

Rev. 0 | Page 27 of 28

AD9741/AD9743/AD9745/AD9746/AD9747

NOTES

Rev. 0 | Page 28 of 28

Datasheet AD9743 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL AND TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

SERIAL PERIPHERAL INTERFACE

GENERAL OPERATION OF THE SERIAL INTERFACE

INSTRUCTION BYTE

MSB/LSB TRANSFERS

SERIAL INTERFACE PORT PIN DESCRIPTIONS

Chip Select Bar (CSB)

Serial Clock (SCLK)

Serial Data Out (SDO)

SPI REGISTER MAP

SPI REGISTER DESCRIPTIONS

DIGITAL INPUTS AND OUTPUTS

INPUT DATA TIMING

DUAL-PORT MODE TIMING

SINGLE-PORT MODE TIMING

SPI PORT, RESET, AND PIN MODE

DRIVING THE DAC CLOCK INPUT

FULL-SCALE CURRENT GENERATION

DAC TRANSFER FUNCTION

ANALOG MODES OF OPERATION

AUXILIARY DACS

Power Dissipation

OUTLINE DIMENSIONS

ORDERING GUIDE