Page 1
K
12-Bit, 210 MSPS
FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SNR @ 5 MHz output, 125 MSPS: 70 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.2 V Reference
CMOS compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP
packages
Edge-triggered latches
TxDAC
®
D/A Converter
APPLICATIONS
Wideband communication transmit channel:
Direct IF
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
R
SET
CLOC
0.1µF
3.3V
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
REFLO
SEGMENTED
SWITCHES
150pF
LATCHES
AVDD ACOM
CURRENT
SOURCE
ARRAY
LSB
SWITCHES
AD9742
AD9742
IOUTA
IOUTB
MODE
GENERAL DESCRIPTION
The AD97421 is a 12-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface
options, small outline package, and pinout, providing an upward
or downward component selection path based on performance,
resolution, and cost. The AD9742 offers exceptional ac and dc
performance while supporting update rates up to 210 MSPS.
The AD9742’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SLEEP
DIGITAL DATA INPUTS (DB11–DB0)
Figure 1.
Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a
complete monolithic DAC solution. The digital inputs support
3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. The AD9742 is the 12-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
2. Data input supports twos complement or straight binary
data coding.
3. High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9742 includes a 1.2 V
temperature compensated band gap voltage reference.
6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and
32-lead LFCSP packages.
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
02913-B-001
Page 2
AD9742
TABLE OF CONTENTS
Specifications..................................................................................... 3
REVISION HISTORY
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Te r m in o l o g y ...................................................................................... 8
Typical Performance Characteristics............................................. 9
Functional Description ..................................................................12
Reference Operation ..................................................................12
Reference Control Amplifier..................................................... 13
DAC Transfer Function ............................................................. 13
Analog Outputs........................................................................... 13
Digital Inputs ..............................................................................14
Clock Input.................................................................................. 14
DAC Timing................................................................................ 15
Power Dissipation....................................................................... 15
Applying the AD9742 ................................................................ 16
Differential Coupling Using a Transformer................................16
Differential Coupling Using an Op Amp................................ 16
Single-Ended, Unbuffered Voltage Output ............................. 17
Single-Ended, Buffered Voltage Output Configuration ........ 17
Power and Grounding Considerations, Power Supply
Rejection
...................................................................................... 17
6/04—Data Sheet Changed from Rev. A to Rev. B
Changes to the Title.................................................................................1
Changes to General Description............................................................1
Changes to Product Highlights..............................................................1
Changes to Dynamic Specifications...................................................... 4
Changes to Figures 6 and 10...................................................................9
Changes to Figures 12 to 15 .................................................................10
Changes to the Functional Description Section................................12
Changes to the Digital Inputs Section ................................................14
Changes to Figure 29.............................................................................15
Changes to Figure 30.............................................................................16
5/03—Data Sheet Changed from Rev. 0 to Rev. A
Added 32-Lead LFCSP Package ........................................... Universal
Edits to Features..................................................................................... 1
Edits to Product Highlights.................................................................. 1
Edits to DC Specifications.................................................................... 2
Edits to Dynamic Specifications.......................................................... 3
Edits to Digital Specifications .............................................................. 4
Edits to Absolute Maximum Ratings.................................................. 5
Edits to Thermal Characteristics......................................................... 5
Edits to Ordering Guide .......................................................................5
Edits to Pin Configuration ................................................................... 6
Edits to Pin Function Descriptions..................................................... 6
Edits to Figure 2..................................................................................... 7
Replaced TPCs 1, 4, 7, and 8 ................................................................ 8
Edits to Figure 3................................................................................... 10
Edits to Functional Description Section .......................................... 10
Added Clock Input Section................................................................ 12
Added Figure 7..................................................................................... 12
Edits to DAC Timing Section ............................................................ 12
Edits to Sleep Mode Operation Section............................................ 13
Edits to Power Dissipation Section................................................... 13
Renumbered Figures 8 to 26 .............................................................. 13
Added Figure 11................................................................................... 13
Added Figures 27 to 35 ....................................................................... 21
Updated Outline Dimensions............................................................ 26
5/02—Revision 0: Initial Version
Evaluation Board ............................................................................ 19
General Description................................................................... 19
Outline Dimensions ....................................................................... 29
Ordering Guide........................................................................... 30
Rev. B | Page 2 of 32
Page 3
AD9742
SPECIFICATIONS
DC SPECIFICATIONS
T
to T
MIN
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 12 Bits
DC ACCURACY1
Integral Linearity Error (INL) −2.5 ±0.5 +2.5 LSB
Differential Nonlinearity (DNL) −1.3 ±0.4 +1.3 LSB
ANALOG OUTPUT
Offset Error −0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Full-Scale Output Current2 2 20 mA
Output Compliance Range −1 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (Ext. Reference) 1 MΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation4 135 145 mW
Power Dissipation
Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V
Power Supply Rejection Ratio—DVDD6 −0.04 +0.04 % of FSR/V
OPERATING RANGE −40 +85 °C
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
5
Measured as unbuffered voltage output with I
6
±5% power supply variation.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 20 mA, unless otherwise noted.
OUTFS
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V
) 33 36 mA
AVDD
)4 8 9 mA
DVDD
) 5 6 mA
CLKVDD
) 5 6 mA
AVDD
5
= 25 MSPS and f
CLOCK
, is 32 times the I
OUTFS
= 1 MHz.
OUT
current.
REF
= 20 mA and 50 Ω R
OUTFS
at IOUTA and IOUTB, f
LOAD
145 mW
= 100 MSPS and f
CLOCK
= 40 MHz.
OUT
Rev. B | Page 3 of 32
Page 4
AD9742
DYNAMIC SPECIFICATIONS
T
to T
MIN
minated, unless otherwise noted.
Table 2
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (tST) (to 0.1%)1 11 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)1 2.5 ns
Output Fall Time (10% to 90%)1 2.5 ns
Output Noise (I
Output Noise (I
Noise Spectral Density3 −152 dBm/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
Spurious-Free Dynamic Range within a Window
Total Harmonic Distortion
Signal-to-Noise Ratio
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
) 210 MSPS
CLOCK
= 20 mA)2 50 pA/√Hz
OUTFS
= 2 mA)2 30 pA/√Hz
OUTFS
f
= 25 MSPS; f
CLOCK
= 1.00 MHz
OUT
= 20 mA, differential transformer coupled output, 50 Ω doubly ter-
OUTFS
0 dBFS Output 74 84 dBc
−6 dBFS Output 85 dBc
−12 dBFS Output 82 dBc
−18 dBFS Output 76 dBc
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
= 1.00 MHz 85 dBc
OUT
= 2.51 MHz 83 dBc
OUT
= 10 MHz 80 dBc
OUT
= 15 MHz 75 dBc
OUT
= 25 MHz 74 dBc
OUT
= 21 MHz 72 dBc
OUT
= 41 MHz 60 dBc
OUT
= 40 MHz 67 dBc
OUT
= 69 MHz 60 dBc
OUT
= 1.00 MHz; 2 MHz Span 80 dBc
OUT
= 5.02 MHz; 2 MHz Span 90 dBc
OUT
= 5.03 MHz; 2.5 MHz Span 90 dBc
OUT
= 5.04 MHz; 4 MHz Span 90 dBc
OUT
= 1.00 MHz −82 −74 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 20 mA 78 dB
OUTFS
= 5 mA 86 dB
OUTFS
= 20 mA 73 dB
OUTFS
= 5 mA 78 dB
OUTFS
= 20 mA 69 dB
OUTFS
= 5 mA 71 dB
OUTFS
= 20 mA 69 dB
OUTFS
= 5 mA 66 dB
OUTFS
Rev. B | Page 4 of 32
Page 5
AD9742
Parameter Min Typ Max Unit
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
f
= 78 MSPS; f
CLOCK
0 dBFS Output 65 dBc
−6 dBFS Output 67 dBc
−12 dBFS Output 65 dBc
−18 dBFS Output 63 dBc
1
Measured single-ended into 50 Ω load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
T
to T
MIN
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS1
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 µA
Logic 0 Current −10 +10 µA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (t
CLK INPUTS2
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
1
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2
Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 15.0 MHz to 18.2 MHz
OUT
= 20 mA, unless otherwise noted.
OUTFS
) 1.5 ns
LPW
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
H
t
LPW
t
ST
0.1%
02912-B-002
Figure 2. Timing Diagram
Rev. B | Page 5 of 32
Page 6
AD9742
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD ACOM −0.3 +3.9 V
DVDD DCOM −0.3 +3.9 V
CLKVDD CLKCOM −0.3 +3.9 V
ACOM DCOM −0.3 +0.3 V
ACOM CLKCOM −0.3 +0.3 V
DCOM CLKCOM −0.3 +0.3 V
AVDD DVDD −3.9 +3.9 V
AVDD CLKVDD −3.9 +3.9 V
DVDD CLKVDD −3.9 +3.9 V
CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V
REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V
CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V
Junction
Temperature
Storage
Temperature
Lead Temperature
(10 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may effect
device reliability.
With
Respect to Min Max Unit
150 °C
−65 +150 °C
300 °C
THERMAL CHARACTERISTICS
1
Thermal Resistance
28-Lead 300-Mil SOIC
= 55.9°C/W
θ
JA
28-Lead TSSOP
= 67.7°C/W
θ
JA
32-Lead LFCSP
= 32.5°C/W
θ
JA
1
Thermal impedance measurements were taken on a 4-layer board in still air,
in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or
loss of functionality.
Rev. B | Page 6 of 32
Page 7
AD9742
(
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
)
B
9
8
7
B
B
B
D
D
D
9
0
1
2
3
3
PIN 1
INDICATOR
AD9742
TOP VIEW
1
2
0
1
1
1
+
D
M
K
D
O
L
V
C
C
K
D
L
C
S
M
(
P
M
1
0
E
O
1
1
E
C
B
B
L
D
D
S
D
6
7
5
8
2
2
2
2
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
5
6
4
3
1
1
1
1
–
E
E
M
K
D
D
O
L
O
O
C
C
M
M
K
L
C
C
02912-B-004
(MSB) DB11
(LSB) DB0
1
DB10
2
3
DB9
4
DB8
5
DB7
6
DB6
7
DB5
8
DB4
9
DB3
10
DB2
11
DB1
12
13
NC
14
NC
NC = NO CONNECT
AD9742
TOP VIEW
(Not to Scale)
Figure 3. 28-Lead SOIC and TSSOP Pin Configuration
28
CLOCK
DVDD
27
26
DCOM
25
MODE
24
AVDD
23
RESERVED
22
IOUTA
21
IOUTB
20
ACOM
19
NC
18
FS ADJ
17
REFIO
16
REFLO
15
SLEEP
6
B
D
2
3
DB5 1
DB4 2
DVDD 3
DB3 4
DB2 5
DB1 6
LSB) DB0 7
NC 8
02912-B-003
(Not to Scale)
9
C
N
NC = NO CONNECT
Figure 4. 32-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SOIC/TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Description
1 27 DB11 Most Significant Data Bit (MSB).
2 to 11
28 to 32,
1, 2, 4 to 6
DB10 to
DB1
Data Bits 10 to 1.
12 7 DB0 Least Significant Data Bit (LSB).
13, 14 8, 9 N/C No Internal Connection.
15 25 SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
16 N/A REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
17 23 REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie
REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie
REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.
18 24 FS ADJ Full-Scale Current Output Adjust.
19 N/A NC No Internal Connection.
20 19, 22 ACOM Analog Common.
21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 N/A RESERVED Reserved. Do not connect to common or supply.
24 17, 18 AVDD Analog Supply Voltage (3.3 V).
25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
N/A 15 CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and
float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations
on-chip).
26 10, 26 DCOM Digital Common.
27 3 DVDD Digital Supply Voltage (3.3 V).
28 N/A CLOCK Clock Input. Data latched on positive edge of clock.
N/A 12 CLK+ Differential Clock Input.
N/A 13 CLK− Differential Clock Input.
N/A 11 CLKVDD Clock Supply Voltage (3.3 V).
N/A 14 CLKCOM Clock Common.
Rev. B | Page 7 of 32
Page 8
AD9742
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious
signal in the region of a removed tone.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
DVDD
DCOM
0.1µF
R
SET
2kΩ
50Ω
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
3.3V
REFLO
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
CLOCK
OUTPUT
Figure 5. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages)
150pF
CURRENT SOURCE
SEGMENTED SWITCHES
FOR DB11–DB3
LATCHES
DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
PMOS
ARRAY
3.3V
AVDD ACOM
AD9742
LSB
SWITCHES
MINI-CIRCUITS
IOUTA
IOUTB
MODE
50Ω
T1-1T
50Ω
*AWG2021 CLOCK RETIMED
SO THAT THE DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
02912-B-005
Rev. B | Page 8 of 32
Page 9
AD9742
TYPICAL PERFORMANCE CHARACTERISTICS
95
90
85
80
65MSPS
75
210MSPS
70
65
SFDR (dBc)
60
55
50
45
1 10 100
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
–12dBFS
0 5 10 15 20 25
0 5 10 15 20 25 30 35 40 45
125MSPS
165MSPS
125MSPS (LFCSP)
f
OUT
Figure 6. SFDR vs . f
f
OUT
Figure 7. SFDR vs . f
f
OUT
Figure 8. SFDR vs . f
210MSPS (LFCSP)
(MHz)
@ 0 dBFS
OUT
0dBFS
–6dBFS
(MHz)
@ 65 MSPS
OUT
(MHz)
@ 125 MSPS
OUT
165MSPS (LFCSP)
–6dBFS
–12dBFS
0dBFS
02912-B-006
02912-B-009
02912-B-012
95
0dBFS
90
85
80
75
–12dBFS
70
65
SFDR (dBc)
–12dBFS (LFCSP)
60
55
50
45
Figure 9. SFDR vs . f
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
0dBFS (LFCSP)
–12dBFS
010 3020 40 50 60 70
Figure 10. SFDR vs. f
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
0 5 10 15 20 25
Figure 11. SFDR vs. f
–6dBFS (LFCSP)
–6dBFS
20 300 10 405060
f
–12dBFS (LFCSP)
f
f
and I
OUT
0dBFS (LFCSP)
(MHz)
OUT
@ 165 MSPS
OUT
–6dBFS (LFCSP)
(MHz)
OUT
@ 210 MSPS
OUT
(MHz)
OUT
@ 65 MSPS and 0 dBFS
OUTFS
0dBFS
20mA
10mA
5mA
02912-B-007
–6dBFS
02912-B-054
02912-B-010
Rev. B | Page 9 of 32
Page 10
AD9742
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
–25 –20 –15 –10 –5 0
Figure 12. Single-Tone SFDR vs. A
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
65MSPS
125MSPS
210MSPS
–25 –20 –15 –10 –5 0
Figure 13. Single-Tone SFDR vs. A
80
75
70
65
SNR
60
55
50
25 45 65 85 105 125 145 165 205185
Figure 14. SNR vs. f
20mA
5mA
CLOCK
65MSPS
125MSPS
165MSPS
210MSPS (LFCSP)
(dBFS)
A
OUT
125MSPS (LFCSP)
165MSPS (LFCSP)
210MSPS (LFCSP)
(dBFS)
A
OUT
f
(MHz)
CLOCK
and I
OUTFS
@ f
OUT
@ f
OUT
@ f
OUT
10mA
= 5 MHz and 0 dBFS
210MSPS
= f
OUT
165MSPS
= f
OUT
CLOCK
CLOCK
/11
/5
95
90
85
65MSPS (8.3,10.3)
80
75
70
65
165MSPS (22.6, 24.6)
SFDR (dBc)
60
55
50
45
–25 –20 –15 –10 –5 0
02912-B-013
Figure 15. Dual-Tone IMD vs. A
1.0
0.5
0
ERROR (LSB)
–0.5
–1.0
02912-B-008
10240 2048 3072 4096
78MSPS (10.1,12.1)
125MSPS (16.9, 18.9)
210MSPS (29, 31)
A
(dBFS)
OUT
OUT
CODE
210MSPS (29, 31)
@ f
= f
OUT
CLOCK
/7
02912-B-014
02912-B-015
Figure 16. Typical INL
1.0
0.8
0.6
0.4
0.2
0
–0.2
ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
02912-B-011
10240 2048 3072 4096
CODE
02912-B-017
Figure 17. Typical DNL
Rev. B | Page 10 of 32
Page 11
AD9742
90
85
80
75
70
SFDR (dBc)
65
60
55
50
4MHz
19MHz
49MHz
020–40 –20 40 60 80
TEMPERATURE (°C)
Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS
0
–10
–20
–30
–40
–50
–60
MAGNITUDE (dBm)
–70
–80
–90
–100
1 6 11 16 21 26 31 36
FREQUENCY (MHz)
f
= 78MSPS
CLOCK
f
= 15.0MHz
OUT
SFDR = 79dBc
AMPLITUDE = 0dBFS
Figure 19. Single-Tone SFDR
34MHz
02912-B-019
02912-B-016
0
–10
–20
–30
–40
–50
–60
MAGNITUDE (dBm)
–70
–80
–90
–100
1 6 11 16 21 26 31 36
FREQUENCY (MHz)
f
= 78MSPS
CLOCK
f
= 15.0MHz
OUT1
f
= 15.4MHz
OUT2
SFDR = 77dBc
AMPLITUDE = 0dBFS
Figure 20. Dual-Tone SFDR
0
–10
–20
–30
–40
–50
–60
MAGNITUDE (dBm)
–70
–80
–90
–100
1 6 11 16 21 26 31 36
FREQUENCY (MHz)
f
= 78MSPS
CLOCK
f
= 15.0MHz
OUT1
f
= 15.4MHz
OUT2
f
= 15.8MHz
OUT3
f
= 16.2MHz
OUT4
SFDR = 75dBc
AMPLITUDE = 0dBFS
Figure 21. Four-Tone SFDR
02912-B-018
02912-B-020
3.3V
AVDD
PMOS
CURRENT SOURCE
ARRAY
LSB
SWITCHES
ACOM
AD9742
IOUTA
IOUTB
IOUTB
MODE
IOUTA
V
= V
OUTB
LOAD
OUTA
– V
OUTB
V
R
50Ω
OUTA
LOAD
02912-B-021
DIFF
V
R
50Ω
0.1µF
V
REFIO
R
2kΩ
CLOCK
SET
I
3.3V
REF
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
150pF
SEGMENTED SWITCHES
FOR DB11–DB3
LATCHES
DIGITAL DATA INPUTS (DB11–DB0)
Figure 22. Simplified Block Diagram (SOIC/TSSOP Packages)
Rev. B | Page 11 of 32
Page 12
AD9742
A
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9742. The
AD9742 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I
make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16th of an MSB current source. The remaining LSBs
are binary weighted fractions of the middle bits current sources.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance (i.e., >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD9764 family, with further
refinements to reduce distortion contributed by the switching
transient. This switch architecture also reduces various timing
errors and provides matching complementary drive signals to
the inputs of the differential current switches.
The analog and digital sections of the AD9742 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 210 MSPS, consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R
pin. The external resistor, in combination with both the reference control amplifier and voltage reference ,V
reference current, I
current sources with the proper scaling factor. The full-scale
current, I
). The array is divided into 31 equal currents that
OUTFS
, connected to the full-scale adjust (FS ADJ)
SET
, sets the
REFIO
, which is replicated to the segmented
REF
, is 32 times I
OUTFS
REF
.
REFERENCE OPERATION
The AD9742 contains an internal 1.2 V band gap reference. The
internal reference can be disabled by raising REFLO to AVDD.
It can also be easily overridden by an external reference with no
effect on performance. REFIO serves as either an input or an
output depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the
REFIO pin to ACOM with a 0.1 µF capacitor and connect
REFLO to ACOM via a resistance less than 5 Ω. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference
is shown in Figure 23.
CURRENT
SOURCE
CURRENT
SOURCE
ARRAY
REFERENCE
CONTROL
AMPLIFIER
3.3V
AVDD
ARRAY
3.3V
AVDD
02912-B-022
02912-B-023
OPTIONAL
EXTERNAL
DDITIONAL
LOAD
REF BUFFER
0.1µF
2kΩ
1.2V REF
REFIO
FS ADJ
AD9742
REFLO
150pF
Figure 23. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in
Figure 24. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 µF
compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
REFLO
AVDD
EXTERNAL
REF
1.2V REF
V
REFIO
R
I
SET
REF
V
REFIO/RSET
REFIO
FS ADJ
=
AD9742
Figure 24. External Reference Configuration
150pF
Rev. B | Page 12 of 32
Page 13
AD9742
(
)
(
)
×
=
×
=
(
−
=
(){
}
×
=
RIOUTAV
REFERENCE CONTROL AMPLIFIER
The AD9742 contains a control amplifier that is used to regulate
the full-scale output current, I
configured as a V-I converter, as shown in Figure 24, so that its
current output, I
an external resistor, R
, is determined by the ratio of the V
REF
, as stated in Equation 4. I
SET
the segmented current sources with the proper scale factor to
set I
, as stated in Equation 3.
OUTFS
. The control amplifier is
OUTFS
REFIO
is copied to
REF
and
OUTA
OUTB
Note that the full-scale value of V
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
DIFF
(5)
LOAD
RIOUTBV
(6)
LOAD
and V
OUTA
)
RIOUTBIOUTAV ×
LOAD
should not
OUTB
(7)
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 µA and 625 µA. The wide adjustment span of IOUTFS
provides several benefits. The first relates directly to the power
dissipation of the AD9742, which is proportional to IOUTFS
(see the Power Dissipation section). The second relates to the
20 dB adjustment, which is useful for system gain control
purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9742 provide complementary current
outputs, IOUTA and IOUTB. IOUTA provides a near full-scale
current output, I
4095), while IOUTB, the compleme ntary output, provides no
current. The current output appearing at IOUTA and IOUTB is
a function of both the input code and I
expressed as:
where DAC CODE = 0 to 4095 (i.e., decimal representation).
As mentioned previously, I
current I
, which is nominally set by a reference voltage, V
REF
and external resistor, R
OUTFS
where
, when all bits are high (i.e., DAC CODE =
OUTFS
and can be
OUTFS
ICODEDACIOUTA ×= 4096/ (1)
OUTFS
ICODEDACIOUTB ×−= /40964095 (2)
OUTFS
is a function of the reference
OUTFS
REFIO
. It can be expressed as:
SET
II ×= 32
(3)
REF
Substituting the values of IOUTA, IOUTB, I
REF
, and V
DIFF
can be
expressed as:
CODEDACV
DIFF
()
LOAD
/32
SET
−
VRR
××
REFIO
4096/40952
(8)
Equations 7 and 8 highlight some of the advantages of operating the AD9742 differentially. First, the differential operation
helps cancel common-mode error sources associated with
IOUTA and IOUTB, such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, V
output (i.e., V
, is twice the value of the single-ended voltage
DIFF
OUTA
or V
), thus providing twice the signal
OUTB
power to the load.
Note that the gain drift temperature performance for a singleended (V
OUTA
and V
) or differential output (V
OUTB
DIFF
) of the
AD9742 can be enhanced by selecting temperature tracking
resistors for R
LOAD
and R
due to their ratiometric relationship,
SET
as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
IOUTB may be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, V
load resistor, R
, as described in the DAC Transfer Function
LOAD
section by Equations 5 through 8. The differential voltage, V
,
existing between V
OUTA
and V
, can also be converted to a
OUTB
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9742 is optimum
and specified using a differential transformer-coupled output in
which the voltage swing at IOUTA and IOUTB is limited to
±0.5 V.
OUTA
and V
OUTB
, via a
DIFF
,
RVI /=
REF
REFIO
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
R
LOAD
, that are tied to analog common, ACOM. Note that
LOAD
may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply
(4)
SET
The distortion and noise performance of the AD9742 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the
first-order cancellation of various dynamic common-mode
distortion mechanisms, digital feedthrough, and noise.
Rev. B | Page 13 of 32
Page 14
AD9742
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Since the output currents of IOUTA and IOUTB
are complementary, they become additive when processed differentially. A properly selected transformer will allow the
AD9742 to provide the required power and voltage levels to
different loads.
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (i.e., V
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note that the INL/DNL specifications
for the AD9742 are measured with IOUTA maintained at a virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the
AD9742.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.2 V for an I
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9742 digital section consists of 12 input bit channels
and a clock input. The 12-bit parallel data inputs follow standard positive binary coding, where DB11 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
and V
OUTA
DIGITAL
INPUT
Figure 25. Equivalent Digital Input
) due to the nature of a PMOS
OUTB
. It degrades slightly from its
OUTFS
= 20 mA to 1 V for an I
OUTFS
DVDD
= 2 mA.
OUTFS
02912-B-024
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock quality,
and jitter is a key concern. Any noise or jitter in the clock will
translate directly into the DAC output. Optimal performance
will be achieved if the CLOCK input has a sharp rising edge,
since the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes.
The mode selection is controlled by the CMODE input, as
summarized in Table 6. Connecting CMODE to CLKCOM
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings and the CLK− input is
left floating. If CMODE is connected to CLKVDD, the differential receiver mode is selected. In this mode, both inputs are high
impedance. The final mode is selected by floating CMODE.
This mode is also differential, but internal terminations for
positive emitter-coupled logic (PECL) are activated. There is no
significant performance difference between any of the three
clock input modes.
Table 6. Clock Mode Selection
CMODE Pin Clock Input Mode
CLKCOM Single-Ended
CLKVDD Differential
Float PECL
The single-ended input mode operates in the same way as the
CLOCK input in the 28-lead packages, as described previously.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
Rev. B | Page 14 of 32
Page 15
AD9742
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 26. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
CLK+
CLK–
50Ω 50Ω
V
= 1.3V NOM
TT
Figure 26. Clock Termination in PECL Mode
AD9742
CLOCK
RECEIVER
TO DAC CORE
02912-B-025
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at
which the input data changes. The AD9742 is rising edge
triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the goal
when applying the AD9742 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 27 shows the relationship of SFDR
to clock placement with different sample rates. Note that at the
lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken.
75
70
active pull-down circuit that ensures that the AD9742 remains
enabled if this input is left disconnected. The AD9742 takes less
than 50 ns to power down and approximately 5 µs to power
back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9742 is dependent on
several factors that include:
• The power supply voltages (AVDD, CLKVDD, and DVDD)
• The full-scale current output I
• The update rate f
CLOCK
• The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f
digital input waveform, f
29 shows I
(f
OUT/fCLOCK
DVDD
) for various update rates with DVDD = 3.3 V.
35
30
25
(mA)
20
AVDD
I
15
10
, and the digital supply current, I
AVD D
OUTFS
. Conversely, I
CLOCK
, and digital supply DVDD. Figure
CLOCK
as a function of full-scale sine wave output ratios
OUTFS
. I
DVDD
AVD D
, as shown in Figure 28, and is
is dependent on both the
DVDD
65
60
55
dB
50
45
40
50MHz SFDR
35
–3 –2 2–1 0 1
Figure 27. SFDR vs. Clock Placement @ f
20MHz SFDR
50MHz SFDR
ns
= 20 MHz and 50 MHz
OUT
3
02912-B-026
Sleep Mode Operation
The AD9742 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and temperature range. This mode can be activated by applying a Logic
Level 1 to the SLEEP pin. The SLEEP pin logic threshold is
equal to 0.5 Ω AVDD. This digital input also contains an
Rev. B | Page 15 of 32
0
4 6 8 101214161820
2
Figure 28. I
20
18
16
14
12
(mA)
10
DVDD
I
8
6
4
2
0
0.01 10.1
Figure 29. I
RATIO (f
vs. Ratio @ DVDD = 3.3 V
DVDD
I
OUTFS
AVDD
210MSPS
165MSPS
125MSPS
65MSPS
OUT/fCLOCK
(mA)
vs. I
OUTFS
02912-B-027
)
02912-B-028
Page 16
AD9742
Ω
12
10
DIFF
8
(mA)
CLKVDD
I
APPLYING THE AD9742
Output Configurations
The following sections illustrate some typical output
configurations for the AD9742. Unless otherwise noted, it is
assumed that I
requiring the optimum dynamic performance, a differential
output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential
op amp configuration. The transformer configuration provides
the optimum high frequency performance and is recommended
for any application that allows ac coupling. The differential op
amp configuration is suitable for applications requiring dc
coupling, a bipolar output, signal gain, and/or level shifting
within the bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB are connected to an appropriately sized load resistor, R
configuration may be more suitable for a single-supply system
requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier could be configured as an I-V converter,
thus converting IOUTA or IOUTB into a negative unipolar
voltage. This configuration provides the best dc linearity since
IOUTA or IOUTB is maintained at a virtual ground.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 31. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer,
such as the Mini-Circuits T1–1T, provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios may also be used
PECL
6
4
2
0
0 50 250100 150 200
SE
f
(MSPS)
CLOCK
vs. f
Figure 30. I
OUTFS
CLKVDD
is set to a nominal 20 mA. For applications
LOAD
and Clock Mode
CLOCK
, referred to ACOM. This
02912-B-029
for impedance matching purposes. Note that the transformer
provides ac coupling only.
MINI-CIRCUITS
IOUTA
22
AD9742
21
IOUTB
Figure 31. Differential Output Using a Transformer
T1-1T
OPTIONAL R
DIFF
R
LOAD
02912-B-030
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., V
OUTA
and V
OUTB
) swing
symmetrically around ACOM and should be maintained with
the specified output compliance range of the AD9742. A differential resistor, R
output of the transformer is connected to the load, R
passive reconstruction filter or cable. R
, may be inserted in applications where the
DIFF
LOAD
is determined by the
DIFF
, via a
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across R
DIFF
.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 32. The AD9742 is
configured with two equal load resistors, R
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
AD9742
22
IOUTA
21
IOUTB
Figure 32. DC Differential Coupling Using an Op A mp
C
OPT
225Ω
225Ω
25Ω25Ω
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off a dual
supply since its output is approximately ±1 V. A high speed
amplifier capable of preserving the differential performance of
the AD9742 while meeting other system level objectives (e.g.,
cost or power) should be selected. The op amp’s differential gain,
gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit.
, of 25 Ω. The
LOAD
500
AD8047
500Ω
02912-B-031
Rev. B | Page 16 of 32
Page 17
AD9742
The differential circuit shown in Figure 33 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9742 and the op amp, is also used to level shift the
differential output of the AD9742 to midsupply (i.e., AVDD/2).
500Ω
AD8041
1kΩ
n.
AVDD
The AD8041 is a suitable op amp for this applicatio
AD9742
22
IOUTA
21
IOUTB
C
OPT
Figure 33. Single-Supply DC Differential Coupled Circuit
225Ω
225Ω
1kΩ25Ω25Ω
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 34 shows the AD9742 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated 50 Ω cable since the nominal full-scale current, I
20 mA flows through the equivalent R
R
represents the equivalent load resistance seen by IOUTA
LOAD
of 25 Ω. In this case,
LOAD
or IOUTB. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching R
values of I
OUTFS
and R
can be selected as long as the positive
LOAD
LOAD
compliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL), discussed in the
Analog Outputs section. For optimum INL performance, the
single-ended, buffered voltage output configuration is
suggested.
= 20mA
I
AD9742
IOUTA
IOUTB
Figure 34. 0 V to 0.5 V Unbuffered Voltage Output
OUTFS
22
50Ω
21
25Ω
V
OUTA
= 0V TO 0.5V
50Ω
, of
OUTFS
. Different
02912-B-033
02912-B-032
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION
Figure 35 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9742 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the
Analog Outputs section. Although this single-ended configuration typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slew rate capabilities. U1 provides a negative
unipolar output voltage, and its full-scale output voltage is simply the product of R
set within U1’s voltage output swing capabilities by scaling I
and/or R
. An improvement in ac distortion performance may
FB
result with a reduced I
and I
FB
OUTFS
. The full-scale output should be
OUTFS
since U1 will be required to sink less
OUTFS
signal current.
C
OPT
R
FB
200Ω
U1
V
= I
OUTFS
× R
FB
OUT
AD9742
IOUTA
IOUTB
I
= 10mA
OUTFS
22
21
200Ω
Figure 35. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
Many applications seek high speed and high performance
under less than ideal operating conditions. In these application
circuits, the implementation and construction of the printed
circuit board is as important as the circuit design. Proper RF
techniques must be used for device selection, placement, and
routing as well as power supply bypassing and grounding to
ensure optimum performance. Figure 40 to Figure 43
illustrate the recommended printed circuit board ground,
power, and signal plane layouts implemented on the AD9742
evaluation board.
02912-B-034
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, I
is common in applications where the power distribution is generated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR versus frequency of the AD9742 AVDD
supply over this frequency range is shown in Figure 36.
Rev. B | Page 17 of 32
. AC noise on the dc supplies
OUTFS
Page 18
AD9742
85
80
75
70
65
60
PSRR (dB)
55
50
45
40
Note that the ratio in Figure 36 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative different size
of these switches, the PSRR is very code dependent. This can
produce a mixing effect that can modulate low frequency power
supply noise to higher frequencies. Worst-case PSRR for either
one of the differential DAC outputs will occur when the fullscale current is directed toward that output. As a result, the
PSRR measurement in Figure 36 represents a worst-case condition in which the digital inputs remain static and the full-scale
output current of 20 mA is directed to the DAC output being
measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s sake (ignoring harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
24
FREQUENCY (MHz)
Figure 36. Power Supply Rejection Ratio (PSRR)
1268100
02912-B-035
appear as current noise superimposed on the DAC’s full-scale
current, I
at 250 kHz. To calculate the PSRR for a given R
, one must determine the PSRR in dB using Figure 36
OUTFS
, such that the
LOAD
units of PSRR are converted from A/V to V/V, adjust the curve in
Figure 36 by the scaling factor 20 Ω log (R
is 50 Ω, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC
R
LOAD
at 250 kHz, which is 85 dB in Figure 36, becomes 51 dB V
). For instance, if
LOAD
OUT/VIN
).
Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9742
features separate analog and digital supplies and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, AVDD, the analog supply, should be
decoupled to ACOM, the analog common, as close to the chip
as physically possible. Similarly, DVDD, the digital supply,
should be decoupled to DCOM as close to the chip as physically
possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 37. The circuit consists of a differential LC filter with separate power supply and
return lines. Lower noise can be attained by using low ESR type
electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
100µF
ELECT.
10µF–22µF
TANT.
Figure 37. Differential LC Filter for Single 3.3 V Applications
0.1µF
CER.
AVDD
ACOM
02912-B-036
Rev. B | Page 18 of 32
Page 19
AD9742
EVALUATION BOARD
GENERAL DESCRIPTION
The TxDAC family evaluation boards allow for easy setup and
testing of any TxDAC product in the SOIC and LFCSP packages. Careful attention to layout and circuit design, combined
with a prototyping area, allows the user to evaluate the AD9742
easily and effectively in any application where high resolution,
high speed conversion is required.
This board allows the user the flexibility to operate the AD9742
in various configurations. Possible output configurations
include transformer coupled, resistor terminated, and single and
differential outputs. The digital inputs are designed to be driven
from various word generators, with the on-board option to add
a resistor network for proper load termination. Provisions are
also made to operate the AD9742 with either the internal or
external reference or to exercise the power-down feature.
J1
21
4
65
87
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
RIBBON
TB1 1
C7
0.1µF
TB1 2
TB1 3
C9
0.1µF
TB1 4
3
L2 BEAD
BLK
TP4
L3 BEAD
BLK
TP6
JP3
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
RED
TP2
C4
+
10µF
25V
C5
+
10µF
25V
RED
TP5
C6
0.1µF
C8
0.1µF
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
DVDD
BLK BLK
AVDD
BLK BLK
TP7
TP10
DCOM
2R13R24R35R46R57R68R79
1
2R13R24R35R46R57R68R79
1
DCOM
TP8
TP9
RP5
R8
R9
OPT
10
RP3 22Ω
RP3 22Ω
RP3 22Ω
3
RP3 22Ω
4
RP3 22Ω
5
RP3 22Ω
6
RP3 22Ω
7
RP3 22Ω
8
RP4 22Ω
1
RP4 22Ω
2
RP4 22Ω
3
RP4 22Ω
4
RP4 22Ω
5
RP4 22Ω
6
RP4 22Ω
7
RP4 22Ω
10
RP6
OPT
R8
R9
DCOM
2R13R24R35R46R57R68R79
1
161
152
14
13
12
11
10
9
16
15
14
13
12
11
10
98
2R13
1
2
R
DCOM
4R35R46R57R68R79
RP1
R9
R8
OPT
10
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CKEXT
10
RP2
OPT
R8
R9
02912-B-037
Figure 38. SOIC Evaluation Board—Power Supply and Digital Inputs
Rev. B | Page 19 of 32
Page 20
AD9742
C
AVDD
+
C14
10µF
16V
C16
0.1µF
C17
0.1µF
CUT
UNDER DUT
JP6
DVDD
KEXT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
R1
2kΩ
R5
OPT
REF
DVDD
R4
50Ω
TP3
WHT
C11
0.1µF
CLOCK
AVDD
S5
C1
0.1µF
R2
10kΩ
DVDD
JP2
MODE
C2
0.1µF
JP10
1
3
A
1
B
2
OPT
2
AB
JP11
C13
C12
OPT
3
3
2
1
R10
50Ω
R11
50Ω
JP8
T1
T1-1T
JP9
IOUT
4
5
6
S3
02912-B-038
IX
S2
IOUTA
R6
OPT
S1
IOUTB
IY
+
C15
C18
0.1µF
JP4
U1
3
INT
C19
0.1µF
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
SLEEP
TP11
WHT
CLOCK
TP1
DVDD
AVDD
R3
10kΩ
WHT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10µF
16V
1
DB13
2
DB12
3
DB11
4
DB10
5
DB9
6
DB8
7
DB7
8
DB6
AD9742
9
DB5
10
DB4
11
DB3
12
DB2
13
DB1
14
DB0
2
AB
1
JP5
EXT
REF
Figure 39. SOIC Evaluation Board—Output Signal Conditioning
Rev. B | Page 20 of 32
Page 21
AD9742
Figure 40. SOIC Evaluation Board—Primary Side
02912-B-039
Figure 41. SOIC Evaluation Board—Secondary Side
Rev. B | Page 21 of 32
02912-B-040
Page 22
AD9742
Figure 42. SOIC Evaluation Board—Ground Plane
02912-B-041
Figure 43. SOIC Evaluation Board—Power Plane
Rev. B | Page 22 of 32
02912-B-042
Page 23
AD9742
Figure 44. SOIC Evaluation Board Assembly—Primary Side
02912-B-043
Figure 45. SOIC Evaluation Board Assembly—Secondary Side
Rev. B | Page 23 of 32
02912-B-044
Page 24
AD9742
TB1 1
TB1 2
TB3 1
TB3 2
TB4 1
TB4 2
C3
0.1µF
C7
0.1µF
C9
0.1µF
L1
L2
L3
BLK
BLK
BLK
BEAD
TP2
BEAD
TP4
BEAD
TP6
C2
10µF
6.3V
C4
10µF
6.3V
C5
10µF
6.3V
RED
RED
RED
TP12
TP13
TP5
C10
0.1µF
C6
0.1µF
C8
0.1µF
CVDD
DVDD
AVDD
HEADER STRAIGHT UP MALE NO SHROUD
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
JP3
CKEXTX
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
R20
R19
R18
R17
R16
R15
R4
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
R3
100Ω
R21
100Ω
100Ω
R24
100Ω
100Ω
R25
100Ω
100Ω
R26
100Ω
100Ω
100Ω
R27
100Ω
100Ω
R28
100Ω
100Ω
1 RP3
2 RP3
3 RP3
4 RP3
5 RP3
6 RP3
7 RP3
8 RP3
1 RP4
2 RP4
3 RP4
4 RP4
5 RP4
6 RP4
7 RP4
8 RP4
22Ω 16
22Ω 15
22Ω 14
22Ω 13
22Ω 12
22Ω 11
22Ω 10
22Ω 9
22Ω 16
22Ω 15
22Ω 14
22Ω 13
22Ω 12
22Ω 11
22Ω 10
22Ω 9
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CKEXT
02912-B-045
Figure 46. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs
Rev. B | Page 24 of 32
Page 25
AD9742
A
CMODE
TP7
WHT
MODE
DB7
DB6
DVDD
DB5
DB4
DB3
DB2
DB1
DB0
CVDD
CLK
CLKB
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
R30
10kΩ
DB7
DB6
DVDD
DB5
DB4
DB3
DB2
DB1
DB0
DCOM
CVDD
CLK
CLKB
CCOM
CMODE
MODE
AD9744LFCSP
VDD
SLEEP
TP11
WHT
R29
32
DB8
DB9
DB10
DB11
DB12
DB13
DCOM1
SLEEP
FS ADJ
REFIO
U1
ACOM
ACOM1
AVDD
AVDD1
CVDD
JP1 0.1%
DB8
31
DB9
30
DB10
29
DB11
28
DB12
27
DB13
26
25
24
23
22
21
IA
20
IB
19
18
17
10kΩ
AVDD
TP3
WHT
C11
0.1µF
C17
TP1
WHT
R1
2kΩ
0.1µF
DVDD CVDD
C19
C19
0.1
0.1µF
R11
50Ω
DNP
C13
JP8
DNP
C12
3
2
1
T1 – 1T
JP9
R10
50Ω
4
T1
5
6
IOUT
S3
AGND: 3, 4, 5
C32
0.1µF
02912-B-046
Figure 47. LFCSP Evaluation Board Schematic— Output Signal Conditioning
C20
10µF
16V
CVDD
R6
50Ω
C35
0.1µF
S5
AGND: 3, 4, 5
02912-B-047
CLKB
CKEXT
CLK
AGND: 5
CVDD: 8
U4
1
U4
2
CVDD
R5
120Ω
6
R2
120Ω
JP2
7
3
4
AGND: 5
CVDD: 8
Figure 48. LFCSP Evaluation Board Schematic— Clock Input
C34
0.1µF
Rev. B | Page 25 of 32
Page 26
AD9742
Figure 49. LFCSP Evaluation Board Layout—Primary Side
02912-B-048
02912-B-049
Figure 50. LFCSP Evaluation Board Layout—Secondary Side
Rev. B | Page 26 of 32
Page 27
AD9742
02912-B-050
Figure 51. LFCSP Evaluation Board Layout—Ground Plane
02912-B-051
Figure 52. LFCSP Evaluation Board Layout—Power Plane
Rev. B | Page 27 of 32
Page 28
AD9742
02912-B-052
Figure 53. LFCSP Evaluation Board Layout Assembly—Primar y Side
02912-B-053
Figure 54. LFCSP Evaluation Board Layout Assembly—Secondary Side
Rev. B | Page 28 of 32
Page 29
AD9742
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
PIN 1
0.15
0.05
COPLANARITY
0.10
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153AE
1.20 MAX
SEATING
PLANE
15
4.50
4.40
4.30
0.20
0.09
6.40 BSC
8°
0°
0.75
0.60
0.45
141
Figure 55. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
18.10 (0.7126)
17.70 (0.6969)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
28 15
1
1.27 (0.0500)
BSC
0.51 (0.0201)
0.33 (0.0130)
14
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.32 (0.0126)
0.23 (0.0091)
0.75 (0.0295)
0.25 (0.0098)
8°
0°
× 45°
1.27 (0.0500)
0.40 (0.0157)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AE
Figure 56. 28-Lead Standard Small Outline Package [SOIC]
Wide Body (R-28)
Dimensions shown in millimeters and (inches)
Rev. B | Page 29 of 32
Page 30
AD9742
1.00
0.85
0.80
12° MAX
SEATING
PLANE
5.00
BSC SQ
PIN 1
INDICATOR
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
0.60 MAX
0.50
4.75
BSC SQ
0.05 MAX
0.02 NOM
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
BSC
0.50
0.40
0.30
COPLANARITY
0.08
0.60 MAX
25
24
17
16
BOTTOM
VIEW
32
9
1
8
3.50 REF
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
0.25 MIN
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body (CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Models Temperature Range Package Description Package Options
AD9742AR −40°C to +85°C 28-Lead 300-Mil SOIC R-28
AD9742ARRL −40°C to +85°C 28-Lead 300-Mil SOIC R-28
AD9742ARZ2 −40°C to +85°C 28-Lead 300-Mil SOIC R-28
AD9742ARZRL2 −40°C to +85°C 28-Lead 300-Mil SOIC R-28
AD9742ARU −40°C to +85°C 28-Lead TSSOP RU-28
AD9742ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28
AD9742ARUZ2 −40°C to +85°C 28-Lead TSSOP RU-28
AD9742ARUZRL72 −40°C to +85°C 28-Lead TSSOP RU-28
AD9742ACP −40°C to +85°C 32-Lead LFCSP CP-32-2
AD9742ACPRL7 −40°C to +85°C 32-Lead LFCSP CP-32-2
AD9742ACPZ2 −40°C to +85°C 32-Lead LFCSP CP-32-2
AD9742ACPZRL72 −40°C to +85°C 32-Lead LFCSP CP-32-2
AD9742-EB Evaluation Board (SOIC)
AD9742ACP-PCB Evaluation Board (LFCSP)
1
R = Small Outline IC; RU = Thin Shrink Small Outline Package; CP = Lead Frame Chip Scale Package.
2
Z = Pb-free part.
1
Rev. B | Page 30 of 32
Page 31
AD9742
NOTES
Rev. B | Page 31 of 32
Page 32
AD9742
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
C02912–0–6/04(B)
Rev. B | Page 32 of 32
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