10-Bit, 210 MSPS TxDAC® D/A Converter
FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SNR @ 5 MHz output, 125 MSPS: 65 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.2 V Reference
CMOS-compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP
packages
Edge-triggered latches
APPLICATIONS
Wideband communication transmit channel
Direct IF
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
R
SET
CLOCK
0.1μF
3.3V
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
150pF
SEGMENTED
SWITCHES
LATCHES
DIGITAL DATA INPUTS (DB9–DB0)
Figure 1.
AVDD ACOM
CURRENT
SOURCE
ARRAY
LSB
SWITCHES
AD9740
AD9740
IOUTA
IOUTB
MODE
02911-001
GENERAL DESCRIPTION
The AD97401 is a 10-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path
of communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based
on performance, resolution, and cost. The AD9740 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.
The AD9740’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation
can be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.
Edge-triggered input latches and a 1.2 V temperature-compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V CMOS
logic families.
PRODUCT HIGHLIGHTS
1. The AD9740 is the 10-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
2. Data input supports twos complement or straight binary
data coding.
3. High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9740 includes a 1.2 V
temperature-compensated band gap voltage reference.
6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-
lead LFCSP packages.
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD9740
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Transfer Function ............................................................. 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Dynamic Specifications ............................................................... 5
Digital Specifications ................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Te r mi n ol o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Functional Description ..................................................................13
Reference Operation ..................................................................13
Analog Outputs .......................................................................... 14
Digital Inputs .............................................................................. 15
Clock Input.................................................................................. 15
DAC Timing................................................................................ 16
Power Dissipation....................................................................... 16
Applying the AD9740 ................................................................ 17
Differential Coupling Using a Transformer............................... 17
Differential Coupling Using an Op Amp................................ 18
Single-Ended, Unbuffered Voltage Output............................. 18
Single-Ended, Buffered Voltage Output Configuration........ 18
Power and Grounding Considerations, Power Supply
Rejection...................................................................................... 19
Evaluation Board ............................................................................ 20
General Description................................................................... 20
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 31
Reference Control Amplifier .................................................... 14
Rev. B | Page 2 of 32
AD9740
REVISION HISTORY
12/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to General Description and Product Highlights...........1
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................5
Changes to Table 5 ............................................................................8
Changes to Figure 6.........................................................................10
Inserted Figure 11; Renumbered Sequentially ............................10
Changes to Figure 12, Figure 13, Figure 14, and Figure 15 .......11
Changes to Functional Description and Reference
Operation Sections..........................................................................13
Inserted Figure 23; Renumbered Sequentially ............................13
Changes to DAC Transfer Function Section and Figure 25 ......14
Changes to Digital Inputs Section.................................................15
Changes to Figure 30 and Figure 31 .............................................17
Updated Outline Dimensions........................................................30
Changes to Ordering Guide...........................................................31
5/03—Rev. 0 to Rev. A
Added 32-Lead LFCSP Package....................................... Universal
Edits to Features ................................................................................1
Edits to Product Highlights ............................................................. 1
Edits to DC Specifications ...............................................................2
Edits to Dynamic Specifications .....................................................3
Edits to Digital Specifications..........................................................4
Edits to Absolute Maximum Ratings..............................................5
Edits to Thermal Characteristics ....................................................5
Edits to Ordering Guide................................................................... 5
Edits to Pin Configuration...............................................................6
Edits to Pin Function Descriptions ................................................6
Edits to Figure 2 ................................................................................7
Replaced TPCs 1, 4, 7, and 8............................................................ 8
Edits to Figure 3 ..............................................................................10
Edits to Functional Description Section ......................................10
Edits to Digital Inputs Section.......................................................12
Added Clock Input Section............................................................12
Added Figure 7 ................................................................................12
Edits to DAC Timing Section........................................................12
Edits to Sleep Mode Operation Section .......................................13
Edits to Power Dissipation Section...............................................13
Renumbered Figures 8 to 26..........................................................13
Added Figure 11..............................................................................13
Added Figures 27 to 35...................................................................21
Updated Outline Dimensions........................................................26
5/02—Revision 0: Initial Version
Rev. B | Page 3 of 32
AD9740
SPECIFICATIONS
DC SPECIFICATIONS
T
to T
MIN
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 10 Bits
DC ACCURACY1
Integral Linearity Error (INL) −0.7 ±0.15 +0.7 LSB
Differential Nonlinearity (DNL) −0.5 ±0.12 +0.5 LSB
ANALOG OUTPUT
Offset Error −0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) −2 ±0.1 +2 % of FSR
Gain Error (With Internal Reference) −2 ±0.1 +2 % of FSR
Full-Scale Output Current2 2 20 mA
Output Compliance Range −1 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 7 kΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation5 145 mW
Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V
Power Supply Rejection Ratio—DVDD
OPERATING RANGE −40 +85 °C
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
5
Measured as unbuffered voltage output with I
6
±5% power supply variation.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 20 mA, unless otherwise noted.
OUTFS
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V
) 33 36 mA
AVDD
)4 8 9 mA
DVDD
) 5 6 mA
CLKVDD
) 5 6 mA
4
= 25 MSPS and f
CLOCK
AVDD
, is 32 times the I
OUTFS
= 1 MHz.
OUT
6
current.
REF
= 20 mA, 50 Ω R
OUTFS
at IOUTA and IOUTB, f
LOAD
135 145 mW
−0.04 +0.04 % of FSR/V
= 100 MSPS, and f
CLOCK
= 40 MHz.
OUT
Rev. B | Page 4 of 32
AD9740
DYNAMIC SPECIFICATIONS
T
to T
MIN
terminated, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (tST) (to 0.1%)1 11 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I
Noise Spectral Density3 −143 dBm/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
Spurious-Free Dynamic Range within a Window
Total Harmonic Distortion
Signal-to-Noise Ratio
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
) 210 MSPS
CLOCK
1
1
= 20 mA)2 50 pA/√Hz
f
= 25 MSPS; f
CLOCK
OUTFS
OUTFS
= 2 mA)
2
= 1.00 MHz
OUT
= 20 mA, differential transformer coupled output, 50 Ω doubly
OUTFS
2.5 ns
2.5 ns
30 pA/√Hz
0 dBFS Output 71 79 dBc
−6 dBFS Output 75 dBc
−12 dBFS Output 67 dBc
−18 dBFS Output 61 dBc
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
= 1.00 MHz 84 dBc
OUT
= 2.51 MHz 80 dBc
OUT
= 10 MHz 78 dBc
OUT
= 15 MHz 76 dBc
OUT
= 25 MHz 75 dBc
OUT
= 21 MHz 70 dBc
OUT
= 41 MHz 60 dBc
OUT
= 40 MHz 67 dBc
OUT
= 69 MHz 63 dBc
OUT
= 1.00 MHz; 2 MHz Span 80 dBc
OUT
= 5.02 MHz; 2 MHz Span 90 dBc
OUT
= 5.03 MHz; 2.5 MHz Span 90 dBc
OUT
= 5.04 MHz; 4 MHz Span 90 dBc
OUT
= 1.00 MHz −79 −71 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 20 mA 68 dB
OUTFS
= 5 mA 64 dB
OUTFS
= 20 mA 64 dB
OUTFS
= 5 mA 62 dB
OUTFS
= 20 mA 64 dB
OUTFS
= 5 mA 62 dB
OUTFS
= 20 mA 63 dB
OUTFS
= 5 mA 60 dB
OUTFS
Rev. B | Page 5 of 32
AD9740
Parameter Min Typ Max Unit
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
f
= 78 MSPS; f
CLOCK
0 dBFS Output 65 dBc
−6 dBFS Output 66 dBc
−12 dBFS Output 60 dBc
−18 dBFS Output 55 dBc
1
Measured single-ended into 50 Ω load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
T
to T
MIN
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 μA
Logic 0 Current −10 +10 μA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (t
CLK INPUTS
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
1
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2
Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
1
2
= 15.0 MHz to 18.2 MHz
OUT
= 20 mA, unless otherwise noted.
OUTFS
) 1.5 ns
LPW
DB0–DB9
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
t
ST
LPW
t
H
0.1%
02911-002
Figure 2. Timing Diagram
Rev. B | Page 6 of 32
AD9740
ABSOLUTE MAXIMUM RATINGS
Table 4.
With
Parameter
AVDD ACOM −0.3 +3.9 V
DVDD DCOM −0.3 +3.9 V
CLKVDD CLKCOM −0.3 +3.9 V
ACOM DCOM −0.3 +0.3 V
ACOM CLKCOM −0.3 +0.3 V
DCOM CLKCOM −0.3 +0.3 V
AVDD DVDD −3.9 +3.9 V
AVDD CLKVDD −3.9 +3.9 V
DVDD CLKVDD −3.9 +3.9 V
CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V
REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V
CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V
Junction
Temperature
Storage
Temperature
Range
Lead Temperature
(10 sec)
Respect to
150 °C
−65 +150 °C
300 °C
Min Max Unit
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may effect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300-Mil SOIC
= 55.9°C/W
θ
JA
28-Lead TSSOP
= 67.7°C/W
θ
JA
32-Lead LFCSP
= 32.5°C/W
θ
JA
1
Thermal impedance measurements were taken on a 4-layer board in still air,
in accordance with EIA/JESD51-7.
1
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 32
AD9740
(
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
MSB) DB9
1
2
DB8
3
DB7
4
DB6
5
DB5
6
DB4
DB3
DB2
DB1
DB0
NC
NC
NC REFLO
NC
AD9740
7
TOP VIEW
(Not to Scale)
8
9
10
11
12
13
14
NC = NO CONNECT
Figure 3. 28-Lead SOIC and TSSOP Pin Configuration
28
CLOCK
27
DVDD
26
DCOM
25
MODE
24
AVDD
23
RESERVED
22
IOUTA
21
IOUTB
20
ACOM
19
NC
18
FS ADJ
17
REFIO
16
15
SLEEP
02911-003
DB8
DB9 (MSB)
DB6
DB7
DCOM
DB4
DB5
1
2
29
3
30
3
1DB3
2DB2
3DVDD
4DB1
5DB0
6NC
7NC
8NC
PIN 1
INDICATOR
AD9740
TOP VIEW
(Not to Scale)
9
11
12
10
NC
CLK+
DCOM
CLKVDD
NC = NO CONNECT
SLEEP
26
25
28
27
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
13
14
15
16
–
CLK
MODE
CMODE
CLKCOM
02911-004
Figure 4. 32-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SOIC/TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic Description
1 27 DB9 (MSB) Most Significant Data Bit (MSB).
2 to 9 28 to 32, 1, 2, 4 DB8 to DB1 Data Bits 8 to 1.
10 5 DB0 (LSB) Least Significant Data Bit (LSB).
11 to 14, 19 6 to 9 NC No Internal Connection.
15 25 SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it can be
left unterminated if not used.
16 N/A REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both
internal and external reference operation modes.
17 23 REFIO
Reference Input/Output. Serves as reference input when using external reference.
Serves as 1.2 V reference output when using internal reference. Requires 0.1 μF capacitor
to ACOM when using internal reference.
18 24 FS ADJ Full-Scale Current Output Adjust.
20 19, 22 ACOM Analog Common.
21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 N/A RESERVED Reserved. Do Not Connect to Common or Supply.
24 17, 18 AVDD Analog Supply Voltage (3.3 V).
25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
N/A 15 CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+
and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver
(terminations on-chip).
26 10, 26 DCOM Digital Common.
27 3 DVDD Digital Supply Voltage (3.3 V).
28 N/A CLOCK Clock Input. Data latched on positive edge of clock.
N/A 12 CLK+ Differential Clock Input.
N/A 13 CLK− Differential Clock Input.
N/A 11 CLKVDD Clock Supply Voltage (3.3 V).
N/A 14 CLKCOM Clock Common.
Rev. B | Page 8 of 32
AD9740
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Tem p er at u re Dr i ft
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
3.3V
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
T
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
DVDD
DCOM
R
SET
2kΩ
50Ω
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
0.1μF
3.3V
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
1.2V REF
SEGMENTED SWITCHES
FOR DB9–DB1
CLOCK
OUTPUT
150pF
CURRENT SOURCE
LATCHES
DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
AVDD ACOM
PMOS
ARRAY
LSB
SWITCHES
AD9740
IOUTA
IOUTB
MODE
50Ω
Figure 5. Basic AC Characterization Test Setup (SOIC/TSSOP Packages)
Rev. B | Page 9 of 32
MINI-CIRCUITS
T1-1T
50Ω
*AWG2021 CLOCK RETIMED
SO THAT THE DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
02911-005
AD9740
TYPICAL PERFORMANCE CHARACTERISTICS
95
90
85
80
75
70
SFDR (dBc)
65
60
55
50
45
0 10 100
125MSPS
65MSPS
125MSPS (LFCSP)
f
Figure 6. SFDR vs. f
95
90
85
80
75
70
SFDR (dBc)
65
60
55
50
45
0 5 10 15 20 25
f
Figure 7. SFDR vs. f
95
90
0dBFS
85
80
75
70
SFDR (dBc)
65
60
55
50
45
01052015 3025 4035 45
–12dBFS
f
Figure 8. SFDR vs. f
OUT
OUT
OUT
210MSPS
(MHz)
(MHz)
OUT
(MHz)
OUT
210MSPS (LFCSP)
165MSPS (LFCSP)
165MSPS
@ 0 dBFS
OUT
@ 65 MSPS
@ 125 MSPS
–6dBFS
–12dBFS
–6dBFS
0dBFS
02911-006
02911-007
02911-008
95
90
85
80
75
70
SFDR (dBc)
65
60
55
50
45
95
90
85
80
75
70
SFDR (dBc)
65
60
55
50
45
95
90
85
80
75
70
SFDR (dBc)
65
60
55
50
45
0dBFS
–6dBFS
–12dBFS
02010 30 40 50 60
Figure 9. SFDR vs. f
01051520
Figure 10. SFDR vs. f
0dBFS
–12dBFS
02010 30 40 50 60 70 80
Figure 11. SFDR vs. f
f
(MHz)
OUT
OUT
f
(MHz)
OUT
and I
OUT
OUTFS
0dBFS (LFCSP)
–6dBFS
f
(MHz)
OUT
OUT
@ 165 MSPS
20mA
10mA
5mA
@ 65 MSPS and 0 dBFS
–12dBFS (LFCSP)
–6dBFS (LFCSP)
@ 210 MSPS
02911-009
25
02911-010
02911-054
Rev. B | Page 10 of 32
AD9740
95
90
85
80
75
70
SFDR (dBc)
65
60
55
50
45
–25 –15–20 –10 –5 0
(dBFS)
A
OUT
Figure 12. Single-Tone SFDR vs. A
95
90
85
80
75
70
SFDR (dBc)
65
60
55
50
45
–25 –15–20 –10 –5 0
210MSPS (LFCSP)
210MSPS
125MSPS
A
(dBFS)
OUT
Figure 13. Single-Tone SFDR vs. A
90
65MSPS
@ f
OUT
165MSPS
OUT
165MSPS
210MSPS
OUT
@ f
OUT
210MSPS
(LFCSP)
= f
= f
125MSPS
/11
CLOCK
65MSPS
/5
CLOCK
02911-011
02911-012
95
A
OUT
165MSPS
210MSPS (29, 31)
210MSPS (29, 31) LFCSP
78MSPS
(dBFS)
@ f
OUT
CODE
OUT
= f
CLOCK
125MSPS
85
65MSPS
75
SFDR (dBc)
65
55
45
–25 –15–20 –10 –5 0
Figure 15. Dual-Tone IMD vs. A
0.25
0.15
0.05
–0.05
ERROR (LSB)
–0.15
–0.25
0 512256 768 1024
Figure 16. Typical INL
0.25
/7
02911-015
02911-014
85
80
20mA
75
70
SNR (dB)
65
60
10mA (LFCSP)
55
50
0609030
Figure 14. SNR vs. f
20mA (LFCSP)
5mA
CLOCK
f
CLOCK
and I
5mA (LFCSP)
120 180 210
(MSPS)
@ f
OUTFS
OUT
10mA
150
= 5 MHz and 0 dBFS
02911-013
Rev. B | Page 11 of 32
0.15
0.05
–0.05
ERROR (LSB)
–0.15
–0.25
0 512256 768 1024
CODE
Figure 17. Typical DNL
02911-016
AD9740
90
85
80
75
70
SFDR (dBc)
65
60
49MHz
55
50
–40 0 20–20 40 60 80
34MHz
TEMPERATURE (°C)
Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS
0
f
= 78MSPS
–10
–20
–30
–40
–50
–60
MAGNITUDE (dBm)
–70
–80
–90
–100
111166213126 36
FREQUENCY (MHz)
CLOCK
f
= 15.0MHz
OUT
SFDR = 77dBc
AMPLITUDE = 0dBFS
Figure 19. Single-Tone SFDR
4MHz
19MHz
02911-017
02911-018
0
f
= 78MSPS
–10
–20
–30
–40
–50
–60
MAGNITUDE (dBm)
–70
–80
–90
–100
111166213126 36
FREQUENCY (MHz)
CLOCK
f
= 15.0MHz
OUT1
f
= 15.4MHz
OUT2
SFDR = 77dBc
AMPLITUDE = 0dBFS
Figure 20. Dual-Tone SFDR
0
f
= 78MSPS
–10
–20
–30
–40
–50
–60
MAGNITUDE (dBm)
–70
–80
–90
–100
111166213126 36
FREQUENCY (MHz)
CLOCK
f
= 15.0MHz
OUT1
f
= 15.4MHz
OUT2
f
= 15.8MHz
OUT3
f
= 16.2MHz
OUT4
SFDR = 72dBc
AMPLITUDE = 0dBFS
Figure 21. Four-Tone SFDR
02911-019
02911-020
3.3V
AVDD
PMOS
ARRAY
SWITCHES
LSB
ACOM
AD9740
IOUTA
IOUTB
IOUTB
MODE
IOUTA
V
DIFF
V
R
50Ω
= V
OUTB
LOAD
OUTA
– V
OUTB
V
OUTA
R
LOAD
50Ω
02911-021
0.1μF
V
REFIO
R
2kΩ
CLOCK
SET
I
REF
3.3V
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
SEGMENTED SWITCHES
150pF
FOR DB9–DB1
LATCHES
DIGITAL DATA INPUTS (DB9–DB0)
CURRENT SOURCE
Figure 22. Simplified Block Diagram (SOIC/TSSOP Packages)
Rev. B | Page 12 of 32
AD9740
A
V
A
L
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9740. The
AD9740 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I
). The array is divided into 31 equal currents that
OUTFS
make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16 of an MSB current source. The remaining LSBs are
binary weighted fractions of the middle bits current sources.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance (that is, >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (that is, IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
The analog and digital sections of the AD9740 have separate
power supply inputs (that is, AVDD and DVDD) that can
operate independently over a 2.7 V to 3.6 V range. The digital
section, which is capable of operating at a clock rate of up to
210 MSPS, consists of edge-triggered latches and segment
decoding logic circuitry. The analog section includes the PMOS
current sources, the associated differential switches, a 1.2 V
band gap voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R
, connected to the full-scale adjust
SET
(FS ADJ) pin. The external resistor, in combination with both
the reference control amplifier and voltage reference, V
the reference current, I
, which is replicated to the segmented
REF
REFIO
, sets
current sources with the proper scaling factor. The full-scale
current, I
, is 32 times I
OUTFS
REF
.
REFERENCE OPERATION
The AD9740 contains an internal 1.2 V band gap reference. The
internal reference cannot be disabled, but can be easily overridden
by an external reference with no effect on performance.
shows an equivalent circuit of the band gap reference. REFIO
serves as either an output or an input depending on whether
the internal or an external reference is used. To use the internal
reference, simply decouple the REFIO pin to ACOM with a
0.1 μF capacitor and connect REFLO to ACOM via a resistance
less than 5 Ω. The internal reference voltage is present at
REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, then an external buffer amplifier with an input bias
current of less than 100 nA should be used. An example of the
use of the internal reference is shown in
DD
84µA
7kΩ
REFLO
Figure 23. Equivalent Circuit of Internal Reference
OPTIONAL
EXTERNAL
REF BUFFER
1.2V REF
2kΩ
REFIO
FS ADJ
AD9740
DDITIONA
LOAD
0.1μF
Figure 24. Internal Reference Configuration
REFLO
Figure 24.
REFIO
02911-057
150pF
An external reference can be applied to REFIO, as shown in
Figure 25. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. Note that the
0.1 μF compensation capacitor is not required because the
internal reference is overridden, and the relatively high input
impedance of REFIO minimizes any loading of the external
reference.
Figure 23
3.3V
AVDD
CURRENT
SOURCE
ARRAY
02911-022
Rev. B | Page 13 of 32
AD9740
V
REFLO
1.2V REF
REFIO
FS ADJ
AD9740
Figure 25. External Reference Configuration
150pF
3.3
CURRENT
SOURCE
ARRAY
REFERENCE CONTRO L AMPLI FIER
AVD D
02911-023
REFERENCE CONTROL AMPLIFIER
The AD9740 contains a control amplifier that is used to regulate
the full-scale output current, I
configured as a V-I converter, as shown in
current output, I
an external resistor, R
, is determined by the ratio of the V
REF
, as stated in Equation 4. I
SET
. The control amplifier is
OUTFS
Figure 24, so that its
REFIO
is copied
REF
and
to the segmented current sources with the proper scale factor to
set I
, as stated in Equation 3.
OUTFS
The control amplifier allows a wide (10:1) adjustment span of
over a 2 mA to 20 mA range by setting I
I
OUTFS
62.5 μA and 625 μA. The wide adjustment span of I
between
REF
OUTFS
provides several benefits. The first relates directly to the power
dissipation of the AD9740, which is proportional to I
the
Power Dissipation section). The second relates to a 20 dB
OUTFS
(see
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
The AD9740 provides complementary current outputs, IOUTA
and IOUTB. IOUTA provides a near full-scale current output,
I
, when all bits are high (that is, DAC CODE = 1023), while
OUTFS
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and I
IOUTA = (DAC CODE/1023) × I
IOUTB = (1023 − DAC CODE)/1024 × I
where DAC CODE = 0 to 1023 (that is, decimal representation).
As mentioned previously, I
current I
V
REFIO
, which is nominally set by a reference voltage,
REF
, and external resistor, R
I
OUTFS
= 32 × I
(3)
REF
where
I
REF
= V
REFIO/RSET
(4)
and can be expressed as:
OUTFS
(1)
OUTFS
OUTFS
is a function of the reference
OUTFS
. It can be expressed as:
SET
(2)
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, then IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
R
LOAD
, that are tied to analog common, ACOM. Note that
LOAD
can represent the equivalent load resistance seen by
IOUTA or IOUTB, as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply
= IOUTA × R
V
OUTA
V
= IOUTB × R
OUTB
Note that the full-scale value of V
(5)
LOAD
(6)
LOAD
OUTA
and V
should not
OUTB
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
V
= (IOUTA − IOUTB) × R
DIFF
Substituting the values of IOUTA, IOUTB, I
(7)
LOAD
, and V
REF
DIFF
can be
expressed as:
= {(2 × DAC CODE − 1023)/1024}
V
DIFF
(32 × R
LOAD/RSET
) × V
(8)
REFIO
Equation 7 and Equation 8 highlight some of the advantages of
operating the AD9740 differentially. First, the differential
operation helps cancel common-mode error sources associated
with IOUTA and IOUTB, such as noise, distortion, and dc
offsets. Second, the differential code-dependent current and
subsequent voltage, V
voltage output (that is, V
, is twice the value of the single-ended
DIFF
OUTA
or V
), thus providing twice the
OUTB
signal power to the load.
Note that the gain drift temperature performance for a singleended (V
OUTA
and V
OUTB
) or differential output (VB
DIFF
) of the
AD9740 can be enhanced by selecting temperature tracking
resistors for R
LOAD
and R
due to their ratiometric relationship,
SET
as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA,
and IOUTB can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, V
via a load resistor, R
Function
section by Equation 5 through Equation 8. The
differential voltage, V
, as described in the DAC Transfer
LOAD
, existing between V
DIFF
also be converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance of the
AD9740 is optimum and specified using a differential
transformer-coupled output in which the voltage swing at
IOUTA and IOUTB is limited to ±0.5 V.
The distortion and noise performance of the AD9740 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
OUTA
OUTA
and V
and V
OUTB
OUTB
, can
,
Rev. B | Page 14 of 32
AD9740
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases and/or its amplitude decreases. This is due
to the first-order cancellation of various dynamic commonmode distortion mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when
processed differentially. A properly selected transformer allows
the AD9740 to provide the required power and voltage levels to
different loads.
The output impedance of IOUTA and IOUTB is determined by
the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, V
OUTA
and V
) due to the nature of a PMOS
OUTB
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD9740 are measured with IOUTA maintained at a virtual
ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit can result in a
breakdown of the output stage and affect the reliability of the
AD9740.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.2 V for an I
= 20 mA to 1 V for an I
OUTFS
. It degrades slightly from its
OUTFS
OUTFS
= 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9740 digital section consists of 10 input bit channels
and a clock input. The 10-bit parallel data inputs follow
standard positive binary coding, where DB9 is the most
significant bit (MSB) and DB0 is the least significant bit (LSB).
IOUTA produces a full-scale output current when all data bits
are at Logic 1. IOUTB produces a complementary output with
the full-scale current split between the two outputs as a
function of the input code.
DVDD
DIGITAL
INPUT
02911-024
Figure 26. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges can affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock quality,
and jitter is a key concern. Any noise or jitter in the clock
translates directly into the DAC output. Optimal performance is
achieved if the CLOCK input has a sharp rising edge, because
the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes.
The mode selection is controlled by the CMODE input, as
summarized in
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings and the CLK− input is
left floating. If CMODE is connected to CLKVDD, then the
differential receiver mode is selected. In this mode, both inputs
are high impedance. The final mode is selected by floating
CMODE. This mode is also differential, but internal
terminations for positive emitter-coupled logic (PECL) are
activated. There is no significant performance difference
between any of the three clock input modes.
Table 6. Clock Mode Selection
CMODE Pin Clock Input Mode
CLKCOM Single-ended
CLKVDD Differential
Float PECL
The single-ended input mode operates in the same way as the
clock input in the 28-lead packages, as described previously.
Tabl e 6. Connecting CMODE to CLKCOM
Rev. B | Page 15 of 32
AD9740
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave
because the high gain bandwidth of the differential inputs
converts the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 27. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
AD9740
CLK+
CLK–
50Ω 50Ω
V
TT
Figure 27. Clock Termination in PECL Mode
CLOCK
RECEIVER
= 1.3V NOM
TO DAC CORE
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9740 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9740 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases.
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
Figure 28 shows the relationship of
75
70
65
60
55
dB
50
45
40
50MHz SFDR
35
–3 –2 2–1 0 1
f
20MHz SFDR
50MHz SFDR
ns
Figure 28. SFDR vs. Clock Placement @
= 20 MHz and 50 MHz (f
OUT
= 165 MSPS)
CLOCK
3
02911-026
Sleep Mode Operation
The AD9740 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
02911-025
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9740 remains enabled if this
input is left disconnected. The AD9740 takes less than 50 ns
to power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9740 is dependent on
several factors that include:
• The power supply voltages (AVDD, CLKVDD, and
DVDD)
• The full-scale current output (I
• The update rate (f
CLOCK
)
• The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f
digital input waveform, f
shows I
(f
OUT/fCLOCK
as a function of full-scale sine wave output ratios
DVDD
) for various update rates with DVDD = 3.3 V.
, and the digital supply current, I
AVD D
, as shown in Figure 29, and is
OUTFS
. Conversely, I
CLOCK
, and digital supply DVDD. Figure 30
CLOCK
)
OUTFS
is dependent on both the
DVDD
DVDD
. I
AVD D
Rev. B | Page 16 of 32
AD9740
35
30
25
(mA)
20
AVDD
I
15
10
0
4 6 8 101214161820
2
20
18
16
14
12
(mA)
10
DVDD
I
8
6
4
2
0
0.01 10. 1
Figure 30. I
11
10
9
8
7
6
(mA)
5
CLKVDD
I
4
3
2
1
0
0 15010050 200 250
Figure 31. I
I
(mA)
OUTFS
Figure 29. I
RATIO (f
DVDD
CLKVDD
vs. I
AVDD
210MSPS
165MSPS
125MSPS
65MSPS
OUT/fCLOCK
vs. Ratio @ DVDD = 3.3 V
DIFF
PECL
SE
f
(MSPS)
CLOCK
vs. f
and Clock Mode
CLOCK
OUTFS
02911-027
)
02911-055
02911-056
APPLYING THE AD9740
Output Configurations
The following sections illustrate some typical output
configurations for the AD9740. Unless otherwise noted, it is
assumed that I
is set to a nominal 20 mA. For applications
OUTFS
requiring the optimum dynamic performance, a differential
output configuration is suggested. A differential output
configuration can consist of either an RF transformer or a
differential op amp configuration. The transformer
configuration provides the optimum high frequency
performance and is recommended for any application that
allows ac coupling. The differential op amp configuration is
suitable for applications requiring dc coupling, bipolar output,
signal gain, and/or level shifting within the bandwidth of the
chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to an
appropriately sized load resistor, R
, referred to ACOM.
LOAD
This configuration can be more suitable for a single-supply
system requiring a dc-coupled, ground referred output voltage.
Alternatively, an amplifier could be configured as an I-V
converter, thus converting IOUTA or IOUTB into a negative
unipolar voltage. This configuration provides the best dc linearity
because IOUTA or IOUTB is maintained at a virtual ground.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-
T1-1T
Figure 32. A
DIFF
R
LOAD
02911-030
single-ended signal conversion, as shown in
differentially coupled transformer output provides the
optimum distortion performance for output signals whose
spectral content lies within the transformer’s pass band. An
RF transformer, such as the Mini-Circuits® T1–1T, provides
excellent rejection of common-mode distortion (that is, evenorder harmonics) and noise over a wide frequency range. It also
provides electrical isolation and the ability to deliver twice the
power to the load. Transformers with different impedance ratios
can also be used for impedance matching purposes. Note that
the transformer provides ac coupling only.
MINI-CIRCUITS
IOUTA
22
AD9740
21
IOUTB
OPTIONAL R
Figure 32. Differential Output Using a Transformer
Rev. B | Page 17 of 32
AD9740
Ω
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (that is, V
OUTA
and V
OUTB
)
B
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9740. A
differential resistor, R
the output of the transformer is connected to the load, R
via a passive reconstruction filter or cable. R
, can be inserted in applications where
DIFF
is determined
DIFF
LOAD
,
by the transformer’s impedance ratio and provides the proper
source termination that results in a low VSWR. Note that
approximately half the signal power is dissipated across R
DIFF
.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-singleended conversion, as shown in
configured with two equal load resistors, R
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
AD9740
22
IOUTA
21
IOUTB
Figure 33. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the
differential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
off a dual supply because its output is approximately ±1 V. A
high speed amplifier capable of preserving the differential
performance of the AD9740 while meeting other system level
objectives (that is, cost or power) should be selected. The op
amp’s differential gain, gain setting resistor values, and full-scale
output swing capabilities should all be considered when
optimizing this circuit.
The differential circuit shown in
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9740 and the op amp, is also used to level shift the
differential output of the AD9740 to midsupply (that is,
AVDD/2). The AD8041 is a suitable op amp for this application.
Figure 33. The AD9740 is
225Ω
225Ω
C
OPT
25Ω25Ω
Figure 34 provides the
, of 25 Ω. The
LOAD
AD8047
500Ω
500Ω
02911-031
500
AD9740
22
IOUTA
21
IOUTB
Figure 34. Single-Supply DC Differential Coupled Circuit
C
OPT
225Ω
225Ω
1kΩ25Ω25Ω
AD8041
1kΩ
AVDD
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 35 shows the AD9740 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly
terminated 50 Ω cable because the nominal full-scale current,
I
, of 20 mA flows through the equivalent R
OUTFS
In this case, R
represents the equivalent load resistance seen
LOAD
LOAD
of 25 Ω.
by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
Different values of I
OUTFS
and R
can be selected as long as
LOAD
LOAD
.
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL),
discussed in the
Analog Outputs section. For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
I
= 20mA
AD9740
IOUTA
IOUTB
OUTFS
22
50Ω
21
25Ω
Figure 35. 0 V to 0.5 V Unbuffered Voltage Output
V
OUTA
50Ω
= 0V TO 0.5V
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION
Figure 36 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9740 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the
Outputs
section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates can be
limited by U1’s slew rate capabilities. U1 provides a negative
unipolar output voltage, and its full-scale output voltage is
simply the product of R
and I
FB
. The full-scale output
OUTFS
should be set within U1’s voltage output swing capabilities by
scaling I
performance can result with a reduced I
and/or RFB. An improvement in ac distortion
OUTFS
because U1 is
OUTFS
required to sink less signal current.
Analog
02911-032
02911-033
Rev. B | Page 18 of 32
AD9740
AD9740
IOUTA
IOUTB
I
= 10mA
OUTFS
22
21
200Ω
C
OPT
R
FB
200Ω
U1
V
= I
OUTFS
× R
FB
OUT
Figure 36. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
Many applications seek high speed and high performance
under less than ideal operating conditions. In these application
circuits, the implementation and construction of the printed
circuit board is as important as the circuit design. Proper RF
techniques must be used for device selection, placement, and
routing as well as power supply bypassing and grounding to
ensure optimum performance.
the recommended printed circuit board ground, power, and
signal plane layouts implemented on the AD9740 evaluation
board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, I
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9740 AVDD supply over this frequency range is shown in
Figure 37.
85
80
75
70
65
60
PSRR (dB)
55
50
45
40
24
Figure 37. Power Supply Rejection Ratio (PSRR)
Figure 41 to Figure 44 illustrate
. AC noise on the dc supplies
OUTFS
FREQUENCY (MHz)
1268100
02911-035
Note that the ratio in Figure 37 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, is added in a nonlinear
manner to the desired IOUT. Due to the relative different size of
these switches, the PSRR is very code dependent. This can produce
a mixing effect that can modulate low frequency power supply
02911-034
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs occur when the full-scale current
is directed toward that output.
As a result, the PSRR measurement in
Figure 37 represents a
worst-case condition in which the digital inputs remain static
and the full-scale output current of 20 mA is directed to the
DAC output being measured.
The following illustrates the effect of supply noise on the analog
supply. Suppose a switching regulator with a switching frequency
of 250 kHz produces 10 mV of noise and, for simplicity’s sake
(ignoring harmonics), all of this noise is concentrated at 250 kHz.
To calculate how much of this undesired noise appears as current
noise superimposed on the DAC’s full-scale current, I
must determine the PSRR in dB using
calculate the PSRR for a given R
Figure 37 at 250 kHz. To
, such that the units of PSRR
LOAD
are converted from A/V to V/V, adjust the curve in
the scaling factor 20 Ω log (R
). For instance, if R
LOAD
, users
OUTFS
Figure 37 by
is 50 Ω,
LOAD
then the PSRR is reduced by 34 dB (that is, PSRR of the DAC at
250 kHz, which is 85 dB in
Figure 37, becomes 51 dB V
OUT/VIN
).
Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9740 features separate analog and digital supplies and
ground pins to optimize the management of analog and digital
ground currents in a system. In general, AVDD, the analog
supply, should be decoupled to ACOM, the analog common, as
close to the chip as physically possible. Similarly, DVDD, the
digital supply, should be decoupled to DCOM as close to the
chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply can be
generated using the circuit shown in
Figure 38. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
100μF
ELECT.
10μF–22μF
TANT.
Figure 38. Differential LC Filter for Single 3.3 V Applications
0.1μF
CER.
AVDD
ACOM
02911-036
Rev. B | Page 19 of 32
AD9740
EVALUATION BOARD
GENERAL DESCRIPTION
The TxDAC family evaluation boards allow for easy setup and
testing of any TxDAC product in the SOIC and LFCSP packages.
Careful attention to layout and circuit design, combined with a
prototyping area, allows the user to evaluate the AD9740 easily
and effectively in any application where high resolution, high
speed conversion is required.
J1
This board allows the user the flexibility to operate the AD9740
in various configurations. Possible output configurations
include transformer coupled, resistor terminated, and single
and differential outputs. The digital inputs are designed to be
driven from various word generators, with the on-board option
to add a resistor network for proper load termination. Provisions
are also made to operate the AD9740 with either the internal or
external reference or to exercise the power-down feature.
21
4
65
87
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
RIBBON
TB1 1
C7
0.1μF
TB1 2
3
L2 BEAD
BLK
TP4
JP3
+
C4
10μF
25V
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
RED
TP2
C6
0.1μF
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
DVDD
BLK BLK
TP7
DCOM
2R13R24R35R46R57R68R79
1
2R13R24R35R46R57R68R79
1
DCOM
TP8
RP5
R9
R8
OPT
10
RP3 22Ω
RP3 22Ω
RP3 22Ω
3
RP3 22Ω
4
RP3 22Ω
5
RP3 22Ω
6
RP3 22Ω
7
RP3 22Ω
8
RP4 22Ω
1
RP4 22Ω
2
RP4 22Ω
3
RP4 22Ω
4
RP4 22Ω
5
RP4 22Ω
6
RP4 22Ω
7
RP4 22Ω
8
10
RP6
OPT
R8
R9
DCOM
2R13R24R35R46R57R68R79
1
161
152
14
13
12
11
10
9
16
15
14
13
12
11
10
9
2R13
1
2
R
DCOM
4R35R46R57R68R79
RP1
R8
R9
OPT
10
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CKEXT
10
RP2
OPT
R8
R9
TB1 3
TB1 4
C9
0.1μF
L3 BEAD
BLK
TP6
+
C5
10μF
25V
RED
TP5
C8
0.1μF
AVDD
BLK BLK
TP10
TP9
Figure 39. SOIC Evaluation Board—Power Supply and Digital Inputs
Rev. B | Page 20 of 32
02911-037
AD9740
A
V
C
DD
+
C14
10μF
16V
C16
0.1μF
C17
0.1μF
CUT
UNDER DUT
JP6
DVDD
KEXT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
R1
2kΩ
R5
OPT
REF
DVDD
R4
50Ω
TP3
WHT
C11
0.1μF
CLOCK
AVDD
S5
0.1μF
R2
10kΩ
DVDD
JP2
MODE
C2C1
0.1μF
JP10
IOUTA
OPT
S1
1
S2
R6
1
IX
IOUTB
IY
A
2
2
AB
JP11
B
C13
OPT
3
C12
OPT
3
R11
10kΩ
3
2
1
R10
10kΩ
JP8
T1
T1-1T
JP9
IOUT
4
5
6
S3
02911-038
+
C15
10μF
16V
1
DB13
2
DB12
3
DB11
4
DB10
5
DB9
6
DB8
7
DB7
8
DB6
AD9740
9
DB5
10
DB4
11
DB3
12
DB2
13
DB1
14
DB0
2
AB
1
JP5
EXT
REF
C18
0.1μF
JP4
U1
3
INT
C19
0.1μF
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
FS ADJ
REFIO
REFLO
SLEEP
SLEEP
NC
TP11
WHT
CLOCK
TP1
DVDD
AVDD
R3
10kΩ
WHT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 40. SOIC Evaluation Board—Output Signal Conditioning
Rev. B | Page 21 of 32
AD9740
Figure 41. SOIC Evaluation Board—Primary Side
02911-039
Figure 42. SOIC Evaluation Board—Secondary Side
Rev. B | Page 22 of 32
02911-040
AD9740
Figure 43. SOIC Evaluation Board—Ground Plane
02911-041
Figure 44. SOIC Evaluation Board—Power Plane
Rev. B | Page 23 of 32
02911-042
AD9740
Figure 45. SOIC Evaluation Board Assembly—Primary Side
02911-043
Figure 46. SOIC Evaluation Board Assembly—Secondary Side
Rev. B | Page 24 of 32
02911-044
AD9740
TB1 1
TB1 2
TB3 1
TB3 2
TB4 1
TB4 2
C3
0.1μF
C7
0.1μF
C9
0.1μF
L1
L2
L3
BEAD
BLK
BEAD
BLK
BEAD
BLK
TP2
TP4
TP6
C2
10μF
6.3V
C4
10μF
6.3V
C5
10μF
6.3V
RED
RED
RED
TP12
TP13
TP5
C10
0.1μF
C6
0.1μF
C8
0.1μF
CVDD
DVDD
AVDD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
HEADER STRAIGHT UP MALE NO SHROUD
37
39
J1
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
JP3
CKEXTX
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
R3
100Ω
R21
100Ω
R4
100Ω
R24
100Ω
100Ω
R25
100Ω
100Ω
R26
100Ω
100Ω
100Ω
R27
100Ω
100Ω
R28
100Ω
100Ω
1 RP3
2 RP3
3 RP3
4 RP3
5 RP3
6 RP3
7 RP3
8 RP3
1 RP4
2 RP4
3 RP4
4 RP4
5 RP4
6 RP4
7 RP4
8 RP4
22Ω 16
22Ω 15
22Ω 14
22Ω 13
22Ω 12
22Ω 11
22Ω 10
22Ω 9
22Ω 16
22Ω 15
22Ω 14
22Ω 13
22Ω 12
22Ω 11
22Ω 10
22Ω 9
R20
R19
R18
R17
R16
R15
Figure 47. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CKEXT
02911-045
Rev. B | Page 25 of 32
AD9740
A
V
CMODE
TP7
WHT
MODE
DB7
DB6
DVDD
DB5
DB4
DB3
DB2
DB1
DB0
CVDD
CLK
CLKB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R30
10kΩ
DB7
DB6
DVDD
DB5
DB4
DB3
DB2
DB1
DB0
DCOM
CVDD
CLK
CLKB
CCOM
CMODE
MODE
AD9740LFCSP
DD
SLEEP
TP11
WHT
R29
32
DB8
DB9
DB10
DB11
DB12
DB13
DCOM1
SLEEP
FS ADJ
REFIO
U1
ACOM
ACOM1
AVDD
AVDD1
CVDD
JP1 0.1%
DB8
31
DB9
30
DB10
29
DB11
28
DB12
27
DB13
26
25
24
23
22
21
IA
20
IB
19
18
17
AVDD
10kΩ
TP3
WHT
C11
0.1μF
TP1
WHT
R1
2kΩ
C17
0.1μF
DVDD CVDD
C19
C19
0.1μF
R11
50kΩ
DNP
C13
JP8
DNP
C12
3
T1
2
1
T1 – 1T
JP9
R10
50Ω
4
5
6
IOUT
S3
AGND: 3, 4, 5
C32
0.1μF
02911-046
Figure 48. LFCSP Evaluation Board Schematic—Output Signal Conditioning
C20
10μF
16V
CVDD
R6
50Ω
C35
0.1μF
S5
AGND: 3, 4, 5
02911-047
CLKB
CKEXT
CLK
JP2
7
U4
2
AGND: 5
CVDD: 8
CVDD
R5
120Ω
3
1
6
U4
4
AGND: 5
CVDD: 8
R2
C34
0.1μF
120Ω
Figure 49. LFCSP Evaluation Board Schematic—Clock Input
Rev. B | Page 26 of 32
AD9740
02911-048
Figure 50. LFCSP Evaluation Board Layout—Primary Side
02911-049
Figure 51. LFCSP Evaluation Board Layout—Secondary Side
Rev. B | Page 27 of 32
AD9740
02911-050
Figure 52. LFCSP Evaluation Board Layout—Ground Plane
02911-051
Figure 53. LFCSP Evaluation Board Layout—Power Plane
Rev. B | Page 28 of 32
AD9740
Figure 54. LFCSP Evaluation Board Layout Assembly—Primary Side
02911-052
Figure 55. LFCSP Evaluation Board Layout Assembly—Secondary Side
Rev. B | Page 29 of 32
02911-053
AD9740
C
Y
OUTLINE DIMENSIONS
9.80
9.70
9.60
PIN 1
0.15
0.05
OPLANARIT
0.10
28
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AE
1.20 MAX
SEATING
PLANE
15
4.50
4.40
4.30
0.20
0.09
6.40 BSC
8°
0°
0.75
0.60
0.45
141
Figure 56. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
18.10 (0.7126)
17.70 (0.6969)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
28 15
1
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
14
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.33 (0.0130)
0.20 (0.0079)
0.75 (0.0295)
0.25 (0.0098)
8°
0°
× 45°
1.27 (0.0500)
0.40 (0.0157)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AE
Figure 57. 28-Lead Standard Small Outline Package [SOIC]
Wide Body (RW-28)
Dimensions shown in millimeters and (inches)
Rev. B | Page 30 of 32
AD9740
0.08
0.60 MAX
25
24
EXPOSED
PAD
(BOTTOM VIEW)
17
16
32
1
8
9
3.50 REF
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
0.25 MIN
PIN 1
INDICATOR
1.00
0.85
0.80
12° MAX
SEATING
PLANE
5.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
4.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.50
BSC
0.50
0.40
0.30
COPLANARITY
Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9740AR −40°C to +85°C 28-Lead Wide Body SOIC RW-28
AD9740ARRL −40°C to +85°C 28-Lead Wide Body SOIC RW-28
AD9740ARZ
AD9740ARZRL
AD9740ARU −40°C to +85°C 28-Lead TSSOP RU-28
AD9740ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28
AD9740ARUZ
AD9740ARUZRL7
AD9740ACP −40°C to +85°C 32-Lead LFCSP CP-32-2
AD9740ACPRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
AD9740ACPZ
AD9740ACPZRL7
AD9740-EB Evaluation Board (SOIC)
AD9740ACP-PCB Evaluation Board (LFCSP)
1
Z = Pb-free part.
1
1
1
1
1
1
−40°C to +85°C 28-Lead Wide Body SOIC RW-28
−40°C to +85°C 28-Lead Wide Body SOIC RW-28
−40°C to +85°C 28-Lead TSSOP RU-28
−40°C to +85°C 28-Lead TSSOP RU-28
−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
−40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
Rev. B | Page 31 of 32
AD9740
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02911–0–12/05(B)
Rev. B | Page 32 of 32
Loading...