Datasheet AD9739A Datasheet (ANALOG DEVICES)

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14-Bit, 2.5 GSPS,

SCLK

FEATURES

Direct RF synthesis at 2.5 GSPS update rate

DC to 1.25 GHz in baseband mode

1.25 GHz to 3.0 GHz in mix mode Industry leading single/multicarrier IF or RF synthesis Dual-port LVDS data interface

Up to 1.25 GSPS operation

Source synchronous DDR clocking Pin-compatible with the AD9739 Programmable output current: 8.7 mA to 31.7 mA Low power: 1.1 W at 2.5 GSPS

APPLICATIONS

Broadband communications systems

DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics

RF Digital-to-Analog Converter

AD9739A

FUNCTIONAL BLOCK DIAGRAM

SDIO

SDO

DCI

DCO

RESET

SPI

DB0[13:0]DB1[13:0]

LVDS DDR

DATA

CONTROLLER

LVDS DDR

(DIV-BY-4)

IRQ

AD9739A

1.2V

DAC BIAS

RECEIVER

TxDAC

DATA

4-TO-1

DATA ASSEMBLER

RECEIVER

CLK DISTRIBUTION

CORE

LATCH

DLL

(MU CONTROL LER)

VREF I120

IOUTN

IOUTP

GENERAL DESCRIPTION

The AD9739A is a 14-bit, 2.5 GSPS high performance RF DAC capable of synthesizing wideband signals from dc up to 3 GHz. The AD9739A is pin and functionally compatible with the AD9739 with the exception that the AD9739A does not support synchronization and is specified to operate between 1.6 GSPS and 2.5 GSPS. By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and AD9739A.

The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.

The AD9739A is manufactured on a 0.18 μm CMOS process and operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball chip scale ball grid array for reduced package parasitics.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DACCLK

Figure 1.

PRODUCT HIGHLIGHTS

1. Ability to synthesize high quality wideband signals with

bandwidths of up to 1.25 GHz in the first or second Nyquist zone.

2. A proprietary quad-switch DAC architecture provides

exceptional ac linearity performance while enabling mixmode operation.

3. A dual-port, double data rate, LVDS interface supports the

maximum conversion rate of 2500 MSPS.

4. On-chip controllers manage external and internal clock

domain skews.

5. Programmable differential current output with a 8.66 mA

to 31.66 mA range.

09616-001

AD9739A

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

LVDS Digital Specifications ........................................................ 4

Serial Port Specifications ............................................................. 5

AC Specifications .......................................................................... 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 11

AC (Normal Mode) .................................................................... 11

AC (Mix Mode) .......................................................................... 14

One-Carrier DOCSIS Performance (Normal Mode) ............ 16

Four-Carrier DOCSIS Performance (Normal Mode) ........... 17

Eight-Carrier DOCSIS Performance (Normal Mode) .......... 18

16-Carrier DOCSIS Performance (Normal Mode) ............... 19

32-Carrier DOCSIS Performance (Normal Mode) ............... 20

64- and 128-Carrier DOCSIS Performance (Normal Mode)21

Terminolog y .................................................................................... 22

Serial Port Interface (SPI) Register .............................................. 23

SPI Register Map Description .................................................. 23

SPI Operation ............................................................................. 23

SPI Register Map ........................................................................ 25

Theory of Operation ...................................................................... 28

LVDS Data Port Interface .......................................................... 29

Mu Controller ............................................................................. 32

Interrupt Requests ...................................................................... 33

Analog Interface Considerations .................................................. 35

Analog Modes of Operation ..................................................... 35

Clock Input Considerations ...................................................... 36

Voltage Reference ....................................................................... 37

Analog Outputs .......................................................................... 37

Nonideal Spectral Artifacts ....................................................... 39

Lab Evaluation of the AD9739A .............................................. 40

Recommended Start-Up Sequence .......................................... 41

Outline Dimensions ....................................................................... 43

Ordering Guide .......................................................................... 43

REVISION HISTORY

7/11—Rev 0 to Rev. A

Changed Maximum Update Rate (DACCLK Input) Parameter

to DAC Clock Rate Parameter in Table 4 ...................................... 6

Added Adjusted DAC Update Rate Parameter and Endnote 1 in

Table 4 ................................................................................................ 6

Updated Outline Dimensions ....................................................... 43

1/11—Revision 0: Initial Version

Rev. A | Page 2 of 44

AD9739A

SPECIFICATIONS

DC SPECIFICATIONS

VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%, I

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 14 Bits ACCURACY

Integral Nonlinearity (INL) ±2.5 LSB

Differential Nonlinearity (DNL) ±2.0 LSB

ANALOG OUTPUTS

Gain Error (with Internal Reference) 5.5 %

Full-Scale Output Current 8.66 20.2 31.66 mA

Output Compliance Range −1.0 +1.0 V

Common-Mode Output Resistance 10 MΩ

Differential Output Resistance 70 Ω

Output Capacitance 1 pF

DAC CLOCK INPUT (DACCLK_P, DACCLK_N)

Differential Peak-to-Peak Voltage 1.2 1.6 2.0 V

Common-Mode Voltage 900 mV

Clock Rate 1.6 2.5 GHz

TEMPERATURE DRIFT

Gain 60 ppm/°C

Reference Voltage 20 ppm/°C

REFERENCE

Internal Reference Voltage 1.15 1.2 1.25 V

Output Resistance 5 kΩ

ANALOG SUPPLY VOLTAGES

VDDA 3.1 3.3 3.5 V

VDDC 1.70 1.8 1.90 V

DIGITAL SUPPLY VOLTAGES

VDD33 3.10 3.3 3.5 V

VDD 1.70 1.8 1.90 V

SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS

37 38 mA

VDDA

158 167 mA

VDDC

14.5 16 mA

VDD33

173 183 mA

VDD

Power Dissipation 0.770 W

Sleep Mode, I

2.5 2.75 mA

VDDA

Power-Down Mode (All Power-Down Bits Set in Register 0x01 and

0.02 mA

VDDA

6 mA

VDDC

0.6 mA

VDD33

0.1 mA

VDD

SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS

37 mA

VDDA

223 mA

VDDC

14.5 mA

VDD33

215 mA

VDD

Power Dissipation 0.960 W

OUTFS

= 20 mA.

Rev. A | Page 3 of 44

AD9739A

LVDS DIGITAL SPECIFICATIONS

VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%, I Standard 1596.3-1996 reduced range link, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1

Input Common-Mode Voltage Range, V Logic High Differential Input Threshold, V Logic Low Differential Input Threshold, V

825 1575 mV

COM

175 400 mV

IH_DTH

−175 −400 mV

IL_DTH

Receiver Differential Input Impedance, RIN 80 120 Ω Input Capacitance 1.2 pF LVDS Input Rate 1250 MSPS LVDS Minimum Data Valid Period (t

) (See Figure 76) 344 ps

MDE

LVDS CLOCK INPUT (DCI)2

Input Common-Mode Voltage Range, V Logic High Differential Input Threshold, V Logic Low Differential Input Threshold, V

825 1575 mV

COM

175 400 mV

IH_DTH

−175 −400 mV

IL_DTH

Receiver Differential Input Impedance, RIN 80 120 Ω Input Capacitance 1.2 pF Maximum Clock Rate 625 MHz

LVDS CLOCK OUTPUT (DCO)3

Output Voltage High (DCO_P or DCO_N) 1375 mV Output Voltage Low (DCO_P or DCO_N) 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, RO 80 100 120 Ω RO Single-Ended Mismatch 10 % Maximum Clock Rate 625 MHz

DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.

DCI_P and DCI_N pins.

DCO_P and DCO_N pins with 100 Ω differential termination.

= 20 mA. LVDS drivers and receivers are compliant to the IEEE

OUTFS

Rev. A | Page 4 of 44

AD9739A

SERIAL PORT SPECIFICATIONS

VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%.

Tabl e 3

Parameter Min Typ Max Unit

WRITE OPERATION (See Figure 71)

SCLK Clock Rate, f

SCLK Clock High, tHI 18 ns

SCLK Clock Low, t

SDIO to SCLK Setup Time, tDS 2 ns

SCLK to SDIO Hold Time, tDH 1 ns

CS to SCLK Setup Time, tS

SCLK to CS Hold Time, tH

READ OPERATION (See Figure 72 and Figure 73)

SCLK Clock Rate, f

SCLK Clock High, tHI 18 ns

SCLK Clock Low, t

SDIO to SCLK Setup Time, tDS 2 ns

SCLK to SDIO Hold Time, tDH 1 ns

CS to SCLK Setup Time, tS

SCLK to SDIO (or SDO) Data Valid Time, tDV 15 ns

CS to SDIO (or SDO) Output Valid to High-Z, tEZ

INPUTS (SDI, SDIO, SCLK, CS)

Voltage in High, VIH 2.0 3.3 V

Voltage in Low, VIL 0 0.8 V

Current in High, IIH −10 +10 μA

Current in Low, IIL −10 +10 μA

OUTPUT (SDIO)

Voltage Out High, VOH 2.4 3.5 V

Voltage Out Low, VOL 0 0.4 V

Current Out High, IOH 4 mA

Current Out Low, IOL 4 mA

, 1/t

SCLK

LOW

20 MHz

SCLK

18 ns

3 ns 2 ns

, 1/t

SCLK

LOW

20 MHz

SCLK

18 ns

3 ns

2 ns

Rev. A | Page 5 of 44

AD9739A

AC SPECIFICATIONS

VDDA = VDD33 = 3.3 V ± 6%, VDDC = VDD = 1.8 V ± 6%, I

Table 4.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

DAC Clock Rate 800 2500 MSPS Adjusted DAC Update Rate1 800 2500 MSPS Output Settling Time to 0.1% 13 ns

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

= 100 MHz 69.5 dBc

OUT

= 350 MHz 58.5 dBc

OUT

= 550 MHz 54 dBc

OUT

= 950 MHz 60 dBc

OUT

TWO-TONE INTERMODULATION DISTORTION (IMD), f

= 100 MHz 94 dBc

OUT

= 350 MHz 78 dBc

OUT

= 550 MHz 72 dBc

OUT

= 950 MHz 68 dBc

OUT

OUT2

= f

OUT1

NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE

= 100 MHz −166 dBm/Hz

OUT

= 350 MHz −161 dBm/Hz

OUT

= 550 MHz −160 dBm/Hz

OUT

= 850 MHz −160 dBm/Hz

OUT

WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL

= 2457.6 MSPS f

DAC

= 2457.6 MSPS, f

DAC

= 2457.6 MSPS, f

DAC

= 2457.6 MSPS, f

DAC

Adjusted DAC updated rate is calculated as f

with f

= 2500 MSPS, f

DAC

= 350 MHz 80/80 dBc

OUT

= 950 MHz 78/79 dBc

OUT

= 1700 MHz (Mix Mode) 74/74 dBc

OUT

= 2100 MHz (Mix Mode) 69/72 dBc

OUT

divided by the minimum required interpolation factor. For the AD9739A, the minimum interpolation factor is 1. Thus,

, adjusted, = 2500 MSPS.

DAC

= 20 mA.

OUTFS

+ 1.25 MHz

Rev. A | Page 6 of 44

AD9739A

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

VDDA VSSA −0.3 V to +3.6 V VDD33 VSS −0.3 V to +3.6 V VDD VSS −0.3 V to +1.98 V VDDC VSSC −0.3 V to +1.98 V VSSA VSS −0.3 V to +0.3 V VSSA VSSC −0.3 V to +0.3 V VSS VSSC −0.3 V to +0.3 V DACCLK_P,

DACCLK_N DCI, DCO VSS −0.3 V to VDD33 + 0.3 V LVDS Data Inputs VSS −0.3 V to VDD33 + 0.3 V IOUTP, IOUTN VSSA −1.0 V to VDDA + 0.3 V I120, VREF VSSA −0.3 V to VDDA + 0.3 V IRQ, CS, SCLK, SDO, SDIO, RESET Junction

Temperature Storage Temperature −65°C to +150°C

Respect To

VSSC −0.3 V to VDDC + 0.18 V

VSS −0.3 V to VDD33 + 0.3 V

150°C

Rating

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θ

160-Ball CSP_BGA 31.2 7.0 °C/W1

With no airflow movement.

Unit

ESD CAUTION

Rev. A | Page 7 of 44

AD9739A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1413121110876321954

VDDA, 3.3V, ANALOG SUPPLY

VSSA, ANALOG SUPPLY GROUND

VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD

Figure 2. Analog Supply Pins (Top View)

VDD, 1.8V, DIGITAL SUPPLY

VSS DIGITAL SUPPLY GROUND

VDD33, 3.3V DI GITAL SUPPLY

Figure 3. Digital Supply Pins (Top View)

VDDC, 1.8V, CLOCK SUPPLY

VSSC, CLOCK SUPPLY GROUND

09616-002

09616-004

Figure 4. Digital LVDS Clock Supply Pins (Top View)

1413121110876321954

DACCLK_N

DACCLK_P

DB1[0:13] P

DB1[0:13]N

DB0[0:13] P

DB0[0:13]N

09616-003

DIFFERE NTIAL INPUT SIGNAL (CL OCK OR DATA)

1413121110876321954

DCO_P/_N

DCI_P/_N

09616-005

Figure 5. Digital LVDS Input, Clock I/O (Top View)

Rev. A | Page 8 of 44

AD9739A

IOUTN

IOUTP

1413121110876321954

Figure 6. Analog I/O and SPI Control Pins (Top View)

I120

VREF

IRQ

SCLK

RESET

SDIO

SDO

09616-006

Table 7. AD9739A Pin Function Descriptions

Pin No. Mnemonic Description

C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,

VSSC

Clock Supply Return.

C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 VDDA A12, A13, B12, B13, C12, C13, D12, D13, VSSA A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3,

VSSA Shield Analog Supply Return Shield.

F4, E11, E12, E13, E14, F11, F12 A14 NC A7, B7, C7, D7 IOUTN A8, B8, C8, D8 IOUTP B14 I120

3.3 V Analog Supply Input. Analog Supply Return.

Tie to VSSA at the DAC. Do not connect to this pin. DAC Negative Current Output Source. DAC Positive Current Output Source. Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ

resistor to generate a 120 μA reference current.

C14 VREF Voltage Reference Input/Output.

Decouple to VSSA with a 1 nF capacitor. D14 NC C3, D3 DACCLK_N/DACCLK_P F13 IRQ

Factory Test Pin. Do not connect to this pin.

Negative/Positive DAC Clock Input (DACCLK).

Interrupt Request Open Drain Output. Active high. Pull up to

VDD33 with a 10 kΩ resistor. F14 RESET G13

CS G14 SDIO H13 SCLK H14 SDO J3, J4, J11, J12 VDD33 G1, G2, G3, G4, G11, G12 VDD H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS

J1, J2 NC

Reset Input. Active high. Tie to VSS if unused. Serial Port Enable Input.

Serial Port Data Input/Output. Serial Port Clock Input. Serial Port Data Output.

3.3 V Digital Supply Input.

1.8 V Digital Supply. Input. Digital Supply Return. Differential resistor of 200 Ω exists between J1 and J2. Do not

connect to this pin.

K1, K2 NC

Differential resistor of 100 Ω exists between J1 and J2. Do not

connect to this pin. J13, J14 DCO_P/DCO_N K13, K14 DCI_P/DCI_N L1, M1 DB1[0]P/DB1[0]N L2, M2 DB1[1]P/DB1[1]N L3, M3 DB1[2]P/DB1[2]N

Positive/Negative Data Clock Output (DCO).

Positive/Negative Data Clock Input (DCI).

Port 1 Positive/Negative Data Input Bit 0.

Port 1 Positive/Negative Data Input Bit 1.

Port 1 Positive/Negative Data Input Bit 2. L4, M4 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3.

Rev. A | Page 9 of 44

AD9739A

Pin No. Mnemonic Description

L5, M5 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4. L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5. L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6. L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7. L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8. L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9. L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10. L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11. L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12. L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13. N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0. N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1. N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2. N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3. N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4. N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5. N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11. N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12. N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13.

Rev. A | Page 10 of 44

AD9739A

–

TYPICAL PERFORMANCE CHARACTERISTICS

AC (NORMAL MODE)

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

10dB/DIV

Figure 7. Single-Tone Spectrum at f

1.2GSPS

2.4GSPS

SFDR (dBc)

0 100 200 300 400 500 600 700 800 900 1000 1100 1200

2.0GSPS

Figure 8. SFDR vs. f

150

–152

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–166

–168

–170

0 100 200 300 400 500 600 700 800 900 1000 110 0 1200

Figure 9. Single-Tone NSD over f

VBW 10kHz

1.6GSPS

OUT

(MHz)

OUT

1.2GSPS

(MHz)

= 91 MHz, f

over f

DAC

2.4GSPS

OUT

STOP 2.4GHzSTART 20MHz

DAC

= 2.4 GSPS

10dB/DIV

STOP 2.4GHzSTART 20MHz

2.4GSPS

VBW 10kHz

1.2GSPS

OUT

1.2GSPS

OUT

= 1091 MHz, f

OUT

2.4GSPS

(MHz)

over f

OUT

(MHz)

2.0GSPS

DAC

OUT

DAC

= 2.4 GSPS

1100 1200

09616-010

09616-011

09616-012

09616-007

Figure 10. Single-Tone Spectrum at f

100

1.6GSPS

IMD (dBc)

0 100 200 300 400 500 600 700 800 90 0 1000

09616-008

Figure 11. IMD vs. f

160

–161

–162

–163

–164

–165

–166

NSD (dBm/Hz)

–167

–168

–169

–170

0 100 200 300 400 500 600 700 800 900 1000 1100 1200

09616-009

Figure 12. Eight-Tone NSD over f

Rev. A | Page 11 of 44

AD9739A

= 2 GSPS, I

DAC

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

110

SFDR (dBc)

0 100 200 300 400 500 600 700 800 900 1000

Figure 13. SFDR vs. f

SFDR (dB)

0dBFS

–6dBFS

(MHz)

OUT

over Digital Full Scale

OUT

–6dBFS

0dBFS

–3dBFS

100

IMD (dBc)

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

09616-013

Figure 16. IMD vs. f

SFDR (dB)

0dBFS

OUT

over Digital Full Scale

OUT

–6dBFS

–3dBFS

–6dBFS

–3dBFS

0dBFS

09616-016

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

OUT

Figure 14. SFDR for Second Harmonic over f

SFDR (dBc)

0 100 200 300 400 500 600 700 800 900 1000

10mA FS

20mA FS

OUT

Figure 15. SFDR vs. f

(MHz)

OUT

30mA FS

over DAC I

vs. Digital Full Scale

OUTFS

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

10mA FS

OUT

(MHz)

over DAC I

OUT

vs. Digital Full Scale

OUT

30mA FS

OUTFS

09616-014

Figure 17. SFDR for Third Harmonic over f

110

100

IMD (dBc)

0 100 200 300 400 500 600 700 800 900 1000

09616-015

20mA FS

Figure 18. IMD vs. f

9616-017

09616-018

Rev. A | Page 12 of 44

AD9739A

–

110

–40°C

+85°C

SFDR (dBc)

+25°C

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

OUT

Figure 19. SFDR vs. f

over Temperature

OUT

150

–152

–154

–156

–158

–40°C

–160

–162

NSD (dBm/Hz)

–164

–166

–168

–170

0 200 400 600 800 1000100 300 500 700 900

+25°C

Figure 20. Single-Tone NSD vs. f

OUT

+85°C

(MHz)

OUT

over Temperature

100

+85°C

IMD (dBc)

+25°C

–40°C

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

09616-019

Figure 22. IMD vs. f

OUT

over Temperature

OUT

09616-022

150

–152

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–40°C

–166

–168

–170

0 200 400 600 800 1000100300500700900

09616-020

+25°C

OUT

(MHz)

Figure 23. Eight-Tone NSD vs. f

+85°C

over Temperature

OUT

09616-023

10dB/DIV

CENTER 350.27MHz #RES BW 30kHz

RMS RESULTS

CARRIER POW ER –14.54dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25

VBW 300kHz

REF

(dBc)

(MHz)

–79.90

3.84 –80.60

3.84 –80.90

3.84 –80.62

3.84 –80.76

3.84

LOWER

(dBm) –94.44 –95.14 –95.45 –95.16 –95.30

Figure 21. Single-Carrier WCDMA at 350 MHz, f

SPAN 53.84MHz

SWEEP 174.6ms (601p ts)

UPPER

(dBm)

(dBc)

–93.57

–79.03

–94.40

–79.36

–95.27

–80.73

–95.51

–80.97

–95.49

–80.95

= 2457.6 MSPS

DAC

09616-021

Rev. A | Page 13 of 44

–55

–60

–65

–70

ACLR (dBc)

–75

FIRST ADJ CH

–80

–85

–90

122.88

245.76

FIFTH ADJ CH

491.52

368.64

OUT

614.40

(MHz)

737.28

Figure 24. Four-Carrier WCDMA at 350 MHz, f

SECOND ADJ CH

983.04

860.16

1105.90

= 2457.6 MSPS

DAC

1228.80

09616-108

AD9739A

–

AC (MIX MODE)

= 2.4 GSPS, I

DAC

OUTFS

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

10dB/DIV

START 20MHz #RES BW 10kHz

Figure 25. Single-Tone Spectrum at f

SFDR (dBc)

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

VBW 10kHz

(MHz)

OUT

= 2.31 GHz, f

OUT

Figure 26. SFDR in Mix Mode vs. f

10dB/DIV

CENTER 2.10706MHz #RES VW 30kHz

RMS RESULTS

CARRIER PO WER –21.43dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25

VBW 300kHz

REF

(MHz)

3.84

SWEEP 174.6ms ( 601pts)

LOWER

(dBc)

(dBm)

–68.99

–90.43

–72.09

–93.52

–72.86

–94.30

–74.34

–95.77

–74.77

–96.20

STOP 2.4GHz

SWEEP 28.7s (601p ts)

= 2.4 GSPS

DAC

at 2.4 GSPS

OUT

SPAN 53.84MHz

UPPER

(dBc)

(dBm)

–63.94

–90.37

–71.07

–92.50

–71.34

–92.77

–72.60

–94.03

–73.26

–94.70

09616-026

09616-032

Figure 27. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,

= 2457.6 MSPS (Second Nyquist Zone)

DAC

10dB/DIV

START 20MHz #RES BW 10kHz

VBW 10kHz

Figure 28. Single-Tone Spectrum in Mix Mode at f

= 2.4 GSPS

DAC

IMD (dBc)

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

(MHz)

09616-027

OUT

Figure 29. IMD in Mix Mode vs. f

SECOND NYQUIS T ZONE THIRD NYQUIST ZONE

–45

–50

–55

–60

–65

–70

ACLR (dBc)

–75

–80

–85

–90

1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686

FIRST ADJ CH

FIFTH ADJ CH

OUT

(MHz)

Figure 30. Single-Carrier WCDMA ACLR vs. f

STOP 2.4GHz

STOP 2.4GHzSTART 20MHz

SWEEP 28.7s ( 601pts)

= 1.31 GHz,

OUT

at 2.4 GSPS

OUT

SECOND ADJ CH

at 2457.6 MSPS

OUT

09616-030

09616-031

09616-025

Rev. A | Page 14 of 44

AD9739A

10dB/DIV

CENTER 2.807GHz #RES BW 30kHz

RMS RESULTS

CARRIER PO WER –24.4dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25

VBW 300kHz

REF

(dBc)

(MHz)

–64.90

3.84 –66.27

3.84 –68.44

3.84 –70.20

3.84 –70.85

3.84

LOWER

(dBm) –89.30 –90.67 –92.84 –94.60 –95.25

SPAN 53.84MHz

SWEEP 174.6ms (601pts)

UPPER

(dBm)

(dBc)

–88.22

–63.82

–90.10

–65.70

–90.95

–66.55

–93.35

–68.95

–94.85

–70.45

09616-033

Figure 31. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz,

= 2457.6 MSPS (Third Nyquist Zone)

DAC

10dB/DIV

CENTER 2.81271GHz #RES BW 30kHz

RMS RESULTS

CARRIER PO WER –27.98dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25 30

VBW 300kHz

REF

(dBc)

(MHz)

–0.42

3.84 –64.32

3.84 –66.03

3.84 –66.27

3.84 –66.82

3.84 –67.16

3.84

LOWER

(dBm) –28.40 –92.30 –94.01 –94.24 –94.79 –95.13

SPAN 63.84MHz

SWEEP 207ms (601p ts)

UPPER

(dBm)

(dBc)

–28.07

–0.10

–28.06

–0.08

–93.34

–65.37

–94.03

–66.06

–93.34

–63.36

–94.51

–66.54

09616-035

Figure 33. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz,

= 2457.6 MSPS (Third Nyquist Zone)

DAC

CENTER 2.09758GHz #RES BW 30kHz

RMS RESU LTS

CARRIER POW ER –25.53dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25 30

VBW 300kHz

REF

LOWER

(dBc)

(MHz)

0.22

3.84 –66.68

3.84 –68.01

3.84 –68.61

3.84 –68.87

3.84 –69.21

3.84

–25.31 –92.21 –93.53 –94.14 –94.40 –94.74

SPAN 63.84MHz

SWEEP 207ms (601p ts)

UPPER

(dBm)

(dBc)

(dBm)

0.24

0.14 –66.82 –67.83 –67.64 –68.50

–25.29 –25.38 –92.35 –93.36 –93.17 –94.03

09616-034

Figure 32. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz,

= 2457.6 MSPS (Second Nyquist Zone)

DAC

Rev. A | Page 15 of 44

AD9739A

ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

= 20 mA, f

DAC

–31

–42

–53

–64

–75

11dB/DIV

–86

–97

–108

–119

–31

–42

–53

–64

–75

11dB/DI V

–86

–97

–108

–119

–31

–42

–53

–64

–75

11dB/DI V

–86

–97

–108

–119

START 50MHz #RES BW 20kHz

1 2 3 4 5

2∆1

START 50MHz #RES BW 20kHz

1 2 3 4 5 6

= 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.

DAC

4∆1

5∆1

3∆1

2∆1

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VALU E

–11.475dBm

(∆)

–77.042dB

(∆)

–76.238dB

(∆)

–74.526dB

(∆)

–75.919dB

09616-036

MODEMKR S CLTRC N

∆1 ∆1 ∆1 ∆1

VBW 2kHz

X 200MHz

199.60MHz

(∆)

400.05MHz

(∆)

597.65MHz

(∆)

413.35MHz

(∆)

Y –11.476dBm

–77.042dB

(∆)

–76.238dB

(∆)

–74.526dB

(∆)

–75.919dB

(∆)

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

Figure 34. Low Band Wideband ACLR

4∆1

5∆1

MODEMKR SCLTRC

∆1 ∆1 ∆1 ∆1 ∆1

3∆1

VBW 2kHz

549.60MHz

–485.35MHz

(∆)

127.40MHz

(∆)

254.70MHz

(∆)

63.75MHz

(∆)

293.65MHz

(∆)

(∆) (∆) (∆) (∆) (∆)

–10.231dBm –76.444dB –75.649dB –70.658dB –75.836dB –78.054dB

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

6∆1

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VAL UE

–10.231dBm

–76.425dB

(∆)

–75.626dB

(∆)

–70.658dB

(∆)

–75.824dB

(∆)

–78.118dB

(∆)

09616-037

Figure 35. Mid Band Wideband ACLR

4∆1

2∆1

5∆1

3∆1

–80.7dBc –80.7dBc –80.7dBc –81.2dBc –10.2dBm –81.3dBc –80.7dBc –80.8dBc–80.8dBc

–35

–45

–55

–65

–75

10dB/DI

–85

–95

–105

–115

CENTER 200MHz #RES BW 30kHz

CARRIER POWER –10.190dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

–59.38 –81.23 –80.71 –80.72 –80.73

dBc

LOWER

VBW 3kHz

dBm

–69.57

–60.16

–91.42

–81.26

–90.90

–80.72

–90.91

–80.76

–90.92

–80.78

dBc

UPPER

Figure 37. Low Band Narrow-Band ACLR

–78.5dBc –77.6dBc – 76.3dBc – 75.1dBc –10.4dBm –74.4dBc –75 .6dBc –77.7dBc–76 .7dBc

–35

–45

–55

–65

–75

10dB/DI

–85

–95

–105

–115

CENTER 550MHz #RES BW 30kHz

CARRIER POWER –10.368dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–57.91 –75.09 –76.29 –77.63 –78.51

dBc

LOWER

VBW 3kHz

dBm

–68.28

–58.53

–85.46

–74.41

–86.65

–75.55

–88.00

–76.69

–88.88

–77.67

dBc

UPPER

Figure 38. Mid Band Narrow-Band ACLR

–69.9dBc

–68.7dBc – 12.6dBm –67.9dBc –68.6dBc –70.6dBc –72.3dBc

10dB/DI

–72.6dBc –71.1dBc

–35

–45

–55

–65

–75

–85

–95

–105

–115

–70.35 –91.45 –90.91 –90.95 –90.97

dBm –68.90 –84.78 –85.92 –87.06 –88.03

dBm

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

SPAN 54MHz

SWEEP 1.49s

09616-039

09616-040

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-041

START 50MHz #RES BW 20kHz

MODEMKR SCLTRC

∆1

Figure 36. High Band Wideband ACLR

f f f f f

(∆) (∆) (∆) (∆)

979.00MHz –484.40MHz –118.65MH z –613.60MHz –365.65MHz

VBW 2kHz

–13.703dBm

–65.548dB

(∆)

–66.990dB

(∆)

–69.044dB

(∆)

–72.789dB

(∆)

SWEEP 24.1s (1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VALU E

–13.658dBm

(∆)

–65.548dB

(∆)

–66.990dB

(∆)

–69.049dB

(∆)

–72.789dB

CENTER 980MHz #RES BW 30kHz

CARRIER POWER –12.778dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

09616-038

18.00MHz

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

–60.38 –68.67 –69.90 –71.12 –72.61

dBc

LOWER

VBW 3kHz

dBm

–73.15

–59.15

–81.44

–67.94

–82.68

–68.58

–83.90

–70.64

–85.39

–72.35

dBc

UPPER

dBm –71.93 –80.72 –81.35 –83.42 –85.13

Figure 39. High Band Narrow-Band ACLR

Rev. A | Page 16 of 44

AD9739A

FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

= 20 mA, f

OUTFS

–38

–48

–58

–68

–78

10dB/DI V

–88

–98

–108

–118

5∆1

= 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.

DAC

2∆1

6∆1

3∆1

4∆1

–53.4dBc –0.1dBc –0.1dBc –0.5dBc –17.6dBm –73.6dBc –75.4dBc –79.1dBc–78.1dBc

–37

–47

–57

–67

–77

10dB/DI

–87

–97

–107

–117

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

SPAN 54MHz

SWEEP 1.49s

SPAN 54MHz

SWEEP 1.49s

09616-045

09616-046

09616-047

START 50MHz #RES BW 20kHz

MODEMKR S CLTRC N

∆1

f f f f f f

(∆) (∆) (∆) (∆) (∆)

217.50MHz

201.10MHz

417.70MHz

608.65MHz –124.75MHz

395.85MHz

VBW 2kHz

Y –18.065dBm

–72.097dB

(∆)

–72.882dB

(∆)

–72.292dB

(∆)

–76.776dB

(∆)

–71.133dB

(∆)

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VAL UE

–18.064dBm

(∆)

–72.097dB

(∆)

–72.882dB

(∆)

–72.292dB

(∆)

–76.776dB

(∆)

–71.133dB

09616-042

Figure 40. Low Band Wideband ACLR

–38

–48

–58

–68

–78

10dB/DI V

–88

–98

–108

4∆1

–118

START 50MHz #RES BW 20kHz

1 2 3 4 5 6

5∆1

MODEMKR S CLTRC N

∆1 ∆1 ∆1 ∆1 ∆1

2∆1

VBW 2kHz

667.80MHz

(∆)

–192.20MHz

(∆)

–98.15MHz

(∆)

–614.00MHz

(∆)

–567.45MHz

(∆)

–55.40MHz

Y –18.760dBm

(∆)

–69.536dB

(∆)

–71.601dB

(∆)

–72.824dB

(∆)

–75.786dB

(∆)

–71.997dB

6∆1

3∆1

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VAL UE

–18.760dBm

–69.536dB

(∆)

–71.601dB

(∆)

–72.833dB

(∆)

–75.320dB

(∆)

–71.997dB

(∆)

09616-043

Figure 41. Mid Band Wideband ACLR

–38

–48

–58

–68

–78

10dB/DIV

–88

–98

–108

–118

START 50MHz #RES BW 20kHz

1 2 3 4 5 6

MODEMKR S CLTRC

∆1 ∆1 ∆1 ∆

∆1

2∆1

VBW 2kHz

–21.040dBm –60.683dB

(∆)

–69.390dB

(∆)

–71.954dB

(∆)

–66.954dB

(∆)

–68.889dB

(∆)

6∆1

SWEEP 24.1s (1 001pts)

FUNCTION

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

3∆1

4∆1

987.95MHz

–490.50MHz

(∆)

–624.45MHz

(∆)

–738.45MHz

(∆)

–130.46MHz

(∆)

–374.60MHz

(∆)

5∆1

STOP 1GHz

FUNCTION VALU E

–21.029dBm

(∆) (∆) (∆) (∆) (∆)

–60.683dB –69.390dB –71.847dB –66.954dB –68.889dB

09616-044

Figure 42. High Band Wideband ACLR

CENTER 210MHz #RES BW 30kHz

CARRIER POWER –17.556dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

–11.15 –0.454 –0.065 –0.091 –53.44

dBc

LOWER

VBW 3kHz

dBm

–28.70

–58.78

–18.01

–73.56

–17.62

–75.42

–17.65

–78.08

–70.99

–79.06

dBc

UPPER

dBm –76.34 –91.12 –92.98 –95.64 –96.62

Figure 43. Low Band Narrow-Band ACLR (Worst Side)

–76.6dBc –76.4dBc –75.0dBc –72.9dBc –19.5dBm –0.3dBc –0.1dBc –50.2dBc–0.1dBc

–37

–47

–57

–67

–77

10dB/DI

–87

–97

–107

–117

CENTER 650MHz #RES BW 30kHz

CARRIER POWER –19.503dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–61.84 –72.95 –74.99 –76.38 –76.59

dBc

LOWER

VBW 3kHz

dBm

–81.35

–11.18

–92.45

–0.294

–94.49

–0.075

–95.89

–0.145

–96.10

–50.21

dBc

UPPER

dBm –30.68 –19.80 –19.58 –19.65 –69.71

Figure 44. Mid Band Narrow-Band ACLR (Worst Side)

–74.2dBc –73.0dBc –70.7dBc –68.7dBc –20.7dBm –0.5dBc 0.1dBc –52.3dBc–0.5dBc

–37

–47

–57

–67

–77

10dB/DI

–87

–97

–107

–117

CENTER 970MHz #RES BW 30kHz

CARRIER POWER –20.666dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

–60.65 –68.68 –70.67 –72.96 –74.22

dBc

LOWER

VBW 3kHz

dBm

dBc

–81.32

–10.77

–89.34

–0.522

–91.33

–0.140

–93.63

–0.511

–94.89

–52.31

UPPER

dBm –31.44 –21.19 –20.81 –21.18 –72.98

Figure 45. High Band Narrow-Band ACLR (Worst Side)

Rev. A | Page 17 of 44

AD9739A

EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

= 20 mA, f

OUTFS

–38

–48

–58

–68

–78

10dB/DIV

–88

–98

–108

–118

3∆1

= 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.

DAC

6∆1

5∆1

2∆1

4∆1

0dBc 0dBc 0.1dBc –0.3dBc –21.9dBm –70.0dBc –69.9dBc –70.1dBc–69.7dBc

–37

–47

–57

–67

–77

10dB/DI

–87

–97

–107

–117

START 50MHz #RES BW 20kHz

1 2 3 4 5 6

–38

–48

–58

–68

–78

10dB/DIV

–88

–98

–108

4∆1

–118

START 50MHz #RES BW 20kHz

1 2 3 4 5 6

–38

–48

–58

–68

–78

10dB/DIV

–88

–98

–108

–118

VBW 2kHz

MODEMKR S CLTRC

∆1 ∆1 ∆1 ∆1 ∆1

241.25MHz

198.25MHz

(∆)

–135.20MHz

(∆)

746.40MHz

(∆)

20.60MH z

(∆)

371.15MHz

(∆)

(∆) (∆) (∆) (∆) (∆)

–23.278dBm –67.453dB –72.684dB –68.278dB –69.581dB –66.474dB

Figure 46. Low Band Wideband ACLR

5∆1

MODEMKR S CLTRC N

∆1 ∆1 ∆1 ∆1 ∆1

667.80MHz

–171.30MHz

(∆)

–98.15MHz

(∆)

–614.00MHz

(∆)

–567.45MHz

(∆)

–55.40MHz

(∆)

2∆1

VBW 2kHz

Y –23.977dBm

–69.185dB

(∆)

–68.551dB

(∆)

–69.923dB

(∆)

–72.145dB

(∆)

–65.009dB

(∆)

Figure 47. Mid Band Wideband ACLR

2∆1

3∆1

4∆1

SWEEP 24.1s (1 001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

6∆1

3∆1

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

6∆1

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

5∆1

FUNCTION VALU E

–23.279dBm

(∆)

–67.448dB

(∆)

–72.764dB

(∆)

–68.258dB

(∆)

–69.581dB

(∆)

–66.457dB

FUNCTION VAL UE

–23.977dBm

(∆)

–69.185dB

(∆)

–68.551dB

(∆)

–69.938dB

(∆)

–72.083dB

(∆)

–65.009dB

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-051

CENTER 222MHz #RES BW 30kHz

CARRIER POWER –21.874dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

09616-048

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–10.98 –0.334 –0.087 –0.034 –0.031

dBc

LOWER

VBW 3kHz

dBm

dBc

–32.85

–59.41

–22.21

–69.96

–21.79

–69.91

–21.91

–69.74

–21.84

–70.08

UPPER

dBm –81.28 –91.83 –91.78 –91.62 –91.95

Figure 49. Low Band Narrow-Band ACLR (Worst Side)

–37

0dBc –0.1dBc –0.1dBc –0.3dBc –22.7dBm –69.2dBc –68.6dBc –69.2dBc–69.3dBc

–47

–57

–67

–77

10dB/DI

–87

–97

–107

–117

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-052

CENTER 622MHz #RES BW 30kHz

CARRIER POWER –22.691dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

09616-049

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–11.01 –0.339 –0.135 –0.089 –0.049

dBc

LOWER

VBW 3kHz

dBc

–61.38

–33.70

–69.17

–23.03

–68.64

–22.83

–69.33

–22.78

–69.18

–22.74

dBc

UPPER

–84.07 –91.86 –91.33 –92.02 –91.88

dBc

Figure 50. Mid Band Narrow-Band ACLR (Worst Side)

–37

–67.7dBc –67.7dBc –67.3dBc –67.4dBc

–47

–57

–67

–77

10dB/DI

–87

–97

–107

–117

–25.3dBm –0.5dBc –0.2dBc 0dBc0dBc

START 50MHz #RES BW 20kHz

MODEMKR S CLTRC

∆1

Figure 48. High Band Wideband ACLR

f f f f f f

(∆) (∆) (∆) (∆) (∆)

990.80MHz –481.00MHz –633.95MHz –734.65MHz –128.55MHz –378.40MHz

VBW 2kHz

Y –25.435dBm

(∆)

–61.947dB

(∆)

–67.517dB

(∆)

–69.583dB

(∆)

–65.237dB

(∆)

–64.615dB

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VAL UE

–25.435dBm

–61.947dB

(∆)

–67.532dB

(∆)

–69.602dB

(∆)

–65.237dB

(∆)

–64.615dB

(∆)

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-053

CENTER 950MHz #RES BW 30kHz

CARRIER POWER –25.344dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

09616-050

18.00MHz

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–60.39

–67.44

–67.29

–67.65

dBc

LOWER

VBW 3kHz

dBm

dBc

–85.73

–10.93

–92.78

–0.487

–92.63

–0.205

–93.00

–0.047

–93.00

0.016

UPPER

dBm –36.27 –25.83 –25.55 –25.39 –25.33

Figure 51. High Band Narrow-Band ACLR (Worst Side)

Rev. A | Page 18 of 44

AD9739A

16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

= 20 mA, f

OUTFS

= 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.

DAC

–38

–48

–58

–68

–78

10dB/DI V

–88

–98

–108

–118

START 50MHz #RES BW 20kHz

1 2 3 4 5 6

–38

–48

–58

–68

–78

10dB/DIV

–88

–98

–108

–118

3∆1

5∆1

VBW 2kHz

MODEMKR S CLTRC

∆1 ∆1 ∆1 ∆1 ∆1

289.70MHz

(∆)

202.05MHz

(∆)

–183.65MHz

(∆)

697.95MHz

(∆)

18.70MHz

(∆)

322.70MHz

–25.335dBm

(∆)

–66.838dB

(∆)

–70.421dB

(∆)

–65.880dB

(∆)

–67.033dB

(∆)

–64.481dB

Figure 52. Low Band Wideband ACLR

3∆1

6∆1

2∆1

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

2∆1

–67.4dBc –67.3dBc –67.4dBc –68.5dBc –24.8dBm –0.4dBc –0.1dBc 0dBc0dBc

–44

–54

–64

–74

–84

10dB/DI

–94

–104

4∆1

–114

–124

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VAL UE

–26.335dBm

–66.838dB

(∆)

–70.312dB

(∆)

–65.928dB

(∆)

–66.973dB

(∆)

–64.451dB

(∆)

CENTER 200MHz #RES BW 30kHz

CARRIER POWER –24.819dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

09616-054

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

dBc –60.64 –68.49 –67.43 –67.32 –67.44

VBW 3kHz

LOWER

dBm –85.46 –93.30 –92.24 –92.13 –92.26

–11.03

–0.368

0.137

0.010

0.035

dBc

UPPER

dBm –35.85 –25.19 –24.68 –24.81 –24.78

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-057

Figure 55. Low Band Narrow-Band ACLR (Worst Side)

–66.7dBc –66.8dBc –67.1dBc –67.4dBc –26.1dBm –0.5dBc 0.1dBc 0dBc0.2dBc

–44

4∆1

10dB/DI

–54

–64

–74

–84

–94

–104

–114

–124

–38

–48

–58

–68

–78

10dB/DIV

–88

–98

–108

–118

START 50MHz #RES BW 20kHz

MODEMKR S CLTRC N

∆1

Figure 53. Mid Band Wideband ACLR

3∆1

START 50MHz #RES BW 20kHz

MODEMKR S CLTRC

∆1

Figure 54. High Band Wideband ACLR

f f f f

f f f f f f

(∆) (∆) (∆)

4∆1

(∆) (∆) (∆) (∆) (∆)

690.60MHz –141.85MHz –623.50MHz

152.65MHz

989.85MHz –422.10MHz –922.75MHz –668.15MHz –137.10MHz –377.45MHz

VBW 2kHz

Y –28.317dBm

–64.672dB

(∆)

–65.202dB

(∆)

–64.574dB

(∆)

2∆1

VBW 2kHz

Y –27.971dBm

(∆)

–61.110dB

(∆)

–63.327dB

(∆)

–65.509dB

(∆)

–62.779dB

(∆)

–59.828dB

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER

6∆1

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz

5∆1

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz 6MHz 6MHz

FUNCTION VALU E

–28.317dBm

(∆)

–64.672dB

(∆)

–65.207dB

(∆)

–64.574dB

FUNCTION VALU E

–27.960dBm

–61.110dB

(∆)

–63.332dB

(∆)

–65.483dB

(∆)

–62.779dB

(∆)

–59.828dB

(∆)

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-058

CENTER 600MHz #RES BW 30kHz

CARRIER POWER –26.083dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

09616-055

12.00MHz

18.00MHz

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–61.77 –67.40 –67.09 –66.80 –66.67

dBc

LOWER

VBW 3kHz

dBm

dBc

–87.85

–10.38

–93.48

–0.494

–93.18

0.098

–92.88

0.180

–92.75

0.021

UPPER

dBm –36.49 –26.58 –25.98 –25.90 –26.06

Figure 56. Mid Band Narrow-Band ACLR(Worst Side)

–64.9dBc –64.8dB c –64.6dBc –65.0dBc –28.4dBm –0.5dBc –0.1dBc 0.2dBc0dBc

–44

–54

–64

–74

–84

10dB/DI

–94

–104

–114

–124

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-059

CENTER 900MHz #RES BW 30kHz

CARRIER POWER –28.435dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

09616-056

18.00MHz

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

dBc –57.24 –65.03 –64.64 –64.80 –64.86

VBW 3kHz

LOWER

dBm –85.68 –93.46 –93.08 –93.24 –93.29

dBc –11.30 –0.490 –0.119 –0.016

0.153

UPPER

dBm –39.73 –28.92 –28.55 –28.45 –28.28

Figure 57. High Band Narrow-Band ACLR (Worst Side)

Rev. A | Page 19 of 44

AD9739A

32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

= 20 mA, f

OUTFS

= 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.

DAC

–52

–62

–72

–82

–92

10dB/DIV

–102

–112

–122

–132

START 50MHz #RES BW 20kHz

1 2 3 4

–52

–62

–72

–82

–92

10dB/DI V

–102

–112

2∆1

–122

–132

2∆1

VBW 2kHz

MODEMKR S CLTRC

∆1 ∆1 ∆1

384.70MHz

–283.40MHz

(∆)

227.70MHz

(∆)

325.55MHz

(∆)

(∆) (∆) (∆)

–29.646dBm –64.175dB –59.429dB –62.750dB

Figure 58. Low Band Wideband ACLR

3∆1

4∆1

SWEEP 24.1s (1001p ts)

BAND POWER BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz

4∆1

FUNCTION VAL UE

–29.645dBm

(∆)

–64.167dB

(∆)

–59.423dB

(∆)

–62.750dB

–44

–63.5dBc –63.2dBc –63.1dBc –63.3dBc –29.3dBm –0.5dBc –0.2dBc –0.1dBc–0.2dBc

–54

–64

–74

–84

10dB/DI

–94

–104

–114

–124

FILTER

OFF

SPAN 54MHz

SWEEP 1.49s

09616-063

CENTER 200MHz #RES BW 30kHz

CARRIER POWER –29.311dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

09616-060

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–58.76 –63.30 –63.05 –63.21 –63.46

dBc

LOWER

VBW 3kHz

dBm

dBc

–88.07

–10.78

–92.61

–0.487

–92.36

–0.175

–92.52

–0.151

–92.78

–0.061

UPPER

dBm –40.09 –29.80 –29.49 –29.46 –29.37

Figure 61. Low Band Narrow-Band ACLR (Worst Side)

–44

–64.7dBc –64.7dBc –64.7dBc –65.3dBc

–54

–64

–74

–84

10dB/DI

–94

–104

–114

–124

–29.3dBm –0.5dBc –0.1dBc –0.2dBc–0.1dBc

START 50MHz #RES BW 20kHz

1 2 3 4

–52

–62

–72

–82

–92

10dB/DIV

–102

–112

–122

–132

START 50MHz #RES BW 20kHz

1 2 3 4

VBW 2kHz

MODEMKR S CLTRC

∆1 ∆1 ∆1

685.85MHz

–611.15MHz

(∆)

–243.50MHz

(∆)

162.15MHz

(∆)

(∆) (∆) (∆)

–30.335dBm –63.136dB –63.860dB –62.151dB

Figure 59. Mid Band Wideband ACLR

3∆1

VBW 2kHz

MODEMKR SCLTRC N

∆1 ∆1 ∆1

985.10MHz

(∆)

–334.70MHz

(∆)

–909.45MHz

(∆)

–373.65MHz

(∆) (∆) (∆)

Y –31.616dBm

–59.997dB –60.458dB –57.761dB

Figure 60. High Band Wideband ACLR

SWEEP 24.1s (1001p ts)

BAND POWER BAND POWER BAND POWER BAND POWER

4∆1

2∆1

SWEEP 24.1s (1001pts)

BAND POWER BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz 6MHz

FUNCTION VAL UE

–30.335dBm

(∆)

–63.112dB

(∆)

–63.860dB

(∆)

–62.151dB

FUNCTION VALU E

–31.516dBm

–59.997dB

(∆)

–60.535dB

(∆)

–57.763dB

(∆)

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-064

CENTER 600MHz #RES BW 30kHz

CARRIER POWER –29.255dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

09616-061

12.00MHz

18.00MHz

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–60.64 –65.26 –64.73 –64.65 –64.68

dBc

LOWER

VBW 3kHz

dBc

dBm

–10.40

–89.90

–0.515

–94.52

–0.178

–93.99

–0.069

–93.91

–0.197

–93.93

UPPER

dBm –39.65 –29.77 –29.43 –29.32 –29.45

Figure 62. Mid Band Narrow-Band ACLR(Worst Side)

09616-062

–44

–62.8dBc –62.7dBc –62.8dBc

–54

–64

–74

–84

10dB/DI

–94

–104

–114

–124

CENTER 800MHz #RES BW 30kHz

CARRIER POWER –30.746dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

dBc –60.75 –63.18 –62.76 –62.74 –62.84

–63.2dBc

LOWER

–91.49 –93.92 –93.50 –93.48 –93.59

VBW 3kHz

dBc

dBm

–10.84 –0.437 –0.354 –0.455 –0.410

UPPER

dBm –41.59 –31.18 –31.10 –31.20 –31.16

–0.4dBc–30.7dBm –0.4dBc –0.4dBc–0.5dBc

SPAN 54MHz

SWEEP 1.49s

FILTER OFF OFF OFF OFF OFF

09616-065

Figure 63. High Band Narrow-Band ACLR (Worst Side)

Rev. A | Page 20 of 44

AD9739A

64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

= 20 mA, f

OUTFS

= 2.4576 GSPS, nominal supplies, 25°C, unless otherwise noted.

DAC

–52

–62

–72

–82

–92

10dB/DIV

–102

–112

–122

–132

START 50MHz #RES BW 20kHz

1 2 3

–52

–62

–72

–82

–92

10dB/DIV

–102

–112

2∆1

–122

–132

VBW 2kHz

MODEMKR S CLTRC

∆1 ∆1

478.75MHz

372.10MHz

(∆)

132.70MHz

(∆)

–33.210dBm –58.746dB

(∆)

–55.165dB

(∆)

Figure 64. Low Band Wideband ACLR

3∆1

SWEEP 24.1s (1001pts)

BAND POWER BAND POWER BAND POWER

2∆1

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz

FUNCTION VAL UE

–33.209dBm

–58.804dB

(∆)

–55.165dB

(∆)

0.3dBc 0.2dBc 0.1dBc –0.3dBc –32.4dBm –62.3dBc –61.5dBc –61.4dBc–61.5dBc

–51

–61

–71

–81

–91

10dB/DI

–101

–111

–121

–131

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz

SWEEP 1.49s

09616-069

CENTER 478MHz #RES BW 30kHz

CARRIER POWER –32.409dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

09616-066

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTE G BW

750.0kHz

5.250MHz

6.000MHz

–10.83 –0.267

0.139

0.201

0.308

dBc

LOWER

VBW 3kHz

dBm

–43.24

–60.80

–32.68

–62.25

–32.27

–61.47

–32.21

–61.54

–32.10

–61.40

dBc

UPPER

dBm –93.21 –94.66 –93.88 –93.95 –93.81

Figure 67. Low Band Narrow-Band ACLR (Worst Side)

–60.6dBc 33.6dBm 0.3dBc 0.1dBc 0.1dBc0.2dBc–60.6dBc –61.1dBc–60.6dBc

10dB/DI

–101

–111

–121

–131

–51

–61

–71

–81

–91

FILTER OFF OFF OFF OFF OFF

SPAN 54MHz SWEEP 1.49s

09616-070

START 50MHz #RES BW 20kHz

1 2 3

–52

–62

–72

–82

–92

10dB/DIV

–102

–112

3∆1

–122

–132

START 50MHz #RES BW 20kHz

1 2 3

VBW 2kHz

MODEMKR SCLTRC

∆1 ∆1

978.45MHz

(∆)

–901.85MHz

(∆)

–561.75MHz

–35.872dBm

(∆)

–58.581dB

(∆)

–59.214dB

Figure 65. Mid Band Wideband ACLR

2∆1

VBW 2kHz

MODEMKR SCLTRC N

∆1 ∆1

988.90MHz

(∆)

–481.95MHz

(∆)

–925.60MHz

Y –37.954dBm

(∆)

–55.764dB

(∆)

–57.007dB

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER

SWEEP 24.1s ( 1001pts)

BAND POWER BAND POWER BAND POWER

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz

STOP 1GHz

FUNCTION WIDTHFUNCTION

6MHz 6MHz 6MHz

FUNCTION VAL UE

–35.873dBm

–58.625dB

(∆)

–59.286dB

(∆)

FUNCTION VAL UE

–37.983dBm

–55.764dB

(∆)

–56.953dB

(∆)

CENTER 600MHz #RES BW 30kHz

CARRIER POWER –33.558dBm/6MHz ACP-IBW

OFFSET FREQ

3.375MHz

09616-067

6.375MHz

12.00MHz

18.00MHz

24.00MHz

INTEG B W

750.0kHz

5.250MHz

6.000MHz

–60.02

–61.11 –60.57 –60.64 –60.58

dBc

LOWER

VBW 3kHz

dBm

dBc

–93.58

–11.84

–94.66

–0.284

–94.13

–0.099

–94.20

–0.221

–94.14

–0.060

UPPER

dBm –45.04 –33.84 –33.46 –33.34 –33.50

Figure 68. Mid Band Narrow-Band ACLR(Worst Side)

09616-068

Figure 66. 128-Carrier High Band Wideband ACLR

Rev. A | Page 21 of 44

AD9739A

TERMINOLOGY

Linearity Error (Integral Nonlinearity or INL)

The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale.

Differential Nonlinearity (DNL)

The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of 0 is called the offset error. For IOUTP, 0 mA output is expected when the inputs are all 0s. For IOUTN, 0 mA output is expected when all inputs are set to 1.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0.

Output Compliance Range

The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Temp er at u re D ri ft

Specified as the maximum change from the ambient (25°C) value to the value at either T drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

MIN

or T

. For offset and gain

MAX

Power Supply Rejection

The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.

Spurious-Free Dynamic Range

The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).

Noise Spectral Density (NSD)

NSD is the converter noise power per unit of bandwidth. This is usually specified in dBm/Hz in the presence of a 0 dBm fullscale signal.

Adjacent Channel Leakage Ratio (ACLR)

The adjacent channel leakage (power) ratio is a ratio, in dBc, of the measured power within a channel relative to its adjacent channels.

Modulation Error Ratio (MER)

Modulated signals create a discrete set of output values referred to as a constellation. Each symbol creates an output signal corresponding to one point on the constellation. MER is a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol.

Intermodulation Distortion (IMD)

IMD is the result of two or more signals at different frequencies mixing together. Many products are created according to the formula, aF1 ± bF2, where a and b are integer values.

Rev. A | Page 22 of 44

AD9739A

SERIAL PORT INTERFACE (SPI) REGISTER

SPI REGISTER MAP DESCRIPTION

The AD9739A contains a set of programmable registers described in Ta ble 9 that are used to configure and monitor various internal parameters. Note the following points when programming the AD9739A SPI registers:

• Registers pertaining to similar functions are grouped

together and assigned adjacent addresses.

• Bits that are undefined within a register should be assigned

a 0 when writing to that register.

• Registers that are undefined should not be written to.

• A hardware or software reset is recommended upon

power-up to place SPI registers in a known state.

• A SPI initialization routine is required as part of the boot

process. See Tab l e 12 for an example procedure.

Reset

Issuing a hardware or software reset places the AD9739A SPI registers in a known state. All SPI registers (excluding 0x00) are set to their default states as described in Tabl e 9 upon issuing a reset. After issuing a reset, the SPI initialization process need only write to registers that are required for the boot process as well as any other register settings that must be modified, depending on the target application.

Although the AD9739A does feature an internal power-on-reset (POR), it is still recommended that a software or hardware reset be implemented shortly after power-up. The internal reset signal is derived from a logical OR operation from the internal POR signal, the RESET pin, and the software reset state. A software reset can be issued via the reset bit (Register 0x00, Bit 5) by toggling the bit high then low. Note that, because the MSB/LSB format may still be unknown upon initial power-up (that is, internal POR is unsuccessful), it is also recommended that the bit settings for Bits[7:5] be mirrored onto Bits[2:0] for the instruction cycle that issues a software reset. A hardware reset can be issued from a host or external supervisory IC by applying a high pulse with a minimum width of 40 ns to the RESET pin (that is, Pin F14). RESET should be tied to VSS if unused.

Table 8. SPI Registers Pertaining to SPI Options

Address (Hex) Bit Description

0x00

7 Enable 3-wire SPI 6 Enable SPI LSB first 5 Software reset

SPI OPERATION

The serial port of the AD9739A shown in Figure 69 has a 3- or 4-wire SPI capability, allowing read/write access to all registers that configure the device’s internal parameters. It provides a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The 3.3 V serial I/O is compatible with most synchronous transfer formats, including the Motorola® SPI and the Intel® SSR protocols.

SDO (PIN H14)

SDIO (PIN G14)

SCLK (PIN H13)

CS (PIN G13)

Figure 69. AD9739A SPI Port

The default 4-wire SPI interface consists of a clock (SCLK), serial port enable (

), serial data input (SDIO), and serial data output (SDO). The inputs to SCLK, Schmitt trigger with a nominal hysteresis of 0.4 V centered

about VDD33/2. The maximum frequency for SCLK is 20 MHz. The SDO pin is active only during the transmission of data and remains three-stated at any other time.

A 3-wire SPI interface can be enabled by setting the SDIO_DIR bit (Register 0x00, Bit 7). This causes the SDIO pin to become bidirectional such that output data only appears on the SDIO pin during a read operation. The SDO pin remains three-stated in a 3-wire SPI interface.

Instruction Header Information

MSB LSB

17 16 15 14 13 12 11 10 R/W

A6 A5 A4 A3 A2 A1 A0

An 8-bit instruction header must accompany each read and write operation. The MSB is a R/

indicating a read operation. The remaining seven bits specify the address bits to be accessed during the data transfer portion. The eight data bits immediately follow the instruction header for both read and write operations. For write operations, registers change immediately upon writing to the last bit of each transfer byte.

can be raised after each sequence of eight bits

(except the last byte) to stall the bus. The serial transfer resumes

when

is lowered. Stalling on nonbyte boundaries resets the

SPI.

AD9739

SPI PORT

09616-072

, and SDIO contain a

indicator bit with logic high

Rev. A | Page 23 of 44

AD9739A

SCLK

The AD9739A serial port can support both most significant bit (MSB) first and least significant bit (LSB) first data formats. Figure 70 illustrates how the serial port words are formed for the MSB first and LSB first modes. The bit order is controlled by the SDIO_DIR bit (Register 0x00, Bit 7). The default value is 0, MSB first. When the LSB first bit is set high, the serial port interprets both instruction and data bytes LSB first.

SCLK

SDATA

SCLK

SDATA

INSTRUCTIO N CYCLE

R/W

INSTRUCTION CYCLE

A3A1 A2A0 A4

Figure 70. SPI Timing, MSB First (Upper) and LSB First (Lower)

Figure 71 illustrates the timing requirements for a write operation to the SPI port. After the serial port enable ( signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of the clock (SCLK). To

DATA TRANSFER CYCL E

A1A3 A2A4N1N1N2

DATA TRANSFER CYCL E

R/W

D01D1

D1ND0

D6ND7

)

initiate a write operation, the read/not-write bit is set low. After the instruction header is read, the eight data bits pertaining to the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles.

Figure 72 illustrates the timing for a 3-wire read operation to the SPI port. After

goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles.

Figure 73 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation with the exception that data appears at the SDO pin only, while the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times.

09616-073

SCLK

SDIO

SCLK

R/W

LOW

N1 N0

9616-074

Figure 71. SPI Write Operation Timing

SDIO

SCLK

R/W

LOW

09616-075

Figure 72. SPI 3-Wire Read Operation Timing

SCLK

SDIO

SDO

SCLK

R/W

LOW

09616-076

Figure 73. SPI 4-Wire Read Operation Timing

Rev. A | Page 24 of 44

AD9739A

SPI REGISTER MAP

Table 9.

Address (Hex)

Name Bit R/W

SPI Port Configuration and Software Reset 0x00

SDIO_DIR 7 R/W 0 0 = 4-wire SPI, 1 = 3-wire SPI. LSB/MSB 6 R/W 0 0 = MSB first, 1 = LSB first. Reset 5 R/W 0

Power-Down LVDS Interface and TxDAC 0x01

LVDS_DRVR_PD 5 R/W 0 LVDS_RCVR_PD4 4 R/W 0 CLK_RCVR_PD 1 R/W 0

DAC_BIAS_PD 0 R/W 0 Controller Clock Disable 0x02

CLKGEN_PD 3 R/W 0 Internal CLK distribution enable: 0 = enable, 1 = disable.

REC_CNT_CLK 1 R/W 1

MU_CNT_CLK 0 R/W 1

Default Setting

Comments

Software reset is recommended before modification of other SPI registers from the default setting. Setting the bit to 1 causes all registers (except 0x00) to be set to the default setting. Setting the bit to 0 corresponds to the inactive state, allowing the user to modify registers from the default setting.

Power-down of the LVDS drivers/receivers and TxDAC. 0 = enable, 1 = disable.

LVDS receiver and Mu controller clock disable. 0 = disable, 1 = enable.

Interrupt Request (IRQ) Enable/Status 0x03

0x04

TxDAC Full-Scale Current Setting (I 0x06 FSC_1 [7:0] R/W 0x00 0x07

MU_LST_EN 3 W 0

MU_LCK_EN 2 W 0

RCV_LST_EN 1 W 0

RCV_LCK_EN 0 W 0

MU_LST_IRQ 3 R 0

MU_LCK_IRQ 2 R 0

RCV_LST_IRQ 1 R 0

RCV_LCK_IRQ 0 R 0

) and Sleep

OUTFS

FSC_2 [1:0] R/W

0x02

Sleep 7 R/W

This register enables the Mu and LVDS Rx controllers to update their corresponding IRQ status bits in Register 0x04, which defines whether the controller is locked (LCK) or unlocked (LST).

0 = disable (resets the status bit), 1 = enable.

This register indicates the status of the controllers. For LCK_IQR bits: 0 = lost locked, 1 = locked. For LST_IQR bits: 0 = not lost locked, 1 = unlocked. Note that, if the controller IRQ is serviced, the relevant bits in Register 0x03 should be reset by writing 0, followed by another write of 1 to enable.

Sets the TxDAC I

= 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023.

OUTFS

current between 8 mA and 31 mA (default = 20 mA).

OUTFS

0 = enable DAC output, 1 = disable DAC output (sleep). TxDAC Quad-Switch Mode of Operation 0x08 DAC-DEC [1:0] R/W 0x00 0x00 = normal baseband mode.

0x01 = return-to-zero mode.

0x02 = mix mode. DCI Phase Alignment Status 0x0C

DCI_PRE_PH0 2 R 0

0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling

edge.

1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling

edge.

DCI_PST_PH0 0 R 0

0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling

edge.

1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling

edge.

Rev. A | Page 25 of 44

AD9739A

Address (Hex) Name Bit R/W

Data Receiver Controller Configuration 0x10

Data Receiver Controller_Data Sample Delay Value 0x11 SMP_DEL[1:0] [7:6] R/W 11

0x12 SMP_DEL[9:2] [7:0] R/W 0x25

Data Receiver Controller_DCI Delay Value/Window and Phase Rotation

0x14 DCI_DEL[9:4] [5:0] R/W 001010

Data Receiver Controller_Delay Line Status

0x19 SMP_DEL[1:0] [1:0] R 00 0x1A SMP_DEL[9:2] [7:0] R 0x00 0x1B DCI_DEL[1:0] [1:0] R 00 0x1C DCI_DEL[9:2] [7:0] R 0x00

RCVR_FLG_RST 2 W 0 Data receiver controller flag reset. Write 1 followed by 0 to reset flags. RCVR_LOOP_ON 1 R/W 1

RCVR_CNT_ENA 0 R/W 0 Data receiver controller enable. 0 = disable, 1 = enable.

DCI_DEL[3:0] [7:4] R/W 0111 Refer to the DCI_DEL description in Register 0x14. 0x13

FINE_DEL_SKEW [3:0] R/W 0001

Default Setting

Comments

0 = disable, 1 = enable. When enabled, the data receiver controller generates an IRQ; it falls out of lock and automatically begins a search/track routine.

Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample data. Leave at the default setting of 167, which represents the midpoint of the delay line.

Controller disabled: the value sets the actual value of the delay line.

A 4-bit value sets the difference (that is, window) for the DCI PRE and POST sampling clocks. Leave at the default value of 1 for a narrow window.

Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample the DCI input. Leave at the default setting of 167, which represents the midpoint of the delay line.

Controller disabled: the value sets the actual value of the delay line.

The actual value of the DCI and data delay lines determined by the data receiver controller (when enabled) after the state machine completes its search and enters track mode. Note that these values should be equal.

Data Receiver Controller Lock/Tracking Status 0x21

CLK Input Common Mode

Mu Controller Configuration and Status

0x25

0x26

Read 3 R/W 0 Set to 1 to read the current value of the Mu delay line in.

RCVR_TRK_ON 3 R 0 0 = tracking not established, 1 = tracking established. RCVR_LST 1 R 0 0 = controller has not lost lock, 1 = controller has lost lock.

RCVR_LCK 0 R 0 0 = controller is not locked, 1 = controller is locked.

DIR_P 4 R/W 0 0x22

CLKP_OFFSET[3:0] [3:0] R/W 0000

DIR_N 4 R/W 0 0x23

CLKN_OFFSET[3:0] [3:0] R/W 0000

CMP_BST 5 R/W 0 0x24

PHS_DET AUTO_EN

MU_DUTY AUTO_EN

Slope 6 R/W 1

Mode[1:0] [5:4] R/W 00 Sets the Mu controller mode of operation.

4 R/W 0

7 R/W 0 Mu controller duty cycle enable.

DIR_P and DIR_N. 0 = VCM at the DACCLK_P input decreases with the offset value. 1 = VCM at the DACCLK_P input increases with the offset value. CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and DACCLK_N

inputs. For optimum performance, set to 1111.

Phase detector enable and boost bias bits. Note that both bits should always be set to 1 to enable these functions.

Note that this bit should always be set to 1 to enable. Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Note that a

setting of 0 is recommended for best ac performance.

00 = search and track (recommended). 01 = search only. 10 = track.

Rev. A | Page 26 of 44

AD9739A

Address (Hex) Name Bit R/W

Gain[1:0] [2:1] R/W 01 Sets the Mu controller tracking gain.

Enable 0 R/W 0 0 = enable the Mu controller.

0x27

MUDEL[0] 7 R/W 0 The LSB of the 9-bit MUDEL setting.

Default Setting

Comments

Recommended to leave at the default 01 setting.

1 = disable the Mu controller.

SRCH_MODE[1:0] [6:5] R/W 0

SET_PHS[4:0] [4:0] R/W 0 Sets the target phase that the Mu controller locks to with a maximum setting of 16.

0x28 MUDEL[8:1] [7:0]

0x29

0x2A

Part ID 0x35 PART_ID [7:0] R 0x24

SEARCH_TOL 7 R/W 0 0 = not exact (can find a phase within two values of the desired phase).

Retry 6 R/W 0 0 = stop the search if the correct value is not found,

CONTRST 5 R/W 0

Guard[4:0] 5 R/W 01011

MU_LST 1 R 0 0 = Mu controller has not lost lock.

MU_LKD 0 R 0 0 = Mu controller is not locked.

W 0x00

R 0x00

Sets the direction in which the Mu controller searches (from its initial MUDEL setting)

for the optimum Mu delay line setting that corresponds to the desired phase/slope

setting (that is, SET_PHS and slope ).

00 = down.

01 = up.

10 = down/up (recommended).

A setting of 4 (that is, 00100) is recommended for optimum ac performance.

With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the value

that the Mu delay is set to. Note that the maximum value is 432.

With enable set to 1, this value represents the Mu delay value at which the

controller begins its search. Setting this value to the delay line midpoint of 216 is

recommended.

When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to the

value written into the register when enable = 0 or the value that the Mu

controller locks to when enable = 1.

1 = finds the exact phase that is targeted (optimal setting).

1 = retry the search if the correct value is not found.

Controls whether the controller resets or continues when it does not find the

desired phase.

0 = continue (optimal setting), 1 = reset.

Sets a guard band from the beginning and end of the mu delay line which the

Mu controller does not enter into unless it does not find a valid phase outside

the guard band (optimal value is Decimal 11 or 0x0B).

1 = Mu controller has lost lock.

1= Mu controller is locked.

Rev. A | Page 27 of 44

AD9739A

THEORY OF OPERATION

The AD9739A is a 14-bit TxDAC with a specified update rate of

1.6 GSPS to 2.5 GSPS. Figure 74 shows a top-level functional diagram of the AD9739A. A high performance TxDAC core delivers a signal dependent, differential current (nominal ±10 mA) to a balanced load referenced to ground. The frequency of the clock signal appearing at the AD9739A differential clock receiver, DACCLK, sets the TxDAC’s update rate. This clock signal, which serves as the master clock, is routed directly to the TxDAC as well as to a clock distribution block that generates all critical internal and external clocks.

The AD9739A includes two 14-bit LVDS data ports (DB0 and DB1) to reduce the data interface rate to ½ the TxDAC update rate. The host processor drives deinterleaved data with offset binary format onto the DB0 and DB1 ports, along with an embedded DCI clock that is synchronous with the data. Because the interface is double data rate (DDR), the DCI clock is essentially an alternating 0-1 bit pattern with a frequency equal to ¼ the TxDAC update rate (f ronization with the host processor, the AD9739A passes an LVDS clock output (DCO) that is also equal to the DCI frequency.

The AD9739A data receiver controller generates an internal sampling clock for the DDR receiver such that the data instance sampling is optimized. When enabled and configured properly for track mode, it ensures proper data recovery between the host and the AD9739A clock domains. The data receiver controller has the ability to track several hundreds of ps of drift between these clock domains, typically caused by supply and temperature variation.

As mentioned, the host processor provides the AD9739A with a deinterleaved data stream such that the DB0 and DB1 data ports receive alternating samples (that is, odd/even data streams). The AD9739A data assembler is used to reassemble (that is, multiplex) the odd/even data streams into their original order before delivery into the TxDAC for signal reconstruction. The pipeline delay from a sample being latched into the data port to when it appears at the DAC output is on the order of 78 (±) DACCLK cycles.

). To simplify synch-

DAC

The AD9739A includes a delay lock loop (DLL) circuit controlled via a Mu controller to optimize the timing hand-off between the AD9739A digital clock domain and TxDAC core. Besides ensuring proper data reconstruction, the TxDAC’s ac performance is also dependent on this critical hand-off between these clock domains with speeds of up to 2.5 GSPS. Once properly initialized and configured for track mode, the DLL maintains optimum timing alignment over temperature, time, and power supply variation.

A SPI interface is used to configure the various functional blocks as well as monitor their status for debug purposes. Proper operation of the AD9739A requires that controller blocks be initialized upon power-up. A simple SPI initialization routine is used to configure the controller blocks (see Tab l e 1 1 ). An IRQ output signal is available to alert the host should any of the controllers fall out of lock during normal operation.

The following sections discuss the various functional blocks in more detail as well as their implications when interfacing to external ICs and circuitry. While a detailed description of the various controllers (and associated SPI registers used to configure and monitor) is also included for completeness, the recommended SPI boot procedure can be used to ensure reliable operation.

SDIO

SDO

CLK

DCO

DCI

RESET

SPI

DB0[13:0]DB1[13:0]

LVDS DDR

DATA

CONTRO LLER

LVDS DDR

(DIV-BY-4)

IRQ

AD9739A

1.2V

DAC BIAS

RECEIVE R

TxDAC

DATA

4-TO-1

DATA ASSEMBLER

RECEIVE R

CLK DISTRIBUT ION

CORE

LATCH

DLL

(MU CONTROL LER)

VREF

I120

IOUTN

IOUTP

DACCLK

Figure 74. Functional Block Diagram of the AD9739A

Rev. A | Page 28 of 44

09616-077

AD9739A

LVDS DATA PORT INTERFACE

The AD9739A supports input data rates from 1.6 GSPS to

2.5 GSPS using dual LVDS data ports. The interface is source synchronous and double data rate (DDR) where the host provides an embedded data clock input (DCI) at f rising and falling edges aligned with the data transitions. The data format is offset binary; however, twos complement format can be realized by reversing the polarity of the MSB differential trace. As shown in Figure 75, the host feeds the AD9739A with deinterleaved input data into two 14-bit LVDS data ports (DB0 and DB1) at ½ the DAC clock rate (that is, f

DAC

AD9739A internal data receiver controller then generates a phase shifted version of DCI to register the input data on both the rising and falling edges.

HOST

PROCESSOR

EVEN DATA

SAMPLES

14 × 2

DAC

SAMPLES

14 × 2

1 × 2

DAC

1 × 2

DAC

DATA

ODD DATA

LVDS DDR DRIVER

DATA DEINTERLEAVER

DCI

DCO

Figure 75. Recommended Digital Interface Between the AD9739A and

Host Processor

AD9739A

DB0[13:0]

DB1[13:0]

DCI

DCO

As shown in Figure 76, the DCI clocks edges must be coincident with the data bit transitions with minimum skew, jitter, and intersymbol interference. To ensure coincident transitions with the data bits, the DCI signal should be implemented as an additional data line with an alternating (010101…) bit sequence from the same output drivers used for the data. Maximizing the opening of the eye in both the DCI and data signals improves the reliability of the data port interface. Differential controlled impedance traces of equal length (that is, delay) should also be

DAC

/2). The

LVDS DDR

RECEIVER

LVDS DDR

RECEIVER

DIV-BY-4

/4 with its

DATA

CONTROLLER

DAC

09616-078

used between the host processor and AD9739A input to limit bit-to-bit skew.

The maximum allowable skew and jitter out of the host processor with respect to the DCI clock edge on each LVDS port is calculated as follows:

MaxSkew + Jitter = Period(ns) − ValidWindow(ps) − Guard

= 800 ps − 344 ps − 100 ps

= 356 ps

where Va li dW in d ow (ps) is represented by t represented by t

in Figure 76.

GUARD

and Guard is

VA L I D

The minimum specified LVDS valid window is 344 ps, and a guard band of 100 ps is recommended. Therefore, at the maximum operating frequency of 2.5 GSPS, the maximum allowable FPGA and PCB bit skew plus jitter is equal to 356 ps.

For synchronous operation, the AD9739A provides a data clock output, DCO, to the host at the same rate as DCI (that is, f

DAC

/4) to maintain the lowest skew variation between these clock domains. The host processor has a worst case skew between DCO and DCI that is both implementation and process dependent. This worst case skew can also vary an additional 30% over temperature and supply corners. The delay line within the data receiver controller can track a ±1.5 ns skew variation after initial lock. While it is possible for the host to have an internal PLL that generates a synchronous f

/4 from which the

DAC

DCI signal is derived, digital implementations that result in the shortest propagation delays result in the lowest skew variation.

The data receiver controller is used to ensure proper data handoff between the host and AD9739A internal digital clock domains. The circuit shown in Figure 77 functions as a delay lock loop in which a 90

phase shifted version of the DCI clock input is used to sample the input data into the DDR receiver registers. This ensures that the sampling instance occurs in the middle of the data pattern eyes (assuming matched DCI and DBx[13:0] delays). Note that, because the DCI delay and sample delay clocks are derived from the DIV-BY-4 circuitry, this 90° phase relationship holds as long as the delay settings (that is, DCI_DEL, SMP_DEL) are also matched.

2 × 1

DAC

DCI

VALID

DB0[13:0]

ND DB1[13:0]

VALID

GUARD

max skew

+ jitter

09616-079

Figure 76. LVDS Data Port Timing Requirements

Rev. A | Page 29 of 44

AD9739A

DCI

DDR

DATA RECEIVER CONT ROLLER

DCI WINDOW PRE

DBx[13:1]

DCO

DDR

DCI WINDOW PO ST

DCI WINDOW SAMPLE

DDR

FINE

DELAY

PRE

FINE

DELAY

POST

FINE

DELAY

SAMPLE

DDR

ELASTIC FIFO

DELAY

Figure 77. Top Level Diagram of the Data Receiver Controller

The DIV-BY-4 circuit generates four clock phases that serve as inputs to the data receiver controller. All of the DDR registers in the data and DCI paths operate on both clock edges; however, for clarity purposes, only the phases (that is, 0

and 90o) corresponding to the positive edge of each path are shown. One of the DIV-BY-4 phases is used to generate the DCO signal; therefore, the phase relationship between DCO and clocks fed into the controller remains fixed. Note that it is this attribute that allows possible factory calibration of images and clock spurs attributed to f

/4 modulation of the critical DAC clock.

DAC

Once this data has been successively sampled into the first set of registers, an elastic FIFO is used to transfer the data into the AD9739A clock domain. To continuously track any phase variation between the two clock domains, the data receiver controller should always be enabled and placed into track mode (Register 0x10, Bit 1 and Bit 0). Tracking mode operates continuously in the background to track delay variations between the host and AD9739A clock domains. It does so by ensuring that the DCI signal is sampled within a very narrow window defined by two internally generated clocks (that is, PRE and PST), as shown in Figure 78. Note that proper sampling of the DCI signal can also be confirmed by monitoring the status of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0 (Register 0x0C, Bit 0). If the delay settings are correct, the state of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0 should be 1.

STATE MACHINE/ TRACKING LO OP

DDR

DELAY

DCI DELAY

SAMPLE

DELAY

FINE DELAY

DCI

DELAY

PATH

SAMPLE

DELAY

PATH

DDR

DCI

PST

PRE

DATA TO CORE

FINE_DEL_S KEW

0 90

180

270

DIV-BY-4

Figure 78. Pre- and Post-Delay Sampling Diagram

The skew or window width (FINE_DEL_SKEW) is set via Register 0x13, Bits[3:0], with a maximum skew of approximately 300 ps and resolution of 20 ps. It is recommended that the skew be set to 60 ps (that is, Register 0x13 = 0x72) during initialization. Note that the skew setting also affects the speed of the controller loop, with tighter skew settings corresponding to longer response time.

Data Receiver Controller Initialization Description

The data controller should be initialized and placed into track mode as the second step in the SPI boot sequence. The following steps are recommended for the initialization of the data receiver controller:

1. Set FINE_DEL_SKEW to 2 for a larger DCI sampling

window (Register 0x13 = 0x72). Note that the default DCI_DEL and SMP_DEL settings of 167 are optimum.

2. Disable the controller before enabling (that is, Register

0x10 = 0x00).

3. Enable the Rx controller in two steps: Register 0x10 – 0x02

followed by Register 0x10 = 0x03.

4. Wait 135 K clock cycles.

DAC

09616-080

09616-081

Rev. A | Page 30 of 44

AD9739A

5. Read back Register 0x21 and confirm that it is equal to

0x05 to ensure that the DLL loop is locked and tracking.

6. Read back the DCI_DEL value to determine whether the

value falls within a user defined tracking guard band. If it does not, go back to Step 2.

Once the controller is enabled during the initial SPI boot process (see Ta b le 1 2), the controller enters a search mode where it seeks to find the closest rising edge of the DCI clock (relative to a delayed version of an internal f

/4 clock) by

DAC

simultaneously adjusting the delays in the clocks used to register the DCI and data inputs. A state machine searches above and below the initial DCI_DEL value. The state machine first searches for the first rising edge above the DCI_DEL and then searches for the first rising edge below the DCI_DEL value. The state machine selects the closest rising edge and then enters track mode. It is recommended that the default midpoint delay setting (that is, Decimal 167) for the DCI_DEL and SMP_DEL bits be kept to ensure that the selected edge remains closest to the delay line midpoint, thus providing the greatest range for tracking timing variations and preventing the controller from falling out of lock.

The adjustable delay span for these internal clocks (that is, DCI and sample delay) is nominally 4 ns. The 10-bit delay value is user programmable from the decimal equivalent code (0 to 334) with approximately 12 ps/LSB resolution via the DCI_DEL and SMP_DEL registers (Register 0x13 and Register14). When the controller is enabled, it overwrites these registers with the delay value it converges upon. The minimum difference between this delay value and the minimum/maximum values (that is, 0 and

334) represents the guard band for tracking. Therefore, if the controller initially converges upon a DCI_DEL and SMP_DEL value between 80 and 254, the controller has a guard band of at least 80 code (approximately 1 ns) to track phase variations between the clock domains.

Upon initialization of the AD9739A, a certain period of time is required for the data receiver controller to establish a lock of the DCI clock signal. Note that, due to its dependency on the Mu controller, the data receiver controller should be enabled only after the Mu controllers have been enabled and established lock. All of the internal controllers operate at a submultiple of the DAC update rate. The number of f

clock cycles required to

DAC

lock onto the DCI clock is typically 70 k clock cycles but can be up to 135 k clock cycles. During the SPI initialization process, the user has the option of polling Register 0x21 (Bit 0, Bit 1, and Bit 3) to determine if the data receiver controller is locked, has lost lock, or has entered into track mode before completing the boot sequence. Alternatively, the appropriate IRQ bit (Register 0x03 and Register 0x04) can be enabled such that an IRQ output signal is generated upon the controller establishing lock.

The data receiver controller can also be configured to generate an interrupt request (IRQ) upon losing lock. Losing lock can be caused by disruption of the main DAC clock input or loss of a

power supply rail. To service the interrupt, the host can poll the RCVR_LCK bit to determine the current state of the controller. If this bit is cleared, the search/track procedure can be restarted by setting the RCVR_LOOP_ON bit in Register 0x10, Bit 1. After waiting the required lock time, the host can poll the RCVR_LCK bit to see if it has been set. Before leaving the interrupt routine, the RCVR_FLG_RST bit should be reset by writing a high followed by a low.

LVDS Driver and Receiver Input

The AD9739A features an LVDS-compatible driver and receivers. The LVDS driver output used for the DCO signal includes an equivalent 200  source resistor that limits its nominal output voltage swing to ±200 mV when driving a 100  load. The DCO output driver can be powered down via Register 0x1, Bit 5. An equivalent circuit is shown in Figure 79.

VDD33

DCO_N

DCI_P

DBx[13:0] P

V+

ESD ESD

V–

Figure 79. Equivalent LVDS Output

ESD

Figure 80. Equivalent LVDS Input

100Ω

VDD33

100Ω

VCM

VSS

100Ω

VSS

V–

V+

ESD

DCO_

DCI_N DBx[13:0]N

09616-082

09616-083

The LVDS receivers include 100  termination resistors, as shown in Figure 80. These receivers meet the IEEE-1596.3-1996 reduced swing specification (with the exception of input hysteresis, which cannot be guaranteed over all process corners). Figure 81 and Tab l e 1 0 show an example of nominal LVDS voltage levels seen at the input of the differential receiver with resulting common-mode voltage and equivalent logic level. Note that the AD9739A LVDS inputs do not include fail-safe capability; hence, any unused input should be biased with an external circuit or static driver. The LVDS receivers can be powered-down via Register 0x01, Bit 4.

Rev. A | Page 31 of 44

AD9739A

= (V

LVD S I NPUT S

(NO FAIL-SAFE)

COM

+ VN)/2

LOGIC BIT

EQUIVALENT

P, N

100Ω

GND

Example

Figure 81. LVDS Data Input Levels

Table 10. Example of LVDS Input Levels

Resulting

Applied Voltages VP V

Resulting Differential Voltage

P, N

CommonModel Voltage

COM

1.4 V 1.0 V +0.4 V 1.2 V 1

1.0 V 1.4 −0.4 V 1.2 V 0

1.0 V 0.8 V +200 mV 900 mV 1

0.8 V 1.0 V −200 mV 900 mV 0

MU CONTROLLER

A delay lock loop (DLL) is used to optimize the timing between the internal digital and analog domains of the AD9739A such that data is successfully transferred into the TxDAC core at rates of up to 2.5 GSPS. As shown in Figure 82, the DAC clock is split into an analog and a digital path with the critical analog path leading to the DAC core (for minimum jitter degradation) and the digital path leading to a programmable delay line. Note that the output of this delay line serves as the master internal digital clock from which all other internal and external digital clocks are derived. The amount of delay added to this path is under the control of the Mu controller, which optimizes the timing between these two clock domains and continuously tracks any variation (once in track mode) to ensure proper data hand-off.

DAC

CLOCK

14-BI

DATA

DIGITAL

CIRCUITRY

DELAY

CONTROLL ER

Figure 82. Mu Delay Controller Block Diagram

DELAY

14-BI

DATA

PHASE

DETECTOR

ANALOG

CIRCUITRY

LVD S

RECEIVER

1.4V

1.0V

0.4V

–0.4V LOGIC 1

LOGIC 0

Logic Bit Binary Equivalent

IOUTP

IOUTN

09616-085

The Mu controller adjusts the timing relationship between the digital and analog domains via a tapped digital delay line having a nominal total delay of 864 ps. The delay value is programmable to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL register, resulting in a nominal resolution of 2 ps/LSB. Because a time delay maps to a phase offset for a fixed clock frequency, the control loop essentially compares the phase relationship between the two clock domains and adjusts the phase (that is, via a tapped delay line) of the digital clock such that it is at the desired fixed phase offset (SET_PHS) from the critical analog clock.

GUARD

BAND

DESIRED PHASE

09616-084

MU PHASE

0 40 80 120 160 200 240 280 320 360 400 440

SEARCH STARTING

LOCATIO N

MU DELAY

GUARD

BAND

09616-086

Figure 83. Typical Mu Phase Characteristic Plot at 2.4 GSPS

Figure 83 maps the typical Mu phase characteristic at 2.4 GSPS versus the 9-bit digital delay setting (MUDEL). The Mu phase scaling is such that a value of 16 corresponds to 180 degrees. The critical keep-out window between the digital and analog domains occurs at a value of 0 (but can extend out to +2 depending on the clock rate). The target Mu phase (and slope) is selected to provide optimum ac performance while ensuring that the Mu controller for any device can establish and maintain lock. While the Mu phase characteristics can vary among devices, a slope/phase setting of −4 has been verified to ensure robust operation and optimum ac performance for 1.6 GSPS to

2.5 GSPS operation.

After the Mu controller completes its search and establishes lock on the target Mu phase, it attempts to maintain a constant timing relationship between the two clock domains over the specified temperature and supply range. If the Mu controller requests a Mu delay setting that exceeds the tapped delay line range (that is, <0 or >432), the Mu controller can lose lock, causing possible system disruption (that is, can generate IRQ or restart the search). To avoid this scenario, symmetrical guard bands are recommended at each end of the Mu delay range. The guard band scaling is such that one LSB of Guard[4:0] corresponds to eight LSBs of MUDEL. The recommended guard band setting of 11 (that is, Register 0x29 = 0xCB) corresponds to 88 LSBs, thus providing sufficient margin.

Rev. A | Page 32 of 44

AD9739A

Mu Controller Initialization Description

The Mu controller must be initialized and placed into track mode as a first step in the SPI boot sequence. The following steps are required for initialization of the Mu controller. Note that the AD9739A data sheet specifications and characterization data are based on the following Mu controller settings:

1. Turn on the phase detector with boost (Register 0x24 =

0x30).

2. Enable the Mu delay controller duty-cycle correction

circuitry and specify the recommended slope for phase. (that is, Register 0x25 = 0x80 corresponds to a negative slope).

3. Specify search/track mode with a recommended target

phase, SET_PHS, of 4 and an initial MUDEL[8:0] setting of 216 (Register 0x27 = 0x44 and Register 0x28 = 0x6C).

4. Set search tolerance to exact and retry if the search fails

its initial attempt. Also, set the guard band to the recommended setting of 11 (Register 0x29 = 0xCB).

5. Set the Mu controller tracking gain to the recommended

setting and enable the Mu controller state machine (Register 0x26 = 0x03).

Upon completion of the last step, the Mu controller begins a search algorithm that starts with an initial delay setting specified by the MUDEL register (that is, 216, which corresponds to the midpoint of the delay line). The initial search algorithm works by sweeping through different Mu delay values in an alternating manner until the desired phase (that is, a SET_PHS of 4) is exactly measured. When the desired phase is measured, the slope of the phase measurement is then calculated and compared against the specified slope (slope = negative).

If everything matches, the search algorithm is finished. If not, the search continues in both directions until an exact match can be found or a programmable guard band is reached in one of the directions. When the guard band is reached, the search still continues but only in the opposite direction. If the desired phase is not found before the guard band is reached in the second direction, the search changes back to the alternating mode and continues looking within the guard band. The typical locking time for the Mu controller is approximately 180 K DAC cycles (at 2 GSPS ~ 75 s).

The search fails if the Mu delay controller reaches the endpoints. The Mu controller can be configured to retry (Register 0x29, Bit 6) the search or stop. For applications that have a microcontroller, the preferred approach is to poll the MU_LKD status bit (Register 0x2A, Bit 0) after the typical locking time has expired. This method allows the system controller to check the status of other system parameters (that is, power supplies and clock source) before reattempting the search (by writing 0x03 to Register 26). For applications not having polling capability, the Mu controller state machine should be reconfigured to restart the search in hopes that the systems condition that did not cause locking on the first attempt has disappeared.

Once the Mu delay value is found that exactly matches the desired Mu phase setting and slope (that is, 4 with a negative. slope), the Mu controller goes into track mode. In this mode, the Mu controller makes slight adjustments to the delay value to track any variations between the two clock paths due to temperature, time, and supply variations. Two status bits, MU_LKD (Register 0x2A, Bit 0) and MU_LST (Register 0x2A, Bit 1) are available to the user to signal the existing status control loop. If the current phase is more than four steps away from the desired phase, the MU_LKD bit is cleared, and the MU_LST bit is set if the lock acquired was previously set. Should the phase deviation return to within three steps, the MU_LKD bit is set again while the MU_LST is cleared. Note that this sort of event may occur if the main clock input (that is, DACCLK) is disrupted or the Mu controller exceeds the tapped delay line range (that is, <0 or >432).

If lock is lost, the Mu controller has the option of remaining in the tracking loop or resetting and starting the search again via the CONTRST bit (Register 0x29, Bit 5). Continued tracking is the preferred state because it is the least disruptive to a system in which the AD9739A temporarily loses lock. The user can poll the Mu delay and phase value by first setting the read bit high (Register 0x26, Bit 3). Once the read bit is set, the MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27 and Register 0x28) that the controller is currently using can be read.

INTERRUPT REQUESTS

The AD9739A can provide the host processor with an interrupt request output signal (IRQ) that indicates that one or more of the AD9739A internal controllers have achieved lock or lost lock. These controllers include the Mu, data receiver, and synchronization controllers. The host can then poll the IRQ status register (Register 0x04) to determine which controller has lost lock. The IRQ output signal is an active high output signal available on Pin F13. If used, its output should be connected via a 10 kΩ pull-up resistor to VDD33.

Each IRQ is enabled by setting the enable bits in Register 0x03, which purposely has the same bit mapping as the IRQ status bits in Register 0x04. Note that these IRQ status bits are set only when the controller transitions from a false to true state. Hence, it is possible for the x_LCK_IRQ and x_LST_IRQ status bits to be set when a controller temporarily loses lock but is able to reestablish lock before the IRQ is serviced by the host. In this case, the host should validate the present status of the suspect controller by reading back its current status bits, which are available in Register 0x21 and/or Register 0x2A. Based on the status of these bits, the host can take appropriate action, if required, to reestablish lock. To clear an IRQ after servicing, it is necessary to reset relevant bits in Register 0x03 by writing 0 followed by another write of 1 to reenable. A detailed diagram of the interrupt circuitry is shown in Figure 84.

Rev. A | Page 33 of 44

AD9739A

(PIN F13)

SPI

DATA

SCLK

INT

SOURCE

IMR

Figure 84. Interrupt Request Circuitry

INT(n)

SPI WRITE

DATA = 1

It is also possible to use the IRQ during the AD9739A initialization phase after power-up to determine when the Mu and data receiver controllers have achieved lock. For example, before enabling the Mu controller, the MU_LCK_EN bit can be set and the IRQ output signal monitored to determine when lock has been established before continuing in a similar manner with the data receiver controllers. Note that the relevant LCK bit should be cleared before continuing to the next controller. After all controllers are locked, the lost lock enable bits (that is, x_LST_EN) should be set.

INT SOURCE

SPI ISR READ DATA

SPI ADDRESS

09616-087

Table 11. Interrupt Request Registers

Address (Hex) Bit Description

0x03

MU_LST_EN 2 MU_LCK_EN 1 RCV_LST_EN 0 RCV_LCK_EN

0x04

3 MU_LST_IRQ 2 MU_LCK_IRQ 1 RCV_LST_IRQ 0 RCV_LCK_IRQ

0x21

3 RCVR_TRK_ON 1 RCVR_LST 0 RCVR_LCK 1 MU_LST 0x2A 0 MU_LKD

Rev. A | Page 34 of 44

AD9739A

ANALOG INTERFACE CONSIDERATIONS

ANALOG MODES OF OPERATION

The AD9739A uses the quad-switch architecture shown in Figure 85. The quad-switch architecture masks the codedependent glitches that occur in a conventional two-switch DAC. Figure 86 compares the waveforms for a conventional DAC and the quad-switch DAC. In the two-switch architecture, a code-dependent glitch occurs each time the DAC switches to a different state (that is, D1 to D2). This code-dependent glitching causes an increased amount of distortion in the DAC. In quad-switch architecture (no matter what the codes are), there are always two switches transitioning at each half clock cycle, thus eliminating the code-dependent glitches. However, a constant glitch occurs at 2 × DACCLK because half the internal switches change state on the rising DACCLK edge while the other half change state on the falling DACCLK edge.

DACCLK_x

DBx[13:0]

DACCLK_x

TWO-SWITCH DAC OUTPUT

FOUR-SWI TCH

DAC OUTPUT

(NORMAL MODE)

Another attribute of the quad-switch architecture is that it also enables the DAC core to operate in one of the following three modes: normal mode, mix mode, and return-to-zero (RZ ) mode. The mode is selected via SPI Register 0x08, Bits[1:0] with normal mode being the default value. In the mix mode, the output is effectively chopped at the DAC sample rate. This has the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the DAC sample rate, thus improving the output power of these images. The RZ mode is similar to the analog mix mode, except that the intermediate data samples are replaced with midscale values.

CLK

VG1

LATCHES

1G4VG3VG2

IOUTP

IOUTN

Figure 85. AD9739A Quad-Switch Architecture

INPU

D1D2D3D4D

DATA

D1D2D3D4D

D6D7D8D9D

Figure 86. Two-Switch and Quad-Switch DAC Waveforms

09616-088

INPU

DATA

DACCLK_x

FOUR-SWI TCH

DAC OUTPUT

MIX MODE)

(

FOUR-SWI TCH

DAC OUTPUT

(RETURN TO

ZERO MODE)

D1D2D3D4D

–D

D1D2D3D4D

D6D7D8D9D

–D

D6D7D8D9D

–D

09616-090

Figure 87. Mix-Mode and RZ DAC Waveforms

Figure 87 shows the DAC waveforms for both the mix mode and the RZ mode. Note that the disadvantage of the RZ mode is the 6 dB loss of power to the load because the DAC is only functioning for ½ the DAC update period. This ability to change modes provides the user the flexibility to place a carrier anywhere in the first three Nyquist zones, depending on the operating mode selected. Switching between the analog modes reshapes the sinc roll-off inherent at the DAC output. The maximum amplitude in all three Nyquist zones is impacted by this sinc roll-off, depending on where the carrier is placed (see Figure 88). As a practical matter, the usable bandwidth in the third Nyquist zone becomes limited at higher DAC clock rates (that is, >2 GSPS) when the output bandwidth of DAC core and the interface network (that is, balun) contributes to additional roll-off.

FIRST

NYQUIS T ZO NE

–5

RZ MODE

–10

09616-089

–15

–20

–25

–30

–35

0FS 1.50FS1.25FS1.00FS0.75FS0.50FS0.25F S

Figure 88. Sinc Roll-Off for Each Analog Operating Mode

SECOND

NYQUIST ZONE

MIX MODE

FREQUENCY (Hz)

NORMAL

MODE

THIRD

NYQUIST Z ONE

09616-091

Rev. A | Page 35 of 44

AD9739A

CLOCK INPUT CONSIDERATIONS

REF

50Ω

10nF

50Ω 50Ω

Figure 89. ADCLK914 Interface to the AD9739A CLK Input

ADF4350

VCO

DIV-BY-2

N = 0 – 4

PLL

FREF

Figure 90. ADF4350 Interface to the AD9739A CLK Input

The quality of the clock source and its drive strength are important considerations in maintaining the specified ac performance. The phase noise and spur characteristics of the clock source should be selected to meet the target application requirements. Phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. It can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 × log10(f

) when the DAC clock path contribution,

OUT/fCLK

along with thermal and quantization effects, are negligible.

The AD9739A clock receiver provides optimum jitter performance when driven by a fast slew rate originating from the LVPECL or CML output drivers. For a low jitter sinusoidal clock source, the ADCLK914 can be used to square-up the signal and provide a CML input signal for the AD9739A clock receiver. Note that all specifications and characterization presented in the data sheet are with the ADCLK914 driven by a high quality RF signal generator with the clock receiver biased at a 800 mV level.

Figure 90 shows a clock source based on the ADF4350 low phase noise/jitter PLL. The ADF4350 can provide output frequencies from 140 MHz up to 4.4 GHz with jitter as low as

0.5 ps rms. Each single-ended output can provide a squared-up output level that can be varied from −4 dBm to +5 dBm allowing for >2 V p-p output differential swings. The ADF4350 also includes an additional CML buffer that can be used to drive another AD9739A device.

VCO

ADCLK914

A+

OUT

A–

OUT

A+

OUT

A–

OUT

DACCLK_P

DACCLK_N

50Ω 50Ω

100Ω

3.9nH

100Ω

1.8V p-p

10nF

1nF

ESD

AD9739A

DACCLK_P

DACCLK_N

AD9739A

DACCLK_P

DACCLK_N

4-BIT PMO S

IOUT ARRAY

CLKx_OFFS ET

DIR_x = 0

CLKx_OFFS ET

DIR_x = 0

4-BIT NMOS

IOUT ARRAY

09616-092

09616-093

Figure 91. Clock Input and Common-Mode Control

The AD9739A clock receiver features the ability to independently adjust the common-mode level of its inputs over a span of ±100 mV centered about is mid-supply point (that is, VDDC/2) as well as an offset for hysteresis purposes. Figure 91 shows the equivalent input circuit of one of the inputs. ESD diodes are not shown for clarity purposes. It has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 V. This can be achieved by writing a 0x0F (corresponding to a −15) setting to both cross controller registers (that is, Register 0x22 and Register 0x23).

VDDC

VSSC

09616-094

Rev. A | Page 36 of 44

AD9739A

1.10

1.05

1.00

0.95

0.90

CLKP CLKN

The following equation relates I

to the FSC[9:0] register,

OUTFS

which can be set from 0 to 1023.

= 22.6 × FSC[9:0]/1000 + 8.7 (1)

OUTFS

Note that a default value of 0x200 generates 20 mA full scale, which is used for most of the characterization presented in this data sheet (unless noted otherwise).

0.85

COMMON MODE (V)

0.80

0.75

0.70 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15

OFFSET CODE

09616-095

Figure 92. Common-Mode Voltage with Respect to

CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N

VOLTAGE REFERENCE

The AD9739A output current is set by a combination of digital control bits and the I120 reference current, as shown in Figure 93.

AD9739

1.2V

1nF

VREF

I120

10kΩ

VSSA

–

I120

Figure 93. Voltage Reference Circuit

The reference current is obtained by forcing the band gap voltage across an external 10 kΩ resistor from I120 (Pin B14) to ground. The 1.2 V nominal band gap voltage (VREF) generates a 120 μA reference current in the 10 kΩ resistor. Note the following constraints when configuring the voltage reference circuit:

 Both the 10 kΩ resistor and 1 nF bypass capacitor are

required for proper operation.

 Adjusting the DAC’s output full-scale current, I

its default setting of 20 mA should be performed digitally.

 The AD9739A is not a multiplying DAC. Modulating the

reference current, I120, with an ac signal is not supported.

 The band gap voltage appearing at the VREF pin must be

buffered for use with an external circuitry because its output impedance is approximately 5 kΩ.

 An external reference can be used to overdrive the internal

reference by connecting it to the VREF pin.

can be adjusted digitally over 8.7 mA to 31.7 mA by using

OUTFS

FSC[9:0] (Register 0x06 and Register 0x07).

FSC[9:0]

CURRENT

SCALING

DAC

IFULL-SCALE

OUTFS

09616-096

, from

ANALOG OUTPUTS

Equivalent DAC Output and Transfer Function

The AD9739A provides complementary current outputs, IOUTP and IOUTN, that source current into an external ground reference load. Figure 94 shows an equivalent output circuit for the DAC. Note that, compared to most current output DACs of this type, the AD9739A outputs exhibit a slight offset current (that is, I current is slightly below I

15/32 × I

Figure 94. Equivalent DAC Output Circuit

As shown in Figure 94, the DAC output can be modeled as a pair of dc current sources that source a current of 17/32 × I to each output. A differential ac current source, I model the signal-dependent nature of the DAC output. The polarity and signal dependency of this ac current source are related to the digital code by the following equation:

F(Code) = (DACCODE − 8192)/8192 (2)

−1 < F(Code) < 1 (3)

where DACCODE = 0 to 16,383 (decimal).

Because I

can swing ±(15/32) × I

PEAK

measured at IOUTP and IOUTN can span from I I

. However, because the ac signal-dependent current

OUTFS

component is complementary, the sum of the two outputs is always constant (that is, IOUTP + IOUTN = (34/32) × I

The code-dependent current measured at the IOUTP (and IOUTN) output is as follows:

IOUTP = 17/32 × I

IOUTN = 17/32 × I

Figure 95 shows the IOUTP vs. DACCODE transfer function when I

is set to 19.65 mA.

OUTFS

/16), and the peak differential ac

OUTFS

/2 (that is, 15/32 × I

OUTFS

= 8.6 – 31.2mA

OUTFS

17/32 × I

OUTFS

PEAK

OUTFS

17/32 × I

OUTFS

70Ω

OUTFS

+ 15/32 × I

− 15/32 × I

, the output currents

OUTFS

2.2pF

09616-097

OUTFS

is used to

PEAK,

/16 to

OUTFS

× F(Code) (4)

× F(Code) (5)

Rev. A | Page 37 of 44

AD9739A

OUTPUT CURRENT (mA)

0 4096 8192 12,288

DAC CODE

Figure 95. Gain Curve for FSC[9:0] = 512, DAC OFFSET = 1.228 mA

Peak DAC Output Power Capability

The maximum peak power capability of a differential current output DAC is dependent on its peak differential ac current, I

, and the equivalent load resistance it sees. Because the

PEAK

AD9739A includes a differential 70  resistance, it is best to use a doubly terminated external output network similar to what is shown in Figure 97. In this case, the equivalent load seen by the DAC’s ac current source is 25 .

= 8.6 – 31.2mA

OUTFS

16,384

09616-098

If the AD9739A is programmed for I

= 20 mA, its peak ac

OUTFS

current is 9.375 mA and its peak power delivered to the equivalent load is 2.2 mW (that is, P = I

R). Because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally; therefore, the output load receives 1.1 mW or

0.4 dBm.

To calculate the rms power delivered to the load, the following must be considered:

• Peak-to-rms of the digital waveform

• Any digital backoff from digital full scale

• The DAC’s sinc response and nonideal losses in external

network

For example, a reconstructed sine wave with no digital backoff ideally measures −2.6 dBm because it has a peak-to-rms ratio of 3 dB. If a typical balun loss of 0.4 dBm is included, −3 dBm of actual power can be expected in the region where the DAC’s sinc response has negligible influence. Increasing the output power is best accomplished by increasing I

, although any

OUTFS

degradation in linearity performance must be considered acceptable for the target application.

SOURCE

= 50Ω

15/32 × I

PEAK

OUTFS

70Ω

180Ω

LOSSLESS

BALUN

1:1

Figure 96. Equivalent Circuit for Determining Maximum Peak Power

to a 50 Ω Load

LOAD

= 50Ω

09616-099

Rev. A | Page 38 of 44

AD9739A

Output Stage Configuration

The AD9739A is intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, DOCSIS CMTS) and/or high IF/RF signal generation. Optimum ac performance can only be realized if the DAC output is configured for differential (that is, balanced) operation with its output common-mode voltage biased to analog ground. The output network used to interface to the DAC should provide a near 0  dc bias path to analog ground. Any imbalance in the output impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. Component selection and layout are critical in realizing the AD9739A’s performance potential.

MINI-CIRCUITS

IOUTP

90Ω

70Ω

IOUTN

90Ω

TC1-33-75G+

Figure 97. Recommended Balun for Wideband Applications with Upper

Bandwidths of up to 2.2 GHz

09616-100

Most applications requiring balanced-to-unbalanced conversion can take advantage of the Ruthroff 1:1 balun configuration shown in Figure 97. This configuration provides excellent amplitude/phase balance over a wide frequency range while providing a 0  dc bias path to each DAC output. Also, its design provides exceptional bandwidth and can be considered for applications requiring signal reconstruction of up to 2.2 GHz. The characterization plots shown in this data sheet are based on the AD9739A evaluation board, which uses this configuration. Figure 98 compares the measured frequency response for normal and mix mode using the AD9739A evaluation board vs. the ideal frequency response.

–3

BASEBAND TC1-33-75G

–6

–9

–12

–15

–18

–21

POWER (dBc)

–24

–27

–30

–33

–36

0 500 1000 1500 2000 2500 3000 3500

Figure 98. Measured vs. Ideal Frequency Response for Normal (Baseband)

and Mix-Mode Operation Using a TC1-33-75G Transformer on

IDEAL BASEBAND MODE

IDEAL MIX MODE

FREQUENCY (MHz)

the AD9739A EVB

MIX MODE

TC1-33-75G

09616-101

Figure 99 shows an interface that can be considered when interfacing the DAC output to a self-biased differential gain

Rev. A | Page 39 of 44

block. The inductors shown serve as RF chokes (L) that provide the dc bias path to analog ground. The value of the inductor, along with the dc blocking capacitors (C), determines the lower cutoff frequency of the composite pass-band response. An RF balun should also be considered before the RF differential gain stage and any filtering to ensure symmetrical common-mode impedance seen by the DAC output while suppressing any common mode noise, harmonics, and clock spurs prior to amplification.

IOUTP

90Ω

70Ω

90Ω

IOUTN

Figure 99. Interfacing the DAC Output to the Self-Biased Differential

OPTIO NAL BALUN AND FIL TER

LPF

Gain Stage

RF DIFF

AMP

For applications operating the AD9739A in mix mode with output frequencies extending beyond 2.2 GHz, the circuits shown in Figure 100 should be considered. The circuit in Figure 100 uses a wideband balun with a configuration similar to the one shown in Figure 99 to provide a dc bias path for the DAC outputs. The circuit in Figure 101 takes advantage of ceramic chip baluns to provide a dc bias path for the DAC outputs while providing excellent amplitude/phase balance over a narrower RF band. These low cost, low insertion loss baluns are available for different popular RF bands and provide excellent amplitude/ phase balance over their specified frequency range.

MINI-CIRCUITS

IOUTP

IOUTN

70Ω

90Ω

TC1-1-462M

09616-103

Figure 100. Recommended Mix-Mode Configuration Offering Extended RF

Bandwidth Using a TC1-1-43A+ Balun

MURATA

JOHANSON TECHNO LOGY

IOUTP

IOUTN

70Ω

180Ω

CHIP BALUNS

09616-104

Figure 101. Lowest Cost and Size Configuration for Narrow RF Band

Operation

NONIDEAL SPECTRAL ARTIFACTS

The AD9739A output spectrum contains spectral artifacts that are not part of the original digital input waveform. These nonideal artifacts included harmonics (including alias harmonics), images, and clock spurs. Figure 102 shows a spectral plot of the AD9739A within the first Nyquist zone (that is, dc to f reconstructing a 650 MHz, 0 dBFS sine wave at 2.4 GSPS. Besides the desired fundamental tone at the −7.8 dBm level, the spectrum also reveals these nonideal artifacts that also appear as spurs

DAC

/2)

09616-102

AD9739A

above the measurement noise floor. Because these nonideal artifacts are also evident in the second and third Nyquist zones during mix-mode operation, the effects of these artifacts should also be considered when selecting the DAC clock rate for a target RF band.

–10

–20

–30

–40

–50

/4 –

DAC

–60

POWER (d Bc)

–100

OUT

–70

–80

–90

HD4

0 200 400 600 800 1000 1200

Note the following important observations pertaining to these nonideal spectral artifacts:

1. A full-scale sine wave (that is, single-tone) typically

represents the worst case condition because it is has a peak-to-rms ratio of 3 dB and is unmodulated. Harmonics and aliased harmonics of a sine wave are easy to identify because they also appear as discrete spurs. Significant characterization of a high speed DAC is performed using single (or multitone) signals for this reason.

2. Modulated signals (that is, AM, PM, or FM) do not appear

as spurs but rather as signals whose power spectral density is spread over a defined bandwidth determined by the modulation parameters of the signals. Any harmonics from the DAC spread over a wider bandwidth determined by the order of the harmonic and bandwidth of the modulated signal. For this reason, harmonics often appear as slight bumps in the measurement noise floor and can be difficult to discern.

3. Images appear as replicas of the original signal, hence, can

be easier to identify. In the case of the AD9739A, internal modulation of the sampling clock at intervals related to f

/4 generate image pairs at ¼ × f

DAC

. Both upper and lower sideband images associated

DAC

with ¼ × f

DAC

the lower image of ½ × f that the lower images appear frequency inverted. The ratio between the fundamental and various images (that is, dBc) remains mostly signal independent because the mechanism causing these images is related to corruption of the sampling clock.

FUND AT –7.6dBm

/2 –

DAC

OUT

HD3

FREQUENCY (MHz)

Figure 102. Spectral Plot

HD5

DAC

3/4 ×

HD6

, ½ × f

/4 –

DAC

OUT

HD2

HD9

, and ¾ ×

DAC

09616-105

fall within the first Nyquist zone, while only

and ¾ × f

DAC

fall back. Note

DAC

4. The magnitude of these images for a given device is

dependent on several factors including DAC clock rate, output frequency, and Mu controller phase setting. Because the image magnitude is repeatable between power-up cycles (assuming the same conditions), a one-time factory calibration procedure can be used to improve suppression. Calibration consists of additional dedicated DSP resources in the host that can generate a replica of the image with proper amplitude, phase, and frequency scaling to cancel the image from the DAC. Because the image magnitude can vary among devices, each device must be calibrated.

5. A clock spur appears at f

/4 and integer multiples of it.

DAC

Similar to images, the spur magnitude is also dependent on the same factors that cause variations in image levels. However, unlike images and harmonics, clock spurs always appear as discrete spurs, albeit their magnitude shows a slight dependency on the digital waveform and output frequency. The calibration method is similar to image calibration; however, only a digital tone of equal amplitude and opposite phase at f

6. A large clock spur also appears at 2 × f

/4 need be generated.

DAC

in either normal or mix-mode operation. This clock spur is due to the quad switch DAC architecture causing switching events to occur on both edges of f

DAC

LAB EVALUATION OF THE AD9739A

Figure 103 shows a recommended lab setup that was used to characterize the AD9739A’s performance. The DPG2 is a dual port LVDS/CMOS data pattern generator available from Analog Devices, Inc., with an up to 1.25 GSPS data rate. The DPG2 directly interfaces to the AD9739A evaluation board via Tyco Z-PACK HM-Zd connectors. A low phase noise/jitter RF source such as an R&S SMA 100A signal generator is used for the DAC clock. A +5 V power supply is used to power up the AD9739A evaluation board, and SMA cabling is used to interface to the supply, clock source, and spectrum analyzer. A USB 2.0 interface to a host PC is used to communicate to both the AD9739A evaluation board and the DPG2.

A high dynamic range spectrum analyzer is required to evaluate the AD9739A reconstructed waveform’s ac performance. This is especially the case when measuring ACLR performance for high dynamic range applications such as multicarrier DOCSIS CMTS applications. Harmonic, SFDR, and IMD measurements pertaining to unmodulated carriers can benefit by using a sufficiently high RF attenuation setting because these artifacts are easy to identify above the spectrum analyzer noise floor. However, reconstructed waveforms having modulated carrier(s) often benefit from the use of a high dynamic range RF amplifier and/or passive filters to measure close-in and wideband ACLR performance when using spectrum analyzers of limited dynamic range.

Rev. A | Page 40 of 44

AD9739A

provides more detail on the SPI register write/read operations required to implement the flow chart steps. Note the following:

• A software reset is optional because the AD9739A has both

an internal POR circuit and a RESET pin.

• The Mu controller must be first enabled (and in track

mode) before the data receiver controller is enabled because the DCO output signal is derived from this circuitry.

• A wait period is related to f

DATA

periods.

• Limit the number of attempts to lock the controllers to

three; locks typically occur on the first attempt.

• Hardware or software interrupts can be used to monitor

the status of the controllers.

RHODE AND

SCHWARTZ

SMA 100A

10 MHz REFIN

ADI PATTERN GENE RATOR

DCO

1.6GHz TO

2.5GHz 3dBm

AD9739

EVAL. BOARD

DPG2

LVDS

DATA

AND DCI

POWER

SUPPLY

10 MHz REOUT

USB 2.0

+5V

LAB

AGILENT PSA

E4440A

GPIB

09616-106

Figure 103. Lab Test Setup Used to Characterize the AD9739A

RECOMMENDED START-UP SEQUENCE

Upon power-up of the AD9739A, a host processor is required to initialize and configure the AD9739A via its SPI port. Figure 104 shows a flow chart of the sequential steps required, while Tab l e 1 2

CONFIG URE

SPI PORT

SOFTWARE

RESET

SET CLK

INPUT CMV

CONFIGUR E

MU CONT.

WAIT A

FEW 100µs

MU CONT. LOCKED?

YES

CONFIGU RE

RX DATA

CONT.

WAIT A

FEW 100µs

RX DATA

CONT.

LOCKED?

YES

RECONFIG URE

TXDAC FRO M

DEFAULT SETTING

OPTIONAL

09616-107

Figure 104. Flowchart for Initialization and Configuration of the AD9739A

Rev. A | Page 41 of 44

AD9739A

Table 12. Recommended SPI Initialization

Step Address (Hex) Write Value Comments

1 0x00 0x00

2 0x00 0x20 Software reset to default SPI values. 3 0x00 0x00 Clear the reset bit. 4 0x22 0x0F 5 0x23 0x0F 6 0x24 0x30 7 0x25 0x80 8 0x27 0x44 9 0x28 0x6C 10 0x29 0xCB 11 0x26 0x02 12 0x26 0x03 Enable the Mu controller search and track mode. 13 Wait for 160 K × 1/f 14 0x2A

15 Ensure that the AD9739A is fed with DCI clock input from the data source. 16 0x13 0x72 Set FINE_DEL_SKEW to 2. 17 0x10 0x00 Disable the data Rx controller before enabling it. 18 0x10 0x02 Enable the data Rx controller for loop and IRQ. 19 0x10 0x03 Enable the data Rx controller for search and track mode. 20 Wait for 135 K × 1/f 21 0x21

0x06 0x07

0x00 0x02

23 0x08 0x00 Optional: modify the TxDAC operation mode (the default is normal mode).

Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up.

Set the common-mode voltage of DACCLK_P and DACCLK_N inputs

Configure the Mu controller.

cycles.

DATA

Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a Mu lock failure.

cycles.

DATA

Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, proceed to Step 16 and repeat. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure.

Optional: modify the TxDAC I

setting (the default is 20 mA).

OUTFS

Rev. A | Page 42 of 44

AD9739A

OUTLINE DIMENSIONS

12.10

A1 BALL CORNER

12.00 SQ

11.90

TOP VIEW

10.40

BSC SQ

0.80

BSC

141312

BOTTOM VIEW

10 876

3219

A B C

D E F G H

J K L M N P

A1 BALL CORNER

1.00 MAX

0.85 MIN

COPLANARITY

0.20

04-15-2011-A

1.40 MAX

DETAIL A

COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1.

0.43 MAX

0.25 MIN

SEATING

PLANE

DETAIL A

0.55

0.50

0.45

BALL DIAMETER

Figure 105. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-160-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9739ABBCZ −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739ABBCZRL −40°C to +85°C 160- Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739A-EBZ Evaluation Board

Z = RoHs Compliant Part.

Rev. A | Page 43 of 44

AD9739A

NOTES

Rev. A | Page 44 of 44

Datasheet AD9739A Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

LVDS DIGITAL SPECIFICATIONS

SERIAL PORT SPECIFICATIONS

AC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

AC (NORMAL MODE)

AC (MIX MODE)

ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

TERMINOLOGY

SERIAL PORT INTERFACE (SPI) REGISTER

SPI REGISTER MAP DESCRIPTION

Reset

SPI OPERATION

Instruction Header Information

SPI REGISTER MAP

THEORY OF OPERATION

LVDS DATA PORT INTERFACE

Data Receiver Controller Initialization Description

LVDS Driver and Receiver Input

MU CONTROLLER

Mu Controller Initialization Description

INTERRUPT REQUESTS

ANALOG INTERFACE CONSIDERATIONS

ANALOG MODES OF OPERATION

CLOCK INPUT CONSIDERATIONS

VOLTAGE REFERENCE

ANALOG OUTPUTS

Equivalent DAC Output and Transfer Function

Peak DAC Output Power Capability

Output Stage Configuration

NONIDEAL SPECTRAL ARTIFACTS

LAB EVALUATION OF THE AD9739A

RECOMMENDED START-UP SEQUENCE

OUTLINE DIMENSIONS

ORDERING GUIDE