Datasheet AD9732 Datasheet (Analog Devices)

10-Bit, 200 MSPS

CONTROL
AMP

INTERNAL
VOLTAGE

REFERENCE

SWITCH NETWORK

DECODERS AND DRIVERS

REGISTER

AD9732

D1
D2
D3
D4
D5
D6
D7
D8
D9

D10

CLOCK

R

SET

DIGITAL

+V

S

CONTROL

AMP IN

REF

OUT

CONTROL

AMP OUT

REF

IN

I

OUT

I

OUT

ANALOG
RETURN

TTL
DRIVE
LOGIC

a

FEATURES
200 MSPS Throughput Rate

3.3 V PECL Digital Input
65 dB SFDR @ 2 MHz A

A

, 200 MSPS

OUT

Low Power: 305 mW
Fast Settling: 5 ns to 1/2 LSB
Low Glitch Energy: 6 pVs
Internal Reference
28-Lead SSOP Packaging

APPLICATIONS
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging

GENERAL DESCRIPTION

The AD9732 is a 10-bit, 200 MSPS, bipolar D/A converter that

is optimized to provide high dynamic performance, yet offers

lower power dissipation and a more economical price than pre-

vious high speed DAC solutions. The AD9732 was primarily

designed for demanding communications systems applications

where maximum spurious-free dynamic range (SFDR) is required

at high throughput rates. The proliferation of digital communi-

cations into base station and high volume subscriber-end mar-

kets has created a demand for high performance bipolar DACs

delivered at CMOS associated levels of power dissipation and

cost. The AD9732 is the answer to that demand.

Optimized for direct digital synthesis (DDS) and digital modu-

lator waveform reconstruction, the AD9732 provides >50 dB of

wideband harmonic suppression over the dc to 80 MHz analog

output bandwidth. This signal bandwidth addresses the transmit

, 200 MSPS/54 dB @ 40 MHz

OUT

D/A Converter

AD9732

FUNCTIONAL BLOCK DIAGRAM

spectrum in many of the emerging digital communications ap-

plications where signal purity is critical. Narrowband (±1 MHz

window), the AD9732 provides an SFDR of greater than 75 dB.
This level of wideband and narrowband ac performance, coupled
with its 200 MSPS throughput rate, enables the AD9732 to
present outstanding value in the high speed DAC function.

The AD9732 is packaged in a 28-lead SSOP and is specified to

operate over the extended industrial temperature range of –40°C
to +85°C. Digital inputs and clock are positive-ECL compatible.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD9732–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(+VS = +5 V, ENCODE = 125 MSPS, R

= 1.95 k⍀ (for 20 mA I

SET

) unless otherwise noted)

OUT

Test AD9732BRS

Parameter Temp Level Min Typ Max Units

THROUGHPUT RATE +25°C IV 165 200 MHz

RESOLUTION 10 Bits

DC ACCURACY

Differential Nonlinearity +25°C I 0.25 1 LSB

Full VI 0.36 1 LSB

Integral Nonlinearity +25°C I 0.6 1.5 LSB

Full VI 0.7 1.5 LSB

INITIAL OFFSET ERROR

Zero-Scale Offset Error +25°C I 35 70 µA

Full VI 40 100 µA
+25°C I 2.5 5 % FS

Full-Scale Gain Error

1

Full VI 2.5 5 % FS

Offset Drift Coefficient V 0.04 µA/°C

REFERENCE/CONTROL AMP

Internal Reference Voltage

Internal Reference Voltage Drift Full IV 150 µV/°C

Internal Reference Output Current

2

3

+25°C I 3.65 3.75 3.85 V

Full VI –50 +500 µA
Amplifier Input Impedance +25°CI 50 kΩ
Amplifier Bandwidth +25°C I 2.5 MHz

4, 6

4

5

+25°C V 75 MHz

Full V 20 mA

REFERENCE INPUT

Reference Input Impedance +25°C V 4.6 kΩ

Reference Multiplying Bandwidth

OUTPUT PERFORMANCE

Output Current
Output Compliance Full IV 2 5.75 V

Output Resistance +25°C V 240 Ω
Output Capacitance +25°CV 5 pF

Voltage Settling Time to 1/2 LSB (t
Propagation Delay (t
Glitch Impulse

9

Output Slew Rate
Output Rise Time
Output Fall Time

8

)

PD

10

10

10

ST

7

)

+25°C V 4.75 ns

+25°C V 2.7 ns

Full V 5.9 pVs

Full V 450 V/µs

Full V 1 ns

Full V 1 ns

DIGITAL INPUTS

Logic “1” Voltage Full VI 2.4 V
Logic “0” Voltage Full VI 1.6 V

Logic “1” Current +25°C I 1.7 10 µA
Logic “0” Current +25°C I –1 0.01 1 µA

Input Capacitance Full V 2 pF
Minimum Data Setup Time (t

Minimum Data Hold Time (t

11

)

S

12

)

H

+25°C IV 0.7 1.5 ns

Full IV 1 1.5 ns

+25°C IV 0.7 1.5 ns

Full IV 1 1.5 ns
Clock Pulsewidth Low (pw
Clock Pulsewidth High (pw

POWER SUPPLY

13

) +25°CIV 2 ns

MIN

) +25°CIV 2 ns

MAX

Digital +V Supply Current +25°C I 15 25 35 mA

Full VI 10 40 mA

Analog +V Supply Current +25°C I 10 20 30 mA

Full VI 10 30 mA

+25°C V 305 mW

Power Dissipation

14

Full V 350 mW

Power Supply Rejection Ratio (PSRR) +25°C V 200 µA/V

–2– REV. A

AD9732

Test AD9732BRS

Parameter Temp Level Min Typ Max Units

SFDR PERFORMANCE (Wideband)

2 MHz A
10 MHz A
20 MHz A
40 MHz A
2 MHz A
10 MHz A
20 MHz A
40 MHz A
65 MHz A
65 MHz A
80 MHz A

OUT

OUT

OUT

OUT

(Clock = 165 MHz) +25°CV 63 dB

OUT

(Clock = 165 MHz) +25°CV 62 dB

OUT

(Clock = 165 MHz) +25°CV 56 dB

OUT

(Clock = 165 MHz) +25°CV 51 dB

OUT

(Clock = 165 MHz) +25°CV 48 dB

OUT

(Clock = 200 MHz) +25°CV 45 dB

OUT

(Clock = 200 MHz) +25°CV 43 dB

OUT

SFDR PERFORMANCE (Narrowband)

2 MHz; 2 MHz Span +25°CV 77 dB
25 MHz; 2 MHz Span +25°CV 65 dB
10 MHz; 5 MHz Span (Clock = 200 MHz) +25°CV 70 dB

INTERMODULATION DISTORTION

F1 = 800 kHz, F2 = 900 kHz to Nyquist +25°CV 69 dB

F1 = 800 kHz, F2 = 900 kHz, Narrowband

(2 MHz) +25°CV 61 dB

NOTES

1

Measured as an error in ratio of full-scale current to current through R

2

Internal reference voltage is tested under load conditions specified in Internal Reference Output Current specification.

3

Internal reference output current defines load conditions applied during Internal Reference Voltage test.

4

Full-scale current variations among devices are higher when driving REFERENCE IN directly.

5

Frequency at which a 3 dB change in output of DAC is observed; R

6

Based on IFS = 32 ([CONTROL AMP IN – (+VS)]/R

7

Measured as voltage settling at midscale transition to 0.1%; R

8

Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.

9

Peak glitch impulse is measured as the largest area under a single positive or negative transient.

10

Measured with R

11

Data must remain stable for a specified time prior to rising edge of CLOCK.

12

Data must remain stable for a specified time after rising edge of CLOCK.

13

Supply voltages should remain stable with ±5% for nominal operation.

14

Power dissipation calculation includes current through a 50 Ω load.

15

SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
The frequency span dc to Nyquist unless otherwise noted.

16

Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at sum and difference frequencies of the two tones.

Specifications subject to change without notice.

= 50 Ω and DAC operating in latched mode.

L

15

+25°CV 66 dB
+25°CV 63 dB
+25°CV 57 dB
+25°CV 52 dB

15

16

(640 µA nominal); ratio is nominally 32. DAC load is virtual ground.

SET

= 50 Ω; 100 mV modulation at midscale.

= 50 Ω.

L

L

) when using internal control amplifier. DAC load is virtual ground.

SET

EXPLANATION OF TEST LEVELS
Test Level

I 100% production tested.

II 100% production tested at +25°C and sample tested at

specified temperatures.

III Sample tested only.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9732BRS –40°C to +85°C 28-Lead Small Outline (SSOP) RS-28
AD9732/PCB +25°C Evaluation Board

IV Parameter is guaranteed by design and characterization

testing.

V Parameter is a typical value only.

VI 100% production tested at +25°C; guaranteed by design

and characterization testing for industrial temperature
range.

–3–REV. A

AD9732

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V

S

+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V

S

Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

Control Amplifier Input Voltage Range . . . . . . . . . 0 V to +V

Reference Input Voltage Range . . . . . . . . . . . . . . . 0 V to +V

S

S

Internal Reference Output Current . . . . . . . . . . . . . . . 500 µA

Control Amplifier Output Current . . . . . . . . . . . . . . ±2.5 mA

Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C

Lead Temperature (10 sec) Soldering . . . . . . . . . . . . +300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

PIN CONFIGURATION

D8
D7
D6
D5
D4
D3
D2
D1

CLOCK

NC
NC

S

1
2
3
4
5
6

AD9732

7

TOP VIEW

(Not to Scale)

8

9
10
11
12
13
14

NC = NO CONNECT

D9 (MSB)

D0 (LSB)

DIGITAL +V

DIGITAL +V

28
27

GND

26

CONTROL AMP IN

25

REF OUT

24

CONTROL AMP OUT

23

REF IN

22

GND

21

I

OUTB

I

20

OUT

19

ANALOG RETURN

18

ANALOG +V

17

R

SET

16

GND

15

DIGITAL +V

S

S

S

PIN FUNCTION DESCRIPTIONS

Pin Number Name Function

1 D9 (MSB) Most significant data bit of digital input word.
2–9 D8–D1 Eight bits of 10-bit digital input word.
10 D0 (LSB) Least significant data bit of digital input word.
11 CLOCK TTL-compatible edge-triggered latch enable signal for on-board registers.
12, 13 NC No internal connection to this pin. Recommend tie to ground.
14, 15, 28 DIGITAL +V

S

+5 V supply voltage for digital circuitry.
16, 22, 27 GND Converter Ground.
18 ANALOG +V
17 R

SET

S

+5 V supply voltage for analog circuitry.

Connection for external reference set resistor; nominal 1.96 kΩ. Full-scale output

current = 32 [Control Amp + V

] (Reset).

S

19 ANALOG RETURN Analog Return. This point and the reference side of the DAC load resistors should be

20 I

OUT

connected to the same potential (Analog +V

Analog current output; full-scale current occurs with a digital word input of all “1s”

with external load resistor, output voltage = I

).

S

OUT

(R

LOAD储RINTERNAL

). R

INTERNAL

is

nominally 240 Ω.

21 I

OUTB

Complementary analog current output; full-scale current occurs with a digital word

input of all “0s.”
23 REF IN Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current

source network. Voltage changes (noise) at this point have a direct effect on the full-

scale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/

R

) when using internal amplifier. DAC load is virtual ground.

SET

24 CONTROL AMP OUT Normally connected to REF IN (Pin 23). Output of internal control amplifier, which

provides a reference for the current switch network.
25 REF OUT Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference,

nominally 3.75 V.
26 CONTROL AMP IN Normally connected to REF OUT (Pin 25) if not connected to external reference.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9732 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. A

AD9732

H

W

GLITCH AREA = 1/2 HEIGHT 3 WIDTH

ANALOG OUTPUT

CLOCK

ANALOG OUTPUT

CLOCK

DATA

DETAIL OF SETTLING TIME

CODE 1

DATA

t

PD

t

S

CODE 1

pw

MIN

SPECIFIED

ERROR BAND

t

CODE 2

DATA

CODE 2

pw

MAX

H

CODE 3

DATA

CODE 3

CODE 4

DATA

CODE 4

a.

b.

t

ST

c.

Figure 1. Timing Diagrams

–5–REV. A

AD9732

I

OUT

– mA

55

50

40

20 218

SFDR – dB

16 14 12 10 8 6 4

45

75

70

65

60

55

SFDR – dB

50

45

40

35

30

0 10010 20 30 40 50 60 70 80 90

Figure 2. Narrowband SFDR (Clock = 200 MHz) vs. A
Frequency

A

– MHz

OUT

OUT

Figure 5. SFDR vs. I

OUT

90

80

70

60

SFDR – dB

50

40

30

56010

15 20 25 30 35 40 45 50 55

A

– MHz

OUT

Figure 3. Narrowband SFDR (Clock = 125 MHz) vs. A
Frequency

65

60

55

50

45

SFDR – dB

40

35

30

10 9020

Figure 4. Wideband SFDR (200 MHz Clock) vs. A

30 40 50 60 70 80

A

– MHz

OUT

OUT

OUT

56

54

52

50

48

SFDR – dB

46

44

42

40

5 145

25 45 65 85 105 125

CLOCK – MHz

Figure 6. SFDR vs. Clock for f

0.4

0.3

0.2

0.1

0

LSB

–0.1

–0.2

–0.3

–0.4

CLK/AOUT

165 185 205

= 3.125

Figure 7. Typical Differential Nonlinearity Performance
(DNL)

–6– REV. A

AD9732

0

–60

–100

START 0Hz STOP 62.5MHz6.25MHz/

–10

–50

–70

–90

–30

–40

–80

–20

ENCODE = 125MHz
A

OUT

= 40MHz

SPAN = 62.5MHz
SFDR = 52dB

1

1

0.6

0.4

0.2

0

LSB

–0.2

–0.4

–0.6

Figure 8. Typical Integral Nonlinearity Performance (INL)

0

1

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1

START 0Hz STOP 62.5MHz6.25MHz/

ENCODE = 125MHz
A

= 2MHz

OUT

SPAN = 62.5MHz
SFDR = 66dB

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz STOP 62.5MHz6.25MHz/

1

1

Figure 11. Wideband SFDR 20 MHz A

ENCODE = 125MHz
A

= 20MHz

OUT

SPAN = 62.5MHz
SFDR = 57dB

; 125 MHz Clock

OUT

Figure 9. Wideband SFDR 2 MHz A

Figure 10. Wideband SFDR 10 MHz A

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1

1

START 0Hz STOP 62.5MHz6.25MHz/

; 125 MHz Clock

OUT

ENCODE = 125MHz
A

= 10MHz

OUT

SPAN = 62.5MHz
SFDR = 63dB

; 125 MHz Clock

OUT

Figure 12. Wideband SFDR 40 MHz A

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz STOP 100MHz10MHz/

Figure 13. Wideband SFDR 40 MHz A

–7–REV. A

; 125 MHz Clock

OUT

1

ENCODE = 200MHz
A

= 40MHz

OUT

SPAN = 100MHz
SFDR = 54dB

1

; 200 MHz Clock

OUT

AD9732

1

START 0Hz STOP 2MHz200MHz/

0

–60

–100

–10

–50

–70

–90

–30

–40

–80

–20

ENCODE = 125MHz
A

OUT

1 = 800kHz

A

OUT

2 = 900kHz

SPAN = 2MHz
IMD = 61dB

1

0

ENCODE = 200MHz
A

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

= 65MHz

OUT

SPAN = 200MHz
SFDR = 45dB

START 0Hz STOP 100MHz10MHz/

Figure 14. Wideband SFDR 65 MHz A

0

ENCODE = 200MHz
A

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

= 80MHz

OUT

SPAN = 100MHz
SFDR = 43dB

1

START 0Hz STOP 100MHz10MHz/

Figure 15. Wideband SFDR 80 MHz A

1

1

; 200 MHz Clock

OUT

1

; 200 MHz Clock

OUT

Figure 16. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 2 MHz

1

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz STOP 62.5MHz6.25MHz/

1

ENCODE = 125MHz
A

1 = 800kHz

OUT

2 = 900kHz

A

OUT

SPAN = 62.5MHz
IMD = 69dB

Figure 17. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 62.5 MHz

–8– REV. A

AD9732

AD9732

R

SET

CONTROL
AMP IN

CONTROL
AMP OUT

REFERENCE IN

R

SET

R

T

3.8V TO 4.4V

2.5MHz TYPICAL

0.1mF

+V

S

APPLICATION NOTES

THEORY OF OPERATION

The AD9732 high speed digital-to-analog converter utilizes most
significant bit decoding and segmentation techniques to reduce
glitch impulse and deliver high dynamic performance on lower
power consumption than previous bipolar DAC technologies.

The design is based on four main subsections: the decode/driver
circuits, the edge-triggered data register, the switch network and
the control amplifier. An internal bandgap reference is included
to allow operation of the device with minimum external support
components.

Digital Inputs/Timing

The AD9732 has PECL high speed single-ended inputs for data
inputs and clock. The switching threshold is +2.0 V.

In the decode/driver section, the three MSBs are decoded to
seven “thermometer code” lines. An equalizing delay is included
for the seven least significant bits and the clock signals. This
delay minimizes data skew and data setup-and-hold times at the
register inputs.

The on-board register is rising-edge triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data setup-and-hold times as shown in the
timing diagram. Although the AD9732 is designed to provide
isolation of the digital inputs to the analog output, some cou­pling of digital transitions is inevitable. Digital feedthrough can
be minimized by forming a low-pass filter at the digital input by
using a resistor in series with the capacitance of each digital
input. This common high speed DAC application technique has
the effect of isolating digital input noise from the analog output.

References

The internal bandgap reference, control amplifier and reference
input are pinned out to provide maximum user flexibility in
configuring the reference circuitry for the AD9732. When using
the internal reference, REF OUT (Pin 25) should be connected
to CONTROL AMP IN (Pin 26). CONTROL AMP OUT (Pin

24) should be connected to REF IN (Pin 23). A 0.1 µF ceramic

capacitor connected from Pin 23 to GND improves settling time
by decoupling switching noise from the current sink baseline. A
reference current cell provides feedback to the control amplifier
by sinking current through R

(Pin 17).

SET

Full-scale current is determined by CONTROL AMP IN and
R

according to the following equation:

SET

I

(FS) = 32 ([CONTROL AMP IN – (+VS)]/R

OUT

SET

)

The internal reference is nominally –1.25 V (referenced to
Analog +V

), with a tolerance of ±8% and typical drift over

S

temperature of 150 ppm/°C. If greater accuracy or temperature

stability is required, an external reference can be used. The

AD589 reference features 10 ppm/°C drift over the 0°C to
+70°C temperature range.

Two modes of multiplying operation are possible with the
AD9732. Signals with bandwidths up to 2.5 MHz and input
swings from 3.8 V to 4.4 V can be applied to the CONTROL
AMP IN pin as shown in Figure 18. Because the control ampli-

fier is internally compensated, the 0.1 µF capacitor discussed

above can be reduced to maximize the multiplying bandwidth.

However, it should be noted that output settling time, for
changes in the digital word, will be degraded.

Figure 18. Lower Frequency Multiplying Circuit

The REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. The analog signal for this
mode of operation must have a signal swing in the range of

0.95 V to 1.9 V. This can be implemented by capacitively cou­pling into REFERENCE IN a signal with a dc bias of 1.9 V (I
= 22.5 mA) to 0.95 V (I

= 3 mA), as shown in Figure 19, or

OUT

OUT

by dividing REFERENCE IN with a low impedance op amp
whose signal swing is limited to the stated range.

APPROX

1.4V

+V

S

REFERENCE IN

AD9732

Figure 19. Wideband Multiplying Circuit

Analog Output

The switch network provides complementary current outputs
I

OUT

and I

. The design of the AD9732 is based on statisti-

OUTB

cal current source matching, which provides a 10-bit linearity
without trim. Current is steered to either I

OUT

or I

OUTB

in pro­portion to the digital input word. The sum of the two currents is
always equal to the full-scale output current. The current can be
converted to a voltage by resistive loading as shown in Figure

20. Both I

OUT

and I

should be equally loaded for best over-

OUTB

all performance. The voltage that is developed is the product of
the output current and the value of the load resistor.

EVALUATION BOARD

The performance characteristics of the AD9732 make it ideally
suited for direct digital synthesis (DDS) and other waveform
synthesis applications. The AD9732 evaluation board provides a
platform for analyzing performance under optimum layout con­ditions. The AD9732 also provides a reference for high speed
circuit board layout techniques.

–9–REV. A

AD9732

DAC_OUT

OUT TO 50V LOAD

OUTPUT DESCRIPTION

DIFFERENTIAL TRANSFORMER

COUPLED TERMINATION

SINGLE-ENDED RESISTIVE TERMINATED

SW2

27 TO 29

30 TO 28

29 TO 32

31 TO 30

J3

(DIFFERENTIAL)

4

6

T1

321

T1–1T

1

1

E8

E10

R1

R18

64.9V

1

1

E7

E5

R15

50V

R16

25V

25

26

REFOUT

+5V

24

C_AMP_IN

C_AMP_OUT

23

REF_IN

C8

10mF

+

C1

0.1mF

C7

0.1mF

+5V

C11

SW2

OUT TO 50V LOAD

C10

0.1mF

E28

E32

11

E27

E29

J2

0.1mF

1

1

DAC_OUT

(SINGLE ENDED)

1

E30

1

E31

21

20

IOUT

I_OUT

U1

AD9732

SET

+5V: 14, 15, 18, 19, 28

ANALOG GND 22

R12

64.9V

DIGITAL GND 16, 27

R7

1960V

CLK

C6

0.1mF

C5

0.1mF

C4

0.1mF

C3

0.1mF

C2

0.1mF

D9 (MSB)D8D7D6D5D4D3D2D1

123456789

1

1

1

1

1

E12

R2

64.9V

64.9V

1

E11

E14

E13

E16

R4

R3

64.9V

64.9V

1

1

E15

E18

E17

E20

R9

R8

64.9V

1

1

E19

D0 (LSB)

CLK

1011121317

1

E221E241E26

R10

64.9V

64.9V

1

E211E231E25

NC1

R11

NC2

64.9V

R

CONNECTIONS

CLOCK MATRIX DESCRIPTION

1 TO 3 ON BOARD XTAL OSCILLATOR

2 TO 4 BNC EXTERNAL PECL CLOCK (50V)

SW1

5 = GND PIN FOR EXTERNAL CLOCK

3 = INPUT PIN FOR EXTERNAL CLOCK

4 TO 6 ADD 50V TERMINATION FOR EXTERNAL CLOCK

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R5

BNC

50V

C9

10mF

NOTE:

SERIES 64.9V RESISTORS

CAN BE BYPASSED BY

JUMPING E7 TO E8, ECT.

+5V

1

234

TB1

24681012141618

H1

J1

13579

20

1113151719

+5V

R13

780V

R17

SW1

CLK

R6

1

E2

E1

11

E4

11

E3

1

E6

E5

50V

+5V

CR1

1N914

14

+V

Y1

SW41

CLKB

180V

8

OSC_OUT

R14

TB4

390V

CLKB

GND

P1

C37DRPF

NO_CONN

1

IN

CMOS CLOCK OSCILLATOR

7

Figure 20. Evaluation Board

–10– REV. A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead SSOP

(RS-28)

0.407 (10.34)

0.397 (10.08)

28 15

AD9732

C3365a–0–4/99

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

PIN 1

0.0256
(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.066 (1.67)

SEATING

PLANE

0.212 (5.38)

141

0.07 (1.79)

0.009 (0.229)

0.005 (0.127)

0.205 (5.21)

88
08

0.03 (0.762)

0.022 (0.558)

PRINTED IN U.S.A.

–11–REV. A