Datasheet AD9709 Datasheet (ANALOG DEVICES)

8-Bit, 125 MSPS, Dual TxDAC+

W

FEATURES

8-bit dual transmit digital-to-analog converter (DAC)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual port or interleaved data
On-chip 1.2 V reference
Single 5 V or 3.3 V supply operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP

APPLICATIONS

Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound

Digital-to-Analog Converter

AD9709

FUNCTIONAL BLOCK DIAGRAM

DCOM1/

PORT1

RT1/IQWRT

WRT2/IQSEL

PORT2

DVDD1/

DCOM2

DVDD2 AVDD ACOM

1

LATCH

DIGITAL

INTERFACE

AD9709

2

LATCH

Figure 1.

CLK1

1

DAC

REFERENCE

BIAS

GENERATOR

2

DAC

CLK2/IQ RESETMODE

I

OUTA1

I

OUTB1

REFIO
FSADJ1
FSADJ2
GAINCTRL

SLEEP

I

OUTA2

I

OUTB2

0606-001

GENERAL DESCRIPTION

The AD97091 is a dual-port, high speed, 2-channel, 8-bit CMOS
DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage
reference, and digital interface circuitry into a small 48-lead LQFP
package. The AD9709 offers exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.

The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of two
double-buffered latches as well as control logic. Separate write
inputs allow data to be written to the two DAC ports independent
of one another. Separate clocks control the update rate of the DACs.

A mode control pin allows the AD9709 to interface to two separate
data ports, or to a single interleaved high speed data port. In inter­leaving mode, the input data stream is demuxed into its original
I and Q data and then latched. The I and Q data is then converted
by the two DACs and updated at half the input data rate.

The GAINCTRL pin allows two modes for setting the full-scale
current (I
independently using two external resistors, or I
DACs can be set by using a single external resistor. See the Gain
Control Mode section for important date code information on
this feature.

The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce

1

Patent pending.

) of the two DACs. I

OUTFS

for each DAC can be set

OUTFS

for both

OUTFS

glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output, thus supporting single­ended or differential applications. Both DACs can be
simultaneously updated and provide a nominal full-scale
current of 20 mA. The full-scale currents between each DAC
are matched to within 0.1%.

The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.3 V or 5 V and
consumes 380 mW of power.

PRODUCT HIGHLIGHTS

1. The AD9709 is a member of a pin-compatible family of

dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.

2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance

DACs optimized for low distortion performance provide
for flexible transmission of I and Q information.

3. Matching. Gain matching is typically 0.1% of full scale, and

offset error is better than 0.02%.

4. Low Power. Complete CMOS dual DAC function operates

at 380 mW from a 3.3 V or 5 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.

5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V

temperature-compensated band gap voltage reference.

6. Dual 8-Bit Inputs. The AD9709 features a flexible dual-

port interface, allowing dual or interleaved input data.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2000–2009 Analog Devices, Inc. All rights reserved.

AD9709

TABLE OF CONTENTS

Features .............................................................................................. 1

Applicat ions ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

Dynamic Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Functional Description .............................................................. 12

Reference Operation .................................................................. 13

Gain Control Mode .................................................................... 13

Setting the Full-Scale Current ................................................... 13

DAC Transfer Function ............................................................. 14

Analog Outputs .......................................................................... 14

Digital Inputs .............................................................................. 15

DAC Timing ................................................................................ 15

Sleep Mode Operation ............................................................... 18

Power Dissipation....................................................................... 18

Applying the AD9709 .................................................................... 19

Output Configurations .............................................................. 19

Differential Coupling Using a Transformer ............................ 19

Differential Coupling Using an Op Amp ................................ 19

Single-Ended, Unbuffered Voltage Output ............................. 20

Single-Ended, Buffered Voltage Output Configuration ........ 20

Power and Grounding Considerations .................................... 20

Applications Information .............................................................. 22

Quadrature Amplitude Modulation (QAM) Using the

AD9709 ........................................................................................ 22

CDMA ......................................................................................... 23

Evaluation Board ............................................................................ 24

General Description ................................................................... 24

Schematics ................................................................................... 24

Evaluation Board Layout ........................................................... 30

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32



REVISION HISTORY

9/09—Rev. A to Rev. B

Changes to Power and Grounding Considerations Section ..... 20

Changes to Schematics Section ..................................................... 24

Changes to Evaluation Board Layout Section ............................. 30

1/08—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Changed Single Supply Operation to 5 V or 3.3 V ........ Universal

Changes to Figure 1 .......................................................................... 1

Added Timing Diagram Section .................................................... 5

Changes to Figure 3 and Table 6 ..................................................... 7

Change to Figure 12 ......................................................................... 9

Changes to Figure 18 to Figure 20 ................................................ 10

Changes to Functional Description Section ............................... 13

Changes to Reference Operation Section .................................... 13

Changes to Figure 23 and Figure 24 ............................................. 13

Changes to Gain Control Mode Section ...................................... 13

Rev. B | Page 2 of 32

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section ...................................................... 13

Changes to DAC Transfer Function Section............................... 14

Changes to Interleaved Mode Timing Section ........................... 16

Added Figure 28 ............................................................................. 16

Changes to Power and Grounding Considerations Section ..... 20

Changes to Figure 44 ...................................................................... 22

Deleted Figure 43 ............................................................................ 17

Changes to CDMA Section ........................................................... 23

Changes to Figure 45 Caption ...................................................... 23

Changes to Figure 46 ...................................................................... 24

Changes to Figure 48 ...................................................................... 26

Updated Outline Dimensions ....................................................... 30

Changes to Ordering Guide .......................................................... 30

5/00—Revision 0: Initial Version

AD9709

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 8 Bits
DC ACCURACY1

Integral Linearity Error (INL) −0.5 ±0.1 +0.5 LSB
Differential Nonlinearity (DNL) −0.5 ±0.1 +0.5 LSB

ANALOG OUTPUT

Offset Error −0.02 +0.02 % of FSR
Gain Error Without Internal Reference −2 ±0.25 +2 % of FSR
Gain Error with Internal Reference −5 +1 +5 % of FSR
Gain Match

Full-Scale Output Current2 2.0 20.0 mA
Output Compliance Range −1.0 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 MΩ
Small-Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C
Gain Drift Without Internal Reference ±50 ppm of FSR/°C
Gain Drift with Internal Reference ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages
AVDD 3 5 5.5 V
DVDD1, DVDD2 2.7 5 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation4 (5 V, I
Power Dissipation5 (5 V, I
Power Dissipation6 (5 V, I
Power Supply Rejection Ratio7—AVDD −0.4 +0.4 % of FSR/V
Power Supply Rejection Ratio7—DVDD1, DVDD2 −0.025 +0.025 % of FSR/V

OPERATING RANGE −40 +85 °C

1

Measured at I

2

Nominal full-scale current, I

3

An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4

Measured at f

5

Measured at f

6

Measured as unbuffered voltage output with I

7

±10% power supply variation.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

= 20 mA, unless otherwise noted.

OUTFS

TA = 25°C −0.3 ±0.1 +0.3 % of FSR
T

to T

MIN

T

MIN

−1.6 +1.6 % of FSR

MAX

to T

−0.14 +0.14 dB

MAX

) 71 75 mA

AVDD

)4 5 7 mA

DVDD

)5 15 mA

DVDD

) 8 12 mA

AVDD

= 20 mA) 380 410 mW

OUTFS

= 20 mA) 420 450 mW

OUTFS

= 20 mA) 450 mW

OUTFS

, driving a virtual ground.

OUTA

= 25 MSPS and f

CLK

= 100 MSPS and f

CLK

, is 32 times the I

OUTFS

= 1.0 MHz.

OUT

= 1 MHz.

OUT

current.

REF

= 20 mA and R

OUTFS

= 50 Ω at I

LOAD

Rev. B | Page 3 of 32

OUTA

and I

, f

= 100 MSPS, and f

OUTB

CLK

= 40 MHz.

OUT

AD9709

DYNAMIC SPECIFICATIONS

T

to T

MIN

doubly terminated, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (tST) to 0.1%1 35 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)1 2.5 ns
Output Fall Time (90% to 10%)1 2.5 ns
Output Noise (I
Output Noise (I

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

Signal to Noise and Distortion Ratio

Total Harmonic Distortion

Multitone Power Ratio (Eight Tones at 110 kHz Spacing)

Channel Isolation

1

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

) 125 MSPS

CLK

= 20 mA) 50 pA/√Hz

OUTFS

= 2 mA) 30 pA/√Hz

OUTFS

f

= 100 MSPS, f

CLK

= 1.00 MHz

OUT

= 20 mA, differential transformer-coupled output, 50 Ω

OUTFS

0 dBFS Output 63 68 dBc
–6 dBFS Output 62 dBc
–12 dBFS Output 56 dBc
–18 dBFS Output 50 dBc

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 50 MHz, f

CLK

f

= 100 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 65 MSPS, f

CLK

= 1.00 MHz 68 dBc

OUT

= 2.51 MHz 68 dBc

OUT

= 5.02 MHz 66 dBc

OUT

= 14.02 MHz 60 dBc

OUT

= 25 MHz 50 dBc

OUT

= 25 MHz 63 dBc

OUT

= 40 MHz 55 dBc

OUT

= 1 MHz 50 dB

OUT

= 1.00 MHz −67 −63 dBc

OUT

= 2.00 MHz −63 dBc

OUT

= 4.00 MHz −63 dBc

OUT

= 10.00 MHz −63 dBc

OUT

= 2.00 MHz to 2.99 MHz

OUT

0 dBFS Output 58 dBc
–6 dBFS Output 51 dBc
–12 dBFS Output 46 dBc
–18 dBFS Output 41 dBc

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

= 10 MHz 85 dBc

OUT

= 40 MHz 77 dBc

OUT

Rev. B | Page 4 of 32

AD9709

DIGITAL SPECIFICATIONS

T

to T

MIN

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V 3.5 5 V
Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V 2.1 3 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V 0 1.3 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V 0 0.9 V
Logic 1 Current −10 +10 μA
Logic 0 Current −10 +10 μA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (t

Timing Diagram

See Tab le 3 and the DAC Timing section for more information about the timing specifications.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V I

MAX

, t

) 3.5 ns

LPW

CPW

DATA IN

= 20 mA, unless otherwise noted.

OUTFS

t

S

t

H

(WRT2) (WRT1/IQWRT)

(CLK2) (CLK1/IQCLK)

I

OUTA

OR

I

OUTB

t

LPW

t

CPW

t

PD

00606-002

Figure 2. Timing for Dual and Interleaved Modes

Rev. B | Page 5 of 32

AD9709

ABSOLUTE MAXIMUM RATINGS

Table 4.

With

Parameter

AVDD ACOM −0.3 V to +6.5 V
DVDD1, DVDD2 DCOM1/DCOM2 −0.3 V to +6.5 V
ACOM DCOM1/DCOM2 −0.3 V to +0.3 V
AVDD DVDD1/DVDD2 −6.5 V to +6.5 V
MODE, CLK1/IQCLK,

CLK2/IQRESET,
WRT1/IQWRT,
WRT2/IQSEL

Digital Inputs DCOM1/DCOM2

I

OUTA1/IOUTA2

I

REFIO, FSADJ1,

FSADJ2
GAINCTRL, SLEEP ACOM −0.3 V to AVDD + 0.3 V
Junction Temperature 150°C
Storage Temperature

Range
Lead Temperature

(10 sec)

,

OUTB1/IOUTB2

Respect To

DCOM1/DCOM2

ACOM −1.0 V to AVDD + 0.3 V

ACOM −0.3 V to AVDD + 0.3 V

−65°C to +150°C

300°C

Rating

−0.3 V to DVDD1/
DVDD2 + 0.3 V

−0.3 V to DVDD1/
DVDD2 + 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA Unit

48-Lead LQFP 91 °C/W

ESD CAUTION

Rev. B | Page 6 of 32

AD9709

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTA1

MODE47AVDD46I

48

OUTB1

I

FSADJ143REFIO42GAINCTRL41FSADJ240I

45

44

OUTB2

OUTA2

I

ACOM37SLEEP

39

38

36

NC

35

NC

34

NC

33

NC

32

NC

31

NC

30

DB0P2 (LSB)

29

DB1P2

28

DB2P2
DB3P2

27

DB4P2

26

DB5P2

25

23

24

DB6P2

DVDD2

DB7P2 (MSB)

0606-003

DB6P1
DB5P1
DB4P1
DB3P1
DB2P1
DB1P1
DB0P1

NC
NC
NC
NC

1
2
3
4
5
6
7
8

9
10
11
12

DB7P1 (MSB)

NC = NO CONNECT

PIN 1
INDICATOR

13NC14NC15

AD9709

TOP VIEW

(Not to Scale)

16

17

DVDD1

DCOM1

18

19

20

21

22

DCOM2

CLK1/IQCLK

WRT2/IQSEL

WRT1/IQWRT

CLK2/IQRESET

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 8 DB7P1 to DB0P1 Data Bit Pins (Port 1)
9 to 14, 31 to 36 NC No Connection
15, 21 DCOM1, DCOM2 Digital Common
16, 22 DVDD1, DVDD2 Digital Supply Voltage
17 WRT1/IQWRT Input Write Signal for Port 1 (IQWRT in Interleaving Mode)
18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode)
19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode)
20 WRT2/IQSEL Input Write Signal for Port 2 (IQSEL in Interleaving Mode)
23 to 30 DB7P2 to DB0P2 Data Bit Pins (Port 2)
37 SLEEP Power-Down Control Input
38 ACOM Analog Common
39, 40 I

OUTA2

, I

Port 2 Differential DAC Current Outputs

OUTB2

41 FSADJ2 Full-Scale Current Output Adjust for DAC2
42 GAINCTRL Master/Slave Resistor Control Mode.
43 REFIO Reference Input/Output
44 FSADJ1 Full-Scale Current Output Adjust for DAC1
45, 46 I

OUTB1

, I

Port 1 Differential DAC Current Outputs

OUTA1

47 AVDD Analog Supply Voltage
48 MODE Mode Select (1 = dual port, 0 = interleaved)

Rev. B | Page 7 of 32

AD9709

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.3 V or 5 V, DVDD = 3.3 V, I
unless otherwise noted.

75

70

65

60

SFDR (dBc)

55

50

f

CLK

= 5MSPS

f

CLK

f

= 65MSPS

CLK

= 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist,

OUTFS

75

f

= 25MSPS

CLK

= 125MSPS

SFDR (dBc)

70

0dBFS

65

60

55

50

–6dBFS

–12dBFS

45

0.1 1 10 100

Figure 4. SFDR vs. f

75

70

65

60

SFDR (dBc)

55

50

45

0 0.5 1.0 1.5 2.0 2.5

0dBFS

–6dBFS

–12dBFS

Figure 5. SFDR vs. f

75

70

65

0dBFS

f

OUT

f

OUT

(MHz)

OUT

(MHz)

OUT

@ 0 dBFS

@ 5 MSPS

45

0 5 10 15 20 25 30 35

00606-005

Figure 7. SFDR vs. f

75

70

0dBFS

65

–6dBFS

60

SFDR (dBc)

00606-006

–12dBFS

55

50

45

0 10203040506070

Figure 8. SFDR vs. f

75

70

65

f

f

OUT

OUT

(MHz)

@ 65 MSPS

OUT

(MHz)

@ 125 MSPS

OUT

I

OUTFS

00606-008

00606-009

= 20mA

60

SFDR (dBc)

55

50

45

024681012

–6dBFS

–12dBFS

f

OUT

Figure 6. SFDR vs. f

(MHz)

@ 25 MSPS

OUT

00606-007

Rev. B | Page 8 of 32

60

SFDR (dBc)

55

50

45

0 5 10 15 20 25 30 35

Figure 9. SFDR vs. f

I

OUTFS

OUT

= 10mA

I

OUTFS

f

OUT

and I

= 5mA

(MHz)

@ 65 MSPS and 0 dBFS

OUTFS

00606-010

AD9709

75

70

70

65

60

25MSPS/2.27MHz

55

SFDR (dBc)

50

45

40

–25 –22 –19 –16 –13 –10 –7 –4 –1 2

10MSPS/0.91MHz

Figure 10. Single-Tone SFDR vs. A

75

70

65

60

55

SFDR (dBc)

10MSPS/2.0MHz

50

45

40

–25 –20 –15 –10 –5 0

Figure 11. Single-Tone SFDR vs. A

5MSPS/0.46MHz

125MSPS/11.37MHz

A

(dBFS)

OUT

OUT

5MSPS/1.0MHz

65MSPS/13.0MHz

25MSPS/5.0MHz

A

(dBFS)

OUT

OUT

65MSPS/5.91MHz

@ f

= f

OUT

125MSPS/5.0MHz

@ f

= f

OUT

65

60

I

55

SINAD (dBc)

50

45

40

0 20 40 60 80 100 120 140

00606-011

/11

CLK

/5

CLK

00606-012

Figure 13. SINAD vs. f

0.06

0.04

0.02

0

–0.02

INL (LSBs)

–0.04

–0.06

–0.08

–0.10

0 32 64 96 160 224128 192 256

I

= 5mA

OUTFS

f

(MSPS)

CLK

and I

CLK

OUTFS

CODE

Figure 14. Typical INL

= 20mA

OUTFS

I

= 10mA

OUTFS

@ f

= 5 MHz and 0 dBFS

OUT

00606-014

00606-015

75

70

65

60

55

SFDR (dBc)

50

45

40

–25 –20 –15 –10 –5 0

Figure 12. Dual-Tone SFDR vs. A

0.965MHz/1.035MHz @ 7MSPS

16.9MHz/19.1MHz @ 125MSPS

8.8MHz/9. 8M Hz @ 65MSPS

3.3MHz/3. 4M Hz @ 25MSPS

A

(dBFS)

OUT

@ f

OUT

OUT

= f

0.07

0.06

0.05

0.04

0.03

DNL (LSBs)

0.02

0.01

0

–0.01

0 50 100 150 200 250

/7

CLK

00606-013

Figure 15. Typical DNL

CODE

00606-016

Rev. B | Page 9 of 32

AD9709

75

70

65

60

SFDR (dBc)

55

50

45

–50 –30 –10 10 30 50 70 90

Figure 16. SFDR vs. Temperature @ f

0.05

0.03

OFFSET ERROR

0

OFFSET ERROR (%F S)

–0.03

–0.05

–40 –20 0 20 40 60 80

f

= 10MHz

OUT

f

= 25MHz

OUT

f

= 40MHz

OUT

f

= 60MHz

OUT

TEMPERATURE (°C)

TEMPERATURE (°C)

CLK

Figure 17. Gain and Offset Error vs. Temperature @ f

= 125 MSPS, 0 dBFS

GAIN ERROR

= 125 MSPS

CLK

1.0

0.5

0

–0.5

–1.0

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

SFDR (dBm)

065040302010

Figure 19. Dual-Tone SFDR @ f

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

065040302010

Figure 20. Four-Tone SFDR @ f

FREQUENCY (MHz)

CLK

FREQUENCY (MHz )

CLK

= 125 MSPS

= 125 MSPS

00606-017

GAIN ERROR (%F S )

0606-018

0

0606-020

0

00606-021

SFDR (dBm)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

065040302010

Figure 18. Single-Tone SFDR @ f

FREQUENCY (MHz )

CLK

0

0606-019

= 125 MSPS

Rev. B | Page 10 of 32

AD9709

TERMINOLOGY

Linearity Error (Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full-scale.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output either increases or remains
constant as the digital input increases.

Offset Error

Offset error is the deviation of the output current from the ideal of
zero. For I
For I

OUTB

, 0 mA output is expected when the inputs are all 0s.

OUTA

, 0 mA output is expected when all inputs are set to 1s.

Gain Error

Gain error is the difference between the actual and ideal output
spans. The actual span is determined by the output when all
inputs are set to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits may cause either output stage
saturation or breakdown resulting in nonlinear performance.

Temp er at u re D ri ft

Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T

MIN

or T

. For offset

MAX

and gain drift, the drift is reported in part per million (ppm) of
full-scale range (FSR) per degree Celsius. For reference drift, the
drift is reported in ppm per degree Celsius (pm/°C).

Power Supply Rejection (PSR)

PSR is the maximum change in the full-scale output as the
supplies are varied from nominal to minimum and maximum
specified voltages.

Settling Time

Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolts per second (pV-s).

Spurious-Free Dynamic Range

The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).

Rev. B | Page 11 of 32

AD9709

V

V

THEORY OF OPERATION

5

AVDD

DIVIDER

MULTIPLEXING LOGIC

CHANNEL 1 LATCH

PORT 1 PORT 2

DIGITAL

DATA

TEKTRONIX

AWG2021

WITH OPTION 4

R

1

SET

2kΩ

0.1µF

R

DVDD1/DVDD2

DCOM1/DCOM2

FSADJ1

REFIO

FSADJ2

2

SET

2kΩ

1.2V REF

GAINCTRL

RETIMED CLOCK OUTPUT*

LECROY 9210

PULSE

GENERATOR

CURRENT

CURRENT

WRT1/

IQWRT

50Ω

PMOS

SOURCE

ARRAY

PMOS

SOURCE

ARRAY

Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2

5

AVDD

R

1

I

REF

SET

2kΩ

1

I

2

REF

0.1µF

R

SET

2kΩ

2

FSADJ1

REFIO

FSADJ2

1.2V REF

GAINCTRL

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

AD9709

WRT1/
IQWRT

CHANNEL 1 LATCH CHANNEL 2 LATCH

DIVIDER

MULTIPLEXING LOGIC

PORT 1 PORT 2 WRT2/

DIGITAL DATA INPUTS

FUNCTIONAL DESCRIPTION

Figure 22 shows a simplified block diagram of the AD9709. The
AD9709 consists of two DACs, each one with its own independent
digital control logic and full-scale output current control. Each
DAC contains a PMOS current source array capable of providing
up to 20 mA of full-scale current (I

The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources instead of an R-2R
ladder enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kΩ).

OUTFS

).

CLK1/IQCLK CLK2/IQRESET

CLK

SEGMENTED

DAC1

LATCH

LATCH

CLK1/IQCLK CLK2/IQRESET

CLK

DAC1

LATCH

DAC2

LATCH

SWITCHES FOR

DAC1

SEGMENTED

SWITCHES FOR

DAC2

CHANNEL 2 LATCH

DAC2

WRT2/
IQSEL

*AWG2021 CLOCK RE TIMED SUCH T HAT
DIGITAL DATA TRANSIT IONS ON F AL LING
EDGE OF 50% DUTY CYCLE CLOCK.

SEGMENTED

SWITCHES F O R

DAC1

SEGMENTED

SWITCHES FOR

DAC2

IQSEL

Figure 22. Simplified Block Diagram

All of these current sources are switched to one of the two
output nodes (that is, I
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching of complementary drive signals to the inputs of the
differential current switches.

The analog and digital sections of the AD9709 have separate

th

of an

power supply inputs (that is, AVDD and DVDD1/DVDD2) that
can operate independently over a 3.3 V to 5 V range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.

SLEEP

AD9709

LSB

SWITCH

LSB

SWITCH

DCOM1/

DCOM2

SLEEP

LSB

SWITCH

LSB

SWITCH

MODE

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

MODE

DVDD1/

DVDD2

ACOM

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

DVDD1/

DVDD2

ACOM

DCOM1/

DCOM2

OUTA

V

5V

or I

Mini-Circuits

T1-1T

50Ω

50Ω

5V

V

= V

DIFF

V

OUT

2B

OUT

R

2B

L

50Ω

) via the PMOS differential

OUTB

OUT

2A
R

50Ω

A – V

2A

L

TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER

B

OUT

V

1B

OUT

R

1B

L

50Ω

00606-004

V

1A

OUT

1A

R

L

50Ω

0606-022

Rev. B | Page 12 of 32

AD9709

×

=

The full-scale output current of each DAC is regulated by
separate reference control amplifiers and can be set from 2 mA
to 20 mA via an external network connected to the full-scale
adjust (FSADJ) pin. The external network in combination with
both the reference control amplifier and voltage reference
(V

) sets the reference current (I

REFIO

), which is replicated to

REF

the segmented current sources with the proper scaling factor.
The full-scale current (I

OUTFS

) is 32 × I

REF

.

REFERENCE OPERATION

The AD9709 contains an internal 1.20 V band gap reference.
This can easily be overridden by a low noise external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 µF capacitor. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an external buffer
amplifier with an input bias current of less than 100 nA should
be used. An example of the use of the internal reference is
shown in Figure 23.

OPTIONAL
EXTERNAL

REFERENCE

ADDITIONAL

EXTERNAL

LOAD

BUFFER

0.1µF

I

REF

R

SET

256Ω

22nF

1.2V
REF

REFIO

FSADJ1/
FSADJ2

AD9709

REFERENCE

SECTION

Figure 23. Internal Reference Configuration

An external reference can be applied to REFIO as shown in
Figure 24. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 µF
compensation capacitor is not required because the internal
reference is overridden and the relatively high input impedance
of REFIO minimizes any loading of the external reference.

AVDD

EXTERNAL

REFERENCE

I

REF

1.2V
REF

REFIO

FSADJ1/

256Ω

FSADJ2

R

SET

22nF

Figure 24. External Reference Configuration

AD9709

REFERENCE

SECTION

CURRENT

SOURCE

ARRAY

AVDDGAINCTRL

CURRENT

SOURCE

ARRAY

AVDDGAINCTRL

ACOM

ACOM

0606-024

00606-023

GAIN CONTROL MODE

The AD9709 allows the gain of each channel to be set
independently by connecting one R
another R
system cost, a single R

resistor to FSADJ2. To add flexibility and reduce

SET

resistor can be used to set the gain of

SET

resistor to FSADJ1 and

SET

both channels simultaneously.

When GAINCTRL is low (that is, connected to analog ground),
the independent channel gain control mode using two resistors
is enabled. In this mode, individual RSET resistors should be
connected to FSADJ1 and FSADJ2. When GAINCTRL is high
(that is, connected to AVDD), the master/slave channel gain
control mode using one network is enabled. In this mode, a
single network is connected to FSADJ1, and the FSADJ2 pin
must be left unconnected.

Note that only parts with a date code of 9930 or later have the
master/slave gain control function. For parts with a date code
before 9930, Pin 42 must be connected to AGND, and the part
operates in the two-resistor, independent gain control mode.

SETTING THE FULL-SCALE CURRENT

Both of the DACs in the AD9709 contain a control amplifier
that is used to regulate the full-scale output current (I
control amplifier is configured as a V-I converter, as shown in
Figure 23, so that its current output (I
of the V

The DAC full-scale current, I

and an external resistor, R

REFIO

V

REF

REFIO

R

SET

I =

OUTFS

larger than the reference current, I

II

32

OUTFS

REF

) is determined by the ratio

REF

.

SET

, is an output current 32 times

.

REF

The control amplifier allows a wide (10:1) adjustment span of
I

from 2 mA to 20 mA by setting I

OUTFS

625 A. The wide adjustment range of I

between 62.5 A and

REF

provides several

OUTFS

benefits. The first relates directly to the power dissipation of
the AD9709, which is proportional to I

(refer to the Power

OUTFS

Dissipation section). The second relates to the 20 dB adjustment,
which is useful for system gain control purposes.

It should be noted that when the R

resistors are 2 kΩ or less,

SET

the 22 nF capacitor and 256 Ω resistor shown in Figure 23 and
Figure 24 are not required and the reference current can be set
by the R

resistors alone. For R

SET

values greater than 2 kΩ, the

SET

22 nF capacitor and 256 Ω resistor networks are required to
ensure the stability of the reference control amplifier(s).
Regardless of the value of R

, however, if the R

SET

SET

located more than ~10 cm away from the pin, use of the 22 nF
capacitor and 256 Ω resistor is recommended.

). The

OUTFS

resistor is

Rev. B | Page 13 of 32

AD9709

DAC TRANSFER FUNCTION

Both DACs in the AD9709 provide complementary current out­puts, I
output, I
while I

and I

OUTA

OUTFS

, the complementary output, provides no current.

OUTB

The current output appearing at I
both the input code and I

= (DAC CODE/256) × I

I

OUTA

I

= (255 − DAC CODE)/256 × I

OUTB

. I

OUTB

provides a near full-scale current

OUTA

, when all bits are high (that is, DAC CODE = 256)

and I

OUTA

and can be expressed as

OUTFS

OUTFS

OUTB

OUTFS

is a function of

(1)

(2)

where DAC CODE = 0 to 255 (that is, decimal representation).

I

is a function of the reference current (I

OUTFS

nominally set by a reference voltage (V
resistor (R

I

). It can be expressed as

SET

= 32 × I

OUTFS

REF

REFIO

), which is

REF

) and an external

(3)

where

I

REF

= V

REFIO/RSET

(4)

The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, I
should be connected directly to matching resistive loads, R
that are tied to the analog common, ACOM. Note that R
can represent the equivalent load resistance seen by I
I

, as would be the case in a doubly terminated 50 Ω or 75 Ω

OUTB

cable. The single-ended voltage output appearing at the I
and I

Note the full-scale value of V

OUTB

V

V

OUTA

OUTB

nodes is

= I

OUTA

= I

OUTB

× R

× R

LOAD

LOAD

OUTA

and V

must not exceed the

OUTB

OUTA

and I

OUTA

OUTB

LOAD

or

OUTA

LOAD

(5)

(6)

specified output compliance range to maintain the specified
distortion and linearity performance.

V

DIFF

= (I

OUTA

− I

OUTB

) × R

LOAD

(7)

Equation 7 highlights some of the advantages of operating the
AD9709 differentially. First, the differential operation helps cancel
common-mode error sources associated with I

OUTA

and I

OUTB

,
such as noise, distortion, and dc offsets. Second, the differential
code-dependent current and subsequent voltage, V
the value of the single-ended voltage output (that is, V
V

), thus providing twice the signal power to the load.

OUTB

, is twice

DIFF

OUTA

or

Note that the gain drift temperature performance for a single­ended (V

OUTA

and V

) or differential output (V

OUTB

DIFF

) of the
AD9709 can be enhanced by selecting temperature tracking
resistors for R

LOAD

and R

due to their ratiometric relationship.

SET

ANALOG OUTPUTS

The complementary current outputs, I
DAC can be configured for single-ended or differential
operation. I
single-ended voltage outputs, V
resistor, R
The differential voltage, V

and I

OUTA

, as described in Equation 5 through Equation 7.

LOAD

can be converted into complementary

OUTB

OUTA

, existing between V

DIFF

can be converted to a single-ended voltage via a transformer or

OUTA

and V

and I

, via a load

OUTB

OUTB

OUTA

, in each

and V

OUTB

Rev. B | Page 14 of 32

,

differential amplifier configuration. The ac performance of the
AD9709 is optimum and specified using a differential
transformer-coupled output in which the voltage swing at I
and I
is desirable, I

is limited to ±0.5 V. If a single-ended unipolar output

OUTB

should be selected.

OUTA

OUTA

The distortion and noise performance of the AD9709 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I

OUTA

and I

OUTB

can be
significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases. This is due to the first-order cancellation of
various dynamic common-mode distortion mechanisms, digital
feedthrough, and noise.

Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (that is, assuming no
source termination). Because the output currents of I
I

are complementary, they become additive when processed

OUTB

OUTA

and

differentially. A properly selected transformer allows the AD9709
to provide the required power and voltage levels to different loads.

The output impedance of I

OUTA

and I

is determined by the

OUTB

equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, V
device. As a result, maintaining I

OUTA

and V

) due to the nature of a PMOS

OUTB

OUTA

and/or I

at a virtual

OUTB

ground via an I-V op amp configuration results in the optimum
dc linearity. Note that the INL/DNL specifications for the
AD9709 are measured with I

maintained at a virtual ground

OUTA

via an op amp.

I

OUTA

and I

also have a negative and positive voltage

OUTB

compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a
breakdown of the output stage and affect the reliability of the
AD9709.

The positive output compliance range is slightly dependent on
the full-scale output current, I

OUTFS

. When I

is decreased

OUTFS

from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at I

OUTA

and I

OUTB

does not exceed 0.5 V. Applications requiring the AD9709 output
(that is, V
should size R

and/or V

OUTA

accordingly. Operation beyond this compliance

LOAD

) to extend its output compliance range

OUTB

range adversely affects the linearity performance of the AD9709
and subsequently degrade its distortion performance.

AD9709

W

W

DIGITAL INPUTS

The digital inputs of the AD9709 consist of two independent
channels. For the dual port mode, each DAC has its own
dedicated 8-bit data port: WRT line and CLK line. In the
interleaved timing mode, the function of the digital control pins
changes as described in the Interleaved Mode Timing section.
The 8-bit parallel data inputs follow straight binary coding
where DB7P1 and DB7P2 are the most significant bits (MSBs)
and DB0P1 and DB0P2 are the least significant bits (LSBs).
I

produces a full-scale output current when all data bits are

OUTA

at Logic 1. I

produces a complementary output with the

OUTB

full-scale current split between the two outputs as a function of
the input code.

The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.

DAC TIMING

The AD9709 can operate in two timing modes, dual and
interleaved, which are described in the following sections. The
block diagram in Figure 25 represents the latch architecture in
the interleaved timing mode.

INTERLEAVED

DATA IN, PORT 1

IQWRT

IQSEL

IQCLK

IQRESET

PORT 1

INPUT

LATCH

PORT 2

INPUT

LATCH

÷2

Figure 25. Latch Structure in Interleaved Mode

Dual Port Mode Timing

When the MODE pin is at Logic 1, the AD9709 operates in dual
port mode (refer to Figure 21). The AD9709 functions as two
distinct DACs. Each DAC has its own completely independent
digital input and control lines.

The AD9709 features a double-buffered data path. Data enters the
device through the channel input latches. This data is then trans­ferred to the DAC latch in each signal path. After the data is loaded
into the DAC latch, the analog output settles to its new value.

For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.

DAC1
LATCH

DAC2
LATCH

DAC1

DAC2

DEINTERLEAVED
DATA OUT

00606-027

The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns should
be maintained from rising edge of WRT to rising edge of CLK.

Timing specifications for dual port mode are given in Figure 26
and Figure 27.

DATA IN

RT1/WRT2

CLK1/CLK2

I

OUTA

OR

I

OUTB

DATA IN

RT1/WRT2

CLK1/CLK2

I

OUTA

I

OUTB

t

S

Figure 26. Dual Port Mode Timing

D1 D2 D3 D4 D5

OR

XX

D1

Figure 27. Dual Mode Timing

t

H

t

LPW

t

CPW

t

PD

D2

D3

D4

00606-026

Interleaved Mode Timing

When the MODE pin is at Logic 0, the AD9709 operates in
interleaved mode (refer to Figure 25). In addition, WRT1
functions as IQWRT, CLK1 functions as IQCLK, WRT2
functions as IQSEL, and CLK2 functions as IQRESET.

Data enters the device on the rising edge of IQWRT. The
logic level of IQSEL steers the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper
operation, IQSEL should only change state when IQWRT and
IQCLK are low.

When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the next rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.

Similar to the order of CLK and WRT in dual port mode,
IQCLK should occur before or simultaneously with IQWRT.

00606-025

Rev. B | Page 15 of 32

AD9709

Timing specifications for interleaved mode are shown in Figure 28
and Figure 30.

The digital inputs are CMOS compatible with logic thresholds,
V

THRESHOLD

, set to approximately half the digital positive supply

(DVDDx) or

V

THRESHOLD

= DVDDx/2 (±20%)

t

S

t

H

INTERLEAVED

DATA

IQSEL

IQWRT

IQCLK

IQRESET

xx D1 D2 D3 D4 D5

DATA IN

500 ps

IQSEL

t

*

IQWRT

IQCLK

I

OUTA

OR

I

OUTB

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

H

500 ps

t

LPW

t

PD

00606-056

Figure 28. 5 V or 3.3 V Interleaved Mode Timing

At 5 V it is permissible to drive IQWRT and IQCLK together as
shown in Figure 29, but at 3.3 V the interleaved data transfer is
not reliable.

t

S

DATA IN

IQSEL

t

*

IQWRT

IQCLK

I

OUTA

OR

I

OUTB

*APPLIES T O FALLING EDGE OF IQCLK/ IQWRT AND I QSEL ONL Y .

H

Figure 29. 5 V Only Interleaved Mode Timing

t

H

t

LPW

t

PD

00606-028

DAC OUTPUT

PORT 1

DAC OUTPUT

PORT 2

xx

xx

D1

D2

D3

D4

00606-029

Figure 30. Interleaved Mode Timing

The internal digital circuitry of the AD9709 is capable of operating
at a digital supply of 3.3 V or 5 V. As a result, the digital inputs
can also accommodate TTL levels when DVDD1/DVDD2 is set to
accommodate the maximum high level voltage (V

OH(MAX)

) of the
TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper
compatibility with most TTL logic families. Figure 31 shows the
equivalent digital input circuit for the data and clock inputs.
The sleep mode input is similar with the exception that it
contains an active pull-down circuit, thus ensuring that the
AD9709 remains enabled if this input is left disconnected.

DVDD1

DIGITAL

INPUT

00606-030

Figure 31. Equivalent Digital Input

Because the AD9709 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9709
with reduced logic swings and a corresponding digital supply
(DVDD1/DVDD2) results in the lowest data feedthrough and
on-chip digital noise. The drivers of the digital data interface
circuitry should be specified to meet the minimum setup and
hold times of the AD9709 as well as its required minimum and
maximum input logic level thresholds.

Rev. B | Page 16 of 32

AD9709

Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion of
a low value (that is, 20 Ω to 100 Ω) resistor network between
the AD9709 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to digital feedthrough. For longer board traces and
high data update rates, stripline techniques with proper
impedance and termination resistors should be considered to
maintain “clean” digital inputs.

The external clock driver circuitry provides the AD9709 with a
low-jitter clock input meeting the minimum and maximum logic
levels while providing fast edges. Fast clock edges help minimize
jitter manifesting itself as phase noise on a reconstructed waveform.
Therefore, the clock input should be driven by the fastest logic
family suitable for the application.

Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This typically
results in a slight degradation in the phase noise, which becomes
more noticeable at higher sampling rates and output frequencies.
In addition, at higher sampling rates, the 20% tolerance of the
digital logic threshold should be considered because it affects
the effective clock duty cycle and, subsequently, cut into the
required data setup and hold times.

Input Clock and Data Timing Relationship

SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising-edge triggered and
therefore exhibits SNR sensitivity when the data transition is
close to this edge. In general, the goal when applying the AD9709 is
to make the data transition close to the falling clock edge. This
becomes more important as the sample rate increases. Figure 32
shows the relationship of SNR to clock/data placement.

60

50

40

30

SNR (dBc)

20

10

0

–4 –3 –2 –1 0 1 2 3 4

Figure 32. SNR vs. Clock Placement @ f

TIME OF DATA CHANGE RELATIVE TO

RISING CL OCK EDGE (ns)

= 20 MHz and f

OUT

= 125 MSPS

CLK

00606-031

Rev. B | Page 17 of 32

AD9709

SLEEP MODE OPERATION

The AD9709 has a power-down function that turns off the
output current and reduces the supply current to less than

8.5 mA over the specified supply range of 3.3 V to 5 V and
temperature range. This mode can be activated by applying a
Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold
is equal to 0.5 × AVDD. This digital input also contains an active
pull-down circuit that ensures the AD9709 remains enabled if
this input is left disconnected. The AD9709 requires less than
50 ns to power down and approximately 5 µs to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9709 is dependent on several
factors, including

• the power supply voltages (AVDD and DVDD1/DVDD2)

• the full-scale current output (I

• the update rate (f

CLK

)

• the reconstructed digital input waveform

The power dissipation is directly proportional to the analog
supply current, I
is directly proportional to I
insensitive to f

Conversely, I
f

, and digital supply (DVDD1/DVDD2). Figure 34 and

CLK

Figure 35 show I
ratios (f

OUT/fCLK

, and the digital supply current, I

AVD D

, as shown in Figure 33, and is

OUTFS

.

CLK

is dependent on the digital input waveform,

DVDD

as a function of full-scale sine wave output

DVDD

) for various update rates with DVDD1 =
DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively.
Note how I

is reduced by more than a factor of 2 when

DVDD

DVDD1/DVDD2 is reduced from 5 V to 3.3 V.

OUTFS

)

. I

DVDD

AVD D

80

70

60

50

(mA)

40

AVDD

I

30

20

10

022015105

35

30

25

20

(mA)

15

DVDD

I

10

18

16

14

12

10

(mA)

DVDD

I

5

0

000.40.30.20.1

Figure 34. I

8

6

4

2

0

000.40.30.20.1

Figure 35. I

DVDD

DVDD

I

(mA)

OUTFS

Figure 33. I

125MSPS

100MSPS

RATIO (

vs. I

AVDD

65MSPS

25MSPS

5MSPS

f

OUT

OUTFS

/

f

)

CLK

vs. Ratio @ DVDD1 = DVDD2 = 5 V

125MSPS

100MSPS

65MSPS

25MSPS

5MSPS

RATIO (

f

/

f

)

OUT

CLK

vs. Ratio @ DVDD1 = DVDD2 = 3.3 V

5

00606-032

.5

0606-033

.5

0606-034

Rev. B | Page 18 of 32

AD9709

Ω

APPLYING THE AD9709

R

, can be inserted in applications where the output of the

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura­tions for the AD9709. Unless otherwise noted, it is assumed that
I

is set to a nominal 20 mA. For applications requiring the

OUTFS

optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
can consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the
optimum high frequency performance and is recommended for
any application allowing for ac coupling. The differential op
amp configuration is suitable for applications requiring dc
coupling, bipolar output, signal gain, and/or level shifting,
within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage results
if I

and/or I

OUTA

resistor, R

LOAD

is connected to an appropriately sized load

OUTB

, referred to ACOM. This configuration may be
more suitable for a single-supply system requiring a dc-coupled,
ground-referred output voltage. Alternatively, an amplifier can be
configured as an I-V converter, thus converting I

OUTA

or I

OUTB

into a
negative unipolar voltage. This configuration provides the best dc
linearity because I
Note that I

OUTA

or I

OUTA

is maintained at a virtual ground.

OUTB

provides slightly better performance than I

OUTB

.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used as shown in Figure 36 to perform
a differential-to-single-ended signal conversion. A differentially
coupled transformer output provides the optimum distortion
performance for output signals whose spectral content lies within
the pass band of the transformer. An RF transformer such as the
Mini-Circuits® T1-1T provides excellent rejection of common­mode distortion (that is, even-order harmonics) and noise over
a wide frequency range. It also provides electrical isolation and
the ability to deliver twice the power to the load. Transformers
with different impedance ratios can also be used for impedance
matching purposes. Note that the transformer provides ac
coupling only.

AD9709

I

OUTA

I

OUTB

Figure 36. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both I
at I

OUTA

OUTA

and I

and I

(that is, V

OUTB

. The complementary voltages appearing

OUTB

around ACOM and should be maintained with the specified
output compliance range of the AD9709. A differential resistor,

Mini-Circuits

OPTIONAL
R

DIFF

and V

OUTA

T1-1T

R

LOAD

) swing symmetrically

OUTB

00606-035

DIFF

transformer is connected to the load, R
reconstruction filter or cable. R

is determined by the

DIFF

, via a passive

LOAD

transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately
half the signal power will be dissipated across R

DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used as shown in Figure 37 to perform a
differential-to-single-ended conversion. The AD9709 is configured
with two equal load resistors, R
voltage developed across I

OUTA

ended signal via the differential op amp configuration. An optional
capacitor can be installed across I
in a low-pass filter. The addition of this capacitor also enhances the
op amp’s distortion performance by preventing the DAC’s high­slewing output from overloading the op amp’s input.

AD9709

I

OUTA

I

OUTB

Figure 37. DC Differential Coupling Using an Op Amp

C

OPT

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate from a dual
supply because its output is approximately ±1.0 V. A high speed
amplifier capable of preserving the differential performance of
the AD9709 while meeting other system level objectives (that is,
cost and power) should be selected. The op amp’s differential
gain, gain setting resistor values, and full-scale output swing
capabilities should be considered when optimizing this circuit.

The differential circuit shown in Figure 38 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9709 and the op amp, is used to level shift the differential
output of the AD9709 to midsupply (that is, AVDD/2). The

AD8041 is a suitable op amp for this application.

AD9709

I

OUTA

I

OUTB

Figure 38. Single-Supply DC Differential Coupled Circuit

25Ω

C

OPT

, of 25 Ω each. The differential

LOAD

and I

OUTA

25Ω25Ω

25Ω

is converted to a single-

OUTB

and I

225Ω

225Ω

225Ω

225Ω

, forming a real pole

OUTB

500

AD8047

500Ω

500Ω

AD8041

1kΩ

500Ω

AVDD

0606-036

0606-037

Rev. B | Page 19 of 32

AD9709

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

Figure 39 shows the AD9709 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated
50 Ω cable, because the nominal full-scale current, I
flows through the equivalent R

of 25 Ω. In this case, R

LOAD

represents the equivalent load resistance seen by I
The unused output (I
ACOM or via a matching R
R

can be selected as long as the positive compliance range is

LOAD

OUTA

or I

) can be connected directly to

OUTB

. Different values of I

LOAD

OUTFS

OUTA

OUTFS

, of 20 mA

LOAD

or I

OUTB

and

.

adhered to. One additional consideration in this mode is the
INL (see the Analog Outputs section). For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.

AD9709

I

= 20mA

I

OUTA

I

OUTB

OUTFS

50Ω

25Ω

V

OUTA

= 0V TO 0.5V

50Ω

Figure 39. 0 V to 0.5 V Unbuffered Voltage Output

00606-038

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION

Figure 40 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9709 output current. U1 maintains I
virtual ground, thus minimizing the nonlinear output
impedance effect on the INL performance of the DAC, as
discussed in the Analog Outputs section. Although this single­ended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates may be limited by the slewing capabilities of U1.
U1 provides a negative unipolar output voltage, and its full­scale output voltage is simply the product of R
full-scale output should be set within U1’s voltage output swing
capabilities by scaling I

and/or RFB. An improvement in ac

OUTFS

distortion performance may result with a reduced I
the signal current U1 has to sink will be subsequently reduced.

AD9709

I

OUTA

I

OUTB

I

= 10mA

OUTFS

200Ω

Figure 40. Unipolar Buffered Voltage Output

C

OPT

R

FB

200Ω

U1

OUTA

(or I

FB

V

OUTB

and I

= I

OUT

) at a

OUTFS

OUTFS

. The

OUTFS

because

× R

FB

00606-039

POWER AND GROUNDING CONSIDERATIONS

Power Supply Rejection

Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 52 and Figure 53 illustrate the recommended
circuit board layout, including ground, power, and signal
input/output.

One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, I
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9709 AVDD supply over this frequency range is shown in
Figure 41.

90

85

80

PSRR (dB)

75

70

0.20.30.40.50.60.70.80.91.01.1
FREQUENCY (MHz)

Figure 41. AVDD Power Supply Rejection Ratio vs. Frequency

Note that the data in Figure 41 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired I
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worst­case PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 41 represents a worst­case condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.

. AC noise on the dc supplies

OUTFS

. PSRR is very code

OUT

00606-040

Rev. B | Page 20 of 32

AD9709

An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake, all of this noise is concentrated at 250 kHz (that is, ignore
harmonics). To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC full-scale
current, I
Figure 41 at 250 kHz. To calculate the PSRR for a given R

, one must determine the PSRR in decibels using

OUTFS

LOAD

,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 41 by the scaling factor 20 × log(R
For instance, if R

is 50 Ω, the PSRR is reduced by 34 dB

LOAD

LOAD

).

(that is, the PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 41, becomes 51 dB V

OUT/VIN

).

Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9709 features separate analog and digital supply and ground
pins to optimize the management of analog and digital ground
currents in a system. In general, decouple the analog supply

(AVDD) to the analog common (ACOM) as close to the chip as
physically possible. Similarly, decouple DVDD1/DVDD2, the
digital supply (DVDD1/DVDD2) to the digital common
(DCOM1/DCOM2) as close to the chip as possible.

For applications that require a single 5 V or 3.3 V supply for
both the analog and digital supplies, a clean analog supply can
be generated using the circuit shown in Figure 42. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low-ESR
type electrolytic and tantalum capacitors.

FERRITE

TTL/CMOS

LOGIC

CIRCUITS

5V

POWER SUPPLY

Figure 42. Differential LC Filter for Single 5 V and 3.3 V Applications

BEADS

ELECTROLYTIC

10µF

100µF 0.1µF

TO
22µF

TANTALUM

CERAMIC

AVDD

ACOM

00606-041

Rev. B | Page 21 of 32

AD9709

A

APPLICATIONS INFORMATION

QUADRATURE AMPLITUDE MODULATION (QAM) USING THE AD9709

QAM is one of the most widely used digital modulation
schemes in digital communications systems. This modulation
technique can be found in FDM as well as spread spectrum
(that is, CDMA) based systems. A QAM signal is a carrier
frequency that is modulated in both amplitude (that is, AM
modulation) and phase (that is, PM modulation). It can be
generated by independently modulating two carriers of identical
frequency but with a 90° phase difference. This results in an
in-phase (I) carrier component and a quadrature (Q) carrier
component at a 90° phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier frequency.

A common and traditional implementation of a QAM
modulator is shown in Figure 43. The modulation is performed
in the analog domain in which two DACs are used to generate
the baseband I and Q components. Each component is then
typically applied to a Nyquist filter before being applied to a
quadrature mixer. The matching Nyquist filters shape and limit
each component’s spectral envelope while minimizing intersymbol
interference. The DAC is typically updated at the QAM symbol
rate, or at a multiple of the QAM symbol rate if an interpolating
filter precedes the DAC. The use of an interpolating filter typically
eases the implementation and complexity of the analog filter,
which can be a significant contributor to mismatches in gain
and phase between the two baseband channels. A quadrature
mixer modulates the I and Q components with the in-phase and
quadrature carrier frequencies and then sums the two outputs
to provide the QAM signal.

In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 44 helps improve
the matching between the I and Q channels, and it shows a path
for upconversion using the AD8346 quadrature modulator. The
AD9709 provides both I and Q DACs with a common reference
that will improve the gain matching and stability. R
used to compensate for any mismatch in gain between the two
channels. The mismatch may be attributed to the mismatch
between R
channel, and/or the voltage offset of the control amplifier in each
DAC. The differential voltage outputs of both DACs in the
AD9709 are fed into the respective differential inputs of the
AD8346 via matching networks.

DSP

OR

ASIC

VDD

8

DAC

CARRIER

FREQUENCY

8

DAC

NYQUIST

FILTERS

0°

90°

QUADRATURE

MODULATOR

Figure 43. Typical Analog QAM Architecture

SET1

and R

, the effective load resistance of each

SET2

TO

Σ

MIXER

00606-044

can be

CAL

DCOM1/

DVDD1/

DCOM2

DVDD2

TEKTRONIX

AWG2021

WITH

OPTION 4

WRT1/IQWRT

CLK1/IQCLK

PORT Q PORT I

WRT2/IQSEL

SLEEP

256Ω

22nF

NOTES

1. DAC FULL -S CALE OUTPUT CURRENT = I

2. RA, RB, AND RL ARE THI N FILM RESIS T O R NETWORKS
WITH 0. 1% MATCHING, 1% ACCURACY AV AILABLE
FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.

I DAC

LATCH

Q DAC

DIGITAL INTERFACE

LATCH

2kΩ

20kΩ

AD9709

FSADJ1

256Ω

22nF

OUTFS

ACOM

AVDD

DAC

DAC

FSADJ2MODE REFIO

.

Q

I

2kΩ

20kΩ

I

I

I

I

OUT

OUT

OUT

OUT

A

CA

B

A

CA

B

0.1µF

RL

RL

LA

CB

LA

RL

RL

RL

RL

LA

CB

LA

DIFFERENTIAL
RLC FILTER

RL = 200Ω
RA = 2500Ω
RB = 500Ω
RP = 200Ω
CA = 280pF
CB = 45pF
LA = 10µH
I

= 11mA

OUTFS

AVDD = 5.0V
VCM = 1.2V

RA RA

RB

RB

RA

RB

C

FILTER

RB

RLRL

VDIFF = 1 .82V p-p

RA

0.1µF

BBIP

BBIN

BBQP

BBQN

AD976x

0 TO I

Figure 44. Baseband QAM Implementation Using an AD9709 and AD8346

Rev. B | Page 22 of 32

VPBF

SPLITTER

OUTFS

PHASE

AD8346

ROHDE & S C HWARZ

FSEA30B

OR EQUIVAL ENT

SPECTRUM ANALYZ ER

VOUT

+

LOIP

LOIN

ROHDE & S CH WARZ

SIGNAL GE NERAT O R

AVDD

RA

RL

RB

V

DAC

AD8346

V

MOD

00606-045

AD9709

–

I and Q digital data can be fed into the AD9709 in two ways. In
dual port mode, the digital I information drives one input port,
and the digital Q information drives the other input port. If no
interpolation filter precedes the DAC, the symbol rate is the rate
at which the system clock drives the CLK and WRT pins on the
AD9709. In interleaved mode, the digital input stream at Port 1
contains the I and the Q information in alternating digital words.
Using IQSEL and IQRESET, the AD9709 can be synchronized
to the I and Q data streams. The internal timing of the AD9709
routes the selected I and Q data to the correct DAC output. In
interleaved mode, if no interpolation filter precedes the AD9709,
the symbol rate is half that of the system clock driving the digital
data stream and the IQWRT and IQCLK pins on the AD9709.

CDMA

Code division multiple access (CDMA) is an air transmit/receive
scheme where the signal in the transmit path is modulated with a
pseudorandom digital code (sometimes referred to as the spreading
code). The effect of this is to spread the transmitted signal across
a wide spectrum. Similar to a discrete multitone (DMT) wave­form, a CDMA waveform containing multiple subscribers can
be characterized as having a high peak to average ratio (that is,
crest factor), thus demanding highly linear components in the
transmit signal path. The bandwidth of the spectrum is defined
by the CDMA standard being used, and in operation it is
implemented by using a spreading code with particular
characteristics.

Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference
with other signals being transmitted by air. Regulatory bodies
define a spectral mask outside of the transmit band, and the ACP
must fall under this mask. If distortion in the transmit path causes
the ACP to be above the spectral mask, filtering or different
component selection is needed to meet the mask requirements.

Figure 45 displays the results of using the application circuit shown
in Figure 44 to reconstruct a wideband CDMA (W-CDMA) test
vector using a bandwidth of 8 MHz that is centered at 2.4 GHz
and sampled at 65 MHz. The IF frequency at the DAC output is

15.625 MHz. The adjacent channel power ratio (ACPR) for the
given test vector is measured at greater than 54 dB.

30

–40

–50

–60

==

–70

–80

(dB)

–90

–100

–110

c11

–120

–130

CENTER 2.4GHz

Figu re 45. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS,

Recreated at 2.4 GHz, Adja cent C hannel Power > 54 d B

c11

C0

FREQUENCY

cu1

C0

cu1

SPAN 30MHz3MHz

00606-046

Rev. B | Page 23 of 32

AD9709

EVALUATION BOARD

GENERAL DESCRIPTION

The AD9709-EB is an evaluation board for the AD9709 8-bit
dual DAC. Careful attention to layout and circuit design,
combined with a prototyping area, allow the user to easily and
effectively evaluate the AD9709 in any application where high
resolution, high speed conversion is required.

SCHEMATICS

RED

DVDDIN 3

TB1

1

L1

DCASE

VAL
VOLT

DVDD AVDD

BLKBLKBLK

This board allows the user flexibility to operate the AD9709 in
various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single-ended and
differential outputs. The digital inputs can be used in dual port
or interleaved mode and are designed to be driven from various
word generators, with the on-board option to add a resistor
network for proper load termination. When operating the
AD9709, best performance is obtained when running the digital
supply (DVDD1/DVDD2) at 3.3 V and the analog supply
(AVDD) at 5 V.

RED

AVDDIN

TB1

L2

BEADBEAD

DCASE

C10C9
VAL

VOLT

BLKBLKBLK

TB1

2

INP31
INP32
INP33
INP34
INP35
INP36

INCK2

BLK

1

RCOM

22 22

R1
R2

3

R3

4

R4

5

R5

6

R6

7

R7

8

R8

9

R9

10

INP23
INP24
INP25
INP26
INP27
INP28
INP29
INP30

DGND

1

RCOM

R1

22
3
4
5
6
7
8
9

10

RP10RP15

INP9

R2

INP10

R3

INP11

R4

INP12

R5

INP13

R6

INP14

R7
R8

INCK1

R9

TB1

4

BLK

AGND

10

1
2
3
4
5
6
7
8
9

RCOM

22

RP16

R1
R2
R3
R4
R5
R6
R7
R8
R9

00606-146

1

RCO M

22

R1

2
3
4
5
6
7
8
9

10

RP9

INP1

R2

INP2

R3

INP3

R4

INP4

R5

INP5

R6

INP6

R7

INP7

R8

INP8

R9

Figure 46. Power Decoupling and Clocks on AD9709 Evaluation Board (1)

Rev. B | Page 24 of 32

AD9709

9

712

Q

Q_

DVDD;16

DGND;8

CLR

PRE

U6

C8

CC0805CC0805

.1UF

C7

10

.01UF

DVDD

DVDD

1

B

A

3

PRE

C

4

2

SW1

JP2

C34

.01UF

CC0805

C33

.1UF

DVDD

CC0805

DCLKIN2

+IN

7

14

CLK

J

K

13

11

SN74F112

5

Q

Q_

DVDD;16

DGND;8

A

CLR

U6

15

K

CLK

J

3126

SN74F112

3

C

2

B

1

SW2

DVDD

DVDD

JP1

10

OUT

U2

11

SO16

OUT

DS90LV048B

U2

-IN

+IN

8

5

14

SO16

DS90LV048B

-IN

6

SO16

OUT

DS90LV048B

U2

+IN

-IN

3

4

CLK2

CLK1

WRT1

WRT2

SLEEP

/2 CLOCK DI VIDER

DVDD

12

13

VCC

GND

SO16

U2

DS90LV048B

EN

DVDD

VAL

R30

RC0603

EN

9

16

00606-147

JP9

JP16

JP5

DCLKIN1

15

OUT

U2

+IN

1

1K

RC0603RC0603

R19

1K

R16

DVDD

RC0603

1KR17 R18 1K

RC0603

.1

CC0805

.1

CC0805

C18

C19

1234

T1-1TCUP

5

6

DVDD

JP17

SO16

DS90LV048B

-IN

2

T3

RC0603

JP14

R63 50

JP13

WHT

DGND;3,4,5

SMA200UP

SMA200UP

S1

RT1IN

IQWRT

JP4

JP3

R4

5050

RC0805

R3

50

RC0805

R2

50

RC0805

R1

RC0805

S3

CLK2IN

DGND;3,4,5

RESET

WHT

DGND;3,4,5

SMA200UP

S4

RT2IN

IQSEL

WHT

WHT

DGND;3,4,5

SMA200UP

S2

1QCLK

CLK1IN

50

R13

RC0805

WHT

SLEEP

Figure 47. Power Decoupling and Clocks on AD9709 Evaluation Board (2)

Rev. B | Page 25 of 32

AD9709

A

O2N

O2P

C24

L6 DNP

LC0805

DNPL5

LC0805

PNDPND

CC0805CC0805

C23

R23 51

RC0603

JP19

RC0603 RC0603

C31

R22 DNP51R21

DNP

CC0603

MODULATED OUTPUT

AGND2;3,4,5

SMAEDGE

2

AVDD2

RC0603

0R27

RC0603

LOCAL OSC INPUT

R29 0

R20
50

RC0603

J1

2

AGND2;3,4,5

SMAEDGE

J2

2

VDD2

BCASE

C28

.1UF

C20
10UF
10V

2

C29

C27
100PF

CC0603CC0603

.1UF

CC0603

15

16

QBBP

AGND2;17

IBBP

2

1

QBBN

IBBN

9

10

13

14

11712

G2

G3

G4A

G4B

VPS2

VOUT

U3

AD8349

RC0603

G1A

G1B

3

4

5

ENBL

LOIN

LOIP

VPS1

8

6

C30

2

C26

100PF

100PFC25

CC0603 CC0603

CC0603

100PF

2

R28
1K

JP18

ETC1-1-13

SP

1

T4

AVDD2

TP6

RED

AGND2

TP5

BLK

43

5

O1N

O1P

DNP

LC0805

L3 DNP

LC0805

DNPL4

DNP

CC0805CC0805

12C22C

51R26

RC0603

JP20

R25 51

RC0603

Figure 48. Modulator on AD9709 Evaluation Board

C32

2

JP21

JP22

2

DNP

CC0603

DNPR24

RC0603

00606-148

Rev. B | Page 26 of 32

AD9709

00606-149

470470

RC0603

R49R50

RC0603

DUTP1

DUTP5

DUTP4

DUTP3

DUTP2

DUTP9

DUTP8

DUTP7

DUTP6

DUTP13

DUTP14

DUTP12

DUTP11

DUTP10

DCLKIN1

470470

RC0603

R51 R33

RC0603

470 470

RC0603

R53 R52

RC0603

470 470

RC0603

R55R56

RC0603

470

RC0603

R57 R54

RC0603

R58

470470

RC0603

R59

RC0603

R60

470 470

RC0603

470

R61

RC0603

R62

470

RC0603

152

134

116

9

10

10

10

RP5

RP5

161

143

125

10

10

10

RP5

RP5

RP5

152

10

RP5

RP5

8

107

10

10

RP5

RP6

116

10

RP6

134

10

RP6

10

RP6

314

116

10

RP6

10

RP6

512

98

10

RP6

INP1

INP3

INP2

INP4

INP5

INP6

INP7

INP8

9

3

1

P1

87

65

4

2

14 13

12 11

10

Figure 49. Digital Input Signaling (1)

INP9

INP10

INP11

INP12

19

RIBBON RA

24 23

22 21

20

18 17

16 15

INP13

INP14

INCK1

710

RP6

10

SPARES

29

32 31

30

28 27

26 25

39

HDR040RA

HDR040RA

40

38 37

36 35

34 33

Rev. B | Page 27 of 32

AD9709

00606-150

470

RC0603

470

R41 R42

RC0603

DUTP23

DUTP24

DUTP25

DUTP29

DUTP27

DUTP26

DUTP28

DUTP33

DUTP31

DUTP30

DUTP32

DUTP34

DUTP35

DUTP36

DCLKIN2

470470

RC0603

R43 R40

RC0603

470 470

RC0603

R45 R44

RC0603

470 470

RC0603

R39R38

RC0603

470

RC0603

R47 R46

RC0603

R37

470470

RC0603

R36

RC0603

R48

470 470

RC0603

470

R35R34

RC0603

470

RC0603

INP23

10

RP7

116

152

10

RP7

INP25

INP24

10

RP7

314

134

10

RP7

INP26

INP27

10

RP7

512

116

10

RP7

INP28

INP29

10

RP7

710

98

10

RP710152

INP30

INP31

10

RP8

116

RP8

INP32

INP33

10

RP8

314

134

10

RP8

INP34

INP35

10

RP8

512

116

10

RP8

INP36

1

3

56789

1112

1314

1516

1718

19

2122

10

RIBBON RA

20

P2

2

4

Figure 50. Digital Input Signaling (2)

Rev. B | Page 28 of 32

98

10

RP8

INCK2

710

RP8
10

SPARES

2324

2526

2728

29

3132

3334

3536

3738

39

HDR040RA

30

HDR040RA

40

AD9709

OUT1

SMA200UP

AGND;3,4,5

S6

WHT

REFIO

C14

.1UF

CC0805

WHT

6

5

T5

T1-1TCUP

BL1

1234

VAL

R11

RC07CUP

R6

RC0805

5050

C5

CC0805

R5

RC0805

BL2

RC0805

RC0805

JP10

R14 256

R15 256

RC0805

1.92KR10

22NF

22NF

R9 1.92K

C16

WHT

CC0805

CC0805

C17

10PF

BL3

T6

34

RC0805

WHT

50

R8

RC0805

10PF

C6

CC0805

50

R7

RC0805

OUT2

SMA200UP

AGND;3,4,5

S11

WHT

6

5

BL4

T1-1TCUP

1

2

VAL

R12

RC07CUP

AVDD

00606-151

RC0805

R31 10

JP23

CC0805

C4

10PF

O1P

O1N

JP6 JP7

31

BA

2

JP15

ACOM

AVDD

DVDD

C3

.1UF

BA

JP8

2

13

MODE

47

48

DVDD

AVDD

MODE

44

4146404539

43

42

IA1

IB1

REFIO

ACOM1

FSADJ1

FSADJ2

C15

CC0805

10PF

RC0805

10R32

.1UF

C13C11 C12

O2N

O2P

JP24

JP12 JP11

SLEEP

DUTP35

DUTP36

36

38

37

IB2

IA2

ACOM

DB0P2

DB1P2

SLEEP

DUTP31

DUTP32

DUTP33

DUTP34

32

DB2P2

DB3P2

DB4P2

DB5P2

DUTP27

DUTP28

DUTP29

DUTP30

DUTP25

DUTP26

27

DB6P2

DB7P2

DB8P2

DB9P2

DB10P2

DB11P2

.01UF

CC0805

CC0805 CC0805

VAL

U1

AD9763/65/67

.01UF

C2C1

CLK1

DVDD1

CLK2

WRT1

WRT2

18

19

17

20

DB12P2

DB13P2MSB

DCOM2

DVDD2

23

22

DB10P1

DB11P1

DB12P1

DB13P1MSB

VAL

CC0805 CC0805 CC0805

DB8P1

DB9P1

4263252241

DB4P1

DB5P1

DB6P1

DB7P1

9318307296285

DB0P1

DB1P1

DB2P1

DB3P1

DCOM1

14

13351234113310

152116

CLK2

CLK1

WRT2

DUTP5

DUTP6

DUTP7

DUTP8

DUTP1

DUTP2

DUTP3

DUTP4

DUTP9

DUTP10

DUTP11

DUTP12

DUTP13

WRT1

DUTP14

DUTP23

DUTP24

Figure 51. Device Under Test/Analog Output Signal Conditioning

Rev. B | Page 29 of 32

AD9709

EVALUATION BOARD LAYOUT

Figure 52. Assembly, Top Side

00606-152

Rev. B | Page 30 of 32

AD9709

00606-153

Figure 53. Assembly, Bottom Side

Rev. B | Page 31 of 32

AD9709

OUTLINE DIMENSIONS

9.20

1

12

0.50

BSC

48

13

9.00 SQ

8.80

PIN 1

TOP VIEW

(PINS DOWN)

24

37

0.27

0.22

0.17

36

7.20

7.00 SQ

6.80

25

051706-A

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.08
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

1.60
MAX

VIEW A

LEAD PITCH

Figure 54. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9709ASTZ1 –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9709ASTZRL1 –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD9709-EBZ1 Evaluation Board

1

Z = RoHS Compliant Part.

©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00606-0-9/09(B)

Rev. B | Page 32 of 32