Datasheet AD9660KR-REEL, AD9660KR Datasheet (Analog Devices)

200 MHz Laser Diode Driver

a

FEATURES

1.5 ns Rise/2.0 ns Fall Times
Output Current: 180 mA @ 3 V, 200 mA @ 2.5 V

Bias Current: 90 mA @ 3 V
Modulation Current: 60 mA @ 3 V

Offset Current: 30 mA @ 3 V
Single +5 V Power Supply
Switching Rate: 200 MHz
Onboard Light Power Control Loops

APPLICATIONS
Laser Printers and Copiers
Optical Disk Drives
FO Datacomm

GENERAL DESCRIPTION

The AD9660 is a highly integrated driver for laser diode appli­cations such as optical disk drives, printers, and copiers. The
AD9660 gets feedback from an external photo detector and in­cludes two analog feedback loops to allow users to set “bias”
and “write” (for optical disk drives) power levels of the laser,
and switch between the two power levels at up to 200 MHz.
Output rise and fall times are typically 1.5 ns and 2.0 ns to
complement printer applications that use image enhancing tech­niques such as pulse width modulation to achieve gray scale,
and allow disk drive applications to improve density and take
advantage of pulsed write formats. Control signals are TTL/
CMOS compatible.

with Light Power Control

AD9660

FUNCTIONAL BLOCK DIAGRAM

WRITE

PULSE
WRITE

CALIBRATE

WRITE
LEVEL

BIAS

LEVEL

BIAS

CAL

TRANSIMPEDANCE

BIAS

T/H

V:1T/H

AMPLIFIER

V:1

OUTPUT

DRIVER

OUTPUT

DRIVER

AD9660

The driver output provides up to 180 mA of current @ 3 V,
90 mA of BIAS current, 60 mA of modulation current, and
30 mA of offset current. The onboard disable circuit turns off
the output drivers and returns the light power control loops to a
safe state.

The AD9660 can also be used in closed loop applications in
which the output power level follows an analog WRITE LEVEL
voltage input. By optimizing the external hold capacitor, and
the photo detector, the write loop can achieve bandwidths as
high as 25 MHz.

The AD9660 is offered in a 28-pin plastic SOIC for operation

over the commercial temperature range (0°C to +70°C).

OUTPUT

SENSE

INPUT

PHOTO

DETECTOR

DIODE

LASER
DIODE

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

(+V

= +5 V, Temperature = +25°C unless otherwise noted. Sourced currents defined

S

AD9660–SPECIFICATIONS

as positive.)

Test AD9660KR

Parameter Level Temp Min Typ Max Units Conditions

ANALOG INPUTS
(WRITE LEVEL, BIAS LEVEL)

Input Voltage Range IV Full V

REF

V

REF

+ 1.6 V

Input Bias Current I +25°C –50 +50 µA

Analog Bandwidth V Full 25 MHz External Hold Cap = 20 pF

OUTPUTS

Maximum Output Current, I

I

OUT

Bias Current, I

BIAS

Modulation Current, I
Offset Current, I

OFFSET

OUT

MODULATION

I +25°C 200 mA V
I +25°C 180 mA V
I +25°C90 mA V
I +25°C60 mA V
I +25°C30 mA V

OUT

OUT

OUT

OUT

OUT

= 2.5 V
= 3.0 V
= 3.0 V
= 3.0 V
= 3.0 V

Output Compliance Range I +25°C 0 3.0 V
Idle Current I +25°C 3 13 mA WRITE PULSE = LOW,

DISABLE = HIGH

SWITCHING PERFORMANCE

Maximum Pulse Rate IV +25°C 200 250 MHz 3 dB Reduction in I

OUT

Output Propagation Delay (tPD), Rising1IV Full 1.6 3.0 ns
Output Propagation Delay (t
Output Current Rise Time
Output Current Fall Time
WRITE CAL Aperture Delay
Disable Time

5

), Falling1IV Full 1.6 2.5 ns

PD

2

3

4

IV Full 1.1 1.5 1.7 ns
IV Full 1.4 2.0 2.8 ns

V +25°C13 ns
V +25°C5 ns

HOLD NODES
(WRITE HOLD, BIAS HOLD)

Input Bias Current I +25°C –200 200 nA V

Input Voltage Range IV Full V

REF

V

+ 1.6 V Open Loop Application Only

REF

HOLD

= 2.5 V

Minimum External Hold Cap V Full 20 pF

TTL INPUTS

6

Logic “1” Voltage I +25°C 2.0 V DISABLE = LOW

Logic “1” Voltage IV Full 2.0 V While Other

Logic “0” Voltage I +25°C 0.8 V TTL Inputs Are

Logic “0” Voltage IV Full 0.8 V Tested

Logic “1” Current I +25°C –10 20 10 µA
Logic “0” Current I +25°C –1.5 mA

BANDGAP REFERENCE

Output Voltage V

REF

I +25°C 1.55 1.75 1.90 V
Temperature Coefficient V –0.2 mV/°C
Output Current V +25°C –0.5 1.0 mA

SENSE IN

Current Gain V +25°C 1.85 mA/mA
Voltage I +25°C 3.7 4.0 4.3 V I

MONITOR

= 2 mA

Input Resistance V +25°C <150 Ω

POWER SUPPLY (DISABLE = HIGH)

+V

Voltage I +25°C 4.75 5.00 5.25 V DISABLE = HIGH

S

Current I +25°C 75 110 150 mA

+V

S

Power Dissipation I +25°C 550 mW

OFFSET CURRENT

OFFSET SET Voltage I +25°C 1.1 1.4 1.7 V I

NOTES

1

Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to 50% point of the rising/falling edge of the output modulation current.

2

Rise time measured between the 10% and 90% points of the rising transition of the modulation current.

3

Fall time measured between the 10% and 90% points of the falling transition of the modulation current.

4

Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is

held during this test.

5

Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable
is similar to fall time during normal operation.

6

WRITE PULSE, WRITE CAL, BIAS CAL, OFFSET PULSE are TTL compatible inputs.

Specifications subject to change without notice.

MONITOR

= 4.0 mA

–2–

REV. 0

AD9660

100Ω

450Ω

1250Ω

V

BANDGAP

V

REF

+V

S

1mA

+V

S

50Ω 50Ω

SENSE

IN

T/H

WRITE

HOLD

BIAS

HOLD

OUTPUT

+V

S

OFFSET

SET

TTL

INPUT

+V

S

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

V

Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA

REF

WRITE LEVEL, BIAS LEVEL . . . . . . . . . . . . . –0.5 V to +V

TTL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +V

S

S

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA

Operating Temperature

AD9660KR . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature

2

. . . . . . . . . . . . . . . . +150°C

Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C

1

Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.

2

Typical thermal impedance is θJA = 45°C/W, θJC = 41°C/W.

ORDERING GUIDE

Model Temperature Range Package Option

AD9660KR 0°C to +70°C R-28
AD9660KR-REEL 0°C to +70°C R-28 (1000/reel)

PIN ASSIGNMENTS

EXPLANATION OF TEST LEVELS
Test Level

I. 100% Production Tested.

II. 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing done on sample basis.
III. Sample Tested Only.
IV. Parameter is guaranteed by design and characterization

testing.
V. Parameter is a typical value only.

VI. All devices are 100% production tested at +25°C, sample

tested at temperature extremes.

WRITE CAL
WRITE PULSE
WRITE LEVEL

V

REF

WRITE HOLD

GROUND

+V

SENSE IN

GAIN

POWER MONITOR

+V

GROUND

BIAS HOLD

BIAS LEVEL

S

S

1
2
3
4
5
6
7
8

9
10
11
12
13
14

AD9660KR

TOP VIEW

(Not to Scale)

28

OFFSET PULSE

27

OFFSET SET

26

GROUND

25

+V

S

24

OUTPUT

23

+V

S

22

OUTPUT

21

+V

S

20

OUTPUT
+V

19

S

OUTPUT

18
17

GROUND
DISABLE

16
15

BIAS CAL

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9660 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

Equivalent Circuits

REV. 0

–3–

AD9660

PIN DESCRIPTIONS

Pin Function

OUTPUT Analog laser diode current output. Connect to anode of laser diode, cathode connected to GROUND externally.

BIAS LEVEL Analog voltage input, V

tion as follows:

BIAS CAL TTL/CMOS compatible, Bias loop T/H control signal. Logic HIGH enables calibration mode, and the bias loop

T/H immediately goes into track mode. Logic LOW disables the bias loop T/H and immediately places it in hold
mode. WRITE PULSE should be held logic LOW while calibrating. Floats logic HIGH.

BIAS HOLD External hold capacitor for the bias loop T/H. Approximate droop in the bias current while BIAS CAL is logic

LOW is:

±∆I

BIAS

=

WRITE PULSE TTL/CMOS compatible, current control signal. Logic HIGH supplies I

LOW turns I

MODULATION

WRITE CAL TTL/CMOS compatible, write loop T/H control signal. Logic HIGH enables calibration mode; before enabling

calibration the bias loop should be calibrated and OFFSET PULSE driven to an appropriate state. In calibration
mode, 13 ns after the WRITE PULSE goes logic HIGH, the write loop T/H goes into track mode (there is no de­lay if WRITE PULSE is HIGH before WRITE CAL transitions to a HIGH level). The write loop T/H immedi­ately goes into hold mode when the WRITE PULSE goes Logic LOW. WRITE CAL LOW disables the write
loop T/H and places it in hold mode. Floats logic HIGH.

WRITE LEVEL Analog voltage input, V

I

tion as follows:

MONITOR

REF

18 ×10

C

to V

+ 1.6 V. Bias current is set proportional to the BIAS LEVEL during calibra-

REF

I

MONITOR

–9

t

BIAS HOLD

BIAS HOLD

off. Floats logic HIGH.

REF

to V

=

+1.6 V. Write current is set proportional to the input voltage during calibra-

REF

V

WRITE LEVEL−VREF

1. 85 ×(R

GAIN

V

BIAS LEVEL−VREF

=

1. 85 × R

+50 Ω

()

GAIN

. Bandwidth of the loop is:

+ 50 Ω)

BW =

2π (550 Ω)C

MODULATION

1

BIAS HOLD

to the laser diode. Logic

WRITE HOLD External hold capacitor for the write loop T/H. Approximate droop in I

−9

±∆I

logic LOW is:

MODULATED

BW =

2π (550 Ω) C

1

BIAS HOLD

SENSE IN Analog current input, I

MONITOR

18 ×10

=

, from PIN photo detector diode. SENSE IN should be connected to the cathode

t

WRITE HOLD

C

WRITE HOLD

. Bandwidth of the loop is:

MODULATION

current while WRITE CAL is

of the PIN diode, with the PIN anode connected to GROUND or a negative voltage. Voltage at SENSE IN var­ies slightly with temperature and current, but is typically 4.0 V.

GAIN External connection for the feedback network of the transimpedance amplifier. External feedback network, R

and C

, should be connected between GAIN and POWER MONITOR. See text for choosing values.

GAIN

GAIN

POWER Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from photo
MONITOR diode.

OFFSET Set resistor connection for the offset current source. Resistor between OFFSET CURRENT SET and +V

S

CURRENT SET determines offset current level. The input voltage at this node varies slightly with temperature and current, but is

typically 1.4 V. See curves. Can also be driven with a current out DAC.

OFFSET TTL/CMOS compatible, OFFSET current control signal. Logic HIGH adds I
PULSE turns off I

. Floats logic HIGH.

OFFSET

OFFSET

to I

. Logic LOW

OUT

DISABLE TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH disables

the current outputs to the laser diode, and drives the voltage on the hold capacitors close to V

(minimizes the

REF

output current when the device is re-enabled). DISABLE floats logic HIGH.

V

+V

REF

S

Analog Voltage Output, internal bandgap voltage reference, ~1.75 V, provided to user for power level offset.

Positive Power Supply. Nominally +5 V, pin connections should be tied together externally.

GROUND Ground Reference. All grounds should be tied together externally.

–4–

REV. 0

6.25mV

–193.8mV

OUTPUT

AD9660

20mV

ML64116R

PHOTO DETECTOR

–120V

ANTEL

ARS1

50Ω

2ns

TEK 11802

O'SCOPE

50Ω

Figure 1. Driving ML64116R Laser @ 30 mW

Typical Performance Characteristics–AD9660

35

30

25

20

OFFSET

I

15

10

5

0

0255101520

Figure 2. I

R

OFFSET

OFFSET

– kΩ

vs. R

OFFSET

THEORY OF OPERATION

The AD9660 combines a very fast output current switch with
onboard analog light power control loops to provide the user
with a complete laser diode driver solution. The block diagram
illustrates the key internal functions. The control loops of the
AD9660, the bias loop and the write loop, adjust the output
current level, I
I

MONITOR

, out of SENSE IN is proportional to the analog input

, so that the photo diode feedback current,

OUT

voltage at BIAS LEVEL or WRITE LEVEL. Since the monitor

WRITE HOLD

5pF

5pF

V

V

REF

REF

AD9660

V:1

TZA

V:1

C

GAIN

DISABLE

WRITE PULSE

WRITE CAL

WRITE LEVEL

GAIN

R

GAIN

POWER

MONITOR

BIAS LEVEL

BIAS CAL

BIAS HOLD

OFFSET PULSE

TTL

TTL

TTL

ANALOG

ANALOG

ANALOG

TTL

TTL

DISABLE

CIRCUIT

*

DELAY

50

Figure 3. Functional Block Diagram

current is proportional to the laser diode light power, the loops
effectively control laser power to a level proportional to the ana­log inputs. The control loops should be periodically calibrated
independently (see Choosing C

BIAS HOLD

and C

WRITE HOLD

).

The offset current generator produces an open loop output cur­rent, I
a current out DAC (see Figure 2). While I

. Its level is controlled by an external set resistor or

OFFSET

OFFSET

is not cali­brated as the currents from the bias and write loops are, it can
be very versatile (see Offset Current below).

2* I

V

REF

MONITOR

VOLT

I

MODULATION

1:10

1.85:1

1:10

1:10

REF

I

BIAS

I

OFFSET

V

REF

OUTPUT

SENSE IN

4.0V

I

MONITOR

OFFSET CURRENT

1.4V

I

OUT

OUT

WRITE LOOP

PHOTO
DETECTOR

SET

*

10ns DELAY ON RISING

EDGE; 0ns ON FALLING

LASER
DIODE

BIAS LOOP

+V

S

REV. 0 –5–

AD9660

LASER

POWER-UP

OR LASER

NOT IN USE

CALIBRATED WRITE

CALIBRATED BIAS

BIAS

CAL

TIME

WRITE

LOOP

CAL
TIME

WRITE LOOP

HOLD TIME

LASER POWER

MODULATED

BETWEEN

BIAS AND WRITE LEVELS

RECALIBRATE THE BIAS LOOP

RECALIBRATE WRITE LOOP

DISABLE

BIAS CAL

WRITE CAL

WRITE PULSE

OUTPUT POWER

Figure 4. Normal Operating Mode

The disable circuit turns off I

and returns the hold capacitor

OUT

voltages to their minimum levels (minimum output current)
when DISABLE = logic HIGH. It is used during initial power­up of the AD9660 or during time periods when the laser is inac­tive. When the AD9660 is re-enabled the control loops must be
recalibrated.

Normal operation of the AD9660 involves (in order, see figure):

1. The AD9660 is enabled (DISABLE = logic LOW).

2. The input voltages (BIAS LEVEL and WRITE LEVEL) are
driven to the appropriate levels to set the calibrated laser di­ode output power levels.

3. The bias loop is closed for calibration (BIAS CAL = logic
HIGH), and then opened (BIAS CAL = logic LOW).

4. The write loop is closed for calibration (WRITE PULSE and
WRITE CAL = logic HIGH) and then opened.

5. While both loops are open, the laser is pulsed between the
two calibrated levels by WRITE PULSE.

6. The bias and write loops are periodically recalibrated as
needed.

7. The AD9660 is disabled when the laser will not be pulsed for
an indefinite period of time.

Control Loop Transfer Functions

The relationship between I

V

I

MONITOR

BIAS LEVEL−VREF

=

1. 85 ×(R

MONITOR

GAIN

and V

+50 Ω)

BIAS LEVEL

is

once the bias loop is calibrated. When the bias loop is open
(BIAS CAL = logic LOW), its output current, I

, is propor-

BIAS

tional to the held voltage at BIAS HOLD; the external hold ca­pacitor on this pin determines the droop error in the output bias
current between calibrations.

The relationship between I

V

I

MONITOR

WRITE LEVEL−VREF

=

1. 85 ×(R

MONITOR

GAIN

and V

+50 Ω)

WRITE LEVEL

is

once the write loop is calibrated. The current supplied by the write
loop output is referred to as the modulation current, I

MODULATION

.

When the write loop is open (WRITE CAL logic LOW),
I

MODULATION

is proportional to the held voltage at WRITE HOLD.
The external hold capacitor (WRITE HOLD) determines the
droop error between calibrations. I

MODULATION

may be switched

on and off by WRITE PULSE when the write loop is open.

4

0°C CASE

3

2

OPTICAL OUTPUT – mW

1

0

CONSTANT WRITE POWER

BIAS CALIBRATION POWER

0 12020 40 60 80 100

FORWARD CURRENT – mA

BIAS

MOD

25°C

CASE

50°C CASE

Figure 5. Typical Laser Diode Current-to-Optical
Power Curve

The sections below discuss choosing the external components in
the feedback loops for a particular application.

Choosing R

The gain resistor, R

GAIN

, allows the user to match the feedback

GAIN

loop’s transfer function to the laser diode/photo diode
combination.

The user should define the maximum laser diode output power
for the intended application, P
photo diode monitor current, I
ode transfer function is illustrated in Figure 5. R

1. 6 V

MONITOR MAX

chosen as:

R

GAIN

=

1. 85 × I

The laser diode’s output power will then vary from 0 to P
for an input range of V

REF

to V

, and the corresponding

LD MAX

MONITOR MAX

+1.6 V @ the BIAS LEVEL

REF

. A typical laser di-

should be

GAIN

−50 Ω

.

LD MAX

and WRITE LEVEL inputs.

–6–

REV. 0

AD9660

Minimum specifications for I
choosing R

. Users are cautioned that laser diode/photo di-

GAIN

MONITOR MAX

should be used when

ode combinations that produce monitor currents that are less
than I

MONITOR MAX

in the equation above will produce higher la­ser output power than predicted, which may damage the laser
diode. Such a condition is possible if R

is calculated using

GAIN

typical instead of minimum monitor current specifications. In
that case the input range to the AD9660 BIAS LEVEL and
WRITE LEVEL inputs should be limited to avoid damaging
laser diodes.

Although not recommended, another approach would be to
use a potentiometer for R
the value of R

for each laser diode/photo diode combina-

GAIN

. This allows users to optimize

GAIN

tion’s monitor current. The drawback to this approach is that
potentiometer’s stray inductance and capacitance may cause the
transimpedance amplifier to overshoot and degrade its settling,
and the value of C

may not be optimized for the entire

GAIN

potentiometer’s range.

C

optimizes the response of the transimpedance amplifier

GAIN

and should be chosen as from the table below. Choosing C

GAIN

larger than the recommended value will slow the response of the
amplifier. Lower values improve TZA bandwidth but may cause
the amplifier to oscillate.

Table I.

Recommended

R

GAIN

C

GAIN

≥2.5 kΩ 2 pF

1.5 kΩ 3 pF

1 kΩ 4 pF

500 Ω 8 pF

The circuit in Figure 6 allows an adjustable gain with low vari­ance in bandwidth, but requires several external components.

R

INTERNAL

50Ω

C

EQ

R

EQ

V

I

MONITOR

SENSE

IN

1:2

AD9660

2I PIN

V

REF

R

INTERNAL

50Ω

MONITOR

EQUIVALENT

CIRCUIT

GAIN

POWER

V

REF

REF

R1

R2

REQ + 50Ω = (RF + 50Ω)

C1

R

F

R3

1.7kΩ

C

F

R2R1R1

(1+ + )

R

F

Choosing C

BIAS HOLD

Choosing values for the hold capacitors, C

and C

WRITE HOLD

WRITE

and C

HOLD

, is a
tradeoff between output current droop when the control loops
are open, and the time it takes to calibrate and recalibrate the
laser power when the loops are closed.

The amount of output current droop is determined by the value
of the hold capacitor and the leakage current at that node.
When either of the two control loops are open (WRITE CAL or
BIAS CAL logic LOW), the pin connections for the hold
capacitors (WRITE HOLD and BIAS HOLD) are high imped-

ance inputs. Leakage currents will range from ±200 nA; this

low current minimizes the droop in the output power level. As-

suming the worst case current of ±200 nA, the output current

will change as follows:

−9

±∆I

BIAS

±∆I

MODULATED

18 ×10

=

t

C

BIAS HOLD

18 ×10

=

BIAS HOLD

−9

t

WRITE HOLD

C

WRITE HOLD

To choose a value, the user will need to determine the amount
of time the loop will be in hold mode, t

WRITE HOLD

or t

BIAS HOLD

,
the maximum change in laser output power the application can
tolerate, and the laser efficiency (defined as the change in laser
output power to the change in laser diode current). As an ex-

ample, if an application requires 5 mW of laser power ±5%, and

the laser diode efficiency is 0.25 mW/mA, then

∆I

= 5 mW ×(5%) / 0.25

MAX






mW

mA



=1. 0 mA





If the same application had a hold time requirement of 250 µs,

then the minimum value of the hold capacitor would be:

−9

C

HOLD

18 ×10

=

×250 µs

1. 0 mA

= 4.5 nF

When determining the calibration time, the T/H and the exter­nal hold capacitor can be modeled using the simple RC circuit
illustrated in Figure 7.

WRITE LEVEL

OR BIAS LEVEL

POWER MONITOR

AD9660

T/H

TZA

R

WRITE HOLD
OR BIAS HOLD

C

HOLD

EXTERNAL HOLD
CAPACITOR

Figure 7. Circuit Model for Determining Calibration Times

REV. 0

Figure 6. Adjustable Gain Configuration

–7–

AD9660

100

Using this model, the voltage at the hold capacitor is

−t



V

C

HOLD

= V

t = 0

+(V

t =∞

− V

t = 0

)1−e







τ





where t0 is when the calibration begins (WRITE CAL or BIAS
CAL goes logic HIGH), V
t = 0, V

is the steady state voltage at the hold cap with the

t = ∞

loop closed, and τ = R

model the error in V
pared to V

t = ∞

C

HOLD

, can be estimated from the following table and

is the voltage on the hold cap at

t = 0

is the time constant. With this

C

HOLD

for a finite calibration time, as com-

chart:

Table II.

t

CALIBRATION

% Final Value Error %

7τ 99.9 0.09
6τ 99.7 0.25
5τ 99.2 0.79
4τ 98.1 1.83
3τ 95.0 4.97
2τ 86.5 13.5
τ 63.2 36.8

90

80

70

60

50

40

30

% FINAL VALUE – % of Volts

20

10

0

051

CALIBRATION TIME – Time Constants = ␶

24

3

Initial calibration is required after power-up or any other time
the laser has been disabled. Disabling the AD9660 drives the
hold capacitors back down to V

. In this case, or in any case

REF

where the output current is more than 10% out of calibration, R

will range from 300 Ω to 550 Ω for the model above; the higher

value should be used for calculating the worst case calibration
time. Following the example above, if C

were chosen as

HOLD

4.5 nF, then τ = RC = 550 Ω × 4.5 nF would be 2.5 µs. For an

initial calibration error <1%, the initial calibration time should

be >5τ = 12.4 µs.

Initial calibration time will actually be better than this calcula­tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660’s T/H decreases as the hold voltage approaches its
final value.

Recalibration is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (<10%), the

resistance for the model above will be in the range of 75 Ω to
140 Ω. Again, the higher value should be used to estimate the

worst case time needed for recalibration.

Continuing with the example above, since the error during hold
time was chosen as 5%, we meet the criteria for recalibration

and τ = RC = 140 Ω × 4.5 nF = 0.63 µs. To get a final error of

1% after recalibration, the 5% droop must be corrected to

within a 20% error (20% × 5% = 1%). A 2τ recalibration time
of 1.26 µs is sufficient.

Continuous Recalibration

In applications where the hold capacitor is small (<500 pF) and
the WRITE PULSE signals always have a pulse width >25 ns,
the user may continuously calibrate the write loop. In such an
application, the WRITE CAL signal should be held logic
HIGH, and the WRITE PULSE signal will control write loop
calibration via the internal AND gate.

The bias loop may be continuously recalibrated whenever
WRITE PULSE is logic LOW.

Figure 8. Calibration Time Curve

–8–

REV. 0

AD9660

DAC1

DAC2

V

DAC1

V

DAC2

OP291

OP291

+5V

V

REF + VDAC1

= V

BIAS LEVEL

R2
R1

V

REF + VDAC2

= V

WRITE LEVEL

R4
R3

BIAS LEVEL

V

REF

WRITE LEVEL

AD9660

R1

R2

R3

R4

R3

R4

R1

R2

Example Calculations

The example below (in addition to the one included in the sec­tions above) should guide users in choosing R

GAIN

, C

GAIN

, the

hold capacitor values, and worst case calibration times.

System Requirements:

• Bias laser power: 4 mW Bias ± 5%

• Write laser power: 25 mW ± 0.5%

• Bias Hold Time: 1 ms

• Write Hold Time: 1 µs

Laser diode/photo diode characteristics:

• Laser efficiency 0.5 mA/mA

• Monitor current: 5 µA/mA

• From the laser power requirements and efficiency we can

estimate:

∆I

BIAS MAX

= 4 mW ×(5%)/ 0.5






mW

mA



= 400. 0 µA





and

∆I

WRITE MAX

= 25 mW × 0.5%

(



/0.5

)





mW

mA



= 250 µA





• Choosing hold caps based on these:

−9

C

BIAS HOLD

18 ×10

=

×1 ms

400 µA

= 0.045 µF

and

−9

C

WRITE HOLD

18 ×10

=

250 µA

×1 µs

= 72 pF

• The bias loop initial calibration time for a <1% error:
5τ = 5 × RC = 5 × 550

Ω

× 0.045

µ

F = 123.75µs

• Bias loop recalibration for a 1% error after 5% droop (need to

correct within 20%):

2τ = 2 × RC = 2 × 140

Ω

× 0.045

µ

F = 12.6µs

• The write loop initial calibration time for <0.1% error:
7τ = 7 × RC = 7 × 550

Ω

× 72 pF = 277.2 ns

• Write loop re-calibration for a 0.1% error after 0.5% droop

(need to correct within 20%):

2τ = RC = 2 × 140

Ω

× 72 pF = 20.2 ns

• From the monitor current specification and the max power

specified:

I

MONITOR MAX

= 25 mW

5 µA

mW

=125 µA

and

1. 6 V

MONITOR MAX

−50 Ω=6.9 kΩ

• C

R

=

GAIN

GAIN

1. 85 × I

would be chosen as 2 pF (see Table I).

Driving the Analog Inputs

The BIAS LEVEL and WRITE LEVEL inputs of the AD9660
drive the track and hold amplifiers and allow the user to adjust
the amount of output current as described above. The input
voltage range on both inputs is V
the user to create an offset of V

REF

REF

to V

for a ground based signal.

+ 1.6 V, requiring

REF

The circuit in Figure 9 will perform the level shift and scale the
output of a DAC whose output is from ground to a positive
voltage. This solution is attractive because both the DAC and
the op amp can run off a single +5 V supply, and the op amp
doesn’t have to swing rail to rail.

Figure 9. Driving the Analog Inputs

REV. 0

–9–

AD9660

Offset Current Generator

The offset current source allows the user to inject a fixed,
uncalibrated current into the laser diode. The offset current
source is set by an external resistor connected between OFF­SET CURRENT SET and +V

, and is controlled by OFFSET

S

PULSE. See Figure 2 for a transfer function of the offset cur­rent source.

The offset current may be used to increase the output current
provided by the bias and/or write loops after calibration. Alter­natively, the offset current may be added during the calibration
of the bias loop and switched off after calibration to drop the
bias current below the knee of the laser diode power curve.
This is illustrated in Figure 10.

4

0°C CASE

3

2

OPTICAL OUTPUT – mW

1

0

CONSTANT WRITE POWER

BIAS CALIBRATION POWER

OPERATING
BIAS LEVEL

0 12020

1

WITH OFFSET CURRENT TURNED OFF,
BIAS CURRENT IS BELOW THE KNEE OF THE LASER DIODE

2

OFFSET CURRENT TURNED ON DURING BIAS-CAL

40 100

FORWARD CURRENT – mA

1

BIAS

60 80

BIAS

OFFSET

MOD

2

25°C

CASE

50°C CASE

Figure 10. Laser Diode Current-to-Optical Power Curve
Illustrating Bias Below Diode Knee

AD9660 Layout Considerations

As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as pos­sible, and isolated from digital signals to avoid coupling in noise.
In particular, digital lines should be isolated from OUTPUT,
PIN SENSE, WRITE LEVEL, and BIAS LEVEL traces. Digi­tal signal paths should also be kept short, and run lengths
matched to avoid propagation delay mismatch.

Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled

to the ground plane to reduce noise in the circuit. 0.1 µF sur-

face mount capacitors, placed as close as possible to the
AD9660 +V

connections meet this requirement. Multilayer

S

circuit boards allow designers to lay out signal traces without
interrupting the ground plane, and provide low impedance
power planes to further reduce noise.

Minimizing the Impedance of the Output Current Path

Because of the very high current slew that the AD9660 is
capable of producing (70+ mA in 1.5 ns), the inductance of the
output current path to and from the laser diode is critical. A
good layout of the output current path will yield high quality
light pulses with rise times of about 1.5 ns and less than 5%
overshoot. A poor layout can result in significant overshoot and
ringing. The most important guideline for the layout is to mini­mize the impedance (mostly inductance) of the output current
path to the laser. It is important to recognize that the laser cur­rent path is a closed loop. The figure illustrates the path that
current travels: (1) from the output pins of the AD9660 to the
anode of the laser, (2) through the laser to the cathode

(ground), (3) through the return path, (4) through the 0.1 µF

bypass capacitors back to the +V

pins of the AD9660 where (5)

S

the current travels through the output driver circuitry of the
AD9660, and back to the output pins. The inductance of this
loop can be minimized by placing the laser as close to the
AD9660 as possible to keep the loop short, and by placing the
send and return paths on adjacent layers of the PC board to take
advantage of mutual coupling of the path inductances. This
mutual coupling effect is the most important factor in reducing
inductance in the current path.

–10–

REV. 0

AD9660

The trace from the output pins of the AD9660 to the anode of
the laser (send trace) should be several millimeters wide and
should be as direct as possible. The return current will choose
the path of least resistance. If the return path is the ground
plane, it should have an unbroken path, under the output trace,
from the laser cathode back to the AD9660. If the return path is
not the ground plane (such as on a two layer board, or on the

plane), it should still be on the board plane adjacent to the

+V

S

plane of the output trace. If the current cannot return along a
path that follows the output trace, the inductance will be drasti­cally increased and performance will be degraded.

Optimizing the Feedback Layout

In applications where the dynamic performance of the analog
feedback loop is important, it is necessary to optimize the layout
of the gain resistor, R

, as well as the monitor current path to

GAIN

SENSE IN. Such applications include MOD systems which
recalibrate the write loop on pulses as short as 25 ns, and closed
loop applications.

PIN ASSIGNMENTS

PIN CONNECTIONS

+V

S

25

24

23

22

The best possible TZA settling will be achieved by using a
single carbon surface mount resistor (usually 5% tolerance) for

and small surface mount capacitor for C

R

GAIN

. Because the

GAIN

GAIN pin (Pin 9) is essentially connected to the inverting input
of the TZA, it is very sensitive to stray capacitance. R

GAIN

should be placed between Pin 9 and Pin 10, as close as possible
to Pin 9. Small traces should be used, and the ground and +V

S

planes adjacent to the trace should be removed to further mini­mize stray capacitance.

The trace from SENSE IN to the cathode of the PIN photo­detector should be thin and routed away from the laser anode
trace.

MUTUAL COUPLING

REDUCES INDUCTANCE

LASER DIODE CURRENT

PATH SEGMENTS

(SEE TEXT)

1

5

AD9660

OUTPUT PIN CONNECTIONS

CONNECTIONS

21

20

19

4

BYPASS CAPS

GROUND PIN

GROUND PLANE

Figure 11. Laser Diode Current Loop

3

2

REV. 0

–11–

AD9660

0.300 (7.60)

0.292 (7.40)

0.012 (0.30)

0.004 (0.10)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Pin Plastic SOIC

(R-28)

0.712 (18.08)

0.700 (17.78)

28 15

PIN 1

(1.27)

BSC

0.019 (0.48)

0.014 (0.36)

0.0500

0.419 (10.64)

141

SEATING
PLANE

0.393 (9.98)

0.104 (2.64)

0.093 (2.36)

0.013 (0.33)

0.009 (0.23)

C2040–6–7/95

0.04 (1.02)

0.024 (0.61)

–12–

PRINTED IN U.S.A.

REV. 0