Datasheet AD9653 Datasheet (ANALOG DEVICES)

Analog-to-Digital Converter

AD9653

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

AVDD PDWN DRVDD

SENSE

Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V

Data Sheet

FEATURES

1.8 V supply operation
Low power: 164 mW per channel at 125 MSPS
SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span)
SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span)
SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span)
Serial LVDS (ANSI-644, default) and low power, reduced

range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range (supports up to 2.6 V p-p)
Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Multichip sync and clock divider

Programmable output clock and data alignment

Standby mode

APPLICATIONS

Medical ultrasound and MRI
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment

GENERAL DESCRIPTION

The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital con­verter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.

The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such

FUNCTIONAL BLOCK DIAGRAM

VIN+A
VIN–A

VIN+B
VIN–B

RBIAS

VREF

AGND
VIN+C

VIN–C

VIN+D
VIN–D

VCM

PIPELINE

ADC

PIPELINE

ADC

REF

SELECT

PIPELINE

ADC

PIPELINE

ADC

SERIAL PORT

INTERFACE

CSB

SDIO/OLM

16

DIGITAL

SERIALIZER

16

DIGITAL

SERIALIZER

1V

AD9653

16

DIGITAL

SERIALIZER

16

DIGITAL

SERIALIZER

CLOCK

MANAGEMENT

CLK+

SYNC

SCLK/DTP

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

CLK–

Figure 1.

as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).

The AD9653 is available in a RoHS-compliant, 48-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.

D0+A
D0–A

D1+A
D1–A

D0+B
D0–B

D1+B
D1–B

FCO+
FCO–
D0+C
D0–C
D1+C
D1–C

D0+D
D0–D

D1+D
D1–D
DCO+
DCO–

10538-001

PRODUCT HIGHLIGHTS

1. Small Footprint.

Four ADCs are contained in a small, space-saving package.

2. Low power of 164 mW/channel at 125 MSPS with scalable

power options.

3. Pin compatible to the AD9253 14-bit quad and the AD9633

12-bit quad ADC.

4. Ease of Use.

A data clock output (DCO) operates at frequencies of up to
500 MHz and supports double data rate (DDR) operation.

5. User Flexibility.

The SPI control offers a wide range of flexible features to
meet specific system requirements.

responsi bility is as sumed by Anal og Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD9653 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications .......................................................................... 5

Digital Specifications ................................................................... 7

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution ................................................................................ 11

Pin Configuration and Function Descriptions ........................... 12

Typical Performance Characteristics ........................................... 14

V

= 1.0 V ................................................................................. 14

REF

V

= 1.3 V ................................................................................. 17

REF

Equivalent Circuits ......................................................................... 21

Theory of Operation ...................................................................... 22

Analog Input Considerations .................................................... 22

Voltage Reference ....................................................................... 23

Clock Input Considerations ...................................................... 25

Power Dissipation and Power-Down Mode ........................... 27

Digital Outputs and Timing ..................................................... 27

Output Test Modes ..................................................................... 30

Serial Port Interface (SPI) .............................................................. 31

Configuration Using the SPI ..................................................... 31

Hardware Interface ..................................................................... 32

Configuration Without the SPI ................................................ 32

SPI Accessible Features .............................................................. 32

Memory Map .................................................................................. 33

Reading the Memory Map Register Table ............................... 33

Memory Map Register Table ..................................................... 34

Memory Map Register Descriptions ........................................ 37

Applications Information .............................................................. 39

Design Guidelines ...................................................................... 39

Power and Ground Recommendations ................................... 39

Exposed Pad Thermal Heat Slug Recommendations ............ 39

VCM ............................................................................................. 39

Reference Decoupling ................................................................ 39

SPI Por t ........................................................................................ 39

Crosstalk Performance .............................................................. 39

Outline Dimensions ....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

5/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

Data Sheet AD9653

−

−

REF

REF

REF

AVDD

DRVDD

DRVDD

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; V

Table 1.

Parameter1 Temperature Min Typ Max Unit

RESOLUTION 16 Bits
ACCURACY

No Missing Codes Full Guaranteed

Offset Error Full −0.49 −0.3 0.17 % FSR

Offset Matching Full −0.14 +0.2 0.39 % FSR

Gain Error Full −12.3 −5 2.37 % FSR

Gain Matching Full 1.0 1.1 5.8 % FSR

Differential Nonlinearity (DNL) Full

25°C ±0.7 LSB

Integral Nonlinearity (INL) Full

25°C ±3.5
TEMPERATURE DRIFT

Offset Error Full 3.5 ppm/°C
INTERNAL VOLTAGE REFERENCE

Output Voltage (1.0 V Mode) Full 0.98 1.0 1.01 V

Load Regulation at 1.0 mA (V

= 1.0 V) Full 2 mV

Input Resistance 25°C 7.5 kΩ
INPUT-REFERRED NOISE

V

= 1.0 V 25°C 2.7 LSB rms

ANALOG INPUTS

Differential Input Voltage (V

= 1.0 V) Full 2 V p-p
Common-Mode Voltage Full 0.9 V
Common-Mode Range 25°C 0.5 1.3 V
Differential Input Resistance 25°C 2.6 kΩ
Differential Input Capacitance 25°C 7 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V

2

I

Full 305 330 mA

I

(ANSI-644 Mode)2 Full 60 64 mA

I

(Reduced Range Mode)2 25°C 45

TOTAL POWER CONSUMPTION

DC Input Full 607 649 mW
Sine Wave Input (Four Channels Including Output Drivers, ANSI-644 Mode) Full 657 708 mW
Sine Wave Input (Four Channels Including Output Drivers, Reduced Range Mode) 25°C 630 mW
Power-Down 25°C 2 mW
Standby3 Full 356 392 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured with a low input frequency, full-scale sine wave on all four channels.

3

Can be controlled via the SPI.

= 1.0 V, DCS off, unless otherwise noted.

REF

0.77

0.95 LSB

7.26

8.18 LSB
LSB

mA

Rev. 0 | Page 3 of 40

AD9653 Data Sheet

INTERNAL VOLTAGE REFERENCE

REF

REF

REF

AVDD

25°C 1.8 V

DRVDD

25°C 1.8 V

AVDD

2

DRVDD

DRVDD

AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; V

Table 2.

Parameter1 Temperature Min Ty p Max Unit

RESOLUTION 16 Bits
ACCURACY

No Missing Codes 25°C Guaranteed
Offset Error 25°C −0.3 % FSR
Offset Matching 25°C +0.2 % FSR
Gain Error 25°C −5 % FSR
Gain Matching 25°C 1.1 % FSR
Differential Nonlinearity (DNL) 25°C
Integral Nonlinearity (INL) 25°C

TEMPERATURE DRIFT

Offset Error 25°C 3.5 ppm/°C

Output Voltage (1.3 V Programmable Mode) 25°C 1.3 V
Load Regulation at 1.0 mA (V

= 1.3 V) 25°C 6.5 mV

Input Resistance 25°C 7.5 kΩ

INPUT-REFERRED NOISE

V

= 1.3 V 25°C 2.1 LSB rms

ANALOG INPUTS

Differential Input Voltage (V

= 1.3 V) 25°C 2.6 V p-p
Common-Mode Voltage 25°C 0.9 V
Common-Mode Range 25°C 0.6 1.3 V
Differential Input Resistance 25°C 2.6 kΩ
Differential Input Capacitance 25°C 7 pF

POWER SUPPLY

= 1.3 V; 0°C to 85°C, DCS off, unless otherwise noted.

REF

±0.8 LSB
±5.0 LSB

I

25°C 314 mA

I

(ANSI-644 Mode)2 25°C 60 mA

I

(Reduced Range Mode)2 25°C 45 mA

TOTAL POWER CONSUMPTION

DC Input 25°C 614 mW
Sine Wave Input (Four Channels Including Output Drivers, ANSI-644 Mode) 25°C 673 mW
Sine Wave Input (Four Channels Including Output Drivers, Reduced Range Mode) 25°C 646 mW
Power-Down 25°C 2 mW
Standby3 25°C 371 mW

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured with a low input frequency, full-scale sine wave on all four channels.

3

Can be controlled via the SPI.

Rev. 0 | Page 4 of 40

Data Sheet AD9653

fIN = 128 MHz

25°C 73.9 dBFS

fIN = 200 MHz

25°C 71.5 dBFS

fIN = 70 MHz

Full

12.1

12.4 Bits

fIN = 128 MHz

25°C 11.9 Bits

fIN = 70 MHz

Full

−78

−89 dBc

IN1

IN2

87

AVDD

25°C 31 dB

ANALOG INPUT BANDWIDTH, FULL POWER

25°C 650 MHz

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; V

Table 3.

Parameter1 Temperature Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 78 dBFS
fIN = 15 MHz 25°C 77.8 dBFS
fIN = 70 MHz Full 75.5 76.5 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)

fIN = 9.7 MHz 25°C 78 dBFS
fIN = 15 MHz 25°C 77.7 dBFS
fIN = 70 MHz Full 74.6 76.1 dBFS
fIN = 128 MHz 25°C 73.6 dBFS
fIN = 200 MHz 25°C 70.3 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 12.7 Bits
fIN = 15 MHz 25°C 12.6 Bits

= 1.0 V, DCS off, unless otherwise noted.

REF

fIN = 200 MHz 25°C 11.4 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 96 dBc
fIN = 15 MHz 25°C 93 dBc
fIN = 70 MHz Full 78 89 dBc
fIN = 128 MHz 25°C 87 dBc
fIN = 200 MHz 25°C 77 dBc

WORST HARMONIC (SECOND OR THIRD)

fIN = 9.7 MHz 25°C −98 dBc
fIN = 15 MHz 25°C −93 dBc

fIN = 128 MHz 25°C −87 dBc
fIN = 200 MHz 25°C −77 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 9.7 MHz 25°C −96 dBc
fIN = 15 MHz 25°C −98
fIN = 70 MHz Full −85 −94 dBc
fIN = 128 MHz 25°C −89 dBc
fIN = 200 MHz 25°C −83 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS

f

= 70.5 MHz, f
CROSSTALK2 25°C
CROSSTALK (OVERRANGE CONDITION)3 25°C

= 72.5 MHz 25°C −90 dBc

91

dB
dB

POWER SUPPLY REJECTION RATIO (PSRR)4

dBc

DRVDD 25°C 79 dB

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.

3

Overrange condition is defined as the input being 3 dB above full scale.

4

PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the

amplitudes of the spur voltage over the pin voltage, expressed in decibels.

Rev. 0 | Page 5 of 40

AD9653 Data Sheet

IN1

IN2

AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; V
noted.

Table 4.

Parameter1 Temperature Min Ty p Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 80 dBFS
fIN = 15 MHz 25°C 79.4 dBFS
fIN = 70 MHz 25°C 77.5 dBFS
fIN = 128 MHz 25°C 74.4 dBFS
fIN = 200 MHz 25°C 71.7 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)

fIN = 9.7 MHz 25°C 79.8 dBFS
fIN = 15 MHz 25°C 79.2 dBFS
fIN = 70 MHz 25°C 76.1 dBFS
fIN = 128 MHz 25°C 74 dBFS
fIN = 200 MHz 25°C 69.9 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 13 Bits
fIN = 15 MHz 25°C 12.9 Bits
fIN = 70 MHz 25°C 12.3 Bits
fIN = 128 MHz 25°C 12 Bits
fIN = 200 MHz 25°C 11.3 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz 25°C 94 dBc
fIN = 15 MHz 25°C 94 dBc
fIN = 70 MHz 25°C 82 dBc
fIN = 128 MHz 25°C 86 dBc
fIN = 200 MHz 25°C 75 dBc

WORST HARMONIC (SECOND OR THIRD)

fIN = 9.7 MHz 25°C −94 dBc
fIN = 15 MHz 25°C −94 dBc
fIN = 70 MHz 25°C −82 dBc
fIN = 128 MHz 25°C −87 dBc
fIN = 200 MHz 25°C −75 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 9.7 MHz 25°C −100 dBc
fIN = 15 MHz 25°C −99 dBc
fIN = 70 MHz 25°C −96 dBc
fIN = 128 MHz 25°C −86 dBc
fIN = 200 MHz 25°C −84 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS

f

= 70.5 MHz, f

= 72.5 MHz 25°C −90 dBc
CROSSTALK2 25°C 91 dB
CROSSTALK (OVERRANGE CONDITION)3 25°C 87 dB
POWER SUPPLY REJECTION RATIO (PSRR)4

AVDD 25°C 31 dB
DRVDD 25°C 79 dB

ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.

3

Overrange condition is defined as the input being 3 dB above full scale.

4

PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the

amplitudes of the spur voltage over the pin voltage, expressed in decibels.

= 1.3 V; 0 °C to 85°C, DCS off, unless otherwise

REF

Rev. 0 | Page 6 of 40

Data Sheet AD9653

Logic 1 Voltage

Full

1.2 AVDD + 0.2

V

Logic 0 Voltage

Full 0

0.8

V

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.

Table 5.

Parameter1 Temp Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) 25°C 15 kΩ
Input Capacitance 25°C 4 pF

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 2 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 AVDD + 0.2 V

Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 5 pF

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA) Full 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 V

DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644

Logic Compliance LVDS
Differential Output Voltage (VOD) Full 290 345 400 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement

DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER,

REDUCED SIGNAL OPTION
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 160 200 230 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO/OLM pins sharing the same connection.

Rev. 0 | Page 7 of 40

AD9653 Data Sheet

1, 2

Fall Time (tF) (20% to 80%)

Full 300 ps

FCO

CPD

FCO

SAMPLE

DAT A

SAMPLE

SAMPLE

SAMPLE

FRAME

SAMPLE

SAMPLE

SAMPLE

DATA -MAX

DATA -MIN

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.

Table 6.

Parameter

CLOCK3

Input Clock Rate Full 20 1000 MHz
Conversion Rate Full 20 125 MSPS
Clock Pulse Width High (tEH) Full 4.00 ns
Clock Pulse Width Low (tEL) Full 4.00 ns

OUTPUT PARAMETERS3

Propagation Delay (tPD) Full 2.3 ns
Rise Time (tR) (20% to 80%) Full 300 ps

Temp Min Ty p Max Unit

FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t

) Full 1.5 2.3 3.1 ns

)4 Full t

)4 Full (t

) 4 Full (t

/16) − 300 (t
/16) − 300 (t

+ (t

/16) ns
/16) (t
/16) (t

/16) + 300 ps

/16) + 300 ps
Lane Delay (tLD) 90 ps
Data to Data Skew (t

− t

) Full ±50 ±200 ps
Wake-Up Time (Standby) 25°C 250 ns
Wake-Up Time (Power-Down)5 25°C 375 μs
Pipeline Latency Full 16

APERTURE

Aperture Delay (tA) 25°C 1 ns
Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms
Out-of-Range Recovery Time 25°C 1

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

4

t

/16 is based on the number of bits in two LVDS data lanes. t

SAMPLE

5

Wake-up time is defined as the time required to return to normal operation from power-down mode.

SAMPLE

= 1/fS.

Clock cycles

Clock cycles

Rev. 0 | Page 8 of 40

Data Sheet AD9653

SSYNC

HSYNC

CLK

HIGH

LOW

D0–A

D0+A
D1–A

D1+A

FCO–

BYTEWISE

MODE

FCO+

D0–A

D0+A
D1–A

D1+A

FCO–

DCO

DCO+

CLK+

VIN±x

CLK–

DCO–

FCO+

BITWISE

MODE

SDR

DDR

10538-002

MSB

N – 17

D14

N – 17

D13

N – 17

D12

N – 17

D11

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

D12

N – 16

D11

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 17

D06

N – 17

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

D07

N – 16

D06

N – 16

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

MSB

N – 17

D13

N – 17

D11

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

MSB

N – 16

D13

N – 16

D11

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

D14

N – 17

D12

N – 17

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

D14

N – 16

D12

N – 16

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

t

A

t

DATA

t

LD

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N

N + 1

TIMING SPECIFICATIONS

Table 7.

Parameter Description Limit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK+ setup time 0.24 ns typ

t

SYNC to rising edge of CLK+ hold time 0.40 ns typ

SPI TIMING REQUIREMENTS See Figure 75

tDS Setup time between the data and the rising edge of SCLK 2 ns min
tDH Hold time between the data and the rising edge of SCLK 2 ns min
t

Period of the SCLK 40 ns min
tS Setup time between CSB and SCLK 2 ns min
tH Hold time between CSB and SCLK 2 ns min
t

SCLK pulse width high 10 ns min

t

SCLK pulse width low 10 ns min

t

Time required for the SDIO pin to switch from an input to an output relative to the

EN_SDIO

10 ns min

SCLK falling edge (not shown in Figure 75)

t

Time required for the SDIO pin to switch from an output to an input relative to the

DIS_SDIO

10 ns min

SCLK rising edge (not shown in Figure 75)

Timing Diagrams

Refer to the Memory Map Register Descriptions section and Table 23 for SPI register settings.

Unit

Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)

Rev. 0 | Page 9 of 40

AD9653 Data Sheet

D0–A

D0+A

D1–A

D1+A

FCO–

BYTEWISE

MODE

FCO+

D0–A

D0+A

D1–A

D1+A

FCO–

DCO

DCO+

CLK+

VIN±x

CLK–

DCO–

FCO+

BITWISE

MODE

SDR

DDR

MSB

N – 17

D14

N – 17

D13

N – 17

D12

N – 17

D11

N – 17

D10

N – 17

D09

N – 17

D08

N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

D12

N – 16

D11

N – 16

D10

N – 16

D09

N – 16

D08

N – 16

D07

N – 17

D06

N – 17

D05

N – 17

D04

N – 17

D03

N – 17

D02

N – 17

D01

N – 17

LSB

N – 17

D07

N – 16

D06

N – 16

D05

N – 16

D04

N – 16

D03

N – 16

D02

N – 16

D01

N – 16

LSB

N – 16

MSB

N – 17

D13

N – 17

D11

N – 17

D09

N – 17

D07

N – 17

D05

N – 17

D03

N – 17

D01

N – 17

MSB

N – 16

D13

N – 16

D11

N – 16

D09

N – 16

D07

N – 16

D05

N – 16

D03

N – 16

D01

N – 16

D14

N – 17

D12

N – 17

D10

N – 17

D08

N – 17

D06

N – 17

D04

N – 17

D02

N – 17

LSB

N – 17

D14

N – 16

D12

N – 16

D10

N – 16

D08

N – 16

D06

N – 16

D04

N – 16

D02

N – 16

LSB

N – 16

t

A

t

DATA

t

LD

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N + 1

N

10538-003

D0–x

D0+x

FCO–

DCO+

CLK+

VIN±x

CLK–

DCO–

FCO+

D14

N – 17

MSB

N – 17

D13

N – 17

D12

N – 17

D11

N – 17

D10

N – 17D9N – 17D8N – 17D7N – 17D6N – 17D5N – 17D4N – 17D3N – 17D2N – 17D1N – 17

LSB

N – 17

MSB

N – 16

D14

N – 16

D13

N – 16

t

A

t

DATA

t

EH

t

FCO

t

FRAME

t

PD

t

CPD

t

EL

N – 1

N

10538-004

SYNC

CLK+

t

HSYNC

t

SSYNC

10538-005

Figure 3. 16-Bit DDR/SDR, Two-Lane, 2× Frame Mode

Figure 4. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode

Figure 5. SYNC Input Timing Requirements

Rev. 0 | Page 10 of 40

Data Sheet AD9653

AVDD to AGND

−0.3 V to +2.0 V

CLK+, CLK− to AGND

−0.3 V to +2.0 V

REF

REF

JA

JB θJC

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating
Electrical

DRVDD to AGND −0.3 V to +2.0 V
Digital Outputs

−0.3 V to +2.0 V
(D0±x, D1±x, DCO+, DCO−, FCO+,
FCO−) to AGND

VIN+x, VIN−x to AGND −0.3 V to +2.0 V
SCLK/DTP, SDIO/OLM, CSB to AGND −0.3 V to +2.0 V
SYNC, PDWN to AGND −0.3 V to +2.0 V
RBIAS to AGND −0.3 V to +2.0 V
VREF, SENSE to AGND −0.3 V to +2.0 V

Environmental

Operating Temperature

Range (Ambient, V

Operating Temperature

Range (Ambient, V

Maximum Junction

= 1.0 V)

= 1.3 V)

−40°C to +85°C

0°C to 85°C

150°C

Temperature

Lead Temperature

300°C

(Soldering, 10 sec)

Storage Temperature

−65°C to +150°C
Range (Ambient)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

Table 9. Thermal Resistance

Air Flow

Package Type

Velocity
(m/sec)

θ

1

θ

Unit

48-Lead LFCSP 0.0 23.7 7.8 7.1 °C/W

7 mm × 7 mm 1.0 20.0 N/A N/A °C/W
(CP-48-13) 2.5 18.7 N/A N/A °C/W

1

θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

ESD CAUTION

Rev. 0 | Page 11 of 40

AD9653 Data Sheet

21, 22

D1−B, D1+B

Channel B Digital Outputs.

35

VIN−A

ADC A Analog Input Complement.

36 VIN+A

ADC A Analog Input True.

SENSE

D

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN+C
48

1

VIN+D

2

VIN–D

3

AVDD

4

AVDD

5

CLK–

6

CLK+

7

AVDD

8

RVDD

9

D1–D

10

D1+D

11

D0–D

12

D0+D

13

D1–C

PACKAGE PROV IDES THE ANALOG GROUND FOR THE PART.
THIS EXP OSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OP E RATION.

VIN–C

AVDD

AVDD

SYNC

47

46

45

44

AD9653

TOP VIEW

(Not to S cale)

17

16

14

15

D0–C

D0+C

D1+C

DCO–

VCM
43

18

DCO+

Figure 6. 48-Lead LFCSP Pin Configuration, Top View

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND,

Exposed Pad
1
2

VIN+D ADC D Analog Input True.

VIN−D ADC D Analog Input Complement.

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This exposed pad must be connected to ground for proper operation.

3, 4, 7, 34, 39, 45, 46 AVDD 1.8 V Analog Supply Pins.
5, 6
8, 29
9, 10

CLK−, CLK+ Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

DRVDD Digital Output Driver Supply.

D1−D, D1+D Channel D Digital Outputs.
11, 12 D0−D, D0+D Channel D Digital Outputs.
13, 14
15, 16
17, 18
19, 20

D1−C, D1+C Channel C Digital Outputs.

D0−C, D0+C Channel C Digital Outputs.

DCO−, DCO+ Data Clock Outputs.

FCO−, FCO+ Frame Clock Outputs.

VREF
42

19

FCO–

41

20

FCO+

AVDD

RBIAS

39

40

22

21

D1–B

D1+B

VIN+B

VIN–B

37

38

24

23

D0–B

D0+B

36

VIN+A
VIN–A

35

AVDD

34

PDWN

33
32

CSB
SDIO/OLM

31

SCLK/DTP

30

DRVDD

29
28

D0+A
D0–A

27

D1+A

26
25

D1–A

10538-006

23, 24

D0−B, D0+B Channel B Digital Outputs.
25, 26 D1−A, D1+A Channel A Digital Outputs.
27, 28 D0−A, D0+A Channel A Digital Outputs.
30
31
32
33

37
38 VIN−B ADC B Analog Input Complement.
40
41
42
43

SCLK/DTP SPI Clock Input/Digital Test Pattern.

SDIO/OLM SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.

CSB SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.

PDWN Digital Input, 30 kΩ Internal Pull-Down.

VIN+B ADC B Analog Input True.

RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

SENSE Reference Mode Selection.

VREF Voltage Reference Input and Output.

VCM Analog Input Common-Mode Voltage.

PDWN high = power-down device.
PDWN low = run device, normal operation.

Rev. 0 | Page 12 of 40

Data Sheet AD9653

Pin No. Mnemonic Description

44
47
48

SYNC Digital Input. SYNC input to clock divider.
VIN−C ADC C Analog Input Complement.
VIN+C ADC C Analog Input True.

Rev. 0 | Page 13 of 40

AD9653 Data Sheet

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

+

2

3

4

5

6

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

125MSPS

9.7MHz AT –1d BFS

SNR = 77.1dB (78.1dBFS)

SFDR = 96.8d Bc

10538-007

+

2

3

4

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12 186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

125MSPS

15MHZ AT –1dBFS

SNR = 76.8dB (77.8dBFS)

SFDR = 95.2d Bc

5

6

10538-008

0

AMPLITUDE (dBFS)

10538-009

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

+

2

3

4

5

6

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

125MSPS
70MHz AT –1dBF S
SNR = 75.6dB (76.6dBFS)
SFDR = 85.5d Bc

10538-010

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

+

2

3

4

5

6

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

125MSPS

128MHz AT –1dBF S

SNR = 73.2dB (74.2dBFS)

SFDR = 86.6d Bc

10538-011

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

+

2

3

4

5

6

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

125MSPS

200.5MHz AT –1d BFS
SNR = 70.7dB (71.7dBFS)
SFDR = 76.6d Bc

10538-012

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 1.0 V

REF

Figure 7. Single-Tone 16k FFT with fIN = 9.7 MHz,

f

= 125 MSPS, V

SAMPLE

Figure 8. Single-Tone 16k FFT with fIN = 15 MHZ,

f

= 125 MSPS, V

SAMPLE

–15

–30

–45

–60

–75

2

–90

–105

–120

–135

Figure 9. Single-Tone 16k FFT with fIN = 64 MHz, f

4

6

0 12 186 24 30 36 42 48 6054

= 1.0 V

REF

= 1.0 V

REF

125MSPS
64MHz AT –1dBF S
SNR = 75.7dB (76.7dBFS)
SFDR = 87.2d Bc

FREQUENCY (MHz)

V

= 1.0 V

REF

Figure 10. Single-Tone 16k FFT with fIN = 70 MHz,

f

= 125 MSPS, V

SAMPLE

= 1.0 V

REF

Figure 11. Single-Tone 16k FFT with fIN = 128 MHz,

f

= 125 MSPS, V

SAMPLE

3

5

+

= 125 MSPS,

SAMPLE

Figure 12. Single-Tone 16k FFT with fIN = 200.5 MHz at f

V

REF

= 1.0 V

= 1.0 V

REF

= 125 MSPS,

SAMPLE

Rev. 0 | Page 14 of 40

Data Sheet AD9653

–20

0

20

40

60

80

100

120

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0

SNR/SFDR (dBFS/dBc)

INPUT AMPLITUDE (dBFS)

10538-013

SFDRFS

SNRFS

SFDR

SNR

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

F2 – F1

F1 + F2

+

2F2 + F1

2F1 + F2

F2 – F1

2F1 – F2

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

10538-014

IMD3 (dBc)

–120

–100

–80

–60

–40

–20

0

–90 –70 –50 –30 –10

SFDR/IMD3(dBc/dBFS)

INPUT AMPLITUDE (dBFS)

IMD3 (dBFS)

SFDR (dBFS)

SFDR (dBc)

10538-015

0

20

40

60

80

100

120

0 20 40 60 80 100 120 140 160 180 200

SNR/SFDR (dBFS/dBc)

INPUT FRE QUENCY (MHz)

SNR (dBFS)

SFDR (dBc)

10538-016

70

75

80

85

90

95

100

–40 –20 0 20 40 60 80

SNR/SFDR(dBFS/dBc)

TEMPERATURE (C)

SFDR (dBc)

SNR (dBFS)

10538-017

INL (LSB)

OUTPUT CODE

Figure 13. SNR/SFDR vs. Input Amplitude (AIN), fIN = 9.7 MHz,

f

= 125 MSPS, V

SAMPLE

Figure 14. Two-Tone 16k FFT with f

f

= 125 MSPS, V

SAMPLE

= 1.0 V

REF

= 70.5 MHz and f

IN1

= 1.0 V

REF

IN2

= 72.5 MHz,

Figure 16. SNR/SFDR vs. fIN, f

Figure 17. SNR/SFDR vs. Temperature, fIN = 9.7 MHz,

f

SAMPLE

4.5

3.0

= 125 MSPS, Clock Divider = 8, V

SAMPLE

= 125 MSPS, V

= 1.0 V

REF

= 1.0 V

REF

Figure 15. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

f

= 70.5 MHz and f

IN1

= 72.5 MHz, f

IN2

= 125 MSPS, V

SAMPLE

1.5

0

–1.5

–3.0

–4.5

0

6000

12000

18000

24000

30000

36000

42000

48000

54000

= 1.0 V

REF

Figure 18. INL, fIN = 9.7 MHz, f

= 125 MSPS, V

SAMPLE

= 1.0 V

REF

60000

10538-018

Rev. 0 | Page 15 of 40

AD9653 Data Sheet

0

DNL (LSB)

OUTPUT CODE

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.8

0.6

6000

12000

18000

24000

30000

36000

42000

48000

54000

60000

10538-019

0

20000

40000

60000

80000

100000

120000

140000

160000

N – 12

N – 11

N – 10

N – 9

N – 8

N – 7

N – 6

N – 5

N – 4

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

NUMBER OF HI TS

CODE

10538-020

2.7 LSB RMS

0

10

20

30

40

50

60

70

80

90

100

1 10 70

PSRR (dB)

FREQUENCY (MHz)

DRVDD

AVDD

10538-021

0

20

40

60

80

100

20 40 60 80 100 120

SNR/SFDR (dBFS/dBc)

SAMPLE RATE (MSPS)

10538-022

SFDR (dBc)

SNR (dBFS)

0

20

40

60

80

100

20 40 60 80 100 120

SNR/SFDR (dBFS/dBc)

SAMPLE RATE (MSPS)

10538-023

SNR (dBFS)

SFDR (dBc)

Figure 19. DNL, fIN = 9.7 MHz, f

SAMPLE

Figure 20. Input-Referred Noise Histogram, f

= 125 MSPS, V

= 125 MSPS, V

SAMPLE

= 1.0 V

REF

= 1.0 V

REF

Figure 22. SNR/SFDR vs. Sample Rate, fIN = 9.7 MHz, V

= 1.0 V

REF

Figure 23. SNR/SFDR vs. Sample Rate, fIN = 64 MHz, Clock Divider = 4, V

1.0 V

=

REF

Figure 21. PSRR vs. Frequency, f

SAMPLE

= 125 MSPS, V

REF

= 1.0 V

Rev. 0 | Page 16 of 40

Data Sheet AD9653

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

+

2

3

4

5

6

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

125MSPS

9.7MHz AT –1d BFS
SNR = 79.1dB (80.1dBFS)
SFDR = 93.5d Bc

10538-024

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

+

2

3

4

5

6

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

125MSPS
15MHz AT –1dBF S
SNR = 78.3dB (79.3dBFS)
SFDR = 94.5d Bc

10538-025

0

AMPLITUDE (dBFS)

0

AMPLITUDE (dBFS)

0

AMPLITUDE (dBFS)

0

AMPLITUDE (dBFS)

FREQUENCY (MHz)

V

= 1.3 V

REF

125MSPS

–15

70MHz AT –1dBF S
SNR = 76.7dB (77.7dBFS)

–30

SFDR = 82.1d Bc

–45

–60

Figure 24. Single-Tone 16k FFT with fIN = 9.7 MHz,

f

= 125 MSPS, V

SAMPLE

= 1.3 V

REF

–75

–90

–105

–120

–135

0 12

2

+

5

186 24 30 36 42 48 6054

FREQUENCY (MHz)

Figure 27. Single-Tone 16k FFT with fIN = 70 MHz,

f

= 125 MSPS, V

SAMPLE

3

4

REF

6

10538-027

= 1.3 V

Figure 25. Single-Tone 16k FFT with fIN = 15 MHZ,

f

SAMPLE

125MSPS

–15

64MHz AT –1dBF S
SNR = 76.9dB (77.9dBFS)

–30

SFDR = 82.6d Bc

–45

–60

–75

2

–90

–105

–120

–135

4

6

0 12

Figure 26. Single-Tone 16k FFT with fIN = 64 MHz,

f

SAMPLE

= 125 MSPS, V

186 24 30 36 42 48 6054

FREQUENCY (MHz)

= 125 MSPS, V

= 1.3 V

REF

= 1.3 V

REF

–15

–30

–45

–60

–75

–90

–105

–120

–135

125MSPS
128MHz AT –1dBF S
SNR = 73.5dB (74.5dBFS)
SFDR = 86.7d Bc

2

3

0 12

5

6

4

186 24 30 36 42 48 6054

FREQUENCY (MHz)

+

10538-028

Figure 28. Single-Tone 16k FFT with fIN = 128 MHz,

f

= 125 MSPS, V

SAMPLE

–15

–30

–45

–60

3

+

5

10538-026

–75

–90

–105

–120

–135

125MSPS

200.5MHz AT –1d BFS
SNR = 71.1dB (72.1dBFS)
SFDR = 73.7d Bc

5

0 12

3

2

186 24 30 36 42 48 6054

= 1.3 V

REF

+

6

4

10538-029

Figure 29. Single-Tone 16k FFT with fIN = 200.5 MHz,

f

= 125 MSPS, V

SAMPLE

= 1.3 V

REF

Rev. 0 | Page 17 of 40

AD9653 Data Sheet

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

8

+

2

3

1240 16 20 24 28 32 36 40

AMPLITUDE (dBFS)

FREQUENCY (MHz)

80MSPS
15MHz AT –1dBF S
SNR = 79.0dB (80.0dBFS)
SFDR = 90.5d Bc

10538-030

6

4

5

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

8

+

2

3

1240 16 20 24 28 32 36 40

AMPLITUDE (dBFS)

FREQUENCY (MHz)

80MSPS
15MHz AT –1dBF S
SNR = 76.7dB (77.7dBFS)
SFDR = 82.1d Bc

10538-031

6

4

5

120

SNR/SFDR (dBFS/dBc)

10538-032

0

–30

–60

–15

–45

–75

–90

–105

–120

–135

0 12

F2 – F1

F1 + F2

+

2F2 + F1

2F1 + F2

2F2 – F1

2F1 – F2

186 24 30 36 42 48 6054

AMPLITUDE (dBFS)

FREQUENCY (MHz)

10538-033

IMD3 (dBc)

–120

–100

–80

–60

–40

–20

0

–90 –70 –50 –30 –10

SFDR/IM D3 ( dBc/dBFS)

INPUT AMPLITUDE (dBFS)

IMD3 (dBFS)

SFDR (dBFS)

SFDR (dBc)

10538-034

0

10

20

30

40

50

60

70

80

90

100

0 20 40 60 80 100 120 140 160 180 200

SNR/SFDR (dBFS/dBc)

INPUT FRE QUENCY (MHz)

SFDR (dBc)

SNR (dBFS)

10538-035

Figure 30. Single-Tone 16k FFT with fIN = 15 MHz,

f

= 80 MSPS, V

SAMPLE

= 1.3 V

REF

Figure 31. Single-Tone 16k FFT with fIN = 64.5 MHz,

f

100

= 80 MSPS, V

SAMPLE

SFDRFS

80

60

40

SNRFS

SFDR

= 1.3 V

REF

Figure 33. Two-Tone 16k FFT with f

f

= 125 MSPS, V

SAMPLE

= 70.5 MHz and f

IN1

= 1.3 V

REF

= 72.5 MHz,

IN2

Figure 34. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

f

= 70.5 MHz and f

IN1

= 72.5 MHz, f

IN2

= 125 MSPS, V

SAMPLE

REF

= 1.3 V

20

0

–20

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0

Figure 32. SNR/SFDR vs. Input Amplitude (AIN), fIN = 9.7 MHz,

SNR

INPUT AMPLITUDE (dBFS)

f

= 125 MSPS, V

SAMPLE

= 1.3 V

REF

Figure 35. SNR/SFDR vs. fIN, f

= 125 MSPS, Clock Divider = 8, V

SAMPLE

= 1.3 V

REF

Rev. 0 | Page 18 of 40

Data Sheet AD9653

SNR (dBFS)

SFDR (dBc)

78

80

82

84

86

88

90

92

94

0 20 40 60 80

SNR/SFDR (dBFS/dBc)

TEMPERATURE (°C)

10538-036

0

INL (LSB)

OUTPUT CODE

–4.5

–3.0

–1.5

0

1.5

3.0

4.5

6000

12000

18000

24000

30000

36000

42000

48000

54000

60000

10538-037

DNL (LSB)

0

20000

40000

60000

80000

100000

120000

140000

160000

180000

200000

N – 9

N – 8

N – 7

N – 6

N – 5

N – 4

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

NUMBER OF HI TS

CODE

10538-039

2.1 LSB RMS

0

10

20

30

40

50

60

70

80

90

100

1 10 70

PSRR (dB)

FREQUENCY (MHz)

DRVDD

AVDD

10538-040

0

20

40

60

80

100

20 40 60 80 100 120

SNR/SFDR (dBFS/dBc)

SAMPLE RATE (MSPS)

SFDR (dBc)

SNR (dBFS)

10538-041

Figure 36. SNR/SFDR vs. Temperature, fIN = 9.7 MHz,

f

= 125 MSPS, V

SAMPLE

Figure 37. INL, fIN = 9.7 MHz, f

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

0

6000

Figure 38. DNL, fIN = 9.7 MHz, f

12000

18000

24000
OUTPUT CODE

REF

= 125 MSPS, V

SAMPLE

30000

36000

= 125 MSPS, V

SAMPLE

= 1.3 V

42000

48000

REF

REF

= 1.3 V

54000

= 1.3 V

60000

10538-038

Rev. 0 | Page 19 of 40

Figure 39. Input-Referred Noise Histogram, f

Figure 40. PSRR vs. Frequency, f

SAMPLE

= 125 MSPS, V

SAMPLE

Figure 41. SNR/SFDR vs. Sample Rate, fIN = 9.7 MHz, V

= 125 MSPS, V

= 1.3 V

REF

= 1.3 V

REF

= 1.3 V

REF

AD9653 Data Sheet

0

20

40

60

80

100

20 40 60 80 100 120

SNR/SFDR (dBFS/dBc)

SAMPLE RATE (MSPS)

SNR (dBFS)

SFDR (dBc)

10538-042

Figure 42. SNR/SFDR vs . Sample Rate, fIN = 64 MHz, Clock Divider = 4, V

= 1.3 V

REF

Rev. 0 | Page 20 of 40

Data Sheet AD9653

AVDD

VIN±x

10538-043

CLK+

CLK–

10538-044

31kΩ

SDIO/OLM

400Ω

AVDD

10538-045

DRVDD

D0–x, D1–x D0+x, D1+ x

V

V

V

V

10538-046

350Ω

AVDD

30kΩ

SCLK/DTP, SYNC,

AND PDWN

10538-047

RBIAS

AND VCM

375Ω

AVDD

10538-048

CSB

350Ω

AVDD

30kΩ

10538-049

VREF

AVDD

7.5kΩ

375Ω

10538-050

EQUIVALENT CIRCUITS

Figure 43. Equivalent Analog Input Circuit

AVDD

10Ω

15kΩ

0.9V

AVDD

15kΩ

10Ω

Figure 44. Equivalent Clock Input Circuit

Figure 47. Equivalent SCLK/DTP, SY NC, and PDWN Input Circuit

Figure 48. Equivalent RBIAS and VCM Circuit

Figure 45. Equivalent SDIO/OLM Input Circuit

Figure 46. Equivalent Digital Output Circuit

Figure 49. Equivalent CS Input Circuit

Figure 50. Equivalent VREF Circuit

Rev. 0 | Page 21 of 40

AD9653 Data Sheet

S S

H

C

PAR

C

SAMPLE

C

SAMPLE

C

PAR

VIN–x

H

S S

H

VIN+x

H

10538-051

20

30

40

50

60

70

80

90

100

110

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

SNR/SFDR (dBFS/dBc)

COMMON-MODE VOLTAGE (V)

SFDR (dBc)

SNRFS (dBFS)

10538-052

THEORY OF OPERATION

The AD9653 is a multistage, pipelined ADC. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stage. The quantized outputs from each stage are
combined into a final 16-bit result in the digital correction
logic. The serializer transmits this converted data in a 16-bit
output. The pipelined architecture permits the first stage to
operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9653 is a differential switched­capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.

the output stage of the driving source. In addition, low Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a differential capacitor or
two single-ended capacitors can be placed on the inputs to
provide a matching passive network. This ultimately creates a
low-pass filter at the input to limit unwanted broadband noise.
See the AN-742 Application Note, the AN-827 Application Note,
and the Analog Dialogue article “Transformer-Coupled Front-

End for Wideband A/D Converters” (Volume 39, April 2005) for

more information. In general, the precise values depend on the
application.

Input Common Mode

The analog inputs of the AD9653 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that V

= AVDD /2 is

CM

recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 52 and Figure 53.

An on-chip, common-mode voltage reference is included in the
design and is available from the VCM pin. The VCM pin must
be bypassed to ground by a 0.1 µF capacitor, as described in the
Applications Information section.

Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the

AD9653, the input span is dependent on the reference voltage

(see Table 11).

Figure 51. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 51). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from

Figure 52. SNR/SFDR vs. Common-Mode Voltage,

f

= 9.7 MHz, f

IN

= 125 MSPS, V

SAMPLE

= 1.0 V

REF

Rev. 0 | Page 22 of 40

Data Sheet AD9653










+×=

R1

R2

V

REF

15.0

REF

REF

20

30

40

50

60

70

80

90

100

110

0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

SNR/SFDR (dBFS/dBc)

COMMON-MODE VOLTAGE (V)

SFDR (dBc)

SNRFS (dBFS)

10538-053

VREF

SENSE

0.5V

AD9653

SELECT

LOGIC

0.1µF1.0µF

VIN–A

VIN+A

ADC

CORE

10538-054

VREF

SENSE

R1

R2

0.5V

AD9653

SELECT

LOGIC

0.1µF1.0µF

VIN–A

VIN+A

ADC

CORE

10538-055

+

Internal Reference Connection

A comparator within the AD9653 detects the potential at the
SENSE pin and configures the reference into one of three
possible modes, which are summarized in Table 11. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 54), setting the voltage at the

Figure 53. SNR/SFDR vs. Common-Mode Voltage,

f

= 9.7 MHz, f

IN

= 125 MSPS, V

SAMPLE

= 1.3 V

REF

Differential Input Configurations

There are several ways to drive the AD9653 either actively or
passively. However, optimum performance is achieved by driving
the analog inputs differentially. Using a differential double balun
configuration to drive the AD9653 provides excellent performance
and a flexible interface to the ADC (see Figure 56) for baseband
applications.

For applications where SNR is a key parameter, differential trans­former coupling is the recommended input configuration (see
Figure 57), because the noise performance of most amplifiers is
not adequate to achieve the true performance of the AD9653.

Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.

It is not recommended to drive the AD9653 inputs single-ended.

VREF pin, V
resistor divider (see Figure 55), V

where:

7 kΩ ≤ (R1 + R2) ≤ 10 kΩ

, to 1.0 V. If SENSE is connected to an external

REF

is defined as

REF

Figure 54. 1.0 V Internal Reference Configuration

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9653.
VREF can be configured using either the internal 1.0 V refer­ence, an externally applied 1.0 V to 1.3 V reference voltage, or
using an external resistor divider applied to the internal refer­ence to produce a reference voltage of the user’s choice. The
various reference modes are summarized in the Internal Reference
Connection section and the External Reference Operation
section. The VREF pin should be externally bypassed to ground
with a low ESR, 1.0 μF capacitor in parallel with a low ESR,

0.1 μF ceramic capacitor.

Table 11. Reference Configuration Summary

Selected Mode SENSE Voltage (V) Resulting V

Fixed Internal Reference AGND to 0.2 1.0 internal 2.0
Programmable Internal Reference Tie to external R-divider

Fixed External Reference AVDD 1.0 to 1.3 applied to external VREF pin1 2.0 to 2.6

1

Normal operation for V

= 1.3 V is supported over the 0°C to 85°C temperature range.

REF

(see Figure 55)

Figure 55. Programmable Internal Reference Configuration

(V)

0.5 × (1 + R2/R1), example: R1 = 3.5 kΩ,
R2 = 5.6 kΩ for V

Rev. 0 | Page 23 of 40

= 1.3 V1

Resulting Differential Span
(V p-p)

2 × V

REF

AD9653 Data Sheet

ADC

R0.1µF

0.1µF

2V p-p

VCM

C

*C1

*C1

C

R

0.1µF

0.1µF 0.1µF

33Ω

200Ω

33Ω

33Ω

33Ω

VIN+x

VIN–x

ET1-1-I3

C

C

5pF

R

*C1 IS OPT IONAL

10538-056

2Vp-p

R

R

*C1

*C1 IS OPT IONAL

49.9Ω

0.1μF

ADT1-1WT

1:1 Z RATIO

VIN–x

ADC

VIN+x

*C1

C

VCM

33Ω

33Ω

200Ω

0.1µF

5pF

10538-057

0
–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

0 3.02.52.01.51.00.5

V

REF

ERROR (%)

LOAD CURRENT ( mA)

INTERNAL V

REF

= 1.0V

10538-058

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

0 3.02.52.01.51.00.5

V

REF

ERROR (%)

LOAD CURRENT ( mA)

INTERNAL V

REF

= 1.3V

10538-059

Figure 56. Differential Double Balun Input Configuration for Baseband Applications

Figure 57. Differential Transformer-Coupled Configuration

for Baseband Applications

If the internal reference of the AD9653 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 58 and
Figure 59 show how the internal reference voltage is affected by
loading.

Figure 58. V

= 1.0 V Error vs. Load Current

REF

Figure 59. V

=1.3 V Error vs. Load Current

REF

External Reference Operation

The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac­teristics. Figure 60 and Figure 61 show the typical drift characteris­tics of the internal reference in 1.0 V mode and programmable

1.3 V mode, respectively.

Rev. 0 | Page 24 of 40

Data Sheet AD9653

4

–8

–40 85

V

REF

ERROR (mV)

TEMPERATURE (°C)

–6

–4

–2

0

2

–15 10 35 60

10538-060

–15

–10

–5

0

5

10

–40 –20 0 20 40 60 80

V

REF

ERROR (mV)

TEMPERATURE (°C)

10538-061

0.1µF

0.1µF

0.1µF0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits

®

ADT1-1WT, 1:1 Z

XFMR

10538-062

0.1µF

0.1µF0.1µF

CLOCK

INPUT

0.1µF

50Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

10538-063

100Ω

0.1µF

0.1µF

0.1µF

0.1µF

240Ω240Ω

50kΩ 50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD951x

PECL DRIVER

10538-064

The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom­mended for clock frequencies from 20 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9653 to
approximately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9653 while
preserving the fast rise and fall times of the signal that are critical
to achieving low jitter performance. However, the diode capaci­tance comes into play at frequencies above 500 MHz. Care must be
taken in choosing the appropriate signal limiting diode.

Figure 60. Typical V

Figure 61. Typical V

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 50). The internal buffer generates the
positive and negative full-scale references for the ADC core.

It is not recommended to leave the SENSE pin floating.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9653 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 44) and require no external bias.

Clock Input Options

The AD9653 has a flexible clock input structure. The clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regard­less of the type of signal being used, clock source jitter is of the
most concern, as described in the Jitter Considerations section.

Figure 62 and Figure 63 show two preferred methods for clock­ing the AD9653 (at clock rates up to 1 GHz prior to internal clock
divider). A low jitter clock source is converted from a single­ended signal to a differential signal using either an RF transformer
or an RF balun.

= 1.0 V Drift

REF

= 1.3 V Drift

REF

Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz)

Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz)

If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 64. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 65. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 66).

Figure 64. Differential PECL Sample Cl ock (Up to 1 GHz)

Rev. 0 | Page 25 of 40

AD9653 Data Sheet















××

J

A

tf

π

2

1

100Ω

0.1µF

0.1µF

0.1µF

0.1µF

50kΩ 50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

10538-065

OPTIONAL

100Ω

0.1µF

0.1µF

0.1µF

50Ω

1

1

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

V

CC

1kΩ

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

10538-066

84

70

40 60555045

SNR (dBFS)

DUTY CYCLE ( %)

10538-076

72

74

76

78

80

82

SNRFS (DCS O FF)

SNRFS (DCS O N)

84

70

40 60555045

SNR (dBFS)

DUTY CYCLE ( %)

10538-077

72

74

76

78

80

82

SNRFS (DCS O FF)

SNRFS (DCS O N)

Figure 65. Differential LVDS Sample Cl ock (Up to 1 GHz)

Figure 66. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9653 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.

The AD9653 clock divider can be synchronized using the
external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a vari­ety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.

The AD9653 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This feature minimizes
performance degradation in cases where the clock input duty
cycle deviates from 50% greater than the specified ±5%. Noise and
distortion performance are nearly flat for a wider range of duty
cycles with the DCS on, as shown in Figure 67 and Figure 68.

Figure 67. SNR vs. DCS On/Off, V

= 1.0 V

REF

Figure 68. SNR vs. DCS On/Off, V

= 1.3 V

REF

Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f

) due only to aperture jitter (tJ) can be calculated by

A

SNR Degradation = 20 log

10

In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 69).

The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9653.
Power supplies for clock drivers should be separated from the

Rev. 0 | Page 26 of 40

Data Sheet AD9653

ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

130

RMS CLOCK JITTER RE Q U I REMENT

120

110

100

90

80

SNR (dB)

70

10 BITS

60

8 BITS

50

40

30

1 10 100 1000

ANALOG INPUT FREQUENC Y (MHz)

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

16 BITS

14 BITS

12 BITS

10538-067

Figure 69. Ideal SNR vs. Input Frequency and Jitter

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 70, the power dissipated by the AD9653 is
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.

0.60

0.55

0.50

0.45

0.40

0.35

V

=1.3V

REF

=1.0V

V

REF

Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times. When
using the SPI port interface, the user can place the ADC in
power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details on using these features.

DIGITAL OUTPUTS AND TIMING

The AD9653 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.

When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.

The AD9653 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 71. Figure 72 shows
the LVDS output timing example in reduced range mode.

0.30

ANALOG C ORE POWER (W)

0.25

0.20

20 40 60 80 100 120

Figure 70. Analog Core Power vs. f

SAMPLE RATE (MSPS)

for fIN = 9.7 MHz, Four Channels

SAMPLE

10538-068

The AD9653 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 2 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the AD9653 to its normal operating
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.

Rev. 0 | Page 27 of 40

D0 500mV/DIV
D1 500mV/DIV
DCO 500mV/DIV
FCO 500mV/DIV

4ns/DIV

10538-069

Figure 71. LVDS Output Timing Example in ANSI-644 Mode (Default)

AD9653 Data Sheet

500

EYE: ALL BITS ULS: 8000/414024

400
300
200
100

0
–100
–200
–300

EYE DIAGRAM VOLTAGE (mV)

–400
–500

D0 400mV/DIV
D1 400mV/DIV
DCO 400mV/DIV
FCO 400mV/DIV

4ns/DIV

10538-070

Figure 72. LVDS Output Timing Example in Reduced Range Mode

An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histo­gram with trace lengths less than 24 inches on standard FR-4
material is shown in Figure 73.

500

EYE: ALL BITS

400
300
200
100

0
–100
–200
–300

EYE DIAGRAM VOLTAGE (mV)

–400
–500

–0.8ns –0.4ns 0ns 0.4ns 0.8ns

7k

6k

5k

4k

3k

2k

TIE JITTER HISTOGRAM (Hits)

1k

0

200ps 250ps 300ps 350ps 400ps 450ps 500ps

Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End

Termination Only

ULS: 7000/400354

Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End

Figure 74 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Notice that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
It is the user’s responsibility to determine if the waveforms
meet the timing budget of the design when the trace lengths
exceed 24 inches. Additional SPI options allow the user to further
increase the internal termination (increasing the current) of all
four outputs to drive longer trace lengths. This can be achieved
by programming Register 0x15. Even though this produces
sharper rise and fall times on the data edges and is less prone to
bit errors, the power dissipation of the DRVDD supply increases
when this option is used.

The format of the output data is twos complement by default.
An example of the output coding format can be found in Table 12.
To change the output data format to offset binary, see the

10538-071

Memory Map section.

Data from each ADC is serialized and provided on a separate
channel in two lanes in DDR mode. The data rate for each serial
stream is equal to 16 bits times the sample clock rate, with a
maximum of 500 Mbps/lane [(16 bits × 125 MSPS)/(2 × 2) =
500 Mbps/lane]. The lowest typical conversion rate is 20 MSPS.
See the Memory Map section for details on enabling this feature.

–0.8ns –0.4ns 0ns 0.4ns –0.8ns

12k

10k

8k

6k

4k

TIE JITTER HISTOGRAM (Hits)

2k

0k

–800ps –600ps –400ps –200ps 0ps 200ps 400 ps 600ps

Termination Only

10538-072

Rev. 0 | Page 28 of 40

Data Sheet AD9653

0001

Midscale short

1000 0000 0000 0000 (16-bit)

N/A

Yes

Offset binary
1010

1× sync

0000 0001 1111 1100 (16-bit)

N/A

No

Two output clocks are provided to assist in capturing data from
the AD9653. The DCO is used to clock the output data and is
equal to four times the sample clock (CLK) rate for the default
mode of operation. Data is clocked out of the AD9653 and must
be captured on the rising and falling edges of the DCO that
supports double data rate (DDR) capturing. The FCO is used to
signal the start of a new output byte and is equal to the sample
clock rate in 1× frame mode. See the Timing Diagrams section
for more information.

When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.

Table 12. Digital Output Coding

Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode

VIN+ − VIN− <−VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000
VIN+ − VIN− −VREF 0000 0000 0000 0000 1000 0000 0000 0000
VIN+ − VIN− 0 V 1000 0000 0000 0000 0000 0000 0000 0000
VIN+ − VIN− +VREF − 1.0 LSB 1111 1111 1111 1111 0111 1111 1111 1111
VIN+ − VIN− >+VREF − 0.5 LSB 1111 1111 1111 1111 0111 1111 1111 1111

In default mode, as shown in Figure 2, the MSB is first in the
data output serial stream. This can be inverted so that the LSB
is first in the data output serial stream by using the SPI.

There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Tab l e 13 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns do not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses.

Table 13. Flexible Output Test Modes

Output Test
Mode Bit
Sequence Pattern Name Digital Output Word 1 Digital Output Word 2

0000 Off (default) N/A N/A N/A

0010 +Full-scale short 0000 0000 0000 0000 (16-bit) N/A Yes Offset binary

0011 −Full-scale short 0000 0000 0000 0000 (16-bit) N/A Yes Offset binary

0100 Checkerboard 1010 1010 1010 1010 (16-bit) 0101 0101 0101 0100 (16-bit) No
0101 PN sequence long N/A N/A Yes PN23

0110 PN sequence short N/A N/A Yes PN9

0111 One-/zero-word

toggle
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 1000 (16-bit) N/A No

1011 One bit high 1000 0000 0000 0000 (16-bit) N/A No Pattern

1100 Mixed frequency 1010 0001 1001 1100 (16-bit) N/A No

111 1111 1111 1100 (16-bit) 0000 0000 0000 0000 (16-bit) No

Subject to
Data Format
Select Notes

code shown

code shown

code shown

ITU 0.150

23

X

+ X18 + 1

ITU 0.150

9

X

+ X5 + 1

associated with
the external pin

Rev. 0 | Page 29 of 40

AD9653 Data Sheet

The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2

9

− 1 or 511 bits. A descrip­tion of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value
is all 1s (see Table 14 for the initial values). The output is a
parallel representation of the serial PN9 sequence in MSB-first
format. The first output word is the first 14 bits of the PN9
sequence in MSB aligned form.

The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2

23

− 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Table 14 for the initial values) and the

AD9653 inverts the bit stream with relation to the ITU standard.

The output is a parallel representation of the serial PN23 sequence
in MSB-first format. The first output word is the first 14 bits of the
PN23 sequence in MSB aligned form

Table 14. PN Sequence

Sequence

PN Sequence Short 0x1FE0 0x1DF1, 0x3CC8, 0x294E
PN Sequence Long 0x1FFF 0x1FE0, 0x2001, 0x1C00

Initial
Value

First Three Output Samples
(MSB First) Twos Complement

Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.

SDIO/OLM Pin

For applications that do not require SPI mode operation, the
CSB pin is tied to AVDD, and the SDIO/OLM pin controls the
output lane mode according to Table 15.

Note that, when the CSB pin is tied to AVDD, the AD9653 DCS
is on by default and remains on unless the part is placed in SPI
mode and controlled via the SPI. Refer to the Clock Duty Cycle
section for more information on the DCS.

For applications where the SDIO/OLM pin is not used, CSB
should be tied to AVDD. When using the one-lane mode, the
conversion rate should be ≤62.5 MSPS to meet the maximum
output rate of 1 Gbps.

Table 15. Output Lane Mode Pin Settings

OLM Pin
Voltage Output Mode

AVDD (Default) Two-lane. 1× frame, 16-bit serial output
GND One-lane. 1× frame, 16-bit serial output

SCLK/DTP Pin

The SCLK/DTP pin is used to select the digital test pattern
(DTP) for applications that do not require SPI mode operation.
This pin can enable a single digital test pattern if it and the CSB
pin are held high during device power-up. When SCLK/DTP is
tied to AVDD, the ADC channel outputs shift out the following
pattern: 1000 0000 0000 0000. The FCO and DCO function
normally while all channels shift out the repeatable test pattern.
This pattern allows the user to perform timing alignment
adjustments among the FCO, DCO, and output data. This pin has
an internal 10 kΩ resistor to GND. It can be left unconnected.

Table 16. Digital Test Pattern Pin Settings

Selected DTP DTP Voltage

Normal Operation 10 kΩ to AGND Normal operation
DTP AVDD 1000 0000 0000 0000

Resulting
D0±x and D1±x

Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.

CSB Pin

The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored.

Note that, when the CSB pin is tied to AVDD, the AD9653 DCS
is on by default and remains on unless the part is placed in SPI
mode and controlled via the SPI. Refer to the Clock Duty Cycle
section for more information on the DCS.

RBIAS Pin

To set the internal core bias current of the ADC, place a

10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin.

OUTPUT TEST MODES

The output test options are described in Tab l e 13 and controlled by
the output test mode bits at Address 0x0D. When an output test
mode is enabled, the analog section of the ADC is disconnected
from the digital back-end blocks and the test pattern is run
through the output formatting block. Some of the test patterns
are subject to output formatting, and some are not. The PN
generators from the PN sequence tests can be reset by setting
Bit 4 or Bit 5 of Register 0x0D. These tests can be performed
with or without an analog signal (if present, the analog signal is
ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.

Rev. 0 | Page 30 of 40

Data Sheet AD9653

SERIAL PORT INTERFACE (SPI)

The AD9653 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
offers the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are docu­mented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 17). The SCLK (a serial clock) is
used to synchronize the read and write data presented from and
to the ADC. The SDIO (serial data input/output) is a dual­purpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The CSB (chip select bar)
is an active low control that enables or disables the read and
write cycles.

Table 17. Serial Port Interface Pins

Pin Function

SCLK

Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.

SDIO

Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.

CSB

Chip select bar. An active low control that gates the read
and write cycles.

The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 75
and Table 7.

Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.

In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.

All data is composed of 8-bit words. Data can be sent in MSB­first mode or in LSB-first mode. MSB-first mode is the default
on power-up and can be changed via the SPI port configuration
register. For more information about this and other features,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.

CSB

SCLK

SDIO

DON’T CARE

t

t

DS

t

S

R/W W1 W0 A12 A11 A10 A9 A8 A7

t

DH

HIGH

t

LOW

Figure 75. Serial Port Interface Timing Diagram

t

CLK

Rev. 0 | Page 31 of 40

D5 D4 D3 D2 D1 D0

t

H

DON’T CARE

DON’T CAREDON’T CARE

10538-073

AD9653 Data Sheet

Power Mode

Allows the user to set either power-down mode

HARDWARE INTERFACE

The pins described in Ta ble 17 comprise the physical interface
between the user programming device and the serial port of the

AD9653. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.

The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.

The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9653 to prevent these signals from transi­tioning at the converter inputs during critical sampling periods.

Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Table 15 and Table 16 describe the strappable
functions supported on the AD9653.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,
the SDIO/OLM pin, the SCLK/DTP pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
pins as static control lines for the output lane mode, digital test

pattern, and power-down feature control. In this mode, CSB
should be connected to AVDD, which disables the serial port
interface.

Note that, when the CSB pin is tied to AVDD, the AD9653 DCS
is on by default and remains on unless the part is placed in SPI
mode and controlled via the SPI. Refer to the Clock Duty Cycle
section for more information on the DCS.

When the device is in SPI mode, the PDWN pin (if enabled)
remains active. For SPI control of power-down, the PDWN pin
should be set to its default state.

SPI ACCESSIBLE FEATURES

Table 18 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9653 part-specific features are described in detail
following Tabl e 19, the external memory map register table.

Table 18. Features Accessible Using the SPI

Feature Name Description

or standby mode

Clock Allows the user to set the clock divider, set the

clock divider phase, and enable the sync

Offset Allows the user to digitally adjust the

converter offset

Test I/O Allows the user to set test modes to have

known data on output bits
Output Mode Allows the user to set the output mode
Output Phase Allows the user to set the output clock polarity

Rev. 0 | Page 32 of 40

Data Sheet AD9653

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the chip
configuration registers (Address 0x00 to Address 0x02); the device
index and transfer registers (Address 0x05 and Address 0xFF);
and the global ADC functions registers, including setup, control,
and test (Address 0x08 to Address 0x109).

The memory map register table (see Tab l e 19) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x05, the device
index register, has a hexadecimal default value of 0x3F. This
means that in Address 0x05, Bits[7:6] = 0, and the remaining
Bits[5:0] = 1. This setting is the default channel index setting.
The default value results in both ADC channels receiving the
next write command. For more information on this function
and others, see the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI. This application note details the functions
controlled by Register 0x00 to Register 0xFF. The remaining
registers are documented in the Memory Map Register
Descriptions section.

Open Locations

All address and bit locations that are not included in Table 19
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open or not listed in Table 19 (for example, Address 0x13), this
address location should not be written.

Default Values

After the AD9653 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Tabl e 19.

Logic Levels

An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

• “Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel-Specific Registers

Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated
for each channel. These registers and bits are designated in
Table 19 as local. These local registers and bits can be accessed
by setting the appropriate data channel bits (A, B, C, or D) and
the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in
Register 0x05. If all the bits are set, the subsequent write affects
the registers of all channels and the DCO/FCO clock channels.
In a read cycle, only one of the channels (A, B, C, or D) should
be set to read one of the four registers. If all the bits are set
during a SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in Table 19 affect the
entire part or the channel features for which independent
settings are not allowed between channels. The settings in
Register 0x05 do not affect the global registers and bits.

Rev. 0 | Page 33 of 40

AD9653 Data Sheet

MEMORY MAP REGISTER TABLE

The AD9653 uses a 3-wire interface and 16-bit addressing and,
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high,

Table 19.

ADDR
(Hex) Parameter Name

Chip Configuration Registers
0x00

0x01 Chip ID (global) 8-bit chip ID, Bits[7:0]

0x02

Device Index and Transfer Registers
0x05 Device index Open Open

0xFF Transfer Open Open Open Open Open Open Open

Global ADC Function Registers
0x08

0x09 Clock (global) Open Open Open Open Open Open Open

SPI port
configuration

Chip grade
(global)

Power modes
(global)

Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

0 =
SDO
active

Open Speed grade ID[6:4]

Open Open

LSB first

Soft
reset

AD9653 0xB5 = quad, 16-bit, 125 MSPS serial LVDS

110 = 125 MSPS

Clock
Channel
DCO

External
power­down
pin
function
0 = full
power­down
1 =
standby

1 =
16-bit
address

Clock
Channel
FCO

Open Open Open Power mode

the SPI enters a soft reset, where all of the user registers revert
to their default values and Bit 2 is automatically cleared.

Default
Bit 0
(LSB)

1 =
16-bit
address

Open Open Open Open

Data
Channel
D

Soft
reset

Data
Channel
C

LSB first

Data
Channel
B

01 = full power-

0 = SDO
active

Data
Channel
A

Initiate
override

00 = chip run

down

10 = standby

11 = reset

Duty
cycle
stabilize
0 = on
1 = off

Value

(Hex) Comments

0x18

0xB5

0x3F

0x00

0x00

0x01

The nibbles
are mirrored
so that LSB­first or MSB­first mode
registers
correctly. The
default for
ADCs is 16-bit
mode.

Unique chip
ID used to
differentiate
devices; read
only.

Unique
speed grade
ID used to
differentiate
graded
devices; read
only.

Bits are set to
determine
which device
on chip
receives the
next write
command.
The default is
all devices on
chip.

Set sample
rate override.

Determines
various
generic
modes of chip
operation.

Turns duty
cycle stabilizer
on or off.

Rev. 0 | Page 34 of 40

Data Sheet AD9653

Test mode (local

Reset

Reset PN

Output test mode[3:0] (local)

When set, the

0x15

Output adjust

Open

Open

Output driver

Open

Open

Open

Output

0x00

Determines

Default
ADDR
(Hex)

0x0B Clock divide

0x0C

0x0D

0x10

0x14 Output mode Open

Parameter Name

(global)

Enhancement
control

except for PN
sequence resets)

Offset adjust
(local)

Bit 7
(MSB)

Open Open Open Open Open

Open Open Open Open Open

User input test mode

10 = single once

11 = alternate once

(affects user input test

Bits[3:0] = 1000)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Chop
mode
0 = off

1 = on

00 = single

01 = alternate

mode only,

Offset adjust in LSBs from +127 to −128 (twos complement format)

LVDS-ANSI/
LVDS-IEEE
option
0 = LVDS­ANSI
1 = LVDS­IEEE
reduced
range link
(global)
see
Table 20

PN long
gen

8-bit device offset adjustment [7:0] (local)

Open Open Open

short
gen

0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = one/zero word toggle

1000 = user input

1001 = 1-/0-bit toggle

1011 = one bit high

1100 = mixed bit frequency

Output
invert

(local)

Clock divide ratio[2:0]

000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8

Open Open 0x00

1010 = 1× sync

Open

Bit 0
(LSB)

Output
format
0 =
offset
binary
1 =
twos
comple­ment
(global)

Value

(Hex)

0x00

0x00

0x00

0x01

Comments

Enables/
disables chop
mode.

test data is
placed on the
output pins in
place of
normal data.

Device offset
trim.

Configures
the outputs
and the
format of the
data.

0x16 Output phase Open Input clock phase adjust[6:4]

termination[1:0]

00 = none
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω

(value is number of input clock

cycles of phase delay)

see Table 21

Rev. 0 | Page 35 of 40

Output clock phase adjust[3:0]

(0000 through 1011)

see Table 22

drive
0 = 1×
drive
1 = 2×
drive

0x03

LVDS or other
output
properties.

On devices
that use
global clock
divide,
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal
latching is
unaffected.

AD9653 Data Sheet

USER_PATT2_MSB

User Defined

SDIO

Disables SDIO

Default
ADDR
(Hex)

0x18 V

Parameter Name

Open Open Open Open Open V

REF

Bit 7
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

adjustment

REF

digital scheme[2:0]

000 = 1.0 V p-p (1.3 V p-p)
001 = 1.14 V p-p (1.48 V p-p)
010 = 1.33 V p-p (1.73 V p-p)

011 = 1.6 V p-p (2.08 V p-p)

100 = 2.0 V p-p (2.6 V p-p)

0x19

USER_PATT1_LSB

B7 B6 B5 B4 B3 B2 B1 B0 0x00

(global)

0x1A

USER_PATT1_MSB

B15 B14 B13 B12 B11 B10 B9 B8 0x00

(global)

0x1B

USER_PATT2_LSB

B7 B6 B5 B4 B3 B2 B1 B0 0x00

(global)

0x1C

B15 B14 B13 B12 B11 B10 B9 B8 0x00

(global)

0x21

Serial output data
control (global)

LVDS
output
LSB
first

SDR/DDR one-lane/two-lane,

bitwise/bytewise[6:4]

000 = SDR two-lane, bitwise

001 = SDR two-lane, bytewise

Open

Select
2×
frame

number of bits

010 = DDR two-lane, bitwise

011 = DDR two-lane, bytewise

100 = DDR one-lane, wordwise

0x22

Serial channel
status (local)

Open Open Open Open Open Open

Channel
output
reset

0x100

Sample rate
override

Open

Sample
rate
override
enable

0 0 Open Sample rate

000 = 20 MSPS
001 = 40 MSPS
010 = 50 MSPS
011 = 65 MSPS

100 = 80 MSPS
101 = 105 MSPS
110 = 125 MSPS

0x101 User I/O Control 2 Open Open Open Open Open Open Open

0x102 User I/O Control 3 Open Open Open Open

VCM

Open Open Open 0x00 VCM control.
power­down

0x109 Sync Open Open Open Open Open Open

Sync
next
only

Bit 0
(LSB)

Serial output

00 = 16 bits

Channel
power­down

pull­down

Enable
sync

Value
(Hex)

0x04

0x30

0x00

0x00

0x00

0x00

Comments

Selects
internal V
Values shown
are for V

1.0 V (1.3 V).

.

REF

=

REF

User Defined
Pattern 1 LSB.

User Defined
Pattern 1 MSB.

User Defined
Pattern 2 LSB.

Pattern 2 MSB.
Serial stream

control.
Default causes
MSB first and
the native bit
stream.

Used to
power down
individual
sections of a
converter.

Sample rate
override
(requires
transfer
register, 0xFF).

pull-down.

Rev. 0 | Page 36 of 40

Data Sheet AD9653

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.

Device Index (Register 0x05)

There are certain features in the map that can be set inde­pendently for each channel, whereas other features apply
globally to all channels (depending on context) regardless of
which are selected. The first four bits in Register 0x05 can be
used to select which individual data channels are affected. The
output clock channels can be selected in Register 0x05 as well.
A smaller subset of the independent feature list can be applied
to those devices.

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment
they are written. Setting Bit 0 of this transfer register high
initializes the settings in the sample rate override register
(Address 0x100).

Power Modes (Register 0x08)

Bits[7:6]—Open

Bit 5—External Power-Down Pin Function

If set, the external PDWN pin initiates standby mode. If cleared,
the external PDWN pin initiates power-down mode.

Bits[4:2]—Open

Bits[1:0]—Power Mode

In normal operation (Bits[1:0] = 00), all ADC channels are
active.

In power-down mode (Bits[1:0] = 01), the digital datapath clocks
are disabled while the digital datapath is reset. Outputs are
disabled.

In standby mode (Bits[1:0] = 10), the digital datapath clocks
and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), all the digital datapath
clocks and the outputs (where applicable) on the chip are reset,
except the SPI port. Note that the SPI is always left under
control of the user; that is, it is never automatically disabled or
in reset (except by power-on reset).

Clock (Register 0x09)

Bits[7:1]—Open

Bit 0—Duty Cycle Stabilize.

The default state is Bit 0 = 1, duty cycle stabilizer off.

Note that, when the part is not in SPI mode, the duty cycle
stabilizer is on. Refer to the Configuration Without the SPI
section for more information.

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct conversion
receivers, chopping in the first stage of the AD9653 is a feature
that can be enabled by setting Bit 2. In the frequency domain,
chopping translates offsets and other low frequency noise to
f

/2 where it can be filtered.

CLK

Bits[1:0]—Open

Output Mode (Register 0x14)

Bit 7—Open

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting this bit chooses LVDS-IEEE (reduced range) option.
The default setting is LVDS-ANSI. As described in Table 20,
when LVDS-ANSI or LVDS-IEEE reduced range link is selected,
the user can select the driver termination. The driver current
is automatically selected to give the proper output swing.

Table 20. LVDS-ANSI/LVDS-IEEE Options

Output
Mode,
Bit 6

0 LVDS-ANSI User

1 LVDS-IEEE

Output
Mode

reduced
range link

Output
Driver
Termination

selectable

User
selectable

Output Driver
Current

Automatically
selected to give
proper swing

Automatically
selected to give
proper swing

Bits[5:3]—Open

Bit 2—Output Invert

Setting this bit inverts the output bit stream.

Bit 1—Open

Bit 0—Output Format

By default, this bit is set to send the data output in twos
complement format. Resetting this bit changes the output mode
to offset binary.

Output Adjust (Register 0x15)

Bits[7:6]—Open

Bits[5:4]—Output Driver Termination

These bits allow the user to select the internal termination
resistor.

Bits[3:1]—Open

Bit 0—Output Drive

Bit 0 of the output adjust register controls the drive strength on
the LVDS driver of the FCO and DCO outputs only. The default
values set the drive to 1× while the drive can be increased to 2×
by setting the appropriate channel bit in Register 0x05 and then
setting Bit 0. These features cannot be used with the output
driver termination select. The termination selection takes
precedence over the 2× driver strength on FCO and DCO when
both the output driver termination and output drive are selected.

Rev. 0 | Page 37 of 40

AD9653 Data Sheet

Output Clock (DCO),

DCO Phase Adjustment (Degrees

0100

240

0101

300

0x34

16-bit

2×

DDR two-lane, bytewise

4 × fS

Figure 3

0x04

16-bit

2×

SDR two-lane, bitwise

8 × fS

Figure 3

Output Phase (Register 0x16)

Bit 7—Open

Bits[6:4]—Input Clock Phase Adjust

Table 21. Input Clock Phase Adjust Options

Input Clock Phase
Adjust, Bits[6:4]

000 (Default) 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7

Number of Input Clock Cycles of
Phase Delay

Bits[3:0]—Output Clock Phase Adjust

Table 22. Output Clock Phase Adjust Options

Phase Adjust, Bits[3:0]

0000 0
0001 60
0010 120
0011 (Default) 180

Relative to D0±x/D1±x Edge)

Serial Output Data Control (Register 0x21)

The serial output data control register is used to program the

AD9653 in various output data modes depending upon the data

capture solution. Tabl e 23 describes the various serialization
options available in the AD9653.

Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the sample
rate. Settings in this register are not initialized until Bit 0 of the
transfer register (Register 0xFF) is written high.

User I/O Control 2 (Register 0x101)

Bits[7:1]—Open

Bit 0—SDIO Pull-Down

Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bits[7:4]—Open

Bit 3—VCM Power-Down

Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.

Bits[2:0]—Open

0110 360
0111 420
1000 480
1001 540
1010 600
1011 660

Table 23. SPI Register Options

Serialization Options Selected
Register 0x21

Contents

0x30 16-bit 1× DDR two-lane, bytewise 4 × fS Figure 2 (default setting)
0x20 16-bit 1× DDR two-lane, bitwise 4 × fS Figure 2
0x10 16-bit 1× SDR two-lane, bytewise 8 × fS Figure 2
0x00 16-bit 1× SDR two-lane, bitwise 8 × fS Figure 2

0x24 16-bit 2× DDR two-lane, bitwise 4 × fS Figure 3
0x14 16-bit 2× SDR two-lane, bytewise 8 × fS Figure 3

0x40 16-bit 1× DDR one-lane, wordwise 8 × fS Figure 4

Serial Output Number
of Bits (SONB) Frame Mode Serial Data Mode DCO Multiplier Timing Diagram

Rev. 0 | Page 38 of 40

Data Sheet AD9653

SILKSCREEN PARTITION

PIN 1 INDICATOR

10538-074

GROUNDED
FILLED VIAS
FOR ADDED
CROSSTALK
ISOLATION

VIN
CHANNEL B

VIN
CHANNEL C

VIN
CHANNEL A

VIN
CHANNEL D

PIN 1

10538-075

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9653 as a system,
it is recommended that the designer become familiar with these
guidelines, which describes the special circuit connections and
layout requirements that are needed for certain pins.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9653, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9653. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance
is easily achieved.

EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS

It is required that the exposed pad on the underside of the ADC
be connected to analog ground (AGND) to achieve the best
electrical and thermal performance of the AD9653. An exposed
continuous copper plane on the PCB should mate to the

AD9653 exposed pad, Pin 0. The copper plane should have

several vias to achieve the lowest possible resistive thermal path
for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.

To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 76 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,

A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP), at www.analog.com.

VCM

The VCM pin should be bypassed to ground with a 0.1 μF
capacitor.

REFERENCE DECOUPLING

The VREF pin should be externally bypassed to ground with a
low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.

SPI PORT

The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the

AD9653 to keep these signals from transitioning at the con-

verter inputs during critical sampling periods.

CROSSTALK PERFORMANCE

The AD9653 is available in a 48-lead LFCSP package with the
input pairs on either corner of the chip. See Figure 6 for the pin
configuration. To maximize the crosstalk performance on the
board, add grounded filled vias in between the adjacent
channels as shown in Figure 77.

Figure 77. Layout Technique to Maximize Crosstalk Performance

Figure 76. Typical PCB Layout

Rev. 0 | Page 39 of 40

AD9653 Data Sheet

COMPLI ANT TO JEDEC STANDARDS MO-220-WKKD.

1

0.50

BSC

BOTTOM VIEW

TOP VIEW

PIN 1

INDICATOR

48

13

24

36

37

EXPOSED

PAD

PIN 1
INDICATOR

5.65

5.60 SQ

5.55

0.45

0.40

0.35

SEATING

PLANE

0.80

0.75

0.70

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

0.30

0.23

0.18

02-14-2011-B

7.10

7.00 SQ

6.90

FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.

0.20 MIN

©2012 Analog Devices, Inc. All rights reserved. Trademarks and

OUTLINE DIMENSIONS

Figure 78. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

7 mm × 7 mm Body, Very Very Thin Quad

(CP-48-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9653BCPZ-125 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13
AD9653BCPZRL7-125 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-48-13
AD9653-125EBZ Evaluation Board

1

Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.
D10538-0-5/12(0)

Rev. 0 | Page 40 of 40