Datasheet AD9641 Datasheet (ANALOG DEVICES)

Page 1

14-Bit, 80 MSPS/155 MSPS, 1.8 V

Serial Output Analog-to-Digital Converter (ADC)

FEATURES

JESD204A coded serial digital outputs SNR = 73.7 dBFS at 70 MHz/80 MSPS SNR = 72.8 dBFS at 70 MHz and 155 MSPS SFDR = 94 dBc at 70 MHz and 80 MSPS SFDR = 90 dBc at 70 MHz and 155 MSPS Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS

1.8 V supply operation Integer 1-to-8 input clock divider IF sampling frequencies to 250 MHz

−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS Programmable internal ADC voltage reference Flexible analog input range: 1.4 V p-p to 2.1 V p-p ADC clock duty cycle stabilizer (DCS) Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment

GENERAL DESCRIPTION

The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital converter (ADC) with a high speed serial output interface. The

AD9641 is designed to support communications applications

where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth, differential sample-and-hold, analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases the design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9641

FUNCTIONAL BLOCK DIAGRAM

VDD

AD9641

VIN+

VIN–

VCM

REFERENCE

MULTICHIP

AGND

The ADC output data is routed directly to the JESD204A serial output port. This output is at CML voltage levels. A CMOS or LVDS synchronization input (DSYNC) is provided.

The flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9641 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. An on-chip PLL allows users to provide a single ADC

sampling clock. The PLL multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock.

2. The configurable JESD204A output block coded data rate

supports up to 1.6 Gbps.

3. A proprietary differential input maintains excellent SNR

performance for input frequencies of up to 250 MHz.

4. Operation is from a single 1.8 V power supply.

5. The standard serial port interface (SPI) supports various

product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), controlling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

SDIO SCLK CSB

PROGRAMMING DATA

ADC

SYNC

SPI

DATA RATE

MULTIPLIER

DUTY CYCLE STABILIZER

DIVIDE-BY-1

DIVIDE-BY-8

PDWN DRGND

Figure 1.

DRVDD

ENCODER,

DATA SERIALIZ ER,

AND CML DRIVERS

DOUT+

DOUT–

DSYNC+

DSYNC–

CLK+

CLK–

09210-001

Page 2

AD9641

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

ADC DC Specifications ............................................................... 3

ADC AC Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications.............................................................. 6

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Equivalent Circuits......................................................................... 16

Theory of Operation ...................................................................... 17

ADC Architecture ......................................................................17

Analog Input Considerations.................................................... 17

Voltage Reference ....................................................................... 19

Clock Input Considerations...................................................... 19

Chip Synchronization................................................................ 20

Power Dissipation and Standby Mode .................................... 21

Digital Outputs........................................................................... 21

Built-In Self-Test (BIST) and Output Test .................................. 25

Built-In Self-Test (BIST)............................................................ 25

Output Test Modes..................................................................... 25

Serial Port Interface (SPI).............................................................. 27

Configuration Using the SPI..................................................... 27

Hardware Interface..................................................................... 28

SPI Accessible Features.............................................................. 28

Memory Map .................................................................................. 29

Reading the Memory Map Register Table............................... 29

Memory Map Register Table..................................................... 29

Memory Map Register Descriptions........................................ 32

Applications Information.............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

8/11—Rev. 0 to Rev. A

Added Model -155......................................................... Throughout

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 4............................................................................ 6

Changes to Figure 11 to Figure 14 Captions............................... 11

Added Figure 23 to Figure 40; Renumbered Sequentially ........ 13

Changes to Clock Input Considerations Section........................ 19

Changes to Digital Outputs and Timing Section ....................... 23

Moved Figure 65 and Figure 66 .................................................... 23

Added Figure 68.............................................................................. 24

Changes to Output Test Modes Section ...................................... 25

Changes to SPI Accessible Features Section ............................... 28

Changes to Addr (Hex) 0x02, Table 17........................................ 29

Changes to Ordering Guide.......................................................... 36

7/10—Revision 0: Initial Version

Rev. A | Page 2 of 36

Page 3

AD9641

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS dierential input, DCS enabled, unless otherwise noted.

Table 1.

AD9641-80 AD9641-155 Parameter Temperature Min Typ Max Min Typ Max Unit

RESOLUTION Full 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±2 ±10 ±2 ±11 mV Gain Error Full −7 −2.5 +1 −7.5 −2.5 +1 % FSR Differential Nonlinearity (DNL)1 Full ±0.55 ±0.55 LSB

25°C ±0.3 ±0.3 LSB

Integral Nonlinearity (INL)1 Full ±1.1 ±1.2 LSB 25°C ±0.5 ±0.5 LSB TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C

Gain Error Full ±35 ±35 ppm/°C INPUT REFERRED NOISE 25°C 0.7 0.7 LSB rms ANALOG INPUT

Input Span Full 1.383 1.75 2.087 1.383 1.75 2.087 V p-p

Input Capacitance2 Full 6 5 pF

Input Resistance Full 20 20 kΩ VCM OUTPUT LEVEL Full 0.88 0.9 0.92 0.87 0.9 0.92 V POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

IAVDD1 Full 96 100 121 132 mA IDRVDD1 Full 36 40 51 54 mA

POWER CONSUMPTION

Sine Wave Input1 Full 238 252 310 335 mW

Standby Power3 Full 56 56 mW

Power-Down Power Full 7 18 7 18 mW

Measured with a low input frequency, full-scale sine wave.

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Rev. A | Page 3 of 36

Page 4

AD9641

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted.

Table 2.

AD9641-80 AD9641-155 Parameter1 Temperature Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 10 MHz 25°C 73.8 73.0 dBFS fIN = 70 MHz 25°C 73.7 72.8 dBFS

fIN = 180 MHz

fIN = 220 MHz 25°C 71.3 71.6 dBFS

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 10 MHz 25°C 73.7 72.5 dBFS fIN = 70 MHz 25°C 73.6 72.0 dBFS fIN = 180 MHz 25°C 72.5 71.5 dBFS Full 71.4 68.7 dBFS fIN = 220 MHz 25°C 71.2 71.1 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 12.0 fIN = 70 MHz 25°C 11.9 fIN = 180 MHz 25°C 11.8 fIN = 220 MHz 25°C 11.5

WORST SECOND OR THIRD HARMONIC

fIN = 10 MHz 25°C −94 fIN = 70 MHz 25°C −94 fIN = 180 MHz 25°C −91 Full −80 fIN = 220 MHz 25°C −90

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 10 MHz 25°C 94 fIN = 70 MHz 25°C 94 fIN = 180 MHz 25°C 91 Full 80 80 fIN = 220 MHz 25°C 90

WORST OTHER (HARMONIC OR SPUR)

fIN = 10 MHz 25°C −98 fIN = 70 MHz 25°C −98 fIN = 180 MHz 25°C −96 Full −90 fIN = 220 MHz 25°C −90

TWO-TONE SFDR

fIN = 30 MHz (−7 dBFS ), 33 MHz (−7 dBFS ) 25°C 93 fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C 89

ANALOG INPUT BANDWIDTH2 25°C 780

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is 250 MHz.

25°C 72.6 72.1 dBFS Full 71.8 69.8 dBFS

11.8

11.7

11.6

11.5

−90

90 90 90

−95

−93

−90

90 82 780

Bits Bits Bits Bits

dBc dBc dBc

−80 dBc dBc

dBc dBc dBc dBc dBc

dBc dBc dBc

−87 dBc dBc

dBc dBc MHz

Rev. A | Page 4 of 36

Page 5

AD9641

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted.

Table 3.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ

DSYNC INPUT

Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ

LOGIC INPUT (CSB)1

Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK)2

Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

Rev. A | Page 5 of 36

Page 6

AD9641

Parameter Temperature Min Typ Max Unit

LOGIC INPUT/OUTPUT (SDIO)1

Logic Compliance CMOS High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

Logic Compliance Full CML Differential Output Voltage (VOD) Full 0.6 0.8 1.1 V Output Offset Voltage (VOS) Full 0.75 DRVDD/2 1.05 V

Pull up.

Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted.

Table 4.

AD9641-80 AD9641-155 Parameter Temperature Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 640 640 MHz Conversion Rate1 Full 40 80 40 155 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 1.935 3.225 4.515 ns Divide-by-1 Mode, DCS Disabled Full 5.95 6.25 6.55 3.065 3.225 3.385 ns

Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 ns Aperture Delay (tA) Full 0.78 0.78 ns Aperture Uncertainty (Jitter, tJ) Full 0.125 0.125 ps rms

DATA OUTPUT PARAMETERS

Data Output Period or UI (Unit Interval) Full 1/(20 × f Data Output Duty Cycle 25°C

Data Valid Time 25°C 0.8 0.75 UI

PLL Lock Time (t

) 25°C 4 4 μs

LOCK

Wake Up Time (Standby) 25°C

Wake Up Time (Power-Down)2 25°C 2.5 2.5 ms Pipeline Delay (Latency) Full 23 24 23 24 CLK cycles Data Rate (NRZ) 25°C 1.6 3.1 Gbps Deterministic Jitter 25°C 40 40 ps Random Jitter at 1.6 Gbps 25°C 9.5 ps rms Random Jitter at 3.1 Gbps 25°C 5.2 ps rms Output Rise/Fall Time 25°C 50 50 ps

TERMINATION CHARACTERISTICS

Differential Termination Resistance 25°C 100 100 Ω

OUT-OF-RANGE RECOVERY TIME 25°C 2 2 CLK cycles

Conversion rate is the clock rate after the divider.

Wake-up time is defined as the time required to return to normal operation from power-down mode.

) Full 12.5 6.45 ns

CLK

) 1/(20 × f

CLK

) sec

CLK

μs

Rev. A | Page 6 of 36

Page 7

AD9641

TIMING SPECIFICATIONS

Table 5.

Parameter Test Conditions Limit

SYNC TIMING REQUIREMENTS

SYNC to rising edge of CLK+ setup time 0.30 ns typ

SSYNC

SYNC to rising edge of CLK+ hold time 0.30 ns typ

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min t

Period of the SCLK 40 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min t

SCLK pulse width high 10 ns min

HIGH

SCLK pulse width low 10 ns min

LOW

EN_SDIO

DIS_SDIO

Timing Diagrams

NALOG

INPUT

SIGNAL

N – 23

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

SAMPLE

N – 22

N – 21

N – 20

N + 1

N – 1

10 ns min

CLK–

CLK+

CLK–

CLK+

DOUT+

DOUT–

SAMPLE N – 23 ENCODED INTO 2 8b/10b SYMBOLS

SAMPLE N – 22 ENCODED INTO 2 8b/10b SYMBOLS

SAMPLE N – 21 ENCODED INTO 2 8b/10b SY MBOLS

09210-002

Figure 2. Data Output Timing

CLK+

HSYNC

09210-003

SYNC

SSYNC

Figure 3. SYNC Input Timing Requirements

Rev. A | Page 7 of 36

Page 8

AD9641

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0V VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V SYNC to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK to AGND −0.3 V to DRVDD + 0.2 V SDIO to AGND −0.3 V to DRVDD + 0.2 V PDWN to AGND −0.3 V to DRVDD + 0.2 V DOUT+, DOUT− to AGND DSYNC+, DSYNC− to AGND

−0.3 V to DRVDD + 0.2 V

ENVIRONMENTAL

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Airflow Veloc ity

Packa ge Type

32-Lead LFCSP

5 mm × 5 mm (CP-32-12)

1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).

(m/sec) θ

0 36 3 20 °C/W

1.0 32 °C/W

2.5 28 °C/W

1, 2

1, 3

1, 4

Unit

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Ta b le 7 , airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and power planes, reduces θ

ESD CAUTION

Rev. A | Page 8 of 36

Page 9

AD9641

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

VIN+

VIN–

AVDD

VCM 52

2 3

AVDD

PIN 1

DNC

AVDD

CLK+

CLK– AVDD SYNC AVDD

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES T HE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECT ED TO GROUND FOR PRO PER OPERATION.

3 4 5 6 7 8

INDICATOR

AD9641

TOP VIEW

(Not to Scale)

DSYNC–

DSYNC+

Figure 4. LFCSP Pin Configuration (Top View)

DRGND

DRVDD

DRGND

PDWN

DNC

CSB SCLK

21 20

SDIO DRVDD

19 18

DRVDD DRGND

DOUT–

DOUT+

DRVDD

09210-004

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type Description

ADC Power Supplies

12, 16, 18, 19 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 1, 3, 6, 8, 26, 27, 30, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 2, 23 DNC Do Not Connect. 11, 13, 17 DRGND Driver ground Digital Driver Supply Ground. 0 AGND, Exposed pad Ground

The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation.

ADC Analog

29 VIN+ Input Differential Analog Input Pin (+). 28 VIN− Input Differential Analog Input Pin (−). 25 VCM Output Common-Mode Level Bias Output. 4 CLK+ Input ADC Clock Input—True. 5 CLK− Input ADC Clock Input—Complement.

Digital Inputs

7 SYNC Input Input Clock Divider Synchronization Pin. 10 DSYNC+ Input

Active Low JESD204A LVDS Sync Input—True/Active Low JESD204A CMOS Sync Input.

9 DSYNC− Input Active Low JESD204A LVDS Sync Input—Complement.

Digital Outputs

15 DOUT+ Output CML Output Data—True. 14 DOUT− Output CML Output Data—Complement.

SPI Control

21 SCLK Input SPI Serial Clock. 20 SDIO Input/output SPI Serial Data I/O. 22 CSB Input SPI Chip Select (Active Low).

ADC Configuration

24 PDWN Input

Power-Down Input. Using the SPI interface, this input can be configured as power-down or standby.

Rev. A | Page 9 of 36

Page 10

AD9641

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN =

−1.0 dBFS, and 32k sample, T

–20

–40

= 25°C, unless otherwise noted.

80MSPS

10.1MHz @ –1dBF S SNR = 73.0dB (74. 0dBFS) SFDR = 95dBc

80MSPS

140.3MHz @ –1dBF S

–20

SNR = 72.2dB (73. 2dBFS) SFDR = 94.0dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 5. AD9641-80 Single-Tone FFT with f

80MSPS

30.1MHz @ –1dBF S

–20

SNR = 72.7dB (73. 7dBFS) SFDR = 94dBc

–40

–60

–80

AMPLITUDE (dBFS)

THIRD HARMONIC

–100

–120

–140

0 1020304

Figure 6. AD9641-80 Single-Tone FFT with f

THIRD HARMONIC

FREQUENCY (MHz )

SECOND HARMONIC

FREQUENCY (MHz )

= 10.1 MHz

= 30.1 MHz

09210-005

09210-006

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 8. AD9641-80 Single-Tone FFT with f

80MSPS

180.1MHz @ –1dBFS

–20

SNR = 71.6dB (72.6dBFS) SFDR = 93dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 9. AD9641-80 Single-Tone FFT with f

FREQUENCY (MHz )

FREQUENCY (MHz)

= 140.1 MHz

SECOND HARMONIC

= 180.1 MHz

09210-008

09210-009

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

SECOND HARMONIC

FREQUENCY (MHz )

Figure 7. AD9641-80 Single-Tone FFT with f

80MSPS

70.1MHz @ –1dBFS SNR = 72.5dB (73. 5dBFS) SFDR = 94.0dBc

THIRD HARMONIC

= 70.1 MHz

09210-007

Rev. A | Page 10 of 36

80MSPS

220.1MHz @ –1dBF S

–20

SNR = 71.1dB (72. 1dBFS) SFDR = 92dBc

–40

–60

THIRD HARMONIC

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

FREQUENCY (MHz )

Figure 10. AD9641-80 Single-Tone FFT with f

SECOND HARMONIC

= 220.1 MHz

09210-010

Page 11

AD9641

120

100

–100

–95

SFDR (dBFS) SFDR (dBc) SNR (dBFS) SNR (dBc)

–90

–85

–80

–75

–70

–65

–60

–55

–50

–45

–40

INPUT AMPLITUDE (dBF S)

–35

–30

–25

–5

–20

–15

–10

SNR/SFDR (d Bc/dBFS)

Figure 11. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (A

= 10.1 MHz, fS = 80 MSPS

with f

120

100

SFDR (dBFS)

SFDR (dBc) SNR (dBFS) SNR (dBc)

SNR/SFDR (dBc/dBFS)

SNR/SFDR (dBF S/dBc)

09210-011

)

Figure 14. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (f

–20

–40

–60

–80

SFDR/IMD3 ( dBc/dBFS )

–100

SNR @ –40°C SFDR @ –40°C SNR @ +25°C SFDR @ +25°C SNR @ +85°C SFDR @ +85°C

0 50 100 150 200 250

Temperature with 2.0 V p-p Full Scale, f

SFDR (dBc) IMD3 (dBc) SFDR (dBFS) IMD3 (dBFS)

INPUT FREQ UENCY (MHz)

= 80 MSPS

) and

09210-014

–95

–90

–85

–80

–75

–70

–65

–60

–55

–50

–45

–40

–35

–30

–25

–20

–15

–100

INPUT AMPLITUDE (dBFS)

–10

Figure 12. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (A

= 180 MHz, fS = 80 MSPS

with f

100

SNR/SFDR (dBF S/dBc)

SNR @ –40°C SFDR @ –40°C SNR @ +25°C SFDR @ +25°C SNR @ +85°C SFDR @ +85°C

0 50 100 150 200 250

INPUT FREQ UENCY (MHz)

Figure 13. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with 1.75 V p-p Full Scale, f

= 80 MSPS

–5

09210-012

)

09210-013

) and

–120

–90 –78 –66 –54 –42 –30 –18 –6

INPUT AMPLITUDE (dBFS)

Figure 15. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

= 29.9 MHz, f

with f

IN1

–20

–40

–60

–80

SFDR/IMD3 ( dBc/dBFS )

–100

–120

SFDR (dBc) IMD3 (dBc) SFDR (dBFS) IMD3 (dBFS)

–90 –78 –66 –54 –42 –30 –18 –6

= 32.9 MHz, fS = 80 MSPS

IN2

INPUT AMPLITUDE (dBFS)

Figure 16. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

with f

= 169.1 MHz, f

IN1

= 172.1 MHz, fS = 80 MSPS

IN2

09210-015

)

09210-016

)

Rev. A | Page 11 of 36

Page 12

AD9641

80MSPS

29.9MHz @ –7dBF S

–20

32.9MHz @ –7dBF S SFDR = 94.4dBc (101.4dBFS)

–40

14,000

12,000

10,000

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 17. AD9641-80 Two-Tone FFT with f

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 1020304

Figure 18. AD9641-80 Two-Tone FFT with f

FREQUENCY (MHz )

= 29.9 MHz and f

IN1

80MSPS

169.1MHz @ –7dBFS

172.1MHz @ –7dBFS SFDR = 91.9dBc (98.9dBFS )

FREQUENCY (MHz )

= 172.1 MHz

IN2

= 169.1 MHz and

IN1

= 32.9 MHz

IN2

09210-017

09210-018

8000

6000

NUMBER OF HIT S

4000

2000

N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4

OUTPUT CODE

Figure 20. AD9641-80 Grounded Input Histogram

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 200 400 600 800 1000 1200 1400 1600

Figure 21. AD9641-80 INL with f

OUTPUT CODE

= 30.3 MHz

09210-020

09210-021

100

SNR/SFDR (dBFS/dBc)

45 50 55 60 65 70 75 80

SFDR

SNR

SAMPLE RAT E (MSPS)

Figure 19. AD9641-80 Single-Tone SNR/SFDR vs. Sample Rate (f

= 70.1 MHz

with f

09210-019

)

Rev. A | Page 12 of 36

0.50

0.25

DNL ERROR (LSB)

–0.25

–0.50

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000

Figure 22. AD9641-80 DNL with f

OUTPUT CODE

= 30.3 MHz

09210-022

Page 13

AD9641

–20

–40

155MSPS

10.1MHz @ –1d BFS SNR = 71.0dB (72.0dBFS) SFDR = 95dBc

–20

–40

155MSPS

140.1MHz @ –1d BFS SNR = 70.7dB (71.7dBFS) SFDR = 93dBc

–60

–80

AMPLIT UDE (dBFS)

–100

–120

–140

0 7.75 15.50 23.25 31.00 38.75 46. 50 54.25 62.00 69. 75 77.50

Figure 23. AD9641-155 Single-Tone FFT with f

–20

–40

–60

–80

AMPLIT UDE (dBFS)

–100

–120

–140

0 7.75 15.50 23.25 31.00 38.75 46. 50 54.25 62.00 69. 75 77.50

Figure 24. AD9641-155 Single-Tone FFT with f

SECOND HARMO NIC

THIRD HARMO NIC

FREQUENCY (MHz)

SECOND HARMONIC

FREQUENCY (MHz)

= 10.1 MHz

155MSPS

30.1MHz @ –1d BFS SNR = 70.9dB (71.9dBFS) SFDR = 95dBc

THIRD HARMO NIC

= 30.1 MHz

–60

–80

AMPLIT UDE (dBFS)

–100

–120

–140

0 7.75 15.50 23.25 31.00 38.75 46. 50 54.25 62.00 69. 75 77.50

09210-122

SECOND HARMO NIC

FREQUENCY (MHz)

Figure 26. AD9641-155 Single-Tone FFT with f

–20

–40

–60

–80

AMPLIT UDE (dBFS)

–100

–120

–140

0 7.75 15.50 23.25 31.00 38.75 46. 50 54.25 62.00 69. 75 77.50

09210-123

SECOND HARMO NIC

FREQUENCY (MHz)

Figure 27. AD9641-155 Single-Tone FFT with f

THIRD HARMO NIC

= 140.1 MHz

155MSPS

180.1MHz @ –1d BFS SNR = 70.3dB (71.3dBFS) SFDR = 92dBc

THIRD HARMO NIC

= 180.1 MHz

09210-125

09210-126

155MSPS

70.1MHz @ –1dBFS

–20

SNR = 70.7d B (71.7dBFS) SFDR = 93dBc

–40

–60

THIRD HARMO NIC

–80

AMPLIT UDE (dBFS)

SECOND HARMONIC

–100

–120

–140

0 7.75 15.50 23.25 31.00 38.75 46. 50 54.25 62.00 69. 75 77.50

Figure 25. AD9641-155 Single-Tone FFT with f

FREQUENCY (MHz)

= 70.1 MHz

09210-124

Rev. A | Page 13 of 36

155MSPS

220.1MHz @ –1dBFS

–20

SNR = 70.2dB (71.2dBFS) SFDR = 89dBc

–40

–60

SECOND HARMO NIC

–80

AMPLIT UDE (dBFS)

–100

–120

–140

0 7.75 15.50 23.25 31.00 38.75 46. 50 54.25 62.00 69. 75 77.50

Figure 28. AD9641-155 Single-Tone FFT with f

THIRD HARMO NIC

FREQUENCY (MHz)

= 220.1 MHz

09210-127

Page 14

AD9641

120

SFDR (dBFS)

100

SNR/SFDR (d Bc AND dBFS)

–90 –8 0 –70 –60 –50 –40 –30 –20 –10 0

SNR (dBFS)

SFDR (dBc)

SNR (dBc)

INPUT AMPLI TUDE (dBFS)

Figure 29. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (A

= 10.1 MHz, fS = 155 MSPS

with f

120

100

SNR/SFDR (dBc AND dBFS)

–90 –8 0 –70 –60 –5 0 –40 –30 –20 –10 0

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SNR (dBc)

INPUT AMPLI TUDE (dBFS)

Figure 30. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (A

= 180 MHz, fS = 155 MSPS

with f

SNR @ –40°C SFDR @ –40°C

SNR @ +25°C SFDR @ +25°C SNR @ +85°C

SFDR @ +85°C

SNR/SFDR (dBFS AND dBc)

0 50 100 150 200 250 300

09210-128

)

Figure 32. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with 2.0 V p-p Full Scale, f

–20

–40

–60

–80

SFDR/IMD3 ( dBc AND dBFS)

–100

–120

–90 –78 –66 –54 –42 –30 –18 –6

09210-129

)

Figure 33. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

with f

INPUT FREQUENCY (MHz)

IMD3 (dBc)

SFDR (dBFS)

INPUT AMPLI TUDE (dBFS)

= 29.9 MHz, f

IN1

= 155 MSPS

SFDR (dBc)

IMD3 (dBFS )

= 32.9 MHz, fS = 155 MSPS

IN2

) and

09210-131

09210-132

)

100

SNR @ –40°C SFDR @ –40°C

SNR @ +25°C SFDR @ +25°C SNR @ +85°C

SFDR @ +85°C

SNR/SFDR (dBFS AND dBc)

0 50 100 150 200 250 300

INPUT FREQUENCY (MHz)

Figure 31. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with 1.75 V p-p Full Scale, f

= 155 MSPS

09210-130

) and

Rev. A | Page 14 of 36

–20

–40

SFDR (dBc)

–60

–80

SFDR/IMD3 (dBc AND dBFS)

–100

–120

–90 –78 –66 –54 –42 –30 –18 –6

IMD3 (dBc)

SFDR (dBFS)

IMD3 (dBF S)

INPUT AMPLITUDE (dBFS)

Figure 34. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

with f

= 169.1 MHz, f

IN1

= 172.1 MHz, fS = 155 MSPS

IN2

09210-133

)

Page 15

AD9641

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 7.75 15.50 23.25 31. 00 38.75 46. 50 54.25 62.00 69.75 77.50

FREQUENCY (M Hz)

Figure 35. AD9641-155 Two-Tone FFT with f

–20

–40

–60

–80

AMPLIT UDE (dBFS)

–100

–120

–140

0 7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

Figure 36. AD9641-155 Two-Tone FFT with f

= 172.1 MHz

IN2

155MSPS

29.9MHz @ –7dBF S

32.9MHz @ –7dBF S SFDR = 88.7dBc ( 95.7dBFS)

= 29.9 MHz and f

IN1

155MSPS

169.1MHz @ –7d BFS

172.1MHz @ –7d BFS SFDR = 89.8dBc (96.8dBFS)

= 169.1 MHz and

IN1

= 32.9 MHz

IN2

6000

5000

4000

3000

NUMBER OF HITS

2000

1000

09210-134

N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4

OUTPUT CODE

09210-137

Figure 38. AD9641-155 Grounded Input Histogram

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LS B)

–0.4

–0.6

–0.8

–1.0

09210-135

0 2000 40 00 6000 8000 10,000 12,000 14,000 16,000

Figure 39. AD9641-155 INL with f

OUTPUT CO DE

= 30.3 MHz

09210-138

105

100

SNR/SFDR (dBFS AND dBc)

50 65 80 95 110 125 140 155

SFDR

SNR

SAMPLE RATE (MSPS)

Figure 37. AD9641-155 Single-Tone SNR/SFDR vs. Sample Rate (f

= 70.1 MHz

with f

09210-136

)

Rev. A | Page 15 of 36

0.50

0.25

DNL ERROR (LSB)

–0.25

–0.50

0 2000 4000 6000 8000 10,000 12,000 14, 000 16,000

Figure 40. AD9641-155 DNL with f

OUTPUT CODE

= 30.3 MHz

09210-139

Page 16

AD9641

EQUIVALENT CIRCUITS

AVDD

SCLK

PDWN

350Ω

30kΩ

Figure 41. Equivalent Analog Input Circuit

AVDD

AVDD AVDD

LK+

0.9V

15kΩ 15kΩ

Figure 42. Equivalent Clock Input Circuit

DRVDD

4mA

DOUT+ DOUT –

4mA

TERM

Figure 43. Digital CML Output

4mA

09210-023

09210-027

Figure 45. Equivalent SCLK or PDWN Input Circuit

VDD

30kΩ

350Ω

09210-028

CLK–

CSB

09210-024

Figure 46. Equivalent CSB Input Circuit

VDD AVDD

DSYNC ±

OR SYNC

16kΩ

0.9V

09210-025

0.9V

09210-029

Figure 47. Equivalent SYNC and DSYNC Input Circuit

SDIO

DRVDD

30kΩ

350Ω

09210-026

Figure 44. Equivalent SDIO Circuit

Rev. A | Page 16 of 36

Page 17

AD9641

THEORY OF OPERATION

The AD9641 can sample any fS/2 frequency segment from dc to 250 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance.

Synchronization capability is provided to allow synchronized timing between multiple devices.

Programming and control of the AD9641 are accomplished using a 3-wire, SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9641 architecture consists of a front-end sample-andhold circuit, followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low resolution, flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9641 is a differential switchedcapacitor circuit that has been designed for optimum performance while processing a differential input signal.

The clock signal switches the input alternatively between sample mode and hold mode (see Figure 48). When the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle.

A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application.

In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced because the input sample capacitor is unbuffered. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched- Capacitor ADCs; and the Analog Dialogue article, “Tr an s fo r me rCoupled Front-End for Wideband A/D Converters,” for more information on this subject (refer to www.analog.com).

BIAS

IN+

IN–

PAR1

PAR2

Figure 48. Switched-Capacitor Input

BIAS

For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched, and the inputs should be differentially balanced.

Input Common Mode

The analog inputs of the AD9641 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or

0.9 V) is recommended for optimum performance. An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. Using the VCM output to set the input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically, 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 μF capacitor. This decoupling capacitor should be placed close to the pin to minimize the series resistance and inductance between the part and this capacitor.

Differential Input Configurations

Optimum performance is achieved while driving the AD9641 in a differential input configuration. For baseband applications, the

AD8138, ADA4937-2, and ADA4938-2 differential drivers provide

excellent performance and a flexible interface to the ADC.

09210-030

Rev. A | Page 17 of 36

Page 18

AD9641

The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9641 (see Figure 49), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

15p

200Ω

33Ω

5pF

15pF

15Ω

VIN–

VIN+

ADC

AVDD

VCM

09210-031

76.8Ω

0.1µF

90Ω

ADA4938-2

120Ω

200Ω

Figure 49. Differential Input Configuration Using the ADA4938-2

For baseband applications in which SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 50. To bias the analog input, the voltage of VCM can be connected to the center tap of the secondary winding of the transformer.

0.1µF

VIN+

ADC

VCM

VIN–

09210-032

0.1µF

2V p-p

49.9Ω

0.1µF

Figure 50. Differential Transformer-Coupled Configuration

V p-p

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9641. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 51). In this configuration, the input is ac-coupled, and the common-mode voltage (VCM) is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver.

In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. Based on these parameters, the value of the input resistors and capacitors may need to be adjusted, or some components may need to be removed. Tabl e 9 displays recommended values to set the RC network for different input frequency ranges. However, these values are dependent on the input signal and bandwidth and should be used only as a starting guide.

An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8376 variable gain amplifier. An example drive circuit including a band-pass filter is shown in Figure 52. See the AD8376 data sheet for more information.

33Ω

0.1µF

R1R2R2

VIN+

VIN–

ADC

VCM

09210-033

Figure 51. Differential Double Balun Input Configuration

Table 9. Example RC Network

Frequency Range (MHz) R1 Series (Ω Each) C1 Differential (pF) R2 Series (Ω Each) C2 Shunt (pF Each) R3 Shunt (Ω Each)

0 to 100 33 8.2 0 8.2 49.9 100 to 250 15 3.9 0 Open Open

1000p

180n

220n

1µH

VPOS

1nF

1000pF

301Ω

180nH

AD8376

NOTES

1. ALL INDUCTORS ARE COI LCRAFT 0603CS CO MPONENT S WITH T HE EXCEPTI ON OF T HE 1µH CHOKE INDU

2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWI DTH FI LTER CENTERED AT 140MHz.

Figure 52. Differential Input Configuration Using the AD8376

Rev. A | Page 18 of 36

165Ω

5.1pF 3. 9pF

165Ω

220nH

15pF

VCM

1nF

68nH

TORS (0603L S).

AD9641

09210-034

Page 19

AD9641

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9641. The input full-scale range can be adjusted through the SPI port by adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be used to change the full-scale value between 1.383 V p-p and

2.087 V p-p in 0.022 V steps, as shown in Table 17 .

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9641 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins by means of a transformer or a passive component configuration. These pins are biased internally (see Figure 53) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking.

AVDD

The RF balun configuration is recommended for clock frequencies between 125 MHz and 640 MHz, and the RF transformer is recommended for clock frequencies from 40 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9641 to approximately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9641 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance.

If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 56. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/ AD9520/AD9522 clock drivers offer excellent jitter performance.

0.9V

CLK+

CLK–

4pF4pF

09210-035

Figure 53. Equivalent Clock Input Circuit

Clock Input Options

The AD9641 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL , or s i n e w ave sig n a l . R egard less of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. The minimum conversion rate of the AD9641 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance of the AD9641 can degrade.

Figure 54 and Figure 55 show two preferred methods for clocking the AD9641 (at clock rates up to 640 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer.

XFMR

0.1µF

0.1µF0.1µF

0.1µF

0.1µF1nF

0.1µF

SCHOTTKY

DIODES:

HSMS2822

SCHOTTKY

DIODES:

HSMS2822

CLK+

CLK–

CLK+

CLK–

ADC

09210-037

Mini-Circuits

ADT1-1WT , 1:1Z

CLOCK

INPUT

50Ω

100Ω

Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)

CLOCK

INPUT

50Ω

1nF

Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)

240Ω240Ω

0.1µF0.1µF

0.1µF

100Ω

CLK+

CLK–

ADC

09210-038

CLOCK

INPUT

CLOCK

INPUT

0.1µF

50kΩ 50kΩ

AD95xx

PECL DRIVER

Figure 56. Differential PECL Sample Clock (Up to 640 MHz)

A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 57. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ AD9518/AD9520/AD9522 clock drivers offer excellent jitter

performance.

CLOCK

INPUT

CLOCK

INPUT

0.1µF

AD95xx

LVDS DRIVER

0.1µF

50kΩ 50kΩ

Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)

0.1µF

100Ω

0.1µF

CLK+

CLK–

ADC

09210-039

In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor (see Figure 58).

50Ω*

0.1µF

1kΩ

AD95xx

CMOS DRIVER

OPTIONAL

100Ω

0.1µF

0.1µF CLK+

CLK–

ADC

09210-040

09210-036

CLOCK

INPUT

*50Ω RESISTOR IS OPTIONAL.

Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Rev. A | Page 19 of 36

Page 20

AD9641

Input Clock Divider

The AD9641 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS) is optional. For other divide ratios, such as 3, 5, 6, 7, and 8, the DCS must be enabled for proper part operation.

The AD9641 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x03A allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. The AD9641 requires a tight tolerance on the clock duty cycle to maintain dynamic performance characteristics.

The AD9641 contains a DCS that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the

AD9641. Noise and distortion performance are nearly flat for a

wide range of duty cycles with the DCS enabled.

Jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of

1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time when the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the DCS. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. For inputs near full scale, the degradation in SNR from the low frequency SNR (SNR frequency (f

SNR

) due to jitter (t

INPUT

= −10 log[(2π × f

INPUT

JRMS

× t

) at a given input

) can be calculated by

)2 + 10 ]

JRMS

)10/(LFSNR−

In the equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 59. The measured curve in Figure 59 was taken using an ADC clock source with approximately 65 f

of jitter, which combines with the 125 fS of jitter

inherent in the AD9641 to produce the result shown.

SNR (dBFS)

0.05ps

0.2ps

0.5ps 1ps

1.5ps MEASURED

1 10 100 1000

INPUT FREQ UENCY (MHz)

Figure 59. SNR vs. Input Frequency and Jitter

09210-041

The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9641. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756 Appli cation Note for more information about jitter performance as it relates to ADCs.

CHIP SYNCHRONIZATION

The AD9641 has a SYNC input that offers the user flexible synchronization options for synchronizing the clock divider. The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence.

The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Tabl e 5. The SYNC input should be driven using a single-ended CMOS-type signal.

Rev. A | Page 20 of 36

Page 21

AD9641

POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS

As shown in Figure 60, the power dissipated by the AD9641 varies with its sample rate. The data in Figure 60 was taken in JESD204A serial output mode, using the same operating conditions as those used for the Typic a l Pe r formance Characteristics.

0.30

0.20

TOTAL

POWER

AVDD

0.15

0.10

JESD204A Transmit Top Level Description

The AD9641 digital output complies with the JEDEC Standard No. 204A (JESD204A), which describes a serial interface for data converters. JESD204A uses 8b/10b encoding, as well as optional scrambling. K28.5 and K28.7 comma symbols are used for frame synchronization, and the K28.3 control symbol is used for lane synchronization. The receiver is required to lock onto the serial data stream and recover the clock with the use of a PLL. For details on the output interface, users are encouraged to refer to the JESD204A standard.

The JESD204A link is described according to the following nomenclature:

0.10

TOTAL POWER ( W)

DRVDD

40 50 60 70 80

ENCODE FREQUENCY (MSPS)

Figure 60. Power and Current vs. Encode Frequency

0.05

SUPPLY CURRENT (A)

The AD9641 is placed in power-down mode using Register 0x08, Bits[1:0] or by asserting the PDWN pin high. In this state, the ADC typically dissipates 7 mW. During power-down, the output drivers are placed in a high impedance state. Pulling the PDWN pin low returns the AD9641 to its normal operating mode. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation.

When using the SPI port interface, the user can place the ADC in power-down mode or standby mode (Register 0x08, Bits[1:0]). Standby mode allows the user to keep the internal reference circuitry powered and the JESD204A outputs running when faster wake-up times are required.

• S = samples transmitted per single converter per

frame cycle

• M = number of converters per converter device (link)

• L = number of lanes per converter device (link)

• N = converter resolution

09210-042

• N’ = total number of bits per sample

• CF = number of control words per frame clock cycle per

converter device (link)

• CS = number of control bits per conversion sample

• K = number of frames per multiframe

• HD = high density mode

• F = number of octets per frame

• C = control bit (overrange, overflow, underflow)

• T = tail bit

• SCR = scrambling enabled

• FCHK = checksum

The JESD204A block for the AD9641 is designed to support the configurations described in Tab l e 1 0 .

Table 10. AD9641 JESD204A Typical Configuration

Configuration JESD204A Link Settings Comments

M = 1; L = 1; S = 1; F = 2 Maximum sample rate = 80 or 155 MSPS One Converter N’ = 16; CF = 0 One JESD204A Link CS = 0, 1, 2; K = N/A One Lane Per Link SCR = 0, 1; HD = 0

Rev. A | Page 21 of 36

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AD9641

Figure 61 shows a simplified block diagram of the JESD204A link for the AD9641. The 8b/10b encoding works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. By default in the AD9641, the 14-bit converter word is broken into two octets. Bit 13 through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 and two tail bits. The MSB of the tail bits can also be used to indicate an out-of-range condition. The tail bits are configured using the JESD204A link control in JESD204A Link Control Register 1, Address 0x60, Bit 6.

LINK DSYNC

OUTPUT LANE

CONVERTER

INPUT

CONVERTER

AD9641 ADC

CONVERTER

SAMPLE

JESD204 A LINK

(M = 0, 1; L = 0, 1)

Figure 61. AD9641 Transmit Link Simplified Block Diagram

09210-043

The two resulting octets are optionally scrambled and encoded into their corresponding 10-bit code. The scrambler function is controlled by the JESD204A scrambling and lane configuration register, Address 0x06E, Bit 7. Figure 62 shows how the 14-bit data is taken from the ADC, the tail bits are added, the two octets are scrambled, and the octets are encoded into two 10-bit symbols. Figure 63 illustrates the default data format.

The scrambler uses a self-synchronizing, polynomial-based algorithm defined by the following equation: 1 + x

+ x15. The descrambler in the receiver should be a self-synchronizing version of the scrambler polynomial. Figure 64 shows the corresponding receiver data path.

Refer to JEDEC Standard No. 204A, April 2008, Section 5.1, for complete transport layer and data format details. See Section 5.2 for a complete explanation of scrambling and descrambling.

DATA FROM

ADC

FRAME

ASSEMBLER

(ADD TAIL BIT S)

OPTIONAL

SCRAMBLER

1 + x

+ x

8B/10B

ENCODER

TO RECEIVE R

09210-044

Figure 62. ADC Output Data Path

WORD 0[13:6] SYMBO L 0[9:0]

FRAME 0

WORD 0[5:0], TAIL BI TS[1:0] SYMBOL 1[ 9:0]

IME

WORD 1[13:6] SYMBO L 2[9:0]

FRAME 1

WORD 1[5:0], TAIL BI TS[1:0] SYMBOL 3[ 9:0]

09210-045

Figure 63. 14-Bit Data Transmission with Tail Bits

FROM

TRANSMITT ER

8B/10B

DECODER

Figure 64. Required Receiver Data Path

OPTIO NAL

DESCRAMBLER

+ x

1 + x

FRAME

ALIGN MENT

DATA

OUT

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Rev. A | Page 22 of 36

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AD9641

Ω

Initial Frame Synchronization

The serial interface must synchronize to the frame boundaries before data can be properly decoded. The JESD204A standard has a synchronization routine to identify the frame boundary. When the DSYNC pin is taken low for at least two clock cycles, the AD9641 enters the code group synchronization mode. The

AD9641 transmits the K28.5 comma symbol until the receiver

achieves synchronization. The receiver should then deassert the sync signal (take DSYNC high), and the AD9641 begins the initial lane alignment sequence (when enabled through Address 0x60, Bits[3:2]) and, subsequently, begins transmitting sample data. The first non-K28.5 symbol corresponds to the first octet in a frame.

The DSYNC input can be driven either from a differential LVDS source or by using a single-ended CMOS driver circuit. The DSYNC input default to LVDS mode but can be set to CMOS mode by setting Bit 4 in Address 0x61. If it is driven differentially from an LVDS source, an external 100 Ω termination resistor should be provided. If the DSYNC input is driven single endedly, the CMOS signal should be connected to the DSYNC+ signal, and the DSYNC− signal should be left disconnected.

Frame and Lane Alignment Monitoring and Correction

Frame alignment monitoring and correction is part of the JESD204A specification. The 14-bit word requires two octets to transmit all the data. The two octets (MSB and LSB), where F = 2, make up a frame. During normal operating conditions, frame alignment is monitored via alignment characters, which are inserted under certain conditions at the end of a frame. Tabl e 1 1 summarizes the conditions for character insertion, along with the expected characters under the various operation modes. If lane synchronization is enabled, the replacement character value depends on whether the octet is at the end of a frame or at the end of a multiframe.

Based on the operating mode, the receiver can ensure that it is still synchronized to the frame boundary by correctly receiving the replace characters.

Digital Outputs and Timing

The AD9641 has differential digital outputs that power up by default. The driver current is derived on-chip and sets the output current at each output equal to a nominal 4 mA. Each output presents a 100 Ω dynamic internal termination to reduce unwanted reflections.

A 100 Ω differential termination resistor should be placed at each receiver input to result in a nominal 400 mV peak-to-peak swing at the receiver (see Figure 65). Alternatively, single-ended 50 Ω termination can be used. When single-ended termination is used, the termination voltage should be DRVDD/2; otherwise, ac coupling capacitors can be used to terminate to any singleended voltage.

The AD9641 digital outputs can interface with custom ASICs and FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 Ω termination resistor placed as close as possible to the receiver logic. The common mode of the digital output automatically biases itself to half the supply of the receiver (that is, the common-mode voltage is 0.9 V for a receiver supply of 1.8 V) if dc-coupled connecting is used (see Figure 66).

DRVDD

DOUT + x

DOUT – x

OUTPUT SWING = 400mV p-p

Figure 65. AC-Coupled Digital Output Termination Example

DRVDD

DOUT+x

DOUT–x

OUTPUT SWING = 400mV p-p

Figure 66. DC-Coupled Digital Output Termination Example

0.1µF

100

DIFFERENTIAL

TRACE PAIR

100Ω

DIFFERENTIAL

TRACE PAIR

100Ω

100Ω OR

RECEIVER

VCM = DRVDD/2

RXCM

VCM = Rx V

RECEIVER

09210-047

09210-048

For receiver logic that is not within the bounds of the DRVDD supply, an ac-coupled connection should be used. Place a 0.1 μF capacitor on each output pin and derive a 100 Ω differential termination close to the receiver side.

If there is no far-end receiver termination or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 8 inches and that the differential output traces be close together and at equal lengths.

Table 11. AD9641 JESD204A Frame Alignment Monitoring and Correction Replacement Characters

Scrambling

Lane Synchronization Character to Be Replaced Last Octet in Multiframe

Replacement Character

Off On Last octet in frame repeated from previous frame No K28.7 (0xFC) Off On Last octet in frame repeated from previous frame Yes K28.3 (0x7C) Off Off Last octet in frame repeated from previous frame Not applicable K28.7 (0xFC) On On Last octet in frame equals D28.7 (0xFC) No K28.7 (0xFC) On On Last octet in frame equals D28.3 (0x7C) Yes K28.3 (0x7C) On Off Last octet in frame equals D28.7 (0x7C) Not applicable K28.7 (0xFC)

Rev. A | Page 23 of 36

Page 24

AD9641

Figure 67 shows an example of the digital output (default) data eye and a time interval error (TIE) jitter histogram.

Additional SPI options allow the user to further increase the output driver voltage swing of all four outputs to drive longer trace lengths (see Address 0x15 in Tab l e 17 ). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. See the Memory Map section for more details.

The format of the output data is twos complement, by default. Tabl e 1 2 provides an example of this output coding format. To change the output data format to offset binary or Gray code, see the Memory Map section (Address 0x14 in Tab l e 1 7 ).

HEIGHT 1: EYE DI AGRAM PERIOD1: HISTO GRAM

400

200

VOLTAGE (mV)

–200

–400

EYE: TRANSIT ION BI TS OFFSET: –0.004 UIS: 8000; 639999, TOTAL: 8000; 639999

–600 –200–400 0 2 00 400 600 610 620 0635 –0.5 0.5

TIME (ps) TIME (ps) ULS

Figure 67. AD9641-80 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations

25,000

–

20,000

15,000

HITS

10,000

5000

615 625 630

HEIGHT1: EYE DIAGRAM P ERIOD1: HIS TOGRAM

EYE: TRANSITION BITS OFFSET: –0.002 UIS: 8000; 1239996, TOTAL: 48000; 7439996

–300 –100–200

100 200 300 305 315 0330 335 –0.5 0.5

TIME (ps) TIME (p s) ULS

–

400k

350k

300k

250k

HITS

200k

150k

100k

50k

310 320 325

Figure 68. AD9641-155 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations

VOLTAGE (mV)

–200

–400

–600

600

400

200

The lowest typical clock rate is 40 MSPS. For clock rates slower than 60 MSPS, Bit 3 should be set to 0 in the PLL control register (Address 0x21 in Tab le 1 7). This option sets the PLL loop bandwidth to use clock rates between 40 MSPS and 60 MSPS.

Setting Bit 2 in the output mode register (Address 0x14) allows the user to invert the digital samples from their nominal state. As shown in Figure 63, the MSB is transmitted first in the data output serial stream.

WIDTH@BE R1: BATHTUB

–2

–4

–6

BER

–8

–10

–12

–14

–

–2

–4

–6

BER

–8

–10

–12

–14

0.781

WIDTH@BER1: BAT HTUB

0.75

09210-050

–

09210-068

Table 12. Digital Output Coding

Code (VIN+) − (VIN−), Input Span = 1.75 V p-p (V) Digital Output Twos Complement ([D13:D0])

8191 +0.875 01 1111 1111 1111 0 0.00 00 0000 0000 0000

−1 −0.000107 11 1111 1111 1111

−8192 −0.875 10 0000 0000 0000

Rev. A | Page 24 of 36

Page 25

AD9641

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9641 includes built-in test features designed to enable verification of the integrity of the channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9641. Various output test options are also provided to place predictable values on the outputs of the AD9641.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9641 signal path. When enabled, the test runs from an internal

pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value is placed in Register 0x24 and Register 0x25. The outputs are not disconnected during this test; therefore, the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or reset from the beginning, based on the value programmed in Register 0x0E, Bit 2. The BIST signature result varies based on the channel configuration.

ADC TEST PATTE RNS

14-BIT

SPI REGISTER 0x0D

BITS [3:0] ≠ 0000

ADC CORE

JESD204A TEST PATTERNS

SPI REGIST ER 0x62 BITS [5:4] =

16-BIT

00 AND BITS [2:0] ≠ 000

JESD204A

SAMPLE

CONSTRUCTION

OUTPUT TEST MODES

Digital test patterns can be inserted at various points along the signal path within the AD9641 as shown in Figure 69. The ability to inject these signals at several locations facilitates debugging of the JESD204A serial communication link.

Register 0x0D allows test signals generated at the output of the ADC core to be fed directly into the input of the serial link. The output test options available from Register 0x0D are shown in Tabl e 1 4 . When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The seed value for the PN sequence tests can be forced if the PN reset bits are used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock.

For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

FRAME

JESD204A TEST PATTERNS

SPI REGIST ER 0x62 BITS [5:4] =

SCRAMBLER

10-BIT

01 AND BITS [2:0] ≠ 000

(OPTIONAL)

FRAMER

8-BIT/10-BI T

ENCODER

SERIALIZER

OUTPUT

TAIL BITS

Figure 69. Block Diagram Showing Digital Test Modes

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Rev. A | Page 25 of 36

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AD9641

There are nine digital output test pattern options available that can be initiated through the SPI (see Tabl e 1 4 for the output bit sequencing options). This feature is useful when validating receiver capture and timing. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern selected. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the user pattern registers (Address 0x19 and Address 0x20).

The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself ever y 2

− 1 (511) bits. A description of the PN sequence short and how it is generated can be found in Section 5.1 of the ITU-T O.150 (05/96) recommendation. The only difference is that the starting value must be a specific value instead of all 1s (see Tabl e 13 for the initial values).

The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself ever y 2

− 1 (8,388,607) bits.

Table 14. Flexible Output Test Modes from SPI Register 0x0D

Output Test Mode Bit Sequence

0000 Off (default) Not applicable Not applicable Yes 0001 Midscale short 00 0000 0000 0000 Same Yes 0010 +Full-scale short 01 1111 1111 1111 Same Yes 0011 −Full-scale short 10 0000 0000 0000 Same Yes 0100 Checkerboard 10 1010 1010 1010 01 0101 0101 0101 No 0101 PN sequence long Not applicable Not applicable Ye s 0110 PN sequence short Not applicable Not applicable Yes 0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No 1000 User test mode

1001 to 1110 Not used Not applicable Not applicable 1111 Ramp output N N + 1 No

Pattern Name

Digital Output Word 1 (Default Twos Complement Format)

User data from Register 0x19 to Register 0x20

A description of the PN sequence long and how it is generated can be found in Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Ta b le 1 3 for the initial values) and that the AD9641 inverts the bit stream with relation to the ITU-T standard.

Table 13. PN Sequence

Initial

Sequence

PN Sequence Short 0x0092 0x125B, 0x3C9A, 0x2660 PN Sequence Long 0x3AFF 0x3FD7, 0x0002, 0x36E0

Value

First Three Output Samples (MSB First)

Register 0x62 allows patterns that are similar to those described in Tab l e 1 4 to be input at different points along the datapath. This allows the user to provide predictable output data on the serial link without it having been manipulated by the internal formatting logic. Refer to Ta ble 1 7 for additional information on the test modes available in Register 0x62.

Digital Output Word 2 (Default Twos Complement Format)

User data from Register 0x19 to Register 0x20

Subject to Data Format Select

Yes

Rev. A | Page 26 of 36

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AD9641

SERIAL PORT INTERFACE (SPI)

The AD9641 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memor y Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Tabl e 1 5 ). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an activelow control that enables or disables the read and write cycles.

Table 15. Serial Port Interface Pins

Pin Function

Serial clock. The serial shift clock input, which is used to

SCLK

synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that

SDIO

typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active-low control that gates the read

CSB

and write cycles.

CSB

HIGH

LOW

CLK

The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 70 and Tabl e 5.

Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode.

During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits.

In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.

All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

SCL

DON’T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7

Figure 70. Serial Port Interface Timing Diagram

Rev. A | Page 27 of 36

D5 D4 D3 D2 D1 D0

DON’T CARE

09210-049

Page 28

AD9641

HARDWARE INTERFACE

The pins described in Ta b l e 15 comprise the physical interface between the user programming device and the serial port of the AD9641. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.

The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Micro- controller-Based Serial Port Interface (SPI) Boot Circuit.

The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9641 to prevent these signals from transitioning at the converter inputs during critical sampling periods.

SPI ACCESSIBLE FEATURES

Tabl e 1 6 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9641 part-specific features are described in detail in the Reading the Memory Map Register Table section.

Table 16. Features Accessible Using the SPI

Feature Name Description

Mode

Clock

Offset

Tes t I /O

Full Scale

JESD204A Allows user to configure the JESD204A output

Allows the user to set either power-down mode or standby mode

Allows the user to access the DCS, set the clock divider, set the clock divider phase, and enable the sync

Allows the user to digitally adjust the converter offset

Allows the user to set test modes to have known data on output bits

Allows the user to set the input full-scale voltage

Rev. A | Page 28 of 36

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AD9641

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the transfer register (Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x3A); and the JESD204A configuration registers (Address 0x60 to Address 0x78).

The memory map register table (see Tab l e 1 7 ) lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the input span select register, has a hexadecimal default value of 0x00. This means that Bit 0 through Bit 4 = 0, and the remaining bits are 0s. This setting is the default reference selection setting. The default value uses a 1.75 V p-p reference. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF.

Open Locations

All address and bit locations that are not included in Tab l e 1 7 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written.

Default Values

After the AD9641 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Tab l e 1 7 .

Logic Levels

An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

• “Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 through Address 0x78 are shadowed. Writes to the addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and the bit autoclears.

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Tab l e 1 7 are not currently supported for this device.

Table 17. Memory Map Registers

Default

Addr

(Hex)

Name

Chip Configuration Registers 0x00

SPI port configuration

0x01 Chip ID

0x02 Chip grade Open Open Speed grade ID

Transfer Register 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00

Bit 7 (MSB)

0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

8-bit chip ID[7:0]

(AD9641 = 0x80)

(default)

Open Open Open Open 00 = 80 MSPS 10 = 155 MSPS

Bit 0 (LSB)

Value (Hex)

0x80 Read only

Default Notes/ Comments

Nibbles are mirrored so LSB- or MSBfirst mode registers correctly, regardless of shift mode

Speed grade ID used to differentiate devices; read only

Synchronous transfer of data from the master shift register to the slave

Rev. A | Page 29 of 36

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AD9641

Default

Addr

(Hex)

Name

ADC Functions 0x08

Power modes

0x09 Global clock Open Open Open Open Open Open Open

0x0A PLL status PLL locked Open Open Open Open Open Open Open 0x00 Read only. 0x0B Clock divide Open Open Input clock divider phase adjust

0x0D Test mode

0x0E BIST enable Open Open Open Open Open

0x10 Offset adjust Open Open

0x14

Output mode

0x15

Output adjust

0x18

Input span select

0x19

User Test Pattern 1 LSB

0x1A

User Test Pattern 1 MSB

0x1B

User Test Pattern 2 LSB

0x1C

User Test Pattern 2 MSB

0x1D

User Test Pattern 3 LSB

Bit 7 (MSB)

Open Open

User test mode control

0 = continuous/ repeat pattern

1 = single pattern

Open Open Open

Open Open Open Open Open Open Output drive level adjust

Open Open Open Full scale input voltage selection

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Open Open Open Internal power-down mode

000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles

Reset PN short gen

Offset adjust in LSBs from +31 to −32

Output disable

User Test Pattern 1, Bits[7:0] 0x00

User Test Pattern 1, Bits[15:8] 0x00

User Test Pattern 2, Bits[7:0] 0x00

User Test Pattern 2, Bits[15:8] 0x00

User Test Pattern 3, Bits[7:0] 0x00

Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one-/zero- word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output

(twos complement format)

Open

01111 = 2.087 V p-p

00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p

10000 = 1.383 V p-p

Clock divide ratio 000 = divide-by-1 001 = divide-by-2 010 = divide-by-3 011 = divide-by-4 100 = divide-by-5 101 = divide-by-6 110 = divide-by-7 111 = divide-by-8

Reset BIST sequence

Output invert

…

00 = normal operation 01 = full power-down 10 = standby 11 = reserved

Open BIST enable 0x00

Output format 00 = offset binary 01 = twos complement (default)

11 = 320 mV 00 = 400 mV

Open

External powerdown pin function

0 = PDWN 1 = STNDBY

Reset PN long gen

01 = Gray code 11 = offset binary

10 = 440 mV 01 = 500 mV

Bit 0 (LSB)

Duty cycle stabilizer (default)

Value (Hex)

0x00

0x01

0x00

0x01

0x00

Default Notes/ Comments

Determines various generic modes of chip operation.

Clock divide values other than 000 cause the duty cycle stabilizer to become active.

When this register is set, the test data is placed on the output pins in place of normal data.

Configures the outputs and the format of the data.

Full-scale input adjustment in 0.022 V steps.

Rev. A | Page 30 of 36

Page 31

AD9641

Addr

(Hex)

Name

0x1E

User Test Pattern 3 MSB

0x1F

User Test Pattern 4 LSB

0x20

User Test Pattern 4 MSB

0x21 PLL control Open Open Open Open

0x24

BIST signature LSB

0x25

BIST signature MSB

0x3A Sync control Open Open Open Open Open

JESD204A Configuration Registers 0x60

JESD204A Link Control Register 1

0x61

JESD204A Link Control Register 2

0x62

JESD204A Link Control Register 3

0x63

JESD204A Link Control Register 4

0x64

JESD204A device identification number (DID)

0x65

JESD204A bank identification number (BID)

0x66

JESD204A lane identification number (LID)

0x6E

JESD204A scrambler (SCR) and lane (L) configuration

Bit 7 (MSB)

Open

Local DSYNC mode 00 = individual mode

01 = global mode 10 = DSYNC active mode 11 = DSYNC pin disabled

Disable CHKSUM

Open Open Open Open JESD204A serial bank identification (BID) number 0x00

Open Open Open JESD204A serial lane identification (LID) number 0x00

Enable serial scrambler mode (SCR)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

User Test Pattern 3, Bits[15:8] 0x00

User Test Pattern 4, Bits[7:0] 0x00

User Test Pattern 4, Bits[15:8] 0x00

PLL low encode rate enable

BIST signature, Bits[7:0] 0x00 Read only.

BIST signature, Bits[15:8] 0x00 Read only.

Serial tail bit enable

Open

Open Open Open Open Open Open

Serial test sample enable

DSYNC pin input inverted

Link test generation

00 = 16-bit data injected

at sample input to the

01 = 10-bit data injected

at output of 8b/10b

Initial lane assignment sequence repeat count 0x00

JESD204A serial device identification (DID) number 0x00

Serial lane synchronization enable

CMOS DSYNC input

0 = LVDS 1 = CMOS

input selection

link

encoder 10 = reserved 11 = reserved

Serial lane alignment

sequence mode

00 = disabled 01 = enabled

10 = reserved

11 = always on

test mode

Open

Open Link test generation mode

Default Bit 0 (LSB)

Open Open Open 0x00

Clock divider next sync only

Bypass 8b/10b encoding

101 = user test pattern data continuous

110 = user test pattern data single

Clock divider sync enable

Frame alignment character insertion disable

Invert transmit bits

000 = normal operation

001 = alternating checkerboard

010 = 1/0 word toggle

011 = PN sequence, long

100 = PN sequence, short

111 = ramp output

Master sync buffer enable

Serial transmit link power- down

Mirror serial output bits

Serial lane control

0 = one lane per link (L = 1)

1 = reserved

Value

(Hex)

0x00

0x80

Default Notes/ Comments

Bit 3 must be enabled if the ADC clock rate is <60 MHz.

Rev. A | Page 31 of 36

Page 32

AD9641

Addr (Hex)

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

JESD204A number of octets per frame (F)

JESD204A number of frames per multiframe (K)

JESD204A number of converters per link per converter device (link) (M)

JESD 204A converter resolution (N) and control bits per sample (CS)

JESD204A total bits per sample (N’)

JESD204A samples per converter (S) per frame cycle

JESD204A HD and CF configuration

JESD204A Serial Reserved Field 1 (RES1)

JESD204A Serial Reserved Field 2 (RES2)

JESD204A checksum value for lane (FCHK)

Bit 7 (MSB)

Open Open Open JESD204A number of frames per multiframe (K) 0x0F

Open Open Open Open Open Open Open

Number of control bits per

00 = no control bits

01 = one control bit

10 = two control bits

Open Open Open Total number of bits per sample (N’) (read only) 0x0F Read only.

Open Open Open Samples per converter per frame cycle (S) (read only)

Enable HD (high density) format

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

JESD204A number of octets per frame (F)

(bits are calculated based on the equation F = (M × 2)/L)

Open Converter resolution (N) (read only) 0x4D

sample (CS)

(CS = 0)

(CS = 1)

(CS = 2)

11 = unused

Open Open

Serial Reserved Field 1 (RES1)

(these registers are available for customer use)

Serial Reserved Field 2 (RES2)

(these registers are available for customer use)

Serial checksum value for lane (FCHK) 0x00 Read only

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in Register 0x00 to Register 0x25, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

Sync Control (Address 0x3A)

Bits[7:3]—Open

Bit 2—Clock Divider Next Sync Only

If the master sync buffer enable bit (Address 0x3A, Bit 0) and the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it

Bit 0 (LSB)

Number of converters per link per device

0 = link connected to one ADC (M = 1) 1 = reserved

(always 1 for the AD9641)

Number of control words per frame clock cycle per link (CF)

(always 0 for the AD9641 (read only))

receives and to ignore the rest. The clock divider sync enable bit (Address 0x3A, Bit 1) resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 and Bit 0 are high. This is in continuous sync mode.

Bit 0—Master Sync Buffer Enable

Bit 0 must be high to enable any of the sync functions. If the sync capability is not used, this bit should remain low to conserve power.

Default Value (Hex)

0x01 Read only.

0x00 Read only.

0x00

Default Notes/ Comments

Rev. A | Page 32 of 36

Page 33

AD9641

JESD204A Link Control Register 1 (Address 0x60)

Bit 7—Open

Bit 6—Serial Tail Bit Enable

If this bit is set, unused tail bits are padded with a pseudo random number sequence from a 31-bit LFSR (see JESD204A 5.1.4).

Bit 5—Serial Test Sample Enable

If set, JESD204A test samples are enabled, and the transport layer test sample sequence (as specified in JESD204A section

5.1.6.2) sent on all link lanes.

Bit 4—Serial Lane Synchronization Enable

If this bit is set, lane synchronization is enabled. Both sides perform lane sync; frame alignment character insertion uses either /K28.3/ or /K28.7/ control characters (see JESD204A

5.3.3.4).

Bits[3:2]—Serial Lane Alignment Sequence Mode

00: initial lane alignment sequence disabled. 01: initial lane alignment sequence enabled. 10: reserved. 11: initial lane alignment sequence always on test mode; JESD204A data link layer test mode where repeated lane alignment sequence is sent on all lanes.

Bit 1—Frame Alignment Character Insertion Disable

If Bit 1 is set, the frame alignment character insertion is disabled per JESD204A section 5.3.3.4.

Bit 0—Serial Transmit Link Power-Down

If Bit 0 is set high, the serial transmit link is held in reset with its clock gated off. The JESD204A transmitter should be powered down when changing any of the link configuration bits.

JESD204A Link Control Register 2 (Address 0x61)

Bits[7:6]—Local DSYNC Mode

00: individual/separate mode. Each link is controlled by a separate DSYNC pin that independently controls code group synchronization.

01: global mode. Any DSYNC signal causes the link to begin code group synchronization.

10: DSYNC active mode. The DSYNC signal is active; force code group synchronization.

11: DSYNC pin disabled.

Bit 5—DSYNC Pin Input Inverted

If this bit is set, the DSYNC pin of the link is inverted (active high).

Bit 4—CMOS DSYNC Input

0: LVDS differential pair DSYNC input (default).

1: CMOS single-ended DSYNC input.

Bit 3—Open

Rev. A | Page 33 of 36

Bit 2—Bypass 8b/10b Encoding

If this bit is set, the 8b/10b encoding is bypassed and the most significant bits are set to 0.

Bit 1—Invert Transmit Bits

Setting this bit inverts the 10 serial output bits. This effectively inverts the output signals.

Bit 0—Mirror Serial Output Bits

Setting this bit reverses the order of the 10b outputs.

JESD204A Link Control Register 3 (Address 0x62)

Bit 7—Disable CHKSUM

Setting this bit high disables the CHKSUM configuration parameter. (For testing purposes only.)

Bit 6—Open

Bits[5:4]—Link Test Generation Input Selection

00: 16-bit test generation data injected at sample input to the link. 01: 10-bit test generation data injected at output of 8b/10b encoder (at input to PHY). 10: reserved. 11: reserved.

Bit 3—Open

Bits[2:0]—Link Test Generation Mode

000: normal operation (test mode disabled). 001: alternating checkerboard. 010: 1/0 word toggle. 011: PN sequence, long. 100: PN sequence, short. 101: continuous/repeat user test mode. The most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then repeated. (Output User Pattern 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4….) 110: single user test mode. The most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle, and then all zeros are output. (Output User Pattern 1, 2, 3, 4; then output all zeros.) 111: ramp output.

JESD204A Link Control Register 4 (Address 0x63)

Bits[7:0]—Initial Lane Alignment Sequence Repeat Count

Bits[7:0] specify the number of times the initial lane alignment sequence (ILAS) is repeated. If 0 is programmed, the ILAS does not repeat. If 1 is programmed, the ILAS repeats one time, and so on. See Register 0x60, Bits[3:2] to enable the ILAS and for a test mode to continuously enable the initial lane alignment sequence.

JESD204A Device Identification (DID) Number (Address 0x64)

Bits[7:0]—Serial Device Identification (DID) Number

Page 34

AD9641

JESD204A Bank Identification (BID) Number (Address 0x65)

Bits[7:4]—Open

Bits[3:0]—Serial Bank Identification (BID) Number

JESD204A Lane Identification (LID) Number (Address 0x66)

Bits[7:5]—Open

Bits[4:0]—Serial Lane Identification (LID) Number for Lane

JESD204A Scrambler (SCR) and Lane (L) Configuration (Address 0x6E)

Bit 7—Enable Serial Scrambler Mode (SCR)

Setting this bit high enables the scrambler (SCR = 1).

Bits[6:1]—Open.

Bit 0—Serial Lane Control.

0: one lane per link (L = 1). 1: 11111 = reserved.

JESD204A Number of Octets per Frame (Address 0x6F, Read Only)

Bits[7:0]—Number of Octets per Frame (F)

The readback from this register is calculated from the following equation: F = (M × 2)/L.

Valid values for F for the AD9641 are

F = 2, with M = 1 and L = 1

JESD204A Number of Frames per Multiframe (K) (Address 0x70)

Bits[7:5]—Open

Bits[4:0]—Number of Frames per Multiframe (K)

JESD204A Number of Converters per Converter Device (Link) (M) (Address 0x71)

Bits[7:1]—Open

Bit 0—Number of Converters per Converter Device (Link) (M)

0: link connected to one ADC. Only primary input used (M = 1).

1: reserved.

JESD204A Converter Resolution (N) and Control Bits per Sample (CS) (Address 0x72)

Bits[7:6]—Number of Control Bits per Sample (CS)

00: no control bits sent per sample (CS = 0).

01: one control bit sent per sample—overrange bit enabled (CS = 1).

10: two control bits sent per sample—overflow/underflow bits enabled (CS = 2).

11: unused.

Bit 5—Open

Bits [4:0]—Converter Resolution (N).

Read only bits showing the converter resolution (reads back 13 (0xD) for 14-bit resolution).

JESD204A Total Number of Bits per Sample (N’) (Address 0x73)

Bits[7:5]—Reserved

Bits[4:0]—Total Number of Bits per Sample (N’)

Read only bits showing the total number of bits per sample, minus 1 (reads back 15 (0xF) for 16 bits per sample).

JESD204A Samples per Converter per Frame Cycle (S) (Address 0x74)

Bits[7:5]—Open

Bits[4:0]—Samples per Converter per Frame Cycle (S)

Read only bits showing the number of samples per converter frame cycle, minus 1 (reads back 0 (0x0) for one sample per converter frame).

JESD204A HD and CF Configuration (Address 0x75)

Bit 7—High Density Format Enabled (Read Only)

Read only bit. Always 0 in the AD9641.

Bits[6:5]—Open

Bits[4:0]—Number of Control Words per Frame Clock Cycle per Converter Device (Link) (CF)

Read only bits. Reads back 0x0 for the AD9641.

JESD204A Serial Reserved Field 1 (Address 0x76)

Bits[7:0]—Serial Reserved Field 1 (RES1)

This read/write register is available for customer use.

JESD204A Serial Reserved Field 2 (Address 0x77)

Bits[7:0]—Serial Reserved Field 2 (RES2)

This read/write register is available for customer use.

JESD204A Serial Checksum Value for Lane (Address 0x78)

Bits[7:0]—Checksum Value for Lane

This read only register is automatically calculated for the lane. Sum (all link configuration parameters for the lane) MOD 256.

Rev. A | Page 34 of 36

Page 35

AD9641

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9641 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9641, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD), and use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different decoupling capacitors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9641. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the

AD9641 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection.

To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.

VCM

The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 50.

SPI Port

The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the

AD9641 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

Rev. A | Page 35 of 36

Page 36

AD9641

OUTLINE DIMENSIONS

PIN 1

INDICATOR

5.10

5.00 SQ

4.90

0.50

BSC

0.30

0.25

0.18

EXPOSED

PAD

3.75

3.60 SQ

3.55

0.80

0.75

0.70

SEATING

PLANE

0.50

0.40

0.30

0.05 MAX

0.02 NOM COPLANARITY

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION.

BOTTOM VIEWTOP VIEW

0.08

916

0.25 MIN

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

08-16-2010-B

Figure 71. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9641BCPZ-80 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641BCPZRL7-80 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641BCPZ-155 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641BCPZRL7-155 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9641-80KITZ Evaluation Board Kit AD9641-155KITZ Evaluation Board Kit

Z = RoHS Compliant Part.

Rev. A | Page 36 of 36

Datasheet AD9641 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ADC DC SPECIFICATIONS

ADC AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

EQUIVALENT CIRCUITS

THEORY OF OPERATION

ADC ARCHITECTURE

ANALOG INPUT CONSIDERATIONS

Input Common Mode

Differential Input Configurations

VOLTAGE REFERENCE

CLOCK INPUT CONSIDERATIONS

Clock Input Options

Input Clock Divider

Clock Duty Cycle

Jitter Considerations

CHIP SYNCHRONIZATION

POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS

JESD204A Transmit Top Level Description

Initial Frame Synchronization

Frame and Lane Alignment Monitoring and Correction

Digital Outputs and Timing

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

BUILT-IN SELF-TEST (BIST)

OUTPUT TEST MODES

SERIAL PORT INTERFACE (SPI)

CONFIGURATION USING THE SPI

HARDWARE INTERFACE

SPI ACCESSIBLE FEATURES

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Open Locations

Default Values

Logic Levels

Transfer Register Map

MEMORY MAP REGISTER TABLE

MEMORY MAP REGISTER DESCRIPTIONS

Sync Control (Address 0x3A)

Bits[7:3]—Open

Bit 2—Clock Divider Next Sync Only

Bit 1—Clock Divider Sync Enable

Bit 0—Master Sync Buffer Enable

JESD204A Link Control Register 1 (Address 0x60)

Bit 7—Open

Bit 6—Serial Tail Bit Enable

Bit 5—Serial Test Sample Enable

Bit 4—Serial Lane Synchronization Enable

Bits[3:2]—Serial Lane Alignment Sequence Mode

Bit 1—Frame Alignment Character Insertion Disable

Bit 0—Serial Transmit Link Power-Down

JESD204A Link Control Register 2 (Address 0x61)

Bits[7:6]—Local DSYNC Mode

Bit 5—DSYNC Pin Input Inverted

Bit 4—CMOS DSYNC Input

Bit 3—Open

Bit 2—Bypass 8b/10b Encoding

Bit 1—Invert Transmit Bits

Bit 0—Mirror Serial Output Bits

JESD204A Link Control Register 3 (Address 0x62)

Bit 7—Disable CHKSUM

Bit 6—Open