SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 87 dBc at 185 MHz A
−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A
250 MSPS
Total power consumption: 360 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 350 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy-saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
and 250 MSPS
IN
and
IN
1.8 V Analog-to-Digital Converter
AD9634
FUNCTIONAL BLOCK DIAGRAM
DDAGNDDRVDD
VIN+
VIN–
VCM
AD9634
REFERENCE
SCLK SDIOCSBCLK+CLK–
PIPELINE
12-BIT
ADC
SERIAL PORT
12
PAR ALL EL
DDR LVDS
AND
DRIVERS
1-TO-8
CLOCK DIVI DER
Figure 1.
D0±/D1±
.
.
.
D10±/D11±
DCO±
OR±
09996-001
GENERAL DESCRIPTION
The AD9634 is a 12-bit, analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The AD9634 is designed to
support communications applications where low cost, small size,
wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
The ADC output data are routed directly to the external 12-bit
LVDS out p ut p or t .
Flexible power-down options allow significant power savings,
when desired.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Programming for setup and control is accomplished using a
3-wire, SPI-compatible serial interface.
The AD9634 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This product
is protected by a U.S. patent.
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range,
DCS enabled, unless otherwise noted.
Table 1.
AD9634-170 AD9634-210 AD9634-250
Parameter Te mp e r at u r e
RESOLUTION Full 12 12 12 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±11 ±11 ±11 mV
Gain Error Full +2/−11 +1/−8 +3/−7 %FSR
Differential Nonlinearity (DNL) Full ±0.4 ±0.4 ±0.4 LSB
25°C ±0.22 ±0.22 ±0.22 LSB
Integral Nonlinearity (INL)1 Full ±0.4 ±0.4 ±0.6 LSB
25°C ±0.2 ±0.2 ±0.27 LSB
TEMPERATURE DRIFT
Offset Error Full ±7 ±7 ±7 ppm/°C
Gain Error Full ±55 ±58 ±75 ppm/°C
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 0.531 0.391 0.407 LSB rms
ANALOG INPUT
Input Span Full 1.75 1.75 1.75 V p-p
Input Capacitance2 Full 2.5 2.5 2.5 pF
Input Resistance3 Full 20 20 20 kΩ
Input Common-Mode Voltage Full 0.9 0.9 0.9 V
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Current
1
I
Full 123 134 129 139 136 145 mA
AVDD
1
I
Full 50 54 56 60 64 68 mA
DRVDD
POWER CONSUMPTION
Sine Wave Input (DRVDD = 1.8 V) Full 311 340 333 360 360 385 mW
Standby Power4 Full 50 50 50 mW
Power-Down Power Full 5 5 5 mW
1
Measured with a low input frequency, full-scale sine wave.
2
Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current Full 10 22 μA
Low Level Input Current Full −22 −10 μA
Input Capacitance Full 4 pF
Input Resistance Full 12 15 18 kΩ
LOGIC INPUT (CSB)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 50 71 μA
Low Level Input Current Full −5 +5 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 μA
Low Level Input Current Full −5 +5 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUTS (SDIO)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 μA
Low Level Input Current Full −5 +5 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS
LVDS Data and OR Outputs (OR+, OR−)
Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV
Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V
Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV
Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V
1
Pull-up.
2
Pull-down.
CMOS/LVDS/LVPECL
Full 0.9 V
Full 0.3 3.6 V p-p
Full AGND AVDD V
Full 0.9 1.4 V
Rev. 0 | Page 6 of 32
Page 7
AD9634
SWITCHING SPECIFICATIONS
Table 4.
AD9634-170 AD9634-210 AD9634-250
Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS1
Input Clock Rate Full 625 625 625 MHz
Conversion Rate2
DCS Enabled Full 40 170 40 210 40 250 MSPS
DCS Disabled Full 10 170 10 210 10 250 MSPS
CLK Period, Divide-by-1 Mode (t
CLK Pulse Width High (tCH)
Divide-by-8 Mode
Aperture Delay (tA) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms
DATA OUTPUT PARAMETERS1
Data Propagation Delay (tPD) Full 4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns
DCO Propagation Delay (t
DCO to Data Skew (t
DCO
) Full 0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns
SKEW
Pipeline Delay (Latency) Full 10 10 10 Cycles
Wake-Up Time (from Standby) Full 10 10 10 μs
Wake-Up Time (from Power-Down) Full 100 100 100 μs
Out-of-Range Recovery Time Full 3 3 3 Cycles
1
See . Figure 2
2
Conversion rate is the clock rate after the divider.
Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS See Figure 58 for the SPI timing diagram
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
t
Period of the SCLK 40 ns
CLK
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
t
Minimum period that SCLK should be in a logic high state 10 ns
HIGH
t
Minimum period that SCLK should be in a logic low state 10 ns
LOW
t
EN_SDIO
t
DIS_SDIO
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 58)
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 58)
10 ns
10 ns
Rev. 0 | Page 8 of 32
Page 9
AD9634
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2V
VCM to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.3 V
SCLK to AGND −0.3 V to DRVDD + 0.3 V
SDIO to AGND −0.3 V to DRVDD + 0.3 V
D0±/D1± through D10±/D11±
−0.3 V to DRVDD + 0.3 V
to AGND
DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V
OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V
Environmental
Operating Temperature Range
−40°C to +85°C
(Ambient)
Maximum Junction Temperature
150°C
Under Bias
Storage Temperature Range
−65°C to +125°C
(Ambient)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for the
LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints, maximizing
the thermal capability of the package.
Table 7. Thermal Resistance
Airflow
Package
Typ e
32-Lead LFCSP
5 mm × 5 mm
(CP-32-12)
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
Veloc ity
(m/sec) θ
1, 2
JA
1, 3
θ
JC
1, 4
θ
Unit
JB
0 37.1 3.1 20.7 °C/W
1.0 32.4 °C/W
2.0 29.1 °C/W
Typical θJA is specified for a 4-layer PCB with solid ground plane.
As shown in Ta b le 7 , airflow increases heat dissipation, which
reduces θ
. In addition, metal in direct contact with the package
JA
leads from metal traces, through holes, ground, and power
planes reduces the θ
.
JA
ESD CAUTION
Rev. 0 | Page 9 of 32
Page 10
AD9634
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVD D
AVD D
VIN+
VIN–
AVD D
AVD D
VCM
D6–/D7–
D6+/D7+
D8–/D9–
DNC
25
D8+/D9+
24
CSB
23
SCLK
SDIO
22
DCO+
21
20
DCO–
19
D10+/D11+ (MSB)
18
D10–/D11– (MSB)
DRVDD
17
09996-003
32313029282726
1
CLK+
2
CLK–
AVD D
3
4
5
6
7
8
AD9634
TOP VIEW
(Not to Scale)
9
10111213141516
D2–/D3–
D4–/D5–
D2+/D3+
D4+/D5+
OR–
OR+
D0–/D1– (LSB)
D0+/D1+ (LSB)
DRVDD
NOTES
1. DNC = DO NOT CONNE CT. DO NOT CONNECT TO T HIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM O F THE PACKAGE
PROVIDES THE ANALOG GRO UND FOR T HE PART. THIS EXPOSED
PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Type Description
ADC Power Supplies
8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal).
0
AGND, Exposed
Paddl e
Ground
Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed paddle
must be connected to ground for proper operation.
25 DNC Do No Connect. Do not connect to this pin.
ADC Analog
30 VIN+ Input Differential Analog Input Pin (+).
29 VIN− Input Differential Analog Input Pin (−).
26 VCM Output
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 μF capacitor.
1 CLK+ Input ADC Clock Input—True.
2 CLK− Input ADC Clock Input—Complement.
Digital Outputs
5 OR+ Output Overrange—True.
4 OR− Output Overrange—Complement.
7 D0+/D1+ (LSB) Output DDR LVDS Output Data 0/Data 1—True (LSB).
6 D0−/D1− (LSB) Output DDR LVDS Output Data 0/Data 1—Complement (LSB).
10 D2+/D3+ Output DDR LVDS Output Data 2/Data 3—True.
9 D2−/D3− Output DDR LVDS Output Data 2/Data 3—Complement.
12 D4+/D5+ Output DDR LVDS Output Data 4/Data 5—True.
11 D4−/D5− Output DDR LVDS Output Data 4/Data 5—Complement.
14 D6+/D7+ Output DDR LVDS Output Data 6/Data 7—True.
13 D6−/D7− Output DDR LVDS Output Data 6/Data 7—Complement.
16 D8+/D9+ Output DDR LVDS Output Data 8/Data 9—True.
15 D8−/D9− Output DDR LVDS Output Data 8/Data 9—Complement.
19 D10+/D11+ (MSB) Output DDR LVDS Output Data 10/Data 11—True (MSB).
18 D10−/ D11− (MSB) Output DDR LVDS Output Data 10/Data 11—Complement (MSB).
21 DCO+ Output LVDS Data Clock Output—True.
20 DCO− Output LVDS Data Clock Output—Complement.
Rev. 0 | Page 10 of 32
Page 11
AD9634
Pin No. Mnemonic Type Description
SPI Control
23 SCLK Input SPI Serial Clock.
22 SDIO Input/Output SPI Serial Data I/O.
24 CSB Input SPI Chip Select (Active Low).
Rev. 0 | Page 11 of 32
Page 12
AD9634
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input,
VIN = −1.0 dBFS, 32k sample, T
Figure 35. AD9634-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A
= 184.12 MHz, f
with f
IN1
0
250MSPS
89.12MHz @ –7.0dBFS
92.12MHz @ –7.0dBFS
–20
SFDR = 88dBc (95dBF S)
–40
–60
–80
AMPLIT UDE (dBF S)
–100
–120
–140
0125100755025
Figure 36. AD9634-250 Two-Tone FFT with f
= 187.12 MHz, fS = 250 MSPS
IN2
FREQUENCY (MHz)
= 89.12 MHz, f
IN1
IN2
09996-031
) with
IN
09996-032
)
IN
09996-033
= 92.12 MHz
Figure 37. AD9634-250 Two Tone FFT with f
0
250MSPS
184.12MHz @ –7.0dBFS
187.12MHz @ –7.0dBFS
–20
SFDR = 88dBc (95dBFS)
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
0110075502525
FREQUENC Y (MHz)
= 184.12 MHz, f
IN1
= 187.12 MHz
IN2
09996-034
100
95
90
85
80
75
SNR/SFDR (dBFS and dBc)
70
65
40 6080 100 120 140 160 180 200 220 240 260
Figure 38. AD9634-250 Single-Tone SNR/SFDR vs. Sample Rate (f
16000
0.407 LSB rms
16,384 TOTAL HITS
14000
12000
10000
8000
6000
NUMBER OF HITS
4000
2000
0
Figure 39. AD9634-250 Grounded Input Histogram, f
SFDR
SNR
SAMPLE RATE (MSPS)
= 90 MHz
with f
IN
N – 1NN + 1
OUTPUT CODE
= 250 MSPS
S
09996-035
)
S
09996-036
Rev. 0 | Page 17 of 32
Page 18
AD9634
A
V
A
V
R
V
A
V
EQUIVALENT CIRCUITS
DD
VIN
09996-037
Figure 40. Equivalent Analog Input Circuit
DD
DRVDD
SDIO
350Ω
26kΩ
Figure 43. Equivalent SDIO Circuit
09996-040
AVD DAVD D
CLK+
Figure 41. Equivalent Clock lnput Circuit
V+
DATAOUT–
Figure 42. Equivalent LVDS Output Circuit
15kΩ15kΩ
D
V–
0.9V
DD
V–
DATAOUT+
V+
CLK–
SCLK
09996-038
26kΩ
350Ω
09996-041
Figure 44. Equivalent SCLK Input Circuit
DD
26kΩ
CSB
09996-039
350Ω
09996-042
Figure 45. Equivalent CSB Input Circuit
Rev. 0 | Page 18 of 32
Page 19
AD9634
THEORY OF OPERATION
The AD9634 can sample any fS/2 frequency segment from dc to
250 MHz using appropriate low-pass or band-pass filtering at
the ADC inputs with little loss in ADC performance.
Programming and control of the AD9634 are accomplished
using a 3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9634 architecture consists of a front-end sample-andhold circuit, followed by a pipelined, switched-capacitor ADC.
The quantized outputs from each stage are combined into a
final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage contains a differential sampling circuit that can
be ac- or dc-coupled in differential or single-ended modes. The
output staging block aligns the data, corrects errors, and passes the
data to the output buffers. The output buffers are powered from a
separate supply, allowing digital output noise to be separated from
the analog core. During power-down, the output buffers go into
a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9634 is a differential switched-capacitor
circuit that has been designed to attain optimum performance
when processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 46).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within ½ clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article, “Tr an s fo r me r-
Coupled Front-End for Wideband A/D Converters” for more
information on this subject.
BIAS
VIN+
VIN–
C
C
PAR1
PAR1
S
C
S
C
PAR2
H
C
S
C
PAR2
S
Figure 46. Switched-Capacitor Input
BIAS
S
C
FB
S
C
S
FB
S
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD9634 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device so that V
= 0.5 × AVDD (or 0.9 V) is
CM
recommended for optimum performance. An on-board commonmode voltage reference is included in the design and is available
from the VCM pin. Using the VCM output to set the input
common mode is recommended. Optimum performance is
achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). The
VCM pin must be decoupled to ground by a 0.1 μF capacitor,
as described in the Applications Information section. Place this
decoupling capacitor close to the pin to minimize the series
resistance and inductance between the part and this capacitor.
09996-043
Rev. 0 | Page 19 of 32
Page 20
AD9634
V
Differential Input Configurations
Optimum performance can be achieved when driving the
AD9634 in a differential input configuration. For baseband
applications, the AD8138, ADA4937-1, and ADA4930-1
differential drivers provide excellent performance and a flexible
interface to the ADC.
The output common-mode voltage of the ADA4930-1 is easily
set with the VCM pin of the AD9634 (see Figure 47), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
15pF
200Ω
76.8Ω
IN
0.1µF
90Ω
ADA4930-1
120Ω
200Ω
33Ω
33Ω
5pF
15pF
15Ω
15Ω
VIN–
VIN+
AVD D
ADC
VCM
0.1µF
Figure 47. Differential Input Configuration Using the ADA4930-1
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 48. To bias the
analog input, connect the VCM voltage to the center tap of the
secondary winding of the transformer.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz. Excessive signal power can also cause
core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9634. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 49). In this
09996-044
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters
the value of the input resistors and capacitors may need to be
adjusted, or some components may need to be removed. Tabl e 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Tab l e 9 are for the
R1, R2, R3, C1, and C2 components shown in Figure 49.
C2
R3
R2
R1
C1
R1
R3
C2
VIN+
ADC
R2
VIN–
0.1µF
VCM
09996-045
Table 9. Example RC Network
Frequency Range (MHz) R1 Series (Ω) C1 Differential (pF) R2 Series (Ω) C2 Shunt (pF) R3 Shunt (Ω)
0 to 100 33 8.2 0 15 49.9
100 to 300 15 3.9 0 8.2 49.9
1. ALL I NDUCTORS ARE CO ILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz.
1000pF
180nH1000p
301Ω
180nH
220nH
5.1pF 3.9pF
220nH
Figure 50. Differential Input Configuration Using the AD8375
An alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone is to use an amplifier
with variable gain. The AD8375 digital variable gain amplifier
(DVGA) provides good performance for driving the AD9634.
Figure 50 shows an example of the AD8375 driving the AD9634
through a band-pass antialiasing filter.
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9634.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9634 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins by
means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 51) and require no
external bias. If the inputs are floated, the CLK− pin is pulled low
to prevent spurious clocking.
DD
0.9V
CLK+
Figure 51. Equivalent Clock Input Circuit
Clock Input Options
The AD9634 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL , or s i n e w ave sig n a l . R eg ard l es s
of the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 52 and Figure 53 show two preferable methods for clocking
the AD9634 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
CLK–
4pF4pF
09996-048
Rev. 0 | Page 21 of 32
165Ω
15pF
165Ω
VCM
1nF
68nH
2.5kΩ║2pF
AD9634
09996-047
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the secondary windings
of the transformer limit clock excursions into the AD9634 to
approximately 0.8 V p-p differential. This limit helps prevent the
large voltage swings of the clock from feeding through to other
portions of the AD9634, while preserving the fast rise and fall times
of the signal, which are critical for low jitter performance.
XFMR
25Ω
25Ω
®
390pF390pF
390pF
390pF
SCHOTTKY
DIODES:
HSMS2822
SCHOTTKY
DIODES:
HSMS2822
CLK+
CLK–
ADC
CLK+
CLK–
Mini-Circuits
ADT1-1WT, 1: 1Z
CLOCK
INPUT
50Ω
100Ω
Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)
CLOCK
390pF390pF
INPUT
1nF
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input pins
as shown in Figure 54. The AD9510, AD9511,AD9512, AD9513,
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
0.1µF
0.1µF
AD95xx
LVDS DRIVER
0.1µF
100Ω
0.1µF
CLK+
ADC
CLK–
Input Clock Divider
The AD9634 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios other than 1, the DCS is enabled by default on
power-up.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9634 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9634.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate may change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS loop
is relocked to the input signal. During the time that the loop is
not locked, the DCS loop is bypassed, and internal device timing
is dependent on the duty cycle of the input clock signal. In such
applications, it may be appropriate to disable the duty cycle
stabilizer. In all other applications, enabling the DCS circuit is
recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (f
SNR
) due to jitter (tJ) can be calculated by
IN
= −10 log[(2π × fIN × t
HF
)2 + 10]
JRMS
In the equation, the rms aperture jitter represents the rootmean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 56.
09996-052
80
75
70
65
SNR (dBFS)
60
55
50
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
1101001000
Figure 56. AD9634-250 SNR vs. Input Frequency and Jitter
INPUT FREQUENCY (MHz )
In cases where aperture jitter may affect the dynamic range of the
AD9634, treat the clock input as an analog signal. In addition,
use separate power supplies for the clock drivers and the ADC
output driver to avoid modulating the clock signal with digital
noise. Low jitter, crystal controlled oscillators provide the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or another method), it should be retimed by the
original clock during the last step.
Refer to AN-501 Application Note, Aperture Uncertainty and ADC
System Performance, and AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter, for more
information about jitter performance as it relates to ADCs.
)10/(LFSNR−
09996-054
Rev. 0 | Page 22 of 32
Page 23
AD9634
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the power dissipated by the AD9634 is
proportional to its sample rate. The data in Figure 57 was taken
using the same operating conditions as those used for the Typ ic al
Performance Characteristics section.
Figure 57. AD9634-250 Power and Current vs. Sample Rate
ENCODE FREQUENC Y (MSPS)
By setting the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 01, the AD9634 is placed
in power-down mode. In this state, the ADC typically dissipates
5 mW. During power-down, the output drivers are placed in a
high impedance state.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
0.25
0.20
0.15
0.10
SUPPLY CURRENT (A)
0.05
0
09996-053
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. To put the part into standby
mode, set the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 10. See the Memory
Map section and AN-877 Application Note, Interfacingto High Speed ADCs via SPI for additional details.
DIGITAL OUTPUTS
The AD9634 output drivers can be configured for either ANSI
LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.
As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD9634 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the SPI interface.
The data outputs can be three-stated by using the output enable
bar bit (Bit 4) in Register 0x14. This OEB function is not intended
for rapid access to the data bus.
Timing
The AD9634 provides latched data with a pipeline delay of 10 input
sample clock cycles. Data outputs are available one propagation
delay (t
Minimize the length of the output data lines as well as the loads
placed on these lines to reduce transients within the AD9634.
These transients may degrade converter dynamic performance.
The lowest typical conversion rate of the AD9634 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9634 also provides the data clock output (DCO) intended
for capturing the data in an external register. Figure 2 shows
timing diagram of the AD9634 output modes.
) after the rising edge of the clock signal.
PD
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock cycles. An overrange at the
input is indicated by this bit 10 clock cycles after it occurs.
The AD9634 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI offers
added flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that can
be further divided into fields. These fields are documented in the
Memory Map section. For detailed operational information, see
the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Tabl e 1 1 ). The SCLK (serial clock) pin
is used to synchronize the read and write data presented from
and to the ADC. The SDIO (serial data input/output) pin is a
dual-purpose pin that allows data to be sent and read from the
internal ADC memory map registers. The CSB (chip select bar)
pin is an active-low control that enables or disables the read and
write cycles.
Table 11. Serial Port Interface Pins
Pin Function
Serial clock. The serial shift clock input, which is used to
SCLK
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
SDIO
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active-low control that gates the read
CSB
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the serial
timing and its definitions can be found in Figure 58 and Tab l e 5 .
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode turns
on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSBfirst mode is the default on power-up and can be changed via
the SPI port configuration register. For more information about
this and other features, see the
Interfacing to High Speed ADCs via SPI.
AN-877 Application Note,
HARDWARE INTERFACE
The pins described in Ta b l e 11 comprise the physical interface
between the user programming device and the serial port of the
AD9634. The SCLK pin and the CSB pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9634 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Rev. 0 | Page 24 of 32
Page 25
AD9634
SPI ACCESSIBLE FEATURES
Tabl e 1 2 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail in
AN-877 Application Note, Interfacing to High Speed ADCs via
S
PI.
t
HIGH
t
LOW
t
CLK
CSB
t
DS
t
S
t
DH
Table 12. Features Accessible Using the SPI
Feature Name Description
Mode
Allows the user to set either power-down mode
or standby mode
Clock Allows the user to access the DCS via the SPI
Offset
Allows the user to digitally adjust the
converter offset
Tes t I /O
Allows the user to set test modes to have
known data on output bits
Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF Allows the user to set the reference voltage
Digital
Processing
Allows the user to enable the synchronization
features
t
H
SCLK
SDIO
DON’T CARE
R/WW1W0A12A11A10A9A8A7
Figure 58. Serial Port Interface Timing Diagram
D5D4D3D2D1D0
DON’T CARE
DON’T CAREDON’T CARE
09996-055
Rev. 0 | Page 25 of 32
Page 26
AD9634
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit
locations. The memory map is roughly divided into three
sections: the chip configuration registers (Address 0x00 to
Address 0x02), the transfer register (Address 0xFF), and the
ADC functions registers (Address 0x08 to Address 0x25),
including setup, control, and test.
The memory map register table (Ta bl e 13 ) documents the
default hexadecimal value for each hexadecimal address shown.
The Bit 7 (MSB) column is the start of the default hexadecimal
value given. For example, Address 0x14, the output mode register,
has a hexadecimal default value of 0x01. This means that Bit 0 = 1
and the remaining bits are 0s. This setting is the default output
format value, which is twos complement. For more information
on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details
the functions controlled by Register 0x00 to Register 0x25.
Open Locations
All address and bit locations that are not included in Tab l e 1 3
are not currently supported for this device. Write 0s to unused
bits of a valid address location. Writing to these locations is
required only when part of an address location is open (for
example, Address 0x18). If the entire address location is open
(for example, Address 0x13), do not write to this address location.
Default Values
After the AD9634 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Tabl e 1 3 ).
Logic Levels
An explanation of logic level terminology follows:
•“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
•“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x20 are shadowed. Writes to these
addresses do not affect part operation until a transfer command is
issued by writing 0x01 to Address 0xFF, setting the transfer bit. This
allows these registers to be updated internally and simultaneously
when the transfer bit is set. The internal update takes place
when the transfer bit is set, and then the bit autoclears.
Rev. 0 | Page 26 of 32
Page 27
AD9634
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Tab l e 1 3 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01 Chip ID 8-bit chip ID[7:0], AD9634 = 0x87 (default) 0x87 Read only.
0x02 Chip grade Open Open Speed grade ID;
Transfer Register
0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00
ADC Function Registers
0x08 Power modes Open Open Open Open Open Open Internal power-down mode
0x09 Global clock Open Open Open Open Open Open Open
0x0B Clock divide Open Open Input clock divider phase adjust
0x0D Test mode Test mode
Register
Name
SPI port
configuration
Bit 7
(MSB)
0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18
0 = continuous/
repeat
pattern
1 = single
pattern
then zeros
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Open Open Open Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Nibbles are
mirrored so
that LSBfirst mode
or MSB-first
mode is set
correctly,
regardless
of shift
mode.
Speed
grade ID
used to
differentiate
devices;
read only.
Synchronously
transfers
data from
the master
shift
register to
the slave.
Determines
various
generic
modes of
chip
operation.
Clock divide
values other
than 000
automatically
cause the
duty cycle
stabilizer to
become
active.
When this
register is
set, the test
data is
placed on
the output
pins in
place of
normal
data.
Rev. 0 | Page 27 of 32
Page 28
AD9634
Addr
Register
(Hex)
Name
0x0E BIST enable Open Open Open Open Open
0x10 Offset adjust Open Open
0x14 Output mode Open Open Open
0x15 Output adjust Open Open Open Open LVDS output drive current adjust
0x16
Clock phase
control
0x17
DCO output
delay
0x18
Input span
select
0x19
User Test
Pattern 1 LSB
0x1A
User Test
Pattern 1 MSB
0x1B
User Test
Pattern 2 LSB
0x1C
User Test
Pattern 2 MSB
0x1D
User Test
Pattern 3 LSB
0x1E
User Test
Pattern 3 MSB
0x1F
User Test
Pattern 4 LSB
0x20
User Test
Pattern 4 MSB
0x24
BIST signature
LSB
0x25
BIST signature
MSB
Bit 7
(MSB)
Invert
DCO clock
Enable
DCO
clock
delay
Open Open Open Full-scale input voltage selection
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Reset BIST
sequence
Offset adjust in LSBs from +31 to −32
(twos complement format)
Output
enable bar
0 = on
(default)
1 = off
Open Open Open Open Open Open Open 0x00
Open Open DCO clock delay
User Test Pattern 1[7:0]
User Test Pattern 1[15:8]
User Test Pattern 2[7:0]
User Test Pattern 2[15:8]
User Test Pattern 3[7:0]
User Test Pattern 3[15:8]
User Test Pattern 4[7:0]
User Test Pattern 4[15:8]
BIST signature[15:8] 0x00 Read only.
Open
0111 = 2.0 mA output drive current (reduced range)
BIST signature[7:0] 0x00 Read only.
Output
invert
0 = normal
(default)
1 =
inverted
0000 = 3.72 mA output drive current
0001 = 3.5 mA output drive current (default)
0010 = 3.30 mA output drive current
0011 = 2.96 mA output drive current
0100 = 2.82 mA output drive current
0101 = 2.57 mA output drive current
0110 = 2.27 mA output drive current
Configures
the outputs
and the
format of
the data.
Full-scale
input
adjustment
in 0.022 V
steps.
Rev. 0 | Page 28 of 32
Page 29
AD9634
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system-level design and layout of the AD9634, it
is recommended that the designer become familiar with these
guidelines, which describe the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9634, it is recommended that
two separate 1.8 V supplies be used: use one supply for analog
(AVDD) and a separate supply for digital outputs (DRVDD).
The designer can employ several different decoupling capacitors
to cover both high and low frequencies. Locate these capacitors
close to the point of entry at the PC board level and close to the
pins of the part with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9634. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should be connected
to the AD9634 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged with
nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only one
tie point between the ADC and the PCB. See the evaluation
board for a PCB layout example. For detailed information about
the packaging and PCB layout of chip scale packages, refer to
the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
VCM
Decouple the VCM pin to ground with a 0.1 μF capacitor, as
shown in Figure 48.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9634 to keep these signals from transitioning at the converter
input pins during critical sampling periods.
Rev. 0 | Page 29 of 32
Page 30
AD9634
OUTLINE DIMENSIONS
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
0.50
BSC
24
0.30
0.25
0.18
25
EXPOSED
PAD
1
P
N
32
I
R
C
A
O
T
N
I
D
*
3.75
3.60 SQ
3.55
I
1
8
9
0.25 MIN
FOR PROPER CONNE CTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-16-2010-B
0.80
0.75
0.70
SEATING
PLANE
17
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
16
BOTTOM VIEWTOP VI EW
0.08
Figure 59. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9634BCPZ-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZRL7-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZ-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZRL7-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZ-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZRL7-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634-170EBZ Evaluation Board with AD9634 and Software
AD9634-210EBZ Evaluation Board with AD9634 and Software
AD9634-250EBZ Evaluation Board with AD9634 and Software