Ultralow Distortion, Wide
–30
–130
100k 100M10M1M10k
–70
–50
–110
–90
FREQUENCY – Hz
HARMONIC DISTORTION – dBc
VO = 2V p–p
VS = ±5V
RL = 500Ω
2ND HARMONIC
3RD HARMONIC
1
2
3
4
8
7
6
5
AD9631/32
NC
–INPUT
+INPUT
–V
S
NC
+V
S
OUTPUT
NC
(Top View)
NC = NO CONNECT
a
Bandwidth Voltage Feedback Op Amps
FEATURES
Wide Bandwidth AD9631, G = +1 AD9632, G = +2
Small Signal 320 MHz 250 MHz
Large Signal (4 V p-p) 175 MHz 180 MHz
Ultralow Distortion (SFDR), Low Noise
–113 dBc typ @ 1 MHz
–95 dBc typ @ 5 MHz
–72 dBc typ @ 20 MHz
+46 dBm 3rd Order Intercept @ 25 MHz
7.0 nV/√
Hz Spectral Noise Density
High Speed
Slew Rate 1300 V/µs
Settling 16 ns to 0.01%, 2 V Step
±3 V to ±5 V Supply Operation
17 mA Supply Current
APPLICATIONS
ADC Input Driver
Differential Amplifiers
IF/RF Amplifiers
Pulse Amplifiers
Professional Video
DAC Current to Voltage
Baseband and Video Communications
Pin Diode Receivers
Active Filters/Integrators/Log Amps
AD9631/AD9632
FUNCTIONAL BLOCK DIAGRAM
8-Pin Plastic Mini-DIP (N), Cerdip (Q),
and SO (R) Packages
These characteristics position the AD9631/AD9632 ideally for
driving flash as well as high resolution ADCs. Additionally, the
balanced high impedance inputs of the voltage feedback architecture allow maximum flexibility when designing active filters.
The AD9631 is offered in industrial (–40°C to +85°C) and military (–55°C to +125°C) temperature ranges and the AD9632 in
industrial. Industrial versions are available in plastic DIP and
SOIC; MIL versions are packaged in cerdip.
PRODUCT DESCRIPTION
The AD9631 and AD9632 are very high speed and wide bandwidth amplifiers. They are an improved performance alternative
to the AD9621 and AD9622. The AD9631 is unity gain stable.
The AD9632 is stable at gains of two or greater. Utilizing a
voltage feedback architecture, the AD9631/AD9632’s exceptional settling time, bandwidth, and low distortion meet the
requirements of many applications which previously depended
on current feedback amplifiers. Its classical op amp structure
works much more predictably in many designs.
A proprietary design architecture has produced an amplifier that
combines many of the best characteristics of both current feedback and voltage feedback amplifiers. The AD9631 and
AD9632 exhibit exceptionally fast and accurate pulse response
(16 ns to 0.01%) as well as extremely wide small signal and
large signal bandwidth and ultralow distortion. The AD9631
achieves –72 dBc at 20 MHz and 320 MHz small signal and
175 MHz large signal bandwidths.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Figure 1. AD9631 Harmonic Distortion vs. Frequency,
G = +1
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD9631/AD9632–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(±VS = ±5 V; R
= 100 Ω; AV = 1 (AD9631); AV = 2 (AD9632), unless otherwise noted)
LOAD
AD9631A AD9632A
Parameter Conditions Min Typ Max Min Typ Max Units
DYNAMIC PERFORMANCE
Bandwidth (–3 dB)
Small Signal V
Large Signal
1
Bandwidth for 0.1 dB Flatness V
Slew Rate, Average +/– V
Rise/Fall Time V
≤ 0.4 V p-p 220 320 180 250 MHz
OUT
V
= 4 V p-p 150 175 155 180 MHz
OUT
= 300 mV p-p
OUT
9631, R
OUT
OUT
V
OUT
= 140 Ω; 9632, RF = 425 Ω 130 130 MHz
F
= 4 V Step 1000 1300 1200 1500 V/µs
= 0.5 V Step 1.2 1.4 ns
= 4 V Step 2.5 2.1 ns
Settling Time
To 0.1% V
To 0.01% V
= 2 V Step 11 11 ns
OUT
= 2 V Step 16 16 ns
OUT
HARMONIC/NOISE PERFORMANCE
2nd Harmonic Distortion 2 V p-p; 20 MHz, R
= 500 Ω –72 –65 –72 –65 dBc
R
L
3rd Harmonic Distortion 2 V p-p; 20 MHz, R
= 500 Ω –81 –74 –81 –74 dBc
R
L
= 100 Ω –64 –57 –54 –47 dBc
L
= 100 Ω –76 –69 –74 –67 dBc
L
3rd Order Intercept 25 MHz +46 +41 dBm
Noise Figure R
Input Voltage Noise 1 MHz to 200 MHz 7.0 4.3 nV√
Input Current Noise 1 MHz to 200 MHz 2.5 2.0 pA√
= 50 Ω 18 14 dB
S
Hz
Hz
Average Equivalent Integrated
Input Noise Voltage 0.1 MHz to 200 MHz 100 60 µV rms
Differential Gain Error (3.58 MHz) R
Differential Phase Error (3.58 MHz) R
= 150 Ω 0.03 0.06 0.02 0.04 %
L
= 150 Ω 0.02 0.04 0.02 0.04 Degree
L
Phase Nonlinearity dc to 100 MHz 1.1 1.1 Degree
2,
R
DC PERFORMANCE
Input Offset Voltage
3
= 150 Ω
L
T
MIN–TMAX
310 25 mV
13 8 mV
Offset Voltage Drift ±10 ±10 µV/°C
Input Bias Current 2 7 2 7 µA
T
MIN–TMAX
10 10 µA
Input Offset Current 0.1 3 0.1 3 µA
55µA
Common-Mode Rejection Ratio V
Open-Loop Gain V
T
MIN–TMAX
= ±2.5 V 70 90 70 90 dB
CM
= ±2.5 V 46 52 46 52 dB
OUT
T
MIN–TMAX
40 40 dB
INPUT CHARACTERISTICS
Input Resistance 500 500 kΩ
Input Capacitance 1.2 1.2 pF
Input Common-Mode Voltage Range ±3.4 ±3.4 V
OUTPUT CHARACTERISTICS
Output Voltage Range, R
= 150 Ω±3.2 ±3.9 ±3.2 ±3.9 V
L
Output Current 70 70 mA
Output Resistance 0.3 0.3 Ω
Short Circuit Current 240 240 mA
POWER SUPPLY
Operating Range ±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0 V
Quiescent Current 17 18 16 17 mA
T
Power Supply Rejection Ratio T
NOTES
1
See Max Ratings and Theory of Operation sections of data sheet.
2
Measured at AV = 50.
3
Measured with respect to the inverting input.
Specifications subject to change without notice.
MIN–TMAX
MIN–TMAX
50 60 56 66 dB
21 20 mA
–2–
REV. A
AD9631/AD9632
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Voltage Swing × Bandwidth Product . . . . . . . . . .550 V × MHz
Internal Power Dissipation
2
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . 0.9 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . .–65°C to +125°C
Operating Temperature Range (A Grade) . . . – 40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Pin Plastic Package: θ
8-Pin SOIC Package: θJA = 140°C/Watt
= 90°C/Watt
JA
METALIZATION PHOTO
Dimensions shown in inches and (mm).
Connect Substrate to –V
–IN
2
.
S
+V
S
7
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature
of the plastic, approximately +150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a
change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can
result in device failure.
While the AD9631 and AD9632 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0
8-PIN MINI-DIP PACKAGE
1.5
1.0
0.5
8-PIN SOIC PACKAGE
TJ = +150°C
0.046
(1.17)
0.046
(1.17)
MAXIMUM POWER DISSIPATION – Watts
OUT
0
–50 80
–40
6
0 10 –10 –20 –30 20 30 40 50 60 70
AMBIENT TEMPERATURE –
°
C
Figure 2. Plot of Maximum Power Dissipation vs.
90
Temperature
ORDERING GUIDE
0.050 (1.27)
AD9631
Temperature Package Package
+V
S
7
Model Range Description Option*
3
4
+IN
–V
S
–IN
2
AD9631AN –40C to +85°C Plastic DIP N-8
AD9631AR –40°C to +85°C SOIC R-8
AD9631(SMD) –55°C to +125°C Cerdip Q-8
AD9631-EB Evaluation
Board
OUT
6
AD9632AN –40°C to +85°C Plastic DIP N-8
AD9632AR –40°C to +85°C SOIC R-8
AD9632-EB Evaluation
Board
3
4
+IN
–V
S
AD9632
0.050 (1.27)
*N = Plastic DIP; Q = Cerdip; R= SOIC (Small Outline Integrated Circuit).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
AD9631–Typical Characteristics
AD9631/AD9632
R
F
10µF
S
0.1µF
7
6
0.1µF
4
10µF
S
RL = 100Ω
PUL SE
GENERATOR
TR/TF = 350ps
V
IN
R
49.9Ω
+V
2
130Ω
T
AD9631
3
–V
Figure 3. Noninverting Configuration, G = +1
R
F
10µF
S
0.1µF
6
0.1µF
10µF
S
V
OUT
RL = 100Ω
2
3
+V
7
AD9631
4
–V
PULSE
GENERATOR
TR/TF = 350ps
V
V
OUT
130Ω
IN
R
T
49.9Ω
100Ω
Figure 6. Inverting Configuration, G = –1
Figure 4. Large Signal Transient Response; VO = 4 V p-p,
G = +1, RF = 250
Ω
Figure 5. Small Signal Transient Response;
VO = 400 mV p-p, G = +1, RF = 140
Ω
Figure 7. Large Signal Transient Response; VO = 4 V p-p,
G = –1, RF = RIN = 267
Ω
Figure 8. Small Signal Transient Response;
VO = 400 mV p-p, G = –1, RF = R
= 267
IN
Ω
REV. A
–4–
AD9632–Typical Characteristics
AD9631/AD9632
R
F
PULSE
GENERATOR
TR/TF = 350ps
R
V
IN
R
T
49.9Ω
IN
130Ω
2
3
+V
7
AD9632
–V
10µF
S
0.1µF
6
0.1µF
4
10µF
S
RL = 100Ω
Figure 9. Noninverting Configuration, G = +2
R
F
10µF
S
0.1µF
6
0.1µF
10µF
S
V
OUT
RL = 100Ω
2
3
+V
7
AD9632
4
–V
PUL SE
GENERATOR
TR/TF = 350ps
R
T
49.9Ω
130Ω
100Ω
V
V
OUT
IN
Figure 12. Inverting Configuration, G= –1
Figure 10. Large Signal Transient Response; VO = 4 V p-p,
G = +2, RF = RIN = 422
Ω
Figure 11. Small Signal Transient Response;
VO = 400 mV p-p, G = +2, RF = RIN = 274
Ω
Figure 13. Large Signal Transient Response; VO = 4 V p-p,
G = –1, RF = RIN = 422 Ω, RT = 56.2
Ω
Figure 14. Small Signal Transient Response;
VO = 400 mV p-p, G = –1, RF = R
R
= 61.9
T
Ω
= 267 Ω,
IN
REV. A
–5–
AD9631–Typical Characteristics
VALUE OF FEEDBACK RESISTOR (RF) – Ω
–3dB BANDWIDTH – MHz
450
250
20 240
400
300
40
350
200 2201801601401201008060
N PACKAGE
R PACKAGE
R
F
130Ω
AD9631
VS = ±5V
R
L
= 100Ω
GAIN = +1
R
L
1
–4
–9
1M 10M 1G100M
–5
–6
–7
–8
–3
–2
–1
0
FREQUENCY – Hz
GAIN – dB
R
F
267Ω
VS = ±5V
R
L
= 100Ω
V
O
= 300mV p-p
AD9631/AD9632
1
0
–1
VS = ±5V
–2
R
= 100Ω
L
V
= 300mV p-p
O
–3
–4
–5
GAIN – dB
–6
–7
–8
–9
1M 10M 1G100M
R
50Ω
FREQUENCY – Hz
F
R
F
150Ω
R
F
100Ω
R
F
200Ω
Figure 15. AD9631 Small Signal Frequency Response
G = +1
0.1
0
–0.1
V
= ±5V
S
–0.2
–0.3
–0.4
–0.5
GAIN – dB
–0.6
–0.7
–0.8
–0.9
= 100Ω
R
L
G = +1
Vo = 300mV p-p
1M 10M 500M100M
R
F
100Ω
FREQUENCY – Hz
R
F
120Ω
R
F
150Ω
R
F
140Ω
Figure 18. AD9631 Small Signal –3 dB Bandwidth vs. R
1
0
–1
VS = ±5V
–2
–3
–4
–5
OUTPUT – dB
–6
–7
–8
–9
= 4V
V
p-p
O
= 100Ω
R
L
1M 10M 500M100M
RF = 50Ω
TO
250Ω BY 50Ω
FREQUENCY – Hz
R
F
250Ω
F
Figure 16. AD9631 0.1 dB Flatness, N Package (for R
Package Add 20
90
80
70
60
50
40
30
GAIN – dB
20
10
0
–10
–20
10k 100k 10M1M
Figure 17. AD9631 Open-Loop Gain and Phase Margin vs.
Frequency, RL = 100
REV. A
Ω
to RF)
GAIN
FREQUENCY – Hz
Ω
PHASE
100M 1G
100
80
60
40
20
0
–20
–40
–60
PHASE MARGIN – Degrees
–80
–100
–120
–6–
Figure 19. AD9631 Large Signal Frequency Response,
G = +1
Figure 20. AD9631 Small Signal Frequency Response,
G = –1
–30
0.10
–0.10
–0.05
0.00
0.05
DIFF GAIN – %
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
0.05
–0.05
0.00
0.10
DIFF PHASE – Degrees
–0.10
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
–50
–70
VO = 2V
= ±5V
V
S
R
= 500Ω
L
G = +1
AD9631/AD9632
p-p
–90
HARMONIC DISTORTION – dBc
–110
–130
100k 100M10M1M10k
2ND HARMONIC
3RD HARMONIC
FREQUENCY – Hz
Figure 21. AD9631 Harmonic Distortion vs. Frequency,
R
= 500
L
Ω
–30
VO = 2V p-p
V
= ±5V
–50
–70
–90
HARMONIC DISTORTION – dBc
–110
–130
S
R
= 100Ω
L
G = +1
100k 100M10M1M10k
2ND HARMONIC
3RD HARMONIC
FREQUENCY – Hz
Figure 24. AD9631 Differential Gain and Phase Error,
G = +2, RL = 150
0.3
0.2
0.1
0
ERROR – %
–0.1
–0.2
–0.3
0
Ω
SETTLING TIME – ns
80604020
70503010
Figure 22. AD9631 Harmonic Distortion vs. Frequency,
RL = 100
Figure 23. AD9631 Third Order Intercept vs. Frequency
REV. A
Ω
60
55
50
45
40
35
INTERCEPT – +dBm
30
25
20
10
20 40 8060
FREQUENCY – MHz
100
Figure 25. AD9631 Short-Term Settling Time, 2 V Step,
RL = 100
Ω
0.3
0.2
0.1
0
ERROR – %
–0.1
–0.2
1
SETTLING TIME – µs
80
Figure 26. AD9631 Long-Term Settling Time, 2 V Step,
RL = 100
Ω
–7–
109765432
AD9632–Typical Characteristics
AD9631/AD9632
7
6
5
VS = ±5V
4
3
2
GAIN – dB
1
0
–1
–2
–3
1M 10M 1G100M
= 100Ω
R
L
= 300mV p-p
V
O
R
F
125
FREQUENCY – Hz
R
225
R
F
325
R
F
425
F
Figure 27. AD9632 Small Signal Frequency Response,
G = +2
0.1
0
–0.1
–0.2
–0.3
–0.4
OUTPUT – dB
–0.5
–0.6
–0.7
–0.8
–0.9
1M 10M 100M
VS = ±5V
R
= 100Ω
L
G = +2
V
= 300mV p-p
O
FREQUENCY – Hz
275
R
F
325
R
F
375
R
F
425
R
F
49.9Ω
R
IN
AD9632
100Ω
N PACKAGE
R
F
R
L
550500450400350300250200150
350
300
250
200
–3dB BANDWIDTH – MHz
150
VS = ±5V
R
= 100Ω
L
GAIN = +2
R PACKAGE
100
VALUE OF RF,RIN – Ω
Figure 30. AD9632 Small Signal –3 dB Bandwidth
vs. R
, R
F
IN
7
R
6
5
4
3
2
1
OUTPUT – dB
0
–1
–2
–3
1M 10M 500M100M
VS = ±5V
= 4V p-p
V
O
= 100Ω
R
L
FREQUENCY – Hz
RF 125Ω
525Ω
100Ω
TO
BY
525
F
Figure 28. AD9632 0.1 dB Flatness, N Package
(for R Package Add 20 Ω to RF)
65
60
55
50
45
40
35
30
25
– dB
20
OL
A
15
10
5
0
–5
–10
–15
10k 100k 1G100M10M1M
GAIN
FREQUENCY – Hz
PHASE
100
50
0
–50
–100
–150
–200
–250
PHASE – Degrees
Figure 29. AD9632 Open-Loop Gain and Phase Margin vs.
Frequency, R
= 100
L
Ω
REV. A
Figure 31. AD9632 Large Signal Frequency Response,
G = +2
1
0
–1
–2
–3
–4
GAIN – dB
–5
–6
–7
–8
–9
VS = ±5V
R
= 100Ω
L
V
= 300mV p-p
O
1M 10M 1G100M
FREQUENCY – Hz
RF, R
267Ω
IN
Figure 32. AD9632 Small Signal Frequency Response,
G = –1
–8–
AD9631/AD9632
0.2
–0.3
0
–0.2
010 20
30
40 50 60 70 80
–0.1
0.1
SETTLING TIME – ns
ERROR – %
0.3
–0.2
0.1
–0.1
0987654321
0
0.2
SETTLING TIME – µs
ERROR – %
10
–30
VO = 2V p-p
V
–50
–70
–90
HARMONIC DISTORTION – dBc
–110
–130
= ±5V
S
R
= 500Ω
L
G = +2
2ND HARMONIC
3RD HARMONIC
100k 100M10M1M10k
FREQUENCY – Hz
Figure 33. AD9632 Harmonic Distortion vs. Frequency,
RL = 500
–30
–50
–70
Ω
VO = 2V p-p
V
= ±5V
S
= 100Ω
R
L
G = +2
2ND HARMONIC
0.04
0.02
0.00
–0.02
DIFF GAIN – %
–0.04
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
0.04
0.02
0.00
–0.02
–0.04
DIFF PHASE – Degrees
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
Figure 36. AD9632 Differential Gain and Phase Error
G = +2, R
= 150
L
Ω
–90
HARMONIC DISTORTION – dBc
–110
–130
100k 100M10M1M10k
FREQUENCY – Hz
Figure 34. AD9632 Harmonic Distortion vs. Frequency,
RL = 100
Ω
50
45
40
35
30
25
INTERCEPT – +dBm
20
15
10
10 100
FREQUENCY – MHz
Figure 35. AD9632 Third Order Intercept vs. Frequency
3RD HARMONIC
Figure 37. AD9632 Short-Term Settling Time 2 V Step,
RL = 100
Ω
Figure 38. AD9632 Long-Term Settling Time 2 V Step,
R
= 100
L
Ω
REV. A
–9–
17
13
3
100 100k10k1k10
15
9
11
5
7
FREQUENCY – Hz
INPUT NOISE VOLTAGE – nV/√Hz
VS = ±5V
AD9631/AD9632–Typical Characteristics
24
21
18
15
12
9
INPUT NOISE VOLTAGE – nV/√Hz
6
3
100 100k10k1k10
FREQUENCY – Hz
VS = ±5V
Figure 39. AD9631 Noise vs. Frequency
80
75
70
65
+PSRR
60
55
50
45
40
35
PSRR – dB
30
25
20
15
10
5
0
10k 100k 1G100M10M1M
–PSRR
FREQUENCY – Hz
Figure 42. AD9632 Noise vs. Frequency
80
75
70
65
+PSRR
60
55
50
45
40
35
PSRR – dB
30
25
20
15
10
5
0
10k 100k 1G100M10M1M
–PSRR
FREQUENCY – Hz
Figure 40. AD9631 PSRR vs. Frequency
100
90
80
70
60
CMRR – dB
50
40
30
20
100k 1G100M10M1M
Figure 41. AD9631 CMRR vs. Frequency
FREQUENCY – Hz
VS = ±5V
∆V
= 1V
CM
= 100Ω
R
L
–10–
Figure 43. AD9632 PSRR vs. Frequency
100
90
80
70
60
CMRR – dB
50
40
30
20
100k 1G100M10M1M
FREQUENCY – Hz
VS = ±5V
∆V
= 1V
CM
R
= 100Ω
L
Figure 44. AD9632 CMRR vs. Frequency
REV. A
AD9631/AD9632
–98
–86
140
–92
–88
–40
–90
–60
–96
–94
120806040 100200–20
JUNCTION TEMPERATURE – °C
CMRR – –dB
–CMRR
+CMRR
1000
VS = ±5V
GAIN = +1
100
10
– Ω
OUT
R
1
0.1
0.01
100k 100M10M1M10k
FREQUENCY – Hz
Figure 45. AD9631 Output Resistance vs. Frequency
1000
VS = ±5V
GAIN = +2
100
10
– Ω
OUT
R
1
0.1
0.01
100k 100M10M1M10k
FREQUENCY – Hz
1350
1250
1150
1050
950
850
750
650
OPEN-LOOP GAIN – V/V
550
450
350
–40
–60
JUNCTION TEMPERATURE – °C
AD9632
AD9631
+A
OL
–A
OL
+A
OL
–A
OL
140
120100806040200–20
Figure 48. Open-Loop Gain vs. Temperature
76
74
72
70
68
66
64
PSRR – –dB
62
60
58
56
–40
–60
JUNCTION TEMPERATURE – °C
–PSRR
+PSRR
–PSRR
+PSRR
AD9632
AD9632
AD9631
AD9631
120100806040200–20
140
Figure 46. AD9632 Output Resistance vs. Frequency
4.1
VS = ±5V
4.0
3.9
3.8
3.7
3.6
OUTPUT SWING – Volts
3.5
3.4
3.3
–40–60
JUNCTION TEMPERATURE – °C
+V
OUT
|–V
|
OUT
+V
OUT
|–V
|
OUT
}
RL = 150
}
RL = 50
120100806040200–20
140
Figure 47. AD9631/AD9632 Output Swing vs. Temperature
Figure 49. PSRR vs. Temperature
Figure 50. AD9631/AD9632 CMRR vs. Temperature
REV. A
–11–
AD9631/AD9632–Typical Characteristics
250
180
140
210
190
–40
200
–60
240
220
230
120100806040200–20
JUNCTION TEMPERATURE – °C
SHORT CIRCUIT CURRENT – mA
AD9631
AD9632
SINK
SOURCE
SINK
SOURCE
2.0
–2.0
140
–1.0
–1.5
–40–60
0.0
–0.5
0.5
1.0
1.5
120100806040200–20
JUNCTION TEMPERATURE – °C
INPUT BIAS CURRENT – µA
AD9631
AD9632
+I
B
+I
B
–I
B
–I
B
21
20
±6V
AD9631
19
18
17
16
SUPPLY CURRENT – mA
15
14
–40
–60
JUNCTION TEMPERATURE – °C
±6V
±5V
±5V
AD9632
AD9631
AD9632
120100806040200–20
Figure 51. Supply Current vs. Temperature
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
INPUT OFFSET VOLTAGE – mV
–4.5
–5.0
–40–60
JUNCTION TEMPERATURE – °C
AD9632
AD9631
VS = ±5V
VS = ±6V
VS = ±5V
VS = ±6V
120100806040200–20
140
Figure 54. Short Circuit Current vs. Temperature
140
Figure 52. Input Offset Voltage vs. Temperature
220
3 WAFER LOTS
200
COUNT = 1373
180
160
140
120
100
COUNT
FREQ. DIST
80
60
20
0
–640–7
Figure 53. AD9631 Input Offset Voltage Distribution
INPUT OFFSET VOLTAGE – mV
CUMULATIVE
100
90
80
70
60
50
40
30
20
10
0
54321–1–2–3–4–5 0
6
7
PERCENT
–12–
Figure 55. Input Bias Current vs. Temperature
180
160
140
120
100
80
COUNT
60
20
0
3 WAFER LOTS
COUNT = 573
FREQ. DIST
–640–7
INPUT OFFSET VOLTAGE – mV
CUMULATIVE
100
90
80
70
60
50
PERCENT
40
30
20
10
0
54321–1–2–3–4–5 0
7
6
Figure 56. AD9632 Input Offset Voltage Distribution
REV. A
AD9631/AD9632
R
F
V
OUT
AD9631
C
F
C
I
I
I
THEORY OF OPERATION
General
The AD9631 and AD9632 are wide bandwidth, voltage feedback amplifiers. Since their open-loop frequency response follows the conventional 6 dB/octave roll-off, their gain bandwidth
product is basically constant. Increasing their closed-loop gain
results in a corresponding decrease in small signal bandwidth.
This can be observed by noting the bandwidth specification
between the AD9631 (gain of 1) and AD9632 (gain of 2). The
AD9631/AD9632 typically maintain 65 degrees of phase margin. This high margin minimizes the effects of signal and noise
peaking.
Feedback Resistor Choice
The value of the feedback resistor is critical for optimum performance on the AD9631 (gain +1) and less critical as the gain increases. Therefore, this section is specifically targeted at the
AD9631.
At minimum stable gain (+1), the AD9631 provides optimum
dynamic performance with R
= 140 Ω. This resistor acts only
F
as a parasitic suppressor against damped RF oscillations that
can occur due to lead (input, feedback) inductance and parasitic
capacitance. This value of R
provides the best combination of
F
wide bandwidth, low parasitic peaking, and fast settling time.
In fact, for the same reasons, a 100–130 Ω resistor should be
placed in series with the positive input for other AD9631
noninverting and all AD9631 inverting configurations. The correct connection is shown in Figures 57 and 58.
3
AD9631/32
2
R
G
+V
S
10µF
0.1µF
7
6
4
0.1µF
10µF
V
OUT
R
F
R
F
G = 1 +
R
G
IN
R
TERM
100–130Ω
R
IN
V
+V
R
F
G = –
R
G
100–130Ω
R
IN
R
R
G
TERM
V
IN
S
7
3
AD9631/32
2
4
–V
S
10µF
0.1µF
0.1µF
10µF
6
V
OUT
R
F
Figure 58. Inverting Operation
When the AD9631 is used in the transimpedance (I to V) mode,
such as in photodiode detection, the value of R
pacitance (C
) are usually known. Generally, the value of RF se-
I
lected will be in the kΩ range, and a shunt capacitor (C
will be required to maintain good amplifier stability. The
R
F
value of C
required to maintain optimal flatness (<1 dB Peak-
F
and diode ca-
F
) across
F
ing) and settling time can be estimated as:
1/2
2
C
≅ (2 ω
F
[]
where ω
is equal to the unity gain bandwidth product of the
O
amplifier in rad/sec, and C
–1)/ω
OCIRF
is the equivalent total input
I
capacitance at the inverting input. Typically ω
2
R
O
F
= 800 × 10
O
6
rad/sec (see Open-Loop Frequency Response curve (Figure 17).
As an example, choosing R
to be 1.1 pF (Note: CI includes both source and parasitic
C
F
= 10 kΩ and C
F
= 5 pF, requires
I
circuit capacitance). The bandwidth of the amplifier can be estimated using the C
calculated as:
F
f
≅
3 dB
2 πR
1. 6
FCF
–V
S
Figure 57. Noninverting Operation
Figure 59. Transimpedance Configuration
REV. A
–13–
AD9631/AD9632
R
F
R
SERIES
R
L
1kΩ
C
L
R
IN
AD9631/32
R
IN
40
0
25
30
10
5
20
15 2010
R
SERIES
– Ω
CL – pF
For general voltage gain applications, the amplifier bandwidth
can be closely estimated as:
ω
f
≅
3 dB
2π 1+
O
R
F
R
G
This estimation loses accuracy for gains of +2/–1 or lower due
to the amplifier’s damping factor. For these “low gain” cases,
the bandwidth will actually extend beyond the calculated value
(see Closed-Loop BW plots, Figures 15 and 27).
As a rule of thumb, capacitor C
(R
F
will not be required if:
F
i
R
)×CI≤
G
NG
4 ω
O
where NG is the Noise Gain (1 + RF/RG) of the circuit. For
most voltage gain applications, this should be the case.
Pulse Response
Unlike a traditional voltage feedback amplifier, where the slew
speed is dictated by its front end dc quiescent current and gain
bandwidth product, the AD9631 and AD9632 provide “on demand” current that increases proportionally to the input “step”
signal amplitude. This results in slew rates (1300 V/µs) compa-
rable to wideband current feedback designs. This, combined
with relatively low input noise current (2.0 pA/√
Hz), gives the
AD9631 and AD9632 the best attributes of both voltage and
current feedback amplifiers.
Large Signal Performance
The outstanding large signal operation of the AD9631 and
AD9632 is due to a unique, proprietary design architecture.
In order to maintain this level of performance, the maximum
550 V-MHz product must be observed, (e.g., @ 100 MHz,
≤ 5.5 V p-p).
V
O
Power Supply Bypassing
Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of at
least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended.
Some brands of electrolytic capacitors will require a small series
damping resistor ≈4.7 Ω for optimum results.
Driving Capacitive Loads
The AD9631 and AD9632 were designed primarily to drive
nonreactive loads. If driving loads with a capacitive component
is desired, the best frequency response is obtained by the addition of a small series resistance as shown in Figure 60. The accompanying graph shows the optimum value for R
SERIES
vs.
capacitive load. It is worth noting that the frequency response of
the circuit when driving large capacitive loads will be dominated
by the passive roll-off of R
SERIES
and CL.
Figure 60. Driving Capacitive Loads
Figure 61. Recommended R
–14–
REV. A
vs. Capacitive Load
SERIES
AD9631/AD9632
1
5
V
IN
R4
154Ω
C1
50p F
C2
100pF
R1
154Ω
AD9632
R3
78.7Ω
0.1µF
+5V
–5V
0.1µF
7
3
2
4
100Ω
6
V
OUT
10µF
10µF
APPLICATIONS
The AD9631 and AD9632 are voltage feedback amplifiers well
suited for such applications as photodetectors, active filters, and
log amplifiers. The devices’ wide bandwidth (320 MHz), phase
margin (65°), low noise current (2.0 pA/√
Hz), and slew rate
(1300 V/µs) give higher performance capabilities to these appli-
cations over previous voltage feedback designs.
With a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the
devices are an excellent choice for DAC I/V conversion. The
same characteristics along with low harmonic distortion make
them a good choice for ADC buffering/amplification. With superb linearity at relatively high signal frequencies, the AD9631
and AD9632 are ideal drivers for ADCs up to 12 bits.
Operation as a Video Line Driver
The AD9631 and AD9632 have been designed to offer outstanding performance as video line drivers. The important
specifications of differential gain (0.02%) and differential phase
(0.02°) meet the most exacting HDTV demands for driving
video loads.
274Ω
75Ω
CABLE
V
IN
75Ω
2
AD9631/
AD9632
3
+V
–V
274Ω
S
7
4
S
10µF
0.1µF
0.1µF
10µF
75Ω
CABLE
6
75Ω
75Ω
V
OUT
Figure 62. Video Line Driver
Active Filters
The wide bandwidth and low distortion of the AD9631 and
AD9632 are ideal for the realization of higher bandwidth active
filters. These characteristics, while being more common in many
current feedback op amps, are offered in the AD9631 and AD9632
in a voltage feedback configuration. Many active filter configurations are not realizable with current feedback amplifiers.
A multiple feedback active filter requires a voltage feedback
amplifier and is more demanding of op amp performance than
other active filter configurations such as the Sallen-Key. In
general, the amplifier should have a bandwidth that is at least
ten times the bandwidth of the filter if problems due to phase
shift of the amplifier are to be avoided.
Figure 63 is an example of a 20 MHz low pass multiple feedback active filter using an AD9632.
Figure 63. Active Filter Circuit
Choose:
F
= Cutoff Frequency = 20 MHz
O
α = Damping Ratio = 1/Q = 2
H = Absolute Value of Circuit Gain =
Then:
k =2 π F
4 C1(H +1)
C2 =
R1 =
R3 =
R 4 = H(R1)
α
2 HK
2 K (H +1)
–R4
= 1
R1
C1
O
2
α
α
–15–
REV. A
A/D Converter Driver
As A/D converters move toward higher speeds with higher resolutions, there becomes a need for high performance drivers that
will not degrade the analog signal to the converter. It is desirable from a system’s standpoint that the A/D be the element in
the signal chain that ultimately limits overall distortion. This
places new demands on the amplifiers used to drive fast, high
resolution A/Ds.
+5V ANALOG
4
5
1
2
27
28
26
0.1µF
AV
AGND
V
V
REF GND
REF IN
REF OUT
ANALOG IN
130Ω
+5V ANALOG
140Ω
1
2
AD9631
3
4
–5V
ANALOG
7
5
0.1µF
0.1µF
10µF
0.1µF
6
0.1µF
10µF
1µF
AD9631/AD9632
With high bandwidth, low distortion and fast settling time the
AD9631 and AD9632 make high performance A/D drivers for
advanced converters. Figure 64 is an example of an AD9631
used as an input driver for an AD872. A 12-bit, 10 Msps A/D
converter.
+5V DIGITAL
10Ω
0.1µF
+5V DIGITAL
0.1µF
CLOCK INPUT
49.9Ω
DIGITAL OUTPUT
DD
INA
INB
AV
AD872
SS
3
DV
DGND
DRV
DRGND
BIT10
BIT11
BIT12
AGND
AV
SS
CLK
OTR
MSB
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
25
DD
DD
0.1µF
7
6
22
23
21
20
19
18
17
16
15
14
13
12
11
10
9
8
24
REV. A
–5V ANALOG
Figure 64. AD9631 Used as Driver for an AD872, a 12-Bit, 10 Msps A/D Converter
–16–
R
F
R
O
IN
+V
S
–V
S
R
S
R
T
R
G
OUT
C1
1000pF
C3
0.1µF
C5
10µF
C2
1000pF
C4
0.1µF
C6
10µF
+V
S
–V
S
OPTIONAL
R
F
R
O
IN
+V
S
–V
S
R
T
R
G
OUT
R
S
Layout Considerations
The specified high speed performance of the AD9631 and
AD9632 requires careful attention to board layout and component selection. Proper RF design techniques and low pass parasitic component selection are mandatory.
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for the supply bypassing (see
Figure 64). One end should be connected to the ground plane
and the other within 1/8 inch of each power pin. An additional
large (0.47 µF–10 µF) tantalum electrolytic capacitor should be
connected in parallel, though not necessarily so close, to supply
current for fast, large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end.
Evaluation Board
An evaluation board for both the AD9631 and AD9632 is available that has been carefully laid out and tested to demonstrate
that the specified high speed performance of the device can be
realized. For ordering information, please refer to the Ordering
Guide.
The layout of the evaluation board can be used as shown or
serve as a guide for a board layout.
AD9631/AD9632
Inverting Configuration
Noninverting Configuration
Supply Bypassing
Figure 65. Inverting and Noninverting Configurations for
Evaluation Boards
Table I.
AD9631A AD9632A
Gain Gain
Component –1 +1 +2 +10 +100 –1 +2 +10 +100
R
F
R
G
(Nominal) 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 100 Ω 100 Ω 49.9 Ω 49.9 Ω
R
O
R
S
(Nominal) 61.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 61.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω
R
T
Small Signal
BW (MHz) 90 320 90 10 1.3 250 250 20 3
274 Ω 140 Ω 274 Ω 2 kΩ 2 kΩ 274 Ω 274 Ω 2 kΩ 2 kΩ
274 Ω 274 Ω 221 Ω 20.5 Ω 274 Ω 274 Ω 221 Ω 20.5 Ω
100 Ω 130 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω
REV. A
–17–
AD9631/AD9632
DIP (N)
INVERTER
SOIC (R)
INVERTER
Figure 66. Evaluation Board Silkscreen (Top)
DIP (N)
NONINVERTER
SOIC (R)
NONINVERTER
DIP (N)
INVERTER
SOIC (R)
INVERTER
Figure 67. Board Layout (Solder Side)
DIP (N)
NONINVERTER
SOIC (R)
NONINVERTER
REV. A
–18–
AD9631/AD9632
DIP (N)
INVERTER
SOIC (R)
INVERTER
Figure 68. Board Layout (Component Side)
DIP (N)
NONINVERTER
SOIC (R)
NONINVERTER
REV. A
–19–
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic DIP
(N Package)
58
0.280 (7.11)
0.240 (6.10)
0.100
(2.54)
BSC
4
0.070 (1.77)
0.045 (1.15)
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
1
0.430 (10.92)
0.348 (8.84)
8-Pin Plastic SOIC
(R Package)
0.150 (3.81)
0.195 (4.95)
0.115 (2.93)
AD9631/AD9632
C1936a–2.5–11/94
0.244 (6.20)
0.228 (5.79)
0.010 (0.25)
0.004 (0.10)
8
PIN 1
1
0.197 (5.01)
0.189 (4.80)
0.050
(1.27)
BSC
0.005 (0.13) MIN 0.055 (1.4) MAX
PIN 1
1
0.405 (10.29) MAX
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
5
0.157 (3.99)
0.150 (3.81)
4
0.102 (2.59)
0.094 (2.39)
0.019 (0.48)
0.014 (0.36)
8-Pin Cerdip
(Q Package)
0.070 (1.78)
0.100
(2.54)
0.030 (0.76)
BSC
0.098 (0.2482)
0.075 (0.1905)
58
0.310 (7.87)
0.220 (5.59)
4
0.060 (1.52)
0.015 (0.38)
0.020 (0.051) x 45
CHAMF
8
°
0
°
0.150
(3.81)
MIN
SEATING
PLANE
0.190 (4.82)
0.170 (4.32)
10
°
0
°
0.320 (8.13)
0.290 (7.37)
°
0.015 (0.38)
0.008 (0.20)
15
°
0
°
0.030 (0.76)
0.018 (0.46)
0.090
(2.29)
PRINTED IN U.S.A.
REV. A
–20–
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