Datasheet AD9608 Datasheet (ANALOG DEVICES)

Page 1

10-Bit, 125/105 MSPS, 1.8 V Dual

FEATURES

1.8 V analog supply operation

1.8 V CMOS or 1.8 V LVDS output SNR = 61.7 dBFS at 70 MHz SFDR = 85 dBc at 70 MHz Low power: 71 mW/channel ADC core at 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.13 LSB Serial port control options

Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data

alignment

APPLICATIONS

Communications Diversity radio systems I/Q demodulation systems Broadband data applications Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound

Analog-to-Digital Converter (ADC)

AD9608

FUNCTIONAL BLOCK DIAGRAM

DCS

SPI

CSB

MUX OPTION

CONTROLS

PDWN DFSCLK+ CLK–

MODE

CMOS/LVDS

OEB

ORA

D9A

D0A

OUTPUT BUFFER

DCOA

DRVDD

ORB

D9B

D0B

OUTPUT BUFFER

DCOB

GND

DD SCLK

VIN+A

VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B

VIN+B

NOTES

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES.

REF

SELECT

ADC

DIVIDE 1TO 8

SYNC

SDIO

PROGRAMMING DATA

AD9608

DUTY CYCLE

STABILIZER

Figure 1.

PRODUCT HIGHLIGHTS

1. Operates from a single 1.8 V analog power supply and

features a separate digital output driver supply to accommodate 1.8 V CMOS or 1.8 V LVDS logic families.

2. Provides a patented sample-and-hold circuit that maintains

excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.

3. Includes a standard serial port interface that supports various

product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing, and offset adjustments.

4. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin

compatible with the AD9650, AD9269, and AD9268 16-bit ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628 and AD9231 12-bit ADCs, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.

09977-001

This product is protected by a U.S. patent.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

AD9608

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications..................................................................................... 4

DC Specifications........................................................................... 4

AC Specifications........................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications ................................................................ 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings.......................................................... 10

Thermal Characteristics ............................................................10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Typical Performance Characteristics ........................................... 17

AD9608-125 ................................................................................ 17

AD9608-105 ................................................................................ 20

Equivalent Circuits......................................................................... 22

Theory of Operation ...................................................................... 23

ADC Architecture ......................................................................23

Analog Input Considerations.................................................... 23

Voltage Reference....................................................................... 25

Clock Input Considerations...................................................... 26

Channel/Chip Synchronization................................................ 28

Power Dissipation and Standby Mode .................................... 28

Digital Outputs........................................................................... 29

Timing ......................................................................................... 29

Built-In Self-Test (BIST) and Output Test .................................. 30

Built-In Self-Test (BIST)............................................................ 30

Output Test Modes..................................................................... 30

Serial Port Interface (SPI).............................................................. 31

Configuration Using the SPI..................................................... 31

Hardware Interface..................................................................... 32

Configuration Without the SPI................................................ 32

SPI Accessible Features.............................................................. 32

Memory Map .................................................................................. 33

Reading the Memory Map Register Table............................... 33

Memory Map Register Table..................................................... 34

Memory Map Register Descriptions........................................ 37

Applications Information.............................................................. 39

Design Guidelines ...................................................................... 39

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

Page 3

AD9608

GENERAL DESCRIPTION

The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC) that features a high performance sample-and-hold circuit and an on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Logic levels of 1.8 V CMOS and 1.8 V LVDS are supported. Output data can also be multiplexed onto a single output bus.

AD9608 is available in a 64-lead RoHS-compliant LFCSP and

The is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.

Rev. 0 | Page 3 of 40

Page 4

AD9608

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 1.

AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit

RESOLUTION Full 10 10 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full −1.0 −0.3 +0.4 −1.0 −0.3 +0.4 % FSR Gain Error Full −2.8 ±1.5 +9.0 −2.8 ±1.5 +9.0 % FSR Differential Nonlinearity (DNL)1 Full ±0.35 ±0.35 LSB

25°C ±0.12 ±0.13 LSB

Integral Nonlinearity (INL)1 Full ±0.40 ±0.40 LSB 25°C ±0.14 ±0.14 LSB MATCHING CHARACTERISTIC

Offset Error Full ±0.1 ±1.0 ±0.1 ±1.0 % FSR

Gain Error Full ±0.5 ±6.5 ±0.5 ±6.5 % FSR TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C

Gain Error Full ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V

Load Regulation Error at 1.0 mA Full 2 2 mV INPUT REFERRED NOISE

VREF = 1.0 V 25°C 0.08 0.08 LSB rms ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p

Input Capacitance2 Full 5 5 pF

Input Resistance (Differential) Full 7.5 7.5 kΩ

Input Common-Mode Voltage Full 0.9 0.9 V

Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

AVDD

(1.8 V CMOS)

DRVDD

(1.8 V LVDS)

DRVDD

POWER CONSUMPTION

DC Input Full 125 141 mW

Sine Wave Input1 (DRVDD = 1.8 V CMOS Output Mode)

Sine Wave Input1 (DRVDD = 1.8 V LVDS Output Mode)

Standby Power3 Full

Power-Down Power Full 2.0 2.0 mW

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).

Full 76.8 82.0 87.7 93.0 mA Full 14.7 17.4 mA Full 48.5 49.7 mA

Full 165 174 189 199 mW Full 226 247 mW

108

120 mW

Rev. 0 | Page 4 of 40

Page 5

AD9608

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 2.

AD9608-105 AD9608-125 Parameter1 Temp Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)

fIN = 9.7 MHz 25°C 61.7 61.7 dBFS fIN = 30.5 MHz 25°C 61.7 61.7 dBFS fIN = 70 MHz 25°C 61.7 61.7 dBFS Full 61.3 61.3 dBFS

fIN = 100 MHz fIN = 200 MHz 25°C 61.4 61.4 dBFS

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 61.6 61.6 dBFS fIN = 30.5 MHz 25°C 61.6 61.6 dBFS fIN = 70 MHz 25°C 61.6 61.6 dBFS Full 61.1 61.1 dBFS fIN = 100 MHz 25°C 61.5 61.5 dBFS fIN = 200 MHz 25°C

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 200 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 200 MHz

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz

fIN = 100 MHz fIN = 200 MHz

TWO-TONE SFDR

fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) CROSSTALK2 ANALOG INPUT BANDWIDTH

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

25°C 61.6 61.6 dBFS

25°C 25°C 25°C 25°C 25°C

25°C 25°C 25°C Full 25°C 25°C

25°C Full 25°C

61.3

−90 −90

−89 −89

−75 −75

−89 −89

−84 −84

85 85 85 85 85 85 75 75 85 85 84 84

−85 −85

−75 −75

−85 −85

82 82

−95 −95 650 650

9.9

61.3

9.9

dBFS

Bits Bits Bits Bits Bits

dBc dBc dBc dBc dBc dBc

dBc dB MHz

Rev. 0 | Page 5 of 40

Page 6

AD9608

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 3.

Parameter Temp Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK/DFS/SYNC)2

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT/OUTPUT (SDIO/DCS)1

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LOGIC INPUTS (OEB, PDWN)2

High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage

IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V

Low Level Output Voltage

IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V

Rev. 0 | Page 6 of 40

Page 7

AD9608

Parameter Temp Min Typ Max Unit

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

Pull up.

Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 4.

AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 1000 1000 MHz

Conversion Rate1

DCS Enabled Full 20 105 20 125 MSPS

DCS Disabled Full 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (tCH) Full 4.76 4 ns Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 ps rms

DATA OUTPUT PARAMETERS

CMOS Mode CMOS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 1.8 2.9 4.4 1.8 2.9 4.4 ns DCO Propagation Delay (t

DCO to Data Skew (t

SKEW

LVDS Mode (DRVDD = 1.8 V)

Data Propagation Delay (tPD) Full 2.4 DCO Propagation Delay (t DCO to Data Skew (t

SKEW

CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles LVDS Mode Pipeline Delay (Latency)

Channel A/Channel B Wake-Up Time (Power-Down)3 Full 350 350 μs Wake-Up Time (Standby) Full 250 250 ns Out-of-Range Recovery Time Full 2 2 Cycles

Conversion rate is the clock rate after the divider.

Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Ta ). ble 18

Wake-up time is defined as the time required to return to normal operation from power-down mode.

) Full 9.52 8 ns

CLK

)2 Full 2.0 3.1 4.4 2.0 3.1 4.4 ns

DCO

) Full −1.2

)2 Full

DCO

4.4 4.4

−0.1

+1.0 −1.2

−0.1

+1.0 ns

2.4 ns ns

) Full −0.1 +0.2 +0.5 −0.1 +0.2 +0.5 ns

Full 16/16.5 16/16.5 Cycles

Rev. 0 | Page 7 of 40

Page 8

AD9608

TIMING SPECIFICATIONS

Table 5.

Parameter Descriptions Limit

SYNC TIMING REQUIREMENTS

SYNC to rising edge of CLK+ setup time 0.24 ns typ

SSYNC

SYNC to rising edge of CLK+ hold time 0.40 ns typ

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 40 ns min t

Period of the SCLK 2 ns min

CLK

tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 10 ns min t

SCLK pulse width high 10 ns min

HIGH

SCLK pulse width low 10 ns min

LOW

EN_SDIO

DIS_SDIO

Timing Diagrams

CH A/CH B DATA

CLK+

CLK–

DCOA/DCOB

VIN

CLK+

CLK–

DCOA/DCOB

CH A DATA

CH B DATA

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

VIN

N – 1

Figure 2. CMOS Default Output Mode Data Output Timing

N – 1

Figure 3. CMOS Interleaved Output Mode Data Output Timing

CLK

DCO

N – 16N – 17

CLK

DCO

SKEW

CH A

N – 16

CH B

N – 16

Rev. 0 | Page 8 of 40

SKEW

N + 1

CH B

N – 15

CH A

N – 15

N + 3

N + 2

N – 15 N – 14 N – 13 N – 12

N + 3

N + 2

CH A

CH B

CH A

CH B

N – 14

CH B

N – 14

N – 13

CH A

N – 13

N – 12

CH B

N – 12

N – 11

CH A

N – 11

CH A

N – 10

CH B

N – 10

N + 4

CH B N – 9

CH A N – 9

CH A N – 8

CH B N – 8

N + 5

10 ns min

2 ns min

09977-002

09977-003

Page 9

AD9608

VIN

CLK+

N – 1

N + 1

CLK

N + 2

N + 3

N + 4

N + 5

CLK–

DCO

CH A

N – 16

CH A

N – 16

CH A0 N – 16

CH A8 N – 16

CH B0 N – 16

CH B8 N – 16

SKEW

CH B

N – 16

CH B

N – 16

CH A1 N – 16

CH A9 N – 16

CH B1

N – 16

CH B9

N – 16

CH A

N – 15

CH A

N – 15

CH A0 N – 15

CH A8 N – 15

CH B0 N – 15

CH B8 N – 15

CH B

N – 15

CH B

N – 15

CH A1 N – 15

CH A9 N – 15

CH B1 N – 15

CH B9 N – 15

CH A

N – 14

CH A

N – 14

CH A0 N – 14

CH A8 N – 14

CH B0 N – 14

CH B8 N – 14

CH B

N – 14

CH B

N – 14

CH A1 N – 14

CH A9 N – 14

CH B1 N – 14

CH B9 N – 14

CH A

N – 13

CH A

N – 13

CH A0 N – 13

CH A8 N – 13

CH B0 N – 13

CH B8 N – 13

CH B

N – 13

CH B

N – 13

CH A1 N – 13

CH A9 N – 13

CH B1 N – 13

CH B9 N – 13

CH A

N – 12

CH A

N – 12

CH A0 N – 12

CH A8 N – 12

CH B0 N – 12

CH B8 N – 12

09977-004

PARALLEL

INTERLEAVED

MODE

CHANNEL

MULTIPLEXED

MODE

CHANNEL A

CHANNEL

MULTIPLEXED

MODE

CHANNEL B

DCO–

DCO+

D0+ (LSB)

D0– (LSB)

D9+ (MSB)

D9– (MSB)

D1+/D0+ (LSB)

D1–/D0– (LSB)

D9+/D8+ (MSB)

D9–/D8– (MSB)

D1+/D0+ (LSB)

D1–/D0– (LSB)

D9+/D8+ (MSB)

D9–/D8– (MSB)

Figure 4. LVDS Modes for Data Output Timing

CLK+

SSYNC

HSYNC

SYNC

09977-005

Figure 5. SYNC Input Timing Requirements

Rev. 0 | Page 9 of 40

Page 10

AD9608

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

SYNC to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V OEB −0.3 V to DRVDD + 0.2 V PDWN −0.3 V to DRVDD + 0.2 V D0A, D0B through D9A, D9B to AGND −0.3 V to DRVDD + 0.2 V DCOA, DCOB to AGND −0.3 V to DRVDD + 0.2 V

Environmental

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) +

0.2 V but should not exceed 2.1 V.

Package Typ e

64-Lead LFCSP 9 mm × 9 mm (CP-64-4)

Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

Per MIL-Std 883, Method 1012.1.

Per JEDEC JESD51-8 (still air).

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown Tabl e 7, airflow improves heat dissipation, which reduces θ package leads from metal traces, through holes, ground, and power planes reduces θ

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Airflow Veloc ity (m/sec) θ

1, 2

1, 3

1, 4

1, 2

Unit

0 22.3 1.4 N/A 0.1 °C/W

1.0 19.5 N/A 11.8 0.2 °C/W

2.5 17.5 N/A N/A 0.2 °C/W

. In addition, metal in direct contact with the

Rev. 0 | Page 10 of 40

Page 11

AD9608

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVD D

VIN+B

VIN–B

AVD D

RBIAS

VCM

SENSE

VREF

AVD D

VIN–A

VIN+A

AVD D

PDWN

OEB

CSB

SCLK/DFS

SDIO/DCS

ORA

D9A (MSB)

D8A

D7A

D6A

D5A

DRVDD

D4A

D3A

D2A

D1A

CLK+ CLK–

SYNC

NC NC NC NC NC NC

DRVDD

D0B (LSB)

D1B D2B D3B D4B D5B

646362616059585756555453525150

PIN 1

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

AD9608

PARALLEL CMO S

TOP VIEW

(Not to Scal e)

171819202122232425262728293031

D8B

D6B

D7B

DRVDD

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THI S PIN.

2. THE EXP OSED THERMAL PAD ON THE BOTTO M OF THE PACKAGE PROVIDES

THE ANALOG GRO UND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED T O GROUND F OR PROPER OPERATIO N.

NCNCNC

ORB

DCOA

DCOB

D9B (MSB)

NCNCNC

DRVDD

D0A (LSB)

09977-006

Figure 6. Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54,

AVDD Supply Analog Power Supply (1.8 V Nominal).

59, 60, 63, 64 4, 5, 6, 7, 8, 9,

NC No Connect. Do not connect to this pin. 25, 26, 27, 29, 30, 31

AGND,

Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog ground

for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement.

Rev. 0 | Page 11 of 40

Page 12

AD9608

Pin No. Mnemonic Type Description

Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 32 D0A (LSB) Output Channel A CMOS Output Data. 33 D1A Output Channel A CMOS Output Data. 34 D2A Output Channel A CMOS Output Data. 35 D3A Output Channel A CMOS Output Data. 36 D4A Output Channel A CMOS Output Data. 38 D5A Output Channel A CMOS Output Data. 39 D6A Output Channel A CMOS Output Data. 40 D7A Output Channel A CMOS Output Data. 41 D8A Output Channel A CMOS Output Data. 42 D9A (MSB) Output Channel A CMOS Output Data. 43 ORA Output Channel A Overrange Output. 11 D0B (LSB) Output Channel B CMOS Output Data. 12 D1B Output Channel B CMOS Output Data. 13 D2B Output Channel B CMOS Output Data. 14 D3B Output Channel B CMOS Output Data. 15 D4B Output Channel B CMOS Output Data. 16 D5B Output Channel B CMOS Output Data. 17 D6B Output Channel B CMOS Output Data. 18 D7B Output Channel B CMOS Output Data. 20 D8B Output Channel B CMOS Output Data. 21 D9B (MSB) Output Channel B CMOS Output Data. 22 ORB Output Channel B Overrange Output 24 DCOA Output Channel A Data Clock Output. 23 DCOB Output Channel B Data Clock Output. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI.

48 PDWN Input

Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

Rev. 0 | Page 12 of 40

Page 13

AD9608

AVD D

VIN+B

VIN–B

AVD D

RBIAS

VCM

SENSE

VREF

AVD D

VIN–A

VIN+A

AVD D

646362616059585756555453525150

AVD D

CLK+ CLK– SYNC

NC NC NC NC NC NC

DRVDD

12 13

NOTES

1. NC = NO CONNECT. DO NOT CO NNECT TO THIS PIN. . THE EXPO SED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PRO VIDES

THE ANALOG G ROUND FOR THE PART. THI S EXPOSED PAD MUST B CONNECTED TO GROUND FOR PRO PER OPERAT ION.

PIN 1

INDICATOR

2 3 4 5 6 7 8 9

INTERLEAVED PARALLEL LVDS

171819202122232425262728293031

D0– (LSB)

D0+ (LSB)

D1–

DRVDD

AD9608

TOP VIEW

(Not to Scal e)

D2–

D2+

D1+

DCO–

D3–

D4–

D5–

D3+

DCO+

D4+

DRVDD

PDWN

OEB

CSB

SCLK/DFS

SDIO/DCS

OR+

OR–

D9+ (MSB)

D9– (MSB)

D8+

D8–

DRVDD

D7+

D7–

D6+

D6–

D5+

Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54,

AVDD Supply Analog Power Supply (1.8 V Nominal).

59, 60, 63, 64 4, 5, 6, 7, 8, 9,

NC No Connect. Do not connect to this pin. 11, 12, 13, 14, 15, 16

AGND,

Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog ground for

the part. This exposed pad must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only.

09977-007

Rev. 0 | Page 13 of 40

Page 14

AD9608

Pin No. Mnemonic Type Description

Digital Outputs 18 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 17 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 21 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 20 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 23 D2+ Output Channel A/Channel B LVDS Output Data 2 —True. 22 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 27 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 26 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 30 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 29 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 32 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 31 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 34 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 33 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 36 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 35 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 39 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 38 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 41 D9+ (MSB) Output Channel A/Channel B LVDS Output Data 9—True. 40 D9− (MSB) Output Channel A/Channel B LVDS Output Data 9—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI.

48 PDWN Input

Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

Rev. 0 | Page 14 of 40

Page 15

AD9608

AVD D

VIN+B

VIN–B

AVD D

RBIAS

VCM

SENSE

VREF

AVD D

VIN–A

VIN+A

AVD D

646362616059585756555453525150

AVD D

CLK+

CLK–

SYNC

DRVDD

12 B D1–/D0– (LSB) B D1+/D0+ (LSB )

B D3–/D2–

B D3+/D2+

NOTES

1. NC = NO CONNECT. DO NOT CONNECT T O THIS PIN.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES

THE ANALOG GROUND FO R THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER O PERATIO N.

PIN 1 INDICATOR

B D5+/D4+

DRVDD

B D7–/D6–

AD9608

TOP VIEW

(Not to Scale)

DCO–

B D7+/D6+

B D9–/D8– (MSB)

B D9+/D8+ (MSB)

DCO+

DRVDD

CHANNEL MULTIPLEXED LVDS

171819202122232425262728293031

B D5–/D4–

PDWN

OEB

CSB

SCLK/DFS

SDIO/DCS

OR+

OR–

A D9+/D8+ (MSB)

A D9–/D8– (MSB)

A D7+/ D6+

A D7–/D6–

DRVDD

A D5+/ D4+

A D5–/D4–

A D3+/D2+

A D3–/D2–

A D1–/D0– (LSB)

A D1+/D0+ (LSB)

09977-008

Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View)

Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54,

AVDD Supply Analog Power Supply (1.8 V Nominal).

59, 60, 63, 64 4, 5, 6, 7, 8, 9,

NC No Connect. Do not connect to this pin. 11, 12, 26, 27, 29, 30

0 AGND, Exposed Pad Ground

The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground

for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. 0 | Page 15 of 40

Page 16

AD9608

Pin No. Mnemonic Type Description

Digital Outputs 14 B D1+/D0+ (LSB) Output Channel B LVDS Output Data 1/ Data 0—True. 13 B D1−/D0− (LSB) Output Channel B LVDS Output Data 1/ Data 0—Complement. 16 B D3+/D2+ Output Channel B LVDS Output Data 3/ Data 2—True. 15 B D3−/D2− Output Channel B LVDS Output Data 3/ Data 2—Complement. 18 B D5+/D4+ Output Channel B LVDS Output Data 5/ Data 4—True. 17 B D5−/D4− Output Channel B LVDS Output Data 5/ Data 4—Complement. 21 B D7+/D6+ Output Channel B LVDS Output Data 7/ Data 6—True. 20 B D7−/D6− Output Channel B LVDS Output Data 7/ Data 6—Complement. 23 B D9+/D8+ (MSB) Output Channel B LVDS Output Data 9/ Data 8—True. 22 B D9−/D8− (MSB) Output Channel B LVDS Output Data 9/ Data 8—Complement. 32 A D1+/D0+ (LSB) Output Channel A LVDS Output Data 1/ Data 0—True. 31 A D1−/D0− (LSB) 34 A D3+/D2+ Output Channel A LVDS Output Data 3/ Data 2—True. 33 A D3−/D2− Output Channel A LVDS Output Data 3/ Data 2—Complement. 36 A D5+/D4+ Output Channel A LVDS Output Data 5/ Data 4—True. 35 A D5−/D4− Output Channel A LVDS Output Data 5/ Data 4—Complement. 39 A D7+/D6+ Output Channel A LVDS Output Data 7/ Data 6—True. 38 A D7−/D6− Output Channel A LVDS Output Data 7/ Data 6—Complement. 41 A D9+/D8+ (MSB) Output Channel A LVDS Output Data 9/ Data 8—True. 40 A D9−/D8− (MSB) Output Channel A LVDS Output Data 9/ Data 8—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI.

48 PDWN Input

Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

Rev. 0 | Page 16 of 40

Page 17

AD9608

TYPICAL PERFORMANCE CHARACTERISTICS

AD9608-125

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

–20

125MSPS

9.7MHZ AT –1d BFS SNR = 60.6dB ( 61.6dBFS) SFDR = 85.4dBC

–20

125MSPS

100.5MHz AT –1d BFS SNR = 60.6dB ( 61.6dBFS ) SFDR = 85.2d Bc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

06010 20 30 40 50

FREQUENCY (MHz)

Figure 9. Single-Tone FFT with f

–20

–40

–60

–80

AMPLIT UDE (dBFS)

–100

= 9.7 MHz

125MSPS

30.5MHz AT –1dBFS SNR = 60.7dB ( 61.7dBFS) SFDR = 86.3d Bc

–40

–60

–80

AMPLIT UDE (dBFS )

–100

–120

0610 20 30 40 50

09977-009

Figure 12. Single-Tone FFT with f

125MSPS

200.5MHz AT –1dBFS SNR = 60.3dB (61.3d BFS)

–20

SFDR = 83.0dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

FREQUENC Y (MHz)

= 100.5 MHz

09977-012

–120

0610 20 30 40 50

FREQUENCY (MHz)

Figure 10. Single-Tone FFT with f

125MSPS

70.1MHz AT –1dBFS SNR = 60.7dB (61.7dBFS)

–20

SFDR = 86.5dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

0610 20 30 40 50

FREQUENCY (MHz )

Figure 11. Single-Tone FFT with f

= 30.5 MHz

= 70.1 MHz

09977-010

09977-011

–120

0610 20 30 40 50

FREQUENCY (M Hz)

Figure 13. Single-Tone FFT with f

= 200.5 MHz

09977-013

Rev. 0 | Page 17 of 40

Page 18

AD9608

–

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

–15

–30

–45

–60

–75

AMPLITUDE (Hz)

–90

–105

–120

–135

6 121824303642485460

2F1–F2

FREQUENCY (MHz)

Figure 14. Two-Tone FFT with f

100

SNR/SFDR (dBFS/dBc)

0 50 100 150 200 250

ANALOG INPUT FREQUENCY (MHz)

SFDR

SNRFS

2F2–F1

2F1 + F2

= 29 MHz and f

IN1

= 32 MHz

IN2

Figure 15. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale

09977-067

09977-035

–12

–22

–32

–42

–52

–62

–72

–82

–92

–70 –60 –50 –40 –30 –20 –10

IMD3 (dBc)

IMD3 (dBFS)

INPUT AMPLIT UDE (dBFS)

SFDR(dBc)

SFDR(dBFS)

Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f

= 32 MHz

and f

IN2

SNRFS SFDR

SNR SFDRFS

SNR/SFDR (dBc AND dBFS)

–60 –50 –40 –30 –20 –10 0

INPUT AMPLITUDE (dBFS)

Figure 18. SNR/SFDR vs. Input Amplitude (AIN) with f

= 9.7 MHz

= 29 MHz

IN1

09977-022

09977-033

120

100

SFDR (dBc)

SNR/SFDR (dBFS/dBc)

5 25 45 65 85 105 125

SNR (dBFS)

SAMPLE RATE (MSPS)

Figure 16. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

09977-031

120

100

SFDR (dBc)

SNR/SFDR (dBFS/ dBc)

5 25 45 65 85 105 125

SNR (dBFS)

SAMPLE RATE (MSPS)

Figure 19. SNR/SFDR vs. Sample Rate with AIN = 70 MHz

09977-032

Rev. 0 | Page 18 of 40

Page 19

AD9608

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

1.0

2.0

1.5

0.5

DNL ERROR (L SB)

–0.5

–1.0

0 500 1000

OUTPUT CODE

Figure 20. DNL Error with f

1,200

1,000

800

600

400

NUMBER OF HI TS (Th ousands)

200

= 9.7 MHz

1.0

0.5

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

0 200 400 600 800 1000

09977-021

Figure 22. INL Error with f

OUTPUT CODE

= 9.7 MHz

09977-020

N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3

OUTPUT CODE

09977-034

Figure 21. Shorted Input Histogram

Rev. 0 | Page 19 of 40

Page 20

AD9608

AD9608-105

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

–20

105MSPS

9.7MHz AT –1dBFS SNR = 60.7dB (61.7d BFS) SFDR = 84.9dBc

–20

105MSPS

100.5MHz AT –1dBFS SNR = 60.7dB ( 61.7dBFS) SFDR = 85.9dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0510 20 30 40

FREQUENCY (MHz)

Figure 23. Single-Tone FFT with f

105MSPS

30.5MHz AT –1dBFS SNR = 60.6dB (61.6d BFS) SFDR = 84.5dBc

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

= 9.7 MHz

–40

–60

–80

AMPLITUDE (dBFS)

–100

09977-014

–120

0510 20 30 40

Figure 26. Single-Tone FFT with f

–20

–40

–60

–80

AMPLIT UDE (dBFS)

–100

FREQUENCY (MHz)

105MSPS

200.5MHz AT –1dBFS SNR = 60.3dB (61.3dBF S) SFDR = 85.9d Bc

= 100.5 MHz

09977-017

–120

0510 20 30 40

FREQUENCY (MHz)

Figure 24. Single-Tone FFT with f

105MSPS

70.1MHz AT –1d BFS SNR = 60.7dB (61.7dBFS)

–20

SFDR = 86.8d Bc

–40

–60

–80

AMPLIT UDE (dBF S)

–100

–120

0510 20 30 40

FREQUENCY (MHz)

Figure 25. Single-Tone FFT with f

= 30.5 MHz

= 70.1 MHz

09977-015

–120

0510 20 30 40

Figure 27. Single-Tone FFT with f

09977-016

Rev. 0 | Page 20 of 40

FREQUENC Y (MHz)

= 200.5 MHz

09977-018

Page 21

AD9608

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS dierential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

100

SNR/SFDR (dBFS / d Bc)

050

ANALOG INP UT F RE QUENCY (MHz)

SFDR

SNRFS

100 150 200 250

Figure 28. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale

09977-029

SNRFS SFDR

SNR SFDRFS

SNR/SFD R ( d B c AND dBFS)

–60 –50 –40 –30 –20 –10 0

INPUT AMPLI TUDE (dBFS)

Figure 31. SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz

09977-028

120

100

SFDR (dBc)

SNR/SFDR (dBFS/dBc)

5 152535455565758595105

SNR (dBFS)

SAMPLE RATE (MSPS)

Figure 29. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

1.0

0.5

120

100

SFDR (dBc)

SNR/SFDR (d BF S /dBc)

5 152535455565758595105

09977-026

SNR (dBFS)

SAMPLE RATE (MSPS)

09977-027

Figure 32. SNR/SFDR vs. Sample Rate with AIN = 70 MHz

1.0

0.5

DNLERROR (L S B)

–0.5

–1.0

Figure 30. DNL Error with f

OUTPUT CO DE

= 9.7 MHz

1000500

09977-019

INL ERROR ( LSB)

–0.5

–1.0

0 200 400 600 800 1000

OUTPUT CODE

Figure 33. INL Error with f

= 9.7 MHz

09977-025

Rev. 0 | Page 21 of 40

Page 22

AD9608

EQUIVALENT CIRCUITS

VIN±x

Figure 34. Equivalent Analog Input Circuit

CLK+

CLK–

5Ω

15kΩ

0.9V

15kΩ

5Ω

Figure 35. Equivalent Clock Input Circuit

DRVDD

PAD

SCLK/DFS, SYNC,

OEB, AND PDWN

09977-039

350Ω

30kΩ

09977-045

Figure 38. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit

ENSE

09977-040

375Ω

09977-043

Figure 39. Equivalent SENSE Circuit

AVD D

30kΩ

CSB

350Ω

09977-047

Figure 36. Equivalent Digital Output Circuit

DRVDD

30kΩ

DIO/DCS

350Ω

30kΩ

Figure 37. Equivalent SDIO/DCS Input Circuit

Figure 40. Equivalent CSB Input Circuit

REF

7.5kΩ

09977-042

375Ω

Figure 41. Equivalent VREF Circuit

09977-044

09977-048

Rev. 0 | Page 22 of 40

Page 23

AD9608

THEORY OF OPERATION

The AD9608 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any f

/2 frequency segment from dc to 200 MHz, using appropriate

low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion.

In nondiversity applications, the AD9608 can be used as a baseband or direct downconversion receiver, where one ADC is used for I input data and the other is used for Q input data.

Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices.

Programming and control of the AD9608 is accomplished using a 3-bit SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9608 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The output staging block aligns the data, corrects errors, and passes the data to the CMOS/LVDS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9608 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance.

PAR

VIN+x

VIN–x

PAR

Figure 42. Switched-Capacitor Input Circuit

SAMPLE

The clock signal alternately switches the input circuit between sample-and-hold mode (see Figure 42). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application.

09977-049

Rev. 0 | Page 23 of 40

Page 24

AD9608

Input Common Mode

The analog inputs of the AD9608 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 43.

An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 µF capacitor, as described in the Applications Information section.

100

SNR/SFDR (dBFS/dBc)

0.5 0.6 0.7 0.8 0.9 1.0 1. 1 1.2 1.3

INPUT COMMON-MODE VOLTAGE (V)

SFDR (d Bc)

SNR (dBFS)

09977-056

Figure 43. SNR/SFDR vs. Input Common-Mode Voltage,

= 70 MHz, fS = 125 MSPS

Differential Input Configurations

Optimum performance is achieved while driving the AD9608 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC.

The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9608 (see Figure 44), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

200Ω

VIN

0.1µF

76.8Ω 90Ω

120Ω

ADA4938

200Ω

33Ω

10pF

33Ω

VIN–x

VIN+x

AVDD

ADC

VCM

Figure 44. Differential Input Configuration Using the ADA4938-2

For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 45). To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer.

2V p- p

49.9Ω

0.1µF

Figure 45. Differential Transformer-Coupled Configuration

VIN+x

VIN–x

ADC

VCM

The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies that are below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9608. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 46).

09977-050

09977-051

An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver (see Figure 47). See the AD8352 data sheet for more information.

2V p-p

0.1µF

Figure 46. Differential Double Balun Input Configuration

0.1µF

0Ω

ANALOG I NPUT

0.1µF

0Ω

Figure 47. Differential Input Configuration Using the AD8352

0.1µF

8, 13

AD8352

0.1µF

Rev. 0 | Page 24 of 40

25Ω

0.1µF

200Ω

0.1µF

VIN+x

VIN–x

ADC

VIN+x

VIN–x

VCM

ADC

VCM

09977-053

09977-054

Page 25

AD9608

In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Tab l e 1 1 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide.

Table 11. Example RC Network

R Series

Frequency Range (MHz)

(Ω Each) C Differential (pF)

0 to 70 33 22 70 to 200 125 Open

Single-Ended Input Configuration

A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 48 shows a typical single-ended input configuration.

1V p-p

10µF

49.9Ω

10µF

0.1µF

Figure 48. Single-Ended Input Configuration

AVD D

1kΩ

AVDD

VIN+x

ADC

VIN–x

09977-052

Internal Reference Connection

A comparator within the AD9608 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Tabl e 12 . If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 49), setting VREF to 1.0 V.

VIN+A/VIN+B

VIN–A/V IN–B

ADC

CORE

VREF

0.1µF1.0µF

SENSE

SELECT

LOGIC

0.5V

ADC

09977-055

Figure 49. Internal Reference Configuration

If the internal reference of the AD9608 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 50 shows how the internal reference voltage is affected by loading.

VOLTAGE REFERENCE

–0.5

A stable and accurate 1.0 V voltage reference is built into the

AD9608. The VREF pin can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections

–1.0

–1.5

INTERNAL V

REF

= 1.00V

that follow. The Reference Decoupling section describes the best practices PCB layout of the reference.

–2.0

–2.5

REFERENCE VOL TAGE ERROR (%)

–3.0

0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.81.2

LOAD CURRENT (mA)

Figure 50. V

Accuracy vs. Load Current

REF

Table 12. Reference Configuration Summary

Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p)

Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0

09977-057

Rev. 0 | Page 25 of 40

Page 26

AD9608

External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 51 shows the typical drift characteristics of the internal reference in 1.0 V mode.

–1

ERROR (mV)

–2

REF

–3

–4

–5

–6

–40 –20 0 20 40 60 80

ERROR (mV)

REF

TEMPERATURE (°C)

Figure 51. Typical V

REF

Drift

09977-066

When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 41). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9608 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 52) and require no external bias.

0.9V

CLK–CLK+

2pF 2pF

Clock Input Options

The AD9608 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section.

Figure 53 and Figure 54 show two preferred methods for clocking the AD9608 (at clock rates up to 1 GHz prior to internal CLK divider). A low jitter clock source is converted from a singleended signal to a differential signal using either an RF transformer or an RF balun.

The RF balun configuration is recommended for clock frequencies between 125 MHz and 1 GHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9608 to approximately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9608 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance.

XFMR

0.1µF

0.1µF0.1µF

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLK+

ADC

CLK–

Mini-Circuits

ADT1-1WT, 1:1 Z

CLOCK

INPUT

50Ω

100Ω

Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz)

LOCK

INPUT

50Ω

1nF

Figure 54. Balun-Coupled Differential Clock (Up to 1 GHz)

0.1µF1nF

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLK+

ADC

CLK–

09977-059

09977-060

09977-058

Figure 52. Equivalent Clock Input Circuit

Rev. 0 | Page 26 of 40

Page 27

AD9608

If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 55. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

0.1µF

AD951x

PECL DRIVER

0.1µF

50kΩ 50kΩ

Figure 55. Differential PECL Sample Clock (Up to 1 GHz)

0.1µF CLK+

100Ω

0.1µF

240Ω240Ω

ADC

CLK–

A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 56. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance.

LOCK

INPUT

CLOCK

INPUT

0.1µF

AD951x

LVDS DRIVER

0.1µF

50kΩ 50kΩ

Figure 56. Differential LVDS Sample Clock (Up to 1 GHz)

0.1µF

100Ω

0.1µF

CLK+

ADC

CLK–

In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 F capacitor (see Figure 57).

0.1µF

1kΩ

AD951x

CMOS DRIVER

CLOCK

INPUT

50Ω

50Ω RESISTOR IS OPTIONAL.

Figure 57. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

OPTIONAL

100Ω

0.1µF

0.1µF CLK+

ADC

CLK–

09977-061

09977-062

09977-063

Input Clock Divider

The AD9608 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8.

The AD9608 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. A ±5% tolerance is commonly required on the clock duty cycle to maintain dynamic performance characteristics.

The AD9608 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9608. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 58.

Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 µs to 5 µs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal.

DCS ON

SNR (dBFs)

DCS OFF

35 40 45 50 55 60 65

POSITIVE DUTY CYCLE (%)

09977-036

Figure 58. SNR vs. DCS On/Off

Rev. 0 | Page 27 of 40

Page 28

AD9608

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNR jitter (t

) can be calculated by

JRMS

SNR

= −10 log[(2π × f

) at a given input frequency (f

× t

INPUT

)2 + 10 ]

JRMS

INPUT

) due to

)10/(LFSNR−

In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 59.

SNR (dBFS)

1 10 100 1k

FREQUENCY (MHz)

3.0ps

0.05ps

0.2ps

0.5ps

1.0ps

1.5ps

2.0ps

2.5ps

09977-065

Figure 59. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9608. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step.

For more information, see the AN-501 Application Note and the

AN-756 Application Note, available on www.analog.com.

CHANNEL/CHIP SYNCHRONIZATION

The AD9608 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Tabl e 5 . Drive the SYNC input using a single-ended CMOS-type signal.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 60, the analog core power dissipated by the AD9608 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit.

Rev. 0 | Page 28 of 40

The maximum DRVDD current (I

DRVDD

= V

DRVDD

× C

LOAD

× f

where N is the number of output bits (22, in the case of the AD9608).

This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of f

/2. In practice, the DRVDD current is estab-

CLK

lished by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal.

Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 60 was taken in CMOS mode using the same operating conditions as those used for the power supplies and power consumption parameters in Tab l e 1 , with a 5 pF load on each output driver.

0.10

AVDD

DRVDD

0.09

TOTAL POWER

0.08

0.07

0.06

0.05

0.04

0.03

SUPPLY CURRENT (mA)

0.02

0.01

5 25456585105125

ENCODE RATE (Msps)

Figure 60. AD9608-125 Power and Current vs. Clock Rate

(1.8 V CMOS Output Mode)

0.09 I

AVDD

DRVDD

0.08 TOTAL POWER

0.07

0.06

0.05

0.04

0.03

SUPPLY CURRENT (mA)

0.02

0.01

5 152535455565758595105

ENCODE RATE (Msps)

Figure 61. AD9608-105 Power and Current vs. Clock Rate

(1.8 V CMOS Output Mode)

) can be calculated as

DRVDD

× N

CLK

240

190

140

POWER (mW)

240

190

140

POWER (mW)

09977-030

09977-023

Page 29

AD9608

The AD9608 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates <2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9608 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.

Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details.

DIGITAL OUTPUTS

The AD9608 output drivers can be configured to interface with either 1.8 V CMOS or 1.8 V LVDS logic families. The default output mode is CMOS, with each channel output on separate busses as shown in Figure 2.

In CMOS output mode, the CMOS output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies and may affect converter performance.

Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.

The CMOS output can also be configured for interleaved CMOS output mode via the SPI port. In interleaved CMOS mode, the data for both channels is output onto a single output bus to reduce the total number of traces required. The timing diagram for interleaved CMOS output mode is shown in Figure 3.

The interleaved CMOS output mode is enabled globally onto both output channels via Bit 5 in Register 0x14. The unused channel output can be disabled by selecting the appropriate bit (Bit 1 or Bit 0) in Register 0x05 and then writing a 1 to the local (channelspecific) output port disable bit (Bit 4) in Register 0x14.

The output data format can be selected to be either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Tab l e 1 3 ).

As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or Gray code when using the SPI control.

Table 13. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin SCLK/DFS SDIO/DCS

AGND Offset binary (default) DCS disabled DRVDD Twos complement DCS enabled (default)

Digital Output Enable Function (OEB)

The AD9608 has a flexible three-state ability for the digital output pins. The three-state mode is enabled through the SPI interface and can subsequently be controlled using the OEB pin or through the SPI. Once enabled via the SPI (Bit 7) in Register 0x101 and the OEB pin is low, the output data drivers and DCOs are enabled. If the OEB pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.

When using the SPI interface, the data outputs and DCO of each channel can be independently three-stated by using the output port disable bit (Bit 4) in Register 0x14.

TIMING

The AD9608 provides latched data with a pipeline delay of 16 clock cycles. Data outputs are available one propagation delay (t

Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9608. These transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9608 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9608 provides two data clock output (DCO) signals intended for capturing the data in an external register. In CMOS output mode, the data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. In LVDS output mode, the DCO and data output switching edges are closely aligned. Additional delay can be added to the DCO output using SPI Register 0x17 to increase the data setup time. In this case, the Channel A output data is valid on the rising edge of DCO, and the Channel B output data is valid on the falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a graphical timing description of the output modes.

) after the rising edge of the clock signal.

Table 14. Output Data Format

Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR

VIN+ − VIN− < −VREF − 0.5 LSB 00 0000 0000 10 0000 0000 1 VIN+ − VIN− = −VREF 00 0000 0000 10 0000 0000 0 VIN+ − VIN− = 0 10 0000 0000 00 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 11 1111 1111 01 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 11 1111 1111 01 1111 1111 1

Rev. 0 | Page 29 of 40

Page 30

AD9608

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9608 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as to facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9608 is included. Various output test options are also provided to place predictable values on the outputs of the AD9608.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9608 signal path. Perform the BIST test after a reset to ensure

that the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. Once completed, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 of Register 0x24, signifying that the test passed. If the BIST test fails, Bit 0 of Register 0x24 is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs.

Writing the value 0x05 to Register 0x0E runs the BIST. This enables Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (initialize BIST sequence) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN sequence can be continued from its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user needs to rely on verifying the output data.

OUTPUT TEST MODES

The output test options are described in Ta bl e 18 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

Rev. 0 | Page 30 of 40

Page 31

AD9608

SERIAL PORT INTERFACE (SPI)

The AD9608 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memor y Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see Tab l e 1 5 ). The SCLK/DFS (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles.

Table 15. Serial Port Interface Pins

Pin Function

Serial clock. The serial shift clock input, which is used to

SCLK

synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically

SDIO

serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read

CSB

and write cycles.

The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 62 and Tabl e 5.

Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits.

In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.

All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

CSB

SCLK

SDIO

DON’T CARE

R/W W1 W0 A12 A11 A10 A9 A8 A7

HIGH

LOW

Figure 62. Serial Port Interface Timing Diagram

CLK

Rev. 0 | Page 31 of 40

D5 D4 D3 D2 D1 D0

DON’T CARE

DON’T CAREDON’T CARE

09977-046

Page 32

AD9608

HARDWARE INTERFACE

The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the

AD9608. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.

The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Micro- controller-Based Serial Port Interface (SPI) Boot Circuit.

The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9608 to prevent these signals from transitioning at the converter inputs during critical sampling periods.

Some pins serve a dual function when the SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. Table 16 describes the strappable functions supported on the AD9608.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, and power-down feature control. In this mode, the CSB chip select bar should be connected to AVDD, which disables the serial port interface.

When the device is in SPI mode, the PDWN and OEB pins (if enabled) remain active. For SPI control of output enable and power-down, the OEB and PDWN pins should be set to their default states.

Table 16. Mode Selection

Pin External Voltage Configuration

SDIO/DCS DRVDD (default) Duty cycle stabilizer enabled

AGND Duty cycle stabilizer disabled

SCLK/DFS DRVDD Twos complement enabled

AGND (default) Offset binary enabled

OEB DRVDD Outputs in high impedance

AGND (default) Outputs enabled

PDWN DRVDD

AGND (default) Normal operation

Chip in power-down or standby

SPI ACCESSIBLE FEATURES

Table 17 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9608 part-specific features are described in detail following Table 18, the external memory map register table (see the Memory Map Register Descriptions section).

Table 17. Features Accessible Using the SPI

Feature Name

Mode

Clock

Offset Allows user to digitally adjust the converter offset Tes t I /O

Output Mode Allows user to set the output mode, including LVDS Output Phase Allows user to set the output clock polarity Output Delay Allows user to vary the DCO delay

Description

Allows user to set either power-down mode or standby mode

Allows user to access the DCS, set the clock divider, set the clock divider phase, and enable the sync

Allows user to set test modes to have known data on output bits

Rev. 0 | Page 32 of 40

Page 33

AD9608

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF) and the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x102).

The memory map register table (see Tab l e 1 8 ) lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x03. This means that in Address 0x05, Bits[7:2] = 0, and Bits[1:0] = 1. This setting is the default channel index setting. The default value results in both ADC channels receiving the next write command. For more information about this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers are documented in the Memory Map Register Descriptions section.

Open Locations

All address and bit locations that are not included in Tab l e 1 8 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open (for example, Address 0x13), this address location should not be written to.

Default Values

After the AD9608 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Tab l e 1 8 .

Logic Levels

An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

• “Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel-Specific Registers

Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Tab l e 1 8 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Ta b le 18 affect the entire part or the channel features for which independent settings are not allowed between channels.

Rev. 0 | Page 33 of 40

Page 34

AD9608

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Tab l e 1 8 are not currently supported for this device.

Table 18. Memory Map Registers

Addr (Hex)

Chip Configuration Registers 0x00

0x01 Chip ID

0x02

Channel Index and Transfer Registers 0x05

0xFF

ADC Functions 0x08

0x09

SPI port config

(global)

Chip grade

(global)

Device index (global)

Transfer (global)

Power modes

(local)

Global clock

(global)

Bit 7 (MSB)

Open LSB first Soft reset 1 1 Soft reset LSB first Open 0x18

Open Speed grade ID

Open Open Open Open Open Open Channel B Channel A 0x03

Open Open Open Open Open Open Open Transfer 0x00

Open Open

Open Open Open Open Open Open Open

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

8-bit chip ID, Bits[7:0]

AD9608 = 0x9C

100 = 105 MSPS 101 = 125 MSPS

External powerdown pin function

0 = PDWN 1 = standby

Open Open Open Internal power-down mode

Open Open Open Open

00 = normal operation 01 = full power-down 10 = standby 11 = digital reset

Bit 0 (LSB)

Duty cycle stabilizer

0 = disabled 1 = enabled

Default Value (Hex)

Read only

0x00

0x01

Comments

Nibbles are mirrored so LSB-first mode or MSB-first mode registers correctly, regardless of shift mode

Unique chip ID used to differentiate devices; read only

Unique speed grade ID used to differentiate devices; read only

Bits are set to determine which device on the chip receives the next write command; applies to local registers only

Synchronous transfer of data from the master shift register to the slave

Determines various generic modes of chip operation

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AD9608

Default Addr (Hex)

0x0B

0x0C

0x0D

0x0E

0x10

0x14

0x15

0x16

0x17

Clock divide

(global)

Enhancement control (global)

Test mode (local)

BIST enable

(global) Customer

offset adjust

(local) Output

mode

Output adjust

Clock phase control

(global)

Output delay (global)

Bit 7 (MSB)

Open Open Open Open Open Clock divide ratio

Open Open Open Open Open Chop mode

User test mode control

00 = single pattern mode

01 = alternate continuous/repe at pattern mode 10 = single once pattern mode 11 = alternate once pattern mode

Open Open Open Open Open

Output port logic

type (global) 00 = CMOS, 1.8 V 10 = LVDS, ANSI

11 = LVDS, reduced

Open Open

Invert DCO clock

0 = not inverted

1 = inverted

DCO clock delay

0 = disabled

1 = enabled

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8

0 = disabled 1 = enabled

Reset PN long ge n

Output interleave enable

(global)

range

CMOS 1.8 V DCO drive

Open Open Open Open

Open Data delay

0 = disabled 1 = enabled

Reset PN short gen

Offset adjust in LSBs from +127 to −128

(twos complement format)

Output port disable (local)

strength 00 = 1× 01 = 2× 10 = 3× 11 = 4×

Open Open Delay selection

Open (global)

Open Open

Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1111 = ramp output

Initialize BIST sequence

Output invert (local)

Input clock divider phase adjust

relative to the encode clock

Open Open 0x00

Open BIST enable 0x00

Output format

00 = offset binary

01 = twos complement

10 = Gray code

CMOS 1.8 V data

drive strength

000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles

000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns

Bit 0 (LSB)

00 = 1× 01 = 2× 10 = 3× 11 = 4×

Value (Hex) Comments

0x00

The divide ratio is value plus 1

Chop mode enabled if Bit 2 = 1

When this register is set, the test data is placed on the output pins in place of normal data

Configures the outputs and the format of the data

Determines CMOS output drive strength properties

Allows selection of clock delays into the input clock divider

This sets the fine output delay of the output clock but does not change internal timing

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AD9608

Default Addr (Hex)

0x18

0x19

0x1A

0x1B

0x1C

0x24 MISR LSB MISR LSB, Bits[7:0] 0xFF Read only 0x25 MISR MSB MISR MSB, Bits[15:8] 0xFF Read only 0x2A

0x2E

0x3A

0x100

0x101

0x102

VREF select

(global)

User Pattern 1, LSB (global)

User Pattern 1, MSB (global)

User Pattern 2, LSB (global)

User Pattern 2, MSB

Overrange control

(global)

Output assign (local)

Sync control (global)

Sample rate override

User I/O Control Register 2

User I/O Control Register 3

Bit 7 (MSB)

Open Open Open Open Open Internal V

B7 B6 B5 B4 B3 B2 B1 B0 0x00

B15 B14 B13 B12 B11 B10 B9 B8 0x00

B7 B6 B5 B4 B3 B2 B1 B0 0x00

B15 B14 B13 B12 B11 B10 B9 B8 0x00

Open Open Open Open Open Open Open

Open Open Open Open Open

Open

Output enable bar (OEB) pin enable

Open Open Open Open

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

digital adjustment

REF

000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p

Clock divider next sync only

Sample rate override enable

Open Open Open Open Open Open

Open Open Open Sample rate

VCM power-down

Clock divider sync enable

011 = 80 MSPS 100 = 105 MSPS 101 = 125 MSPS

Open 0x00

Bit 0 (LSB)

Overrange output

0 = disabled 1 = enabled

0 = ADC A 1 = ADC B (local)

Open 0x00

Disable SDIO pull-down

Value

(Hex) Comments

0x04

0x01

0x00 =

ADC A

0x01 =

ADC B

0x00

Select and/or adjust V

REF

UserDefined Pattern 1, LSB

UserDefined Pattern 1, MSB

UserDefined Pattern 2, LSB

UserDefined Pattern 2, MSBs

Overrange control settings

Assign an ADC to an output channel

Sets the global sync options

OEB and SDIO pin controls

Rev. 0 | Page 36 of 40

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AD9608

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

Power Modes (Register 0x08)

Bits[7:6]—Open

Bit 5—External Power-Down Pin Function

If set, the external PDWN pin initiates power-down mode. If clear, the external PDWN pin initiates standby mode.

Bits[4:2]—Open

Bits[1:0]—Internal Power-Down Mode

In normal operation (Bits[1:0] = 00), both ADC channels are active.

In power-down mode (Bits[1:0] = 01), the digital data path clocks are disabled while the digital data path is reset. Outputs are disabled.

In standby mode (Bits[1:0] = 10), the digital data path clocks and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), the digital data path clocks are disabled while the digital data path is held in reset. The outputs are enabled in this state. For optimum performance, it is recommended that both ADC channels be reset simultaneously. This is accomplished by ensuring that both channels are selected via Register 0x05 prior to issuing the digital reset instruction.

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct-conversion receivers, chopping in the first stage of the AD9628 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to f

/2 where it can be filtered.

CLK

Bits[1:0]—Open

Output Mode (Register 0x14)

Bits[7:6]—Output Port Logic Type

00 = CMOS, 1.8 V 10 = LVDS, ANSI 11 = LVDS, reduced range

Bit 5—Output Interleave Enable

For LVDS outputs, setting Bit 5 enables interleaving. Channel A is sent coincident with a high DCO clock, and Channel B is coincident with a low DCO clock. Clearing Bit 5 disables the

interleaving feature. Channel A is sent on least significant bits (LSBs), and Channel B is sent on most significant bits (MSBs). The even bits are sent coincident with a high DCO clock, and the odd bits are sent coincident with a low DCO clock.

For CMOS outputs, setting Bit 5 enables interleaving in CMOS DDR mode. On ADC Output Port A, Channel A is sent coincident with a low DCO clock, and Channel B is coincident with a high DCO clock. On ADC Output Port B, Channel B is sent coincident with a low DCO clock, and Channel A is coincident with a high DCO clock. Clearing Bit 5 disables the interleaving feature, and data is output in CMOS SDR mode. Channel A is sent to Port A, and Channel B is sent to Port B.

Bit 4—Output Port Disable

Setting Bit 4 high disables the output port for the channels selected in Bits[1:0] of the device index register (Register 0x05).

Bit 3—Open

Bit 2—Output Invert

Setting Bit 2 high inverts the output port data for the channels selected in Bits[1:0] of the device index register (Register 0x05).

Bits[1:0]—Output Format

00 = offset binary 01 = twos complement 10 = Gray code

Sync Control (Register 0x3A)

Bits[7:3]—Open

Bit 2—Clock Divider Next Sync Only

If the clock divider sync enable bit (Address 0x3A, Bit 1) is high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high. This is continuous sync mode.

Bit 0—Open

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment they are written. Setting Bit 0 of this transfer register high initializes the settings in the ADC sample rate override register (Address 0x100).

Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device. Any attempt to upgrade the default speed grade results in a chip power-down. Settings in this register are not initialized until Bit 0 of the transfer register (Register 0xFF) is written high.

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AD9608

User I/O Control 2 (Register 0x101)

Bit 7—OEB Pin Enable

If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled. If Bit 7 is clear, the OEB pin is disabled (default).

Bits[6:1]—Open

Bit 0—SDIO Pull-Down

Bit 0 can be set to disable the internal 30 k pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bits[7:4]—Open

Bit 3—VCM Power-Down

Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external reference.

Bits[2:0]—Open

Rev. 0 | Page 38 of 40

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AD9608

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9608 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9608, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different decoupling capacitors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9608. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance is easily achieved.

LVDS Operation

The AD9608 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed, using the SPI configuration registers after power-up. When the

AD9608 powers up in CMOS mode with LVDS termination

resistors (100 Ω) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9608, but it should be taken into account when considering the maximum DRVDD current for the part.

To avoid this additional DRVDD current, the AD9608 outputs can be disabled at power-up by taking the PDWN pin high. After the part is placed into LVDS mode via the SPI port, the PDWN pin can be taken low to enable the outputs.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the

AD9608 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection.

To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.

VCM

The VCM pin should be decoupled to ground with a 0.1 F capacitor.

Reference Decoupling

The VREF pin should be externally decoupled to ground with a low ESR, 1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic capacitor.

SPI Port

The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the

AD9608 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

Rev. 0 | Page 39 of 40

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AD9608

OUTLINE DIMENSIONS

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

PIN 1

INDICATOR

6.35

6.20 SQ

6.05

PIN 1

INDICATOR

9.00

BSC SQ

TOP VIE W

8.75

BSC SQ

0.60

MAX

0.50

BSC

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

0.05 MAX

0.02 NOM

0.20 REF

7.50 REF

FOR PROPER CO NNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRI PTIONS SECTION OF THIS DATA SHEET.

0.25 MIN

091707-C

Figure 63. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9608BCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608BCPZ-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608BCPZRL7-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608BCPZRL7-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9608-125EBZ Evaluation Board

Z = RoHS Compliant Part.

Rev. 0 | Page 40 of 40

Datasheet AD9608 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

AD9608-125

AD9608-105

EQUIVALENT CIRCUITS

THEORY OF OPERATION

ADC ARCHITECTURE

ANALOG INPUT CONSIDERATIONS

Input Common Mode

Differential Input Configurations

Single-Ended Input Configuration

Internal Reference Connection

VOLTAGE REFERENCE

External Reference Operation

CLOCK INPUT CONSIDERATIONS

Clock Input Options

Input Clock Divider

Clock Duty Cycle

Jitter Considerations

CHANNEL/CHIP SYNCHRONIZATION

POWER DISSIPATION AND STANDBY MODE

DIGITAL OUTPUTS

Digital Output Enable Function (OEB)

TIMING

Data Clock Output (DCO)

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

BUILT-IN SELF-TEST (BIST)

OUTPUT TEST MODES

SERIAL PORT INTERFACE (SPI)

CONFIGURATION USING THE SPI

HARDWARE INTERFACE

CONFIGURATION WITHOUT THE SPI

SPI ACCESSIBLE FEATURES

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Open Locations

Default Values

Logic Levels

Channel-Specific Registers

MEMORY MAP REGISTER TABLE

MEMORY MAP REGISTER DESCRIPTIONS

Power Modes (Register 0x08)

Bits[7:6]—Open

Bits[1:0]—Internal Power-Down Mode

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

Bits[1:0]—Open

Output Mode (Register 0x14)

Bits[7:6]—Output Port Logic Type

Bit 5—Output Interleave Enable

Bit 4—Output Port Disable

Bits[7:3]—Open

Bit 2—Clock Divider Next Sync Only

Bit 1—Clock Divider Sync Enable

Bit 0—Open

Transfer (Register 0xFF)

Sample Rate Override (Register 0x100)

User I/O Control 2 (Register 0x101)