Datasheet AD9601 Datasheet (ANALOG DEVICES)

10-Bit, 200 MSPS/250 MSPS

FEATURES

SNR = 59.4 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 9.7 @ f SFDR = 81 dBc @ f Excellent linearity

DNL = 0.2 LSB typical INL = 0.2 LSB typical

CMOS outputs

Single data port at up to 250 MHz

Demultiplexed dual port at up to 2 × 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation

274 mW @ 200 MSPS

322 mW @ 250 MSPS Programmable input voltage range

1.0 V to 1.5 V, 1.25 V nominal

1.8 V analog and digital supply operation Selectable output data format (offset binary, twos

complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock

up to 70 MHz @ 250 MSPS (−1.0 dBFS)

IN

up to 70 MHz @ 250 MSPS (−1.0 dBFS)

IN

1.8 V Analog-to-Digital Converter AD9601

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

FUNCTIONAL BLOCK DIAGRAM

AGNDPWDNRBIAS AVDD (1.8V)

CML

VIN+

VIN–

CLK+

CLK–

REFERENCE

TRACK-AND-HOLD

CLOCK

MANAGEMENT

ADC 10-BIT CORE

SERIAL PORT

RESET

SCLK SDIO CSB

10 10

Figure 1.

AD9601

OUTPUT

STAGING

LVDS

DRVDD

DRGND

Dx9 TO Dx0

OVRA

OVRB

DCO+

DCO–

07100-001

GENERAL DESCRIPTION

The AD9601 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.

The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.

Fabricated on an advanced CMOS process, the AD9601 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. High Performance—Maintains 59.4 dBFS SNR @ 250 MSPS

with a 70 MHz input.

2. Low Power—Consumes only 322 mW @ 250 MSPS.

3. Ease of Use—CMOS output data and output clock signal

allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.

4. Serial Port Control—Standard serial port interface supports

various product functions, such as data formatting, powerdown, gain adjust, and output test pattern generation.

5. Pin-Compatible Family—12-bit pin-compatible family

offered as the AD9626.

AD9601

REVISION HISTORY

11/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD9601

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T unless otherwise noted.

Table 1.

Parameter

1

RESOLUTION 10 10 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error 25°C 4.0 4.0 mV Full −12 +12 −12 +12 mV Gain Error 25°C 1.4 1.4 % FS Full −2.1 +4.5 −2.1 +4.5 % FS Differential Nonlinearity (DNL) 25°C 0.2 0.2 LSB Full −0.5 +0.5 −0.5 +0.5 LSB Integral Nonlinearity (INL) 25°C 0.2 0.2 LSB Full −0.5 +0.5 −0.5 +0.5 LSB

TEMPERATURE DRIFT

Offset Error Full 8 8 µV/°C Gain Error Full 0.021 0.021 %/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range Input Common-Mode Voltage Full 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 kΩ Input Capacitance 25°C 2 2 pF

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Currents

3

I

AVDD

3

I

/Single Port Mode

DRVDD

3

I

/Interleaved Mode

DRVDD

Power Dissipation

Single Port Mode

Interleaved Mode

3

4

5

4

5

Power-Down Mode Supply Currents

I

AVDD

I

DRVDD

Standby Mode Supply Currents

I

AVDD

I

DRVDD

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.

3

I

and I

AVDD

4

Single data rate mode; this is the default mode of the AD9601.

5

Interleaved mode; user-programmable feature. See the Memory Map section.

are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.

DRVDD

= −40°C, T

MIN

2

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled,

MAX

AD9601-200 AD9601-250

Temp Min Typ Max Min Typ Max Unit

Full 0.98 1.25 1.5 0.98 1.25 1.5 V p-p

Full 133 142 157 167 mA Full 19 20 22 24 mA Full 16 18 mA Full mW Full 274 291 322 344 mW

Full 268 315 mW

Full 40 40 µA Full 170 170 22 µA

Full 19 19 mA Full 170 170 22 µA

Rev. 0 | Page 3 of 32

AD9601

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

Table 2.

AD9601-200 AD9601-250

Parameter2 Temp Min Typ Max Min Typ Max Unit

SNR

fIN = 10 MHz 25°C 59.5 59.4 dB Full 58.5 57.8 dB fIN = 70 MHz 25°C 59.3 59.4 dB

SINAD

fIN = 10 MHz 25°C 59.5 59.4 dB Full 58.5 57.7 dB fIN = 70 MHz 25°C 59.3 59.4 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 9.6 9.7 Bits fIN = 70 MHz 25°C 9.6 9.7 Bits

WORST HARMONIC (SECOND OR THIRD)

fIN = 10 MHz 25°C 84 84 dBc Full 77 72 dBc fIN = 70 MHz 25°C 78 81 dBc

WORST OTHER (SFDR EXCLUDING SECOND AND THIRD)

fIN = 10 MHz 25°C 88 86 dBc Full 80 75 dBc fIN = 70 MHz 25°C 87 85 dBc

TWO-TONE IMD

170.2 MHz/171.3 MHz @ −7 dBFS 25°C 81 81 dBFS

ANALOG INPUT BANDWIDTH 25°C 700 700 MHz

1

All ac specifications tested by driving CLK+ and CLK− differentially.

2

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

1

Rev. 0 | Page 4 of 32

AD9601

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 3.

AD9601-200 AD9601-250 Parameter1 Temp Min Typ Max Min Typ Max Unit

CLOCK INPUTS

Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 1.2 V Differential Input Voltage Full 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 V Input Resistance (Differential) Full 16 20 24 16 20 24 kΩ Input Capacitance Full 4 4 pF

LOGIC INPUTS

Logic 1 Voltage Full 0.8 × VDD 0.8 × VDD V Logic 0 Voltage Full 0.2 × AVDD 0.2 × AVDD V Logic 1 Input Current (SDIO) Full 0 0 µA Logic 0 Input Current (SDIO) Full −60 −60 µA Logic 1 Input Current

(SCLK, PDWN, CSB, RESET)

Logic 0 Input Current

(SCLK, PDWN, CSB, RESET)

Input Capacitance 25°C 4 4 pF

LOGIC OUTPUTS

High Level Output Voltage Full DRVDD − 0.05 DRVDD − 0.05 V Low Level Output Voltage Full GND + 0.05 GND + 0.05 V Output Coding Twos complement, Gray code, or offset binary (default)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

Full 55 50 µA

Full 0 0 µA

Rev. 0 | Page 5 of 32

AD9601

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, T

Table 4.

AD9601-200 AD9601-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit

Maximum Conversion Rate Full 200 Minimum Conversion Rate Full CLK+ Pulse Width High (tCH) Full 2.15 2.4 1.8 2.0 ns CLK+ Pulse Width Low (tCL) Full 2.15 2.4 1.8 2.0 ns Output, Single Data Port Mode

Data Propagation Delay (tPD) 25°C 3.7 3.7 ns DCO Propagation Delay (t Data to DCO Skew (t

CPD

) Full 0 0.3 0.55 0 0.3 0.55 ns

SKEW

Latency Full 6 6 Cycles

SKEWA

2

PDA

CPDA

, t

SKEWB

Output, Interleaved Mode

Data Propagation Delay (t DCO Propagation Delay (t Data to DCO Skew (t

Latency Full 6 6 Cycles Standby Recovery 25°C 250 250 ns Power-Down Recovery 50 50 µs Aperture Delay (tA) 25°C 0.1 0.1 ns Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms

1

See Figure 2.

2

See Figure 3.

1

= −40°C, T

MIN

= +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

MAX

250 40

40 MSPS

MSPS

) 25°C 3.4 3.4 ns

, t

) 25°C 3.5 3.5 ns

PDB

, t

) 25°C 3.0 3.0 ns

CPDB

) Full 0 0.5 1.1 0 0.5 1.1 ns

Rev. 0 | Page 6 of 32

AD9601

TIMING DIAGRAMS

N + 2

N + 1

N

t

A

t

= 1/

f

CLK+

CLK–

DCO–

DCO+

t

DAX N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7

CLK

t

CPD

t

SKEW

PD

N + 2

CLK+

CLK–

DCO+

DCO–

DAX

N + 1

N

t

A

t

= 1/

f

CLK

t

CPDA

t

PDA

SKEWA

N + 3

CLK

N – 6

N + 3

CLK

Figure 2. Single Port Mode

N + 4

N + 5

t

CPDB

N – 4

N + 4

N + 6

N + 5

N – 2

N + 7

N + 6

N + 8

N + 7

N + 8

07100-042

N

N + 2

t

SKEWB

t

PDB

DBX

N – 7

N – 5

N – 3

N – 1

N + 1

07100-043

Figure 3. Interleaved Mode

Rev. 0 | Page 7 of 32

AD9601

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

ELECTRICAL

AVDD to AGND −0.3 V to +2.0 V

DRVDD to DRGND −0.3 V to +2.0 V

AGND to DRGND −0.3 V to +0.3 V

AVDD to DRVDD −2.0 V to +2.0 V

Dx0 Through Dx9 to DRGND −0.3 V to DRVDD + 0.3 V

DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V

OVRA/OVRB to DGND −0.3 V to DRVDD + 0.3 V

CLK+ to AGND −0.3 V to +3.6 V

CLK− to AGND −0.3 V to +3.6 V

VIN+ to AGND −0.3 V to AVDD + 0.2 V

VIN− to AGND −0.3 V to AVDD + 0.2 V

SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V

PDWN to AGND −0.3 V to +3.6 V

CSB to AGND −0.3 V to +3.6 V

SCLK/DFS to AGND −0.3 V to +3.6 V ENVIRONMENTAL

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +85°C

Lead Temperature

(Soldering, 10 sec)

Junction Temperature 150°C

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 6.

Package Type θ

56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W

JA

θ

JC

Unit

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ

JA

. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 8 of 32

AD9601

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

A1 D

DA0 (LSB)

NIC

DA2

54

53

55

PIN 1 INDICATO R

17

16

18

B6 D

DB5

DB4

NIC

52

51

AD9601

TOP VIEW

(Not to Scale)

20

19

DB8

DB7

DA3

56

1DA4 2DA5 3DA6 4DA7 5DA8 6(MSB) DA9 7DRVDD 8DRGND

9OVRA 10NIC 11NIC 12(L SB) DB0

PIN 0 (EXPOSED PADDLE) = AGND

13DB1 14DB2

15

DB3

DCO+

DCO–

DRGND

50

49

48

21

23

22

OVRB

RGND D

(MSB) DB9

VDD A

CLK+

DRVDD

AVDD

CLK–

43

44

47

46

45

42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ 34 AVDD 33 AVDD 32 AVDD 31 RBIAS 30 AVDD 29 PWDN

28

27

25

26

24

ET

CSB

RES

DRVDD

SDIO/DCS

SCLK/DFS

07100-002

Figure 4. Pin Configuration

Table 7. Single Data Rate Mode Pin Function Descriptions

Pin No. Mnemonic Description

30, 32, 33, 34, 37, 38, 39,

AVDD 1.8 V Analog Supply.

41, 42, 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 0 AGND 8, 23, 48 DRGND

1

Analog Ground.

Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML

Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 RBIAS

Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.)

Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 25 SDIO/DCS

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer

Select (External Pin Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 53 DA0 (LSB) Output Port A Output Bit 0 (LSB). 54 DA1 Output Port A Output Bit 1. 55 DA2 Output Port A Output Bit 2. 56 DA3 Output Port A Output Bit 3. 1 DA4 Output Port A Output Bit 4. 2 DA5 Output Port A Output Bit 5. 3 DA6 Output Port A Output Bit 6.

Rev. 0 | Page 9 of 32

AD9601

Pin No. Mnemonic Description

4 DA7 Output Port A Output Bit 7. 5 DA8 Output Port A Output Bit 8. 6 DA9 (MSB) Output Port A Output Bit 9 (MSB). 10, 11, 51, 52 NIC Not internally connected. 9 OVRA Output Port A Overrange Output Bit. 12 DB0 (LSB) Output Port B Output Bit 0 (LSB). 13 DB1 Output Port B Output Bit 1. 14 DB2 Output Port B Output Bit 2. 15 DB3 Output Port B Output Bit 3. 16 DB4 Output Port B Output Bit 4. 17 DB5 Output Port B Output Bit 5. 18 DB6 Output Port B Output Bit 6. 19 DB7 Output Port B Output Bit 7. 20 DB8 Output Port B Output Bit 8. 21 DB9 (MSB) Output Port B Output Bit 9 (MSB). 22 OVRB Output Port B Overrange Output Bit.

1

AGND and DRGND should be tied to a common quiet ground plane.

Rev. 0 | Page 10 of 32

AD9601

V

C

EQUIVALENT CIRCUITS

CLK+

IN+

10kΩ 10kΩ

Figure 5. Clock Inputs

AVDD

1.2V

2kΩ

BUF

AVDD

V

CML

~1.4V

CLK–

SB

07100-003

Figure 8. Equivalent CSB Input Circuit

AVDD

26kΩ

1kΩ

DRVDD

07100-006

VIN–

Figure 6. Analog Inputs (V

SCLK/DFS

RESET

PDWN

Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit

30kΩ

BUF

1kΩ

= ~1.4 V)

CML

DRGND

7100-004

7100-044

Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−)

DRVDD

SDIO/DCS

07100-005

1kΩ

07100-007

Figure 10. Equivalent SDIO/DCS Input Circuit

Rev. 0 | Page 11 of 32

AD9601

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless otherwise noted.

–20

–40

0

200MSPS

10.3MHz @ –1.0dBFS SNR: 59.48dB ENOB: 9.58 BITS SFDR: 83.79d Bc

70k

60k

50k

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0

FREQUENCY (MHz)

10010 20 30 40 50 60 70 80 90

Figure 11. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz

0

200MSPS

70.3MHz @ –1.0dBF S

–20

SNR: 59.3dB ENOB: 9.7 BITS SFDR: 78dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0

FREQUENCY (MHz)

10010 20 30 40 50 60 70 80 90

Figure 12. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz

40k

30k

NUMBER OF HITS

20k

10k

0

07100-020

N – 1N – 2 N N + 1

BIN

07100-023

Figure 14. AD9601-200 Grounded Input Histogram; 200 MSPS

90

85

80

75

70

65

SNR/SFDR (dB)

60

55

50

07100-021

Figure 15. AD9601-200 Single-Tone SNR/SFDR vs. Input Frequency (f

SFDR (+85°C)

SFDR (–40°C)

SFDR (+25°C)

SNR (+25°C)

SNR (+85°C)

50 100 150 200 250 300 350 400 450

0 500

ANALOG INPUT FREQUENCY (MHz)

SNR (–40°C)

) and

IN

07100-024

Temperature with 1.25 V p-p Full Scale; 200 MSPS

AMPLITUDE (dBFS)

–20

–40

–60

–80

–100

–120

–140

0

FREQUENCY (MHz)

200MSPS

170.3MHz @ –1.0d BFS SNR: 59.35dB ENOB: 9.7 BITS SFDR: 83dBc

10010 20 30 40 50 60 70 80 90

07100-022

Figure 13. AD9601-200 64k Point Single-Tone FFT; 200 MSPS, 170.3 MHz

Rev. 0 | Page 12 of 32

90

80

70

60

SNR (dBFS)

50

40

SNR/SFDR (dB)

30

20

10

0

90 0

80 70 60 50 40 30 20 10

SFDR (dBFS)

SFDR (dBc)

AMPLITUDE (–dBFS)

SNR (dB)

07100-025

Figure 16. AD9601-200 SNR/SFDR vs. Input Amplitude; 170.3 MHz

AD9601

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

01

128 256 384 512 640 768 896

OUTPUT CODE

024

07100-026

Figure 17. AD9601-200 INL; 200 MSPS

90

85

80

75

70

65

SNR/SFDR (dB)

60

SNR (+85°C)

55

50

0 500

50 100 150 200 250 300 350 400 450

SFDR (+25°C)

SFDR (+85°C)

SNR (+25°C)

ANALOG INPUT FREQUENCY (MHz)

SNR (–40°C)

SFDR (–40°C)

Figure 20. SNR/SFDR vs. Analog Input Frequency, Interleaved Mode vs.

Temperature

07100-029

400

350

300

250

200

150

CURRENT (mA)

100

50

0

25 45 65 85 105 125 145 165 185 205 225

5 245

TOTAL POWER (mW)

I

(mA)

AVDD

I

(mA)

DVDD

SAMPLE RATE (MSPS)

07100-027

Figure 18. AD9601-200 Power Supply Current vs. Sample Rate

1.0

0.8

0.6

0.4

0.2

0

DNL (LS B)

–0.2

–0.4

–0.6

–0.8

–1.0

128 256 384 512 640 768 896

01

OUTPUT CODE

024

07100-028

Figure 19. AD9601-200 DNL; 200 MSPS

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0

Figure 21. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz

0

250MSPS

70.3MHz @ –1.0dBFS

–20

SNR: 59.4dB ENOB: 9.7 BITS SFDR: 81dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0

Figure 22. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz

250MSPS

10.3MHz @ –1.0dBFS SNR: 59.4dB ENOB: 9.7 BITS SFDR: 84dBc

20 40 60 80 100 120

FREQUENCY (MHz)

20 40 60 80 100 120

FREQUENCY (MHz)

07100-030

07100-031

Rev. 0 | Page 13 of 32

AD9601

0

250MSPS

170.3MHz @ –1.0dBFS

–20

SNR: 59.1dB ENOB: 9.60 BITS SFDR: 73dBc

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

–140

0

20 40 60 80 100 120

FREQUENCY (MHz)

Figure 23. AD9601-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz

70k

60k

50k

40k

30k

NUMBER OF HITS

20k

10k

0

N – 2 N – 1 N N + 1 N + 2

BIN

Figure 24. AD9601-250 Grounded Input Histogram; 250 MSPS

100

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

90 0

07100-032

SFDR (dBFS)

SNR (dBFS)

SNR (dB)SFDR (dBc)

80 70 60 50 40 30 20 10

AMPLITUDE (–dBFS)

07100-035

Figure 26. AD9601-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

07100-033

128 256 384 512 640 768 896

01

OUTPUT CODE

024

07100-036

Figure 27. AD9601-250 DNL; 250 MSPS

90

85

80

75

70

65

SNR/SFDR (dB)

60

SNR (+85°C)

55

50

0 500

SFDR (+85°C)

SFDR (+25°C)

SFDR (–40°C)

SNR (+25°C)

SNR (–40°C)

50 100 150 200 250 300 350 400 450

ANALOG INPUT FREQUENCY (MHz)

Figure 25. AD9601-250 Single-Tone SNR/SFDR vs. Input Frequency (f

Temperature with 1.25 V p-p Full Scale; 250 MSPS

07100-034

) and

IN

Rev. 0 | Page 14 of 32

400

350

300

250

200

150

CURRENT (mA)

100

50

0

25 45 65 85 105 125 145 165 185 205 225

5 245

TOTAL POWER (mW)

I

(mA)

AVDD

I

(mA)

DVDD

SAMPLE RATE (MSPS)

Figure 28. AD9601 Power Supply Current vs. Sample Rate

07100-037

AD9601

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

128 256 384 512 640 768 896

OUTPUT CODE

07100-038

Figure 29. AD9601-250 DNL; 250 MSPS

2.5

2.0

1.5

1.0

GAIN (%FS)

0.5

–0.5

0

–60 120100806040200–20–40

AD9601-250

AD9601-210

AD9601-170

TEMPERATURE ( °C)

Figure 31. Gain vs. Temperature

07100-040

90

80

70

60

50

40

SNR/SFDR (dB)

30

20

10

0

SFDR

SNR

12575 175 225 275

SAMPLE RATE (MSPS)

07100-039

Figure 30. SNR/SFDR vs. Sample Rate;

6.0

5.5

5.0

4.5

4.0

OFFSET (mV)

3.5

3.0

2.5

2.0

AD9601-210

–40 –30 –20 –10 0 908070605040302010

Figure 32. Offset vs. Temperature

AD9601-250

AD9601-170

TEMPERATURE ( °C)

07100-041

AD9626-250 , 170.3 MHz @ −1 dBFS

Rev. 0 | Page 15 of 32

AD9601

V

A

THEORY OF OPERATION

The AD9601 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac- or dc-coupled. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During powerdown, the output buffers go into a high impedance state.

ANALOG INPUT AND VOLTAGE REFERENCE

The analog input to the AD9601 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially.

A wideband transformer, such as Mini-Circuits® ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.4 V.

An internal differential voltage reference creates positive and negative reference voltages that define the 1.25 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of SPI control. See the the SPI

section for more details.

Differential Input Configurations

Optimum performance is achieved while driving the AD9601 in a differential input configuration. For baseband applications, the

AD8138 differential driver provides excellent performance

and a flexible interface to the ADC. The output common-mode voltage of the

AD8138 is easily set to AVDD/2 + 0.5 V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

AD9601 Configuration Using

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the AD9601. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few millihertz, and excessive signal power can also cause core saturation, which leads to distortion.

In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.

As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the driver can be used (see

NALOG INPUT

49.9Ω1V p-p

499Ω

0.1µF

523Ω

Figure 33. Differential Input Configuration Using the

499Ω

AD8138

499Ω

33Ω

20pF

33Ω

AVDD

VIN+

AD9601

VIN–

CML

AD8138

15Ω

50Ω1.25V p-p

0.1µF

2pF

15Ω

VIN+

AD9601

VIN–

07100-009

Figure 34. Differential Transformer-Coupled Configuration

AD8352 differential

Figure 35).

CC

0.1µF

0Ω

16

1

2

C

DRDRG

0.1µF

3

4

5

0Ω

Figure 35. Differential Input Configuration Using the AD8352

8, 13

AD8352

14

0.1µF

11

10

0.1µF

200Ω

R

C

R

0.1µF

VIN+

AD9601

VIN–

CML

7100-008

07100-010

Rev. 0 | Page 16 of 32

AD9601

A

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9601 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ pin and the CLK− pin via a transformer or capacitors. These pins are biased internally and require no additional bias.

Figure 36 shows one preferred method for clocking the AD9601. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9601 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9601 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance.

In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see

Figure 39). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible.

D9510/AD9511/

AD9512/AD9513/

CLOCK

INPUT

0.1µF

50Ω*

0.1µF

AD9514/AD9515

CLK

CMOS DRIVER

CLK

0.1µF

OPTIONAL

100Ω

39kΩ

0.1µF

CLK+

ADC

AD9601

CLK–

MINI-CIRCUI TS

CLOCK

INPUT

50Ω

ADT1–1WT, 1:1Z

100Ω

XFMR

0.1µF

0.1µF0.1µF

0.1µF

SCHOTTKY

DIODES:

HSM2812

CLK+

ADC

AD9601

CLK–

Figure 36. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in

Figure 37. The AD9510/AD9511/AD9512/AD9513/

AD9514/AD9515 family of clock drivers offers excellent jitter

performance.

AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515

CLOCK

INPUT

CLOCK

INPUT

50Ω* 50Ω*

*50Ω RESISTORS ARE OPTIONAL.

0.1µF

CLK

PECL DRIVER

CLK

0.1µF

CLK+

100Ω

0.1µF

240Ω240Ω

ADC

AD9601

CLK–

Figure 37. Differential PECL Sample Clock

AD9510/AD9511/

CLOCK

INPUT

CLOCK

INPUT

50Ω* 50Ω*

*50Ω RESISTORS ARE OPTIONAL.

0.1µF

Figure 38. Differential LVDS Sample Clock

AD9512/AD9513/ AD9514/AD9515

CLK

LVDS DRIVER

CLK

0.1µF

100Ω

0.1µF

CLK+

ADC

AD9601

CLK–

*50Ω RESISTOR IS OPTIONAL.

07100-014

Figure 39. Single-Ended 1.8 V CMOS Sample Clock

AD9510/AD9511/ AD9512/AD9513/

CLOCK

07100-011

INPUT

*50Ω RESISTOR IS OPT IONAL.

0.1µF

50Ω*

0.1µF

AD9514/AD9515

CLK

CMOS DRIVER

CLK

OPTIONAL

100Ω

0.1µF

CLK+

ADC

AD9601

CLK–

07100-015

Figure 40. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9601 contains a duty cycle

07100-012

stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9601. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the AD9601 Configuration Using the SPI section for more details on using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

07100-013

create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate.

Rev. 0 | Page 17 of 32

AD9601

O

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR for a full-scale input signal at a given input frequency (f

) due only to aperture jitter (tJ) can

A

be calculated by

SNR Degradation = 20 × log

[1/2 × π × fA × tJ]

10

In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see

Figure 41).

The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9601. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit

130

RMS CLOCK JIT TER REQUIREMENT

120

110

100

90

80

SNR (dB)

70

10 BITS

60

8 BITS

50

40

30

1 10 100 1000

Figure 41. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS Input Signal

ANALOG INPUT FREQUENCY (MHz)

0.125ps

0.25ps

www.analog.com).

0.5ps

1.0ps

2.0ps

16 BITS

14 BITS

12 BITS

07100-016

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 28, the power dissipated by the AD9601 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.

By asserting PDWN (Pin 29) high, the AD9601 is placed in standby mode or full power-down mode, as determined by the contents of Serial Port Register 08. Reasserting the PDWN pin low returns the AD9601 into its normal operational mode.

An additional standby mode is supported by means of varying the clock input. When the clock rate falls below 20 MHz, the AD9601 assumes a standby state. In this case, the biasing network

and internal reference remain on, but digital circuitry is powered down. Upon reactivating the clock, the AD9601 resumes normal operation after allowing for the pipeline latency.

DIGITAL OUTPUTS

Digital Outputs and Timing

The off-chip drivers on the AD9601 are CMOS-compatible output levels. The outputs are biased from a separate supply (DRVDD), allowing isolation from the analog supply and easy interface to external logic. The outputs are CMOS devices that swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (<1 inch, for a total C When operating in CMOS mode, it is also recommended to place low value (20 Ω) series damping resistors on the data lines to reduce switching transient effects on performance.

The format of the output data is offset binary by default. An example of the output coding format can be found in If it is desired to change the output data format to twos complement, see the

AD9601 Configuration Using the SPI section.

An output clock signal is provided to assist in capturing data from the AD9601. The DCO+/DCO− signal is used to clock the output data and is equal to the sampling clock (CLK) rate in single port mode, and one-half the clock rate in interleaved output mode. See the timing diagrams shown in Figure 3 for more information.

Out-of-Range

An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OVRA/OVRB is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OVRA/OVRB has the same pipeline latency as the digital data. OVRA/OVRB is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in

Figure 42. OVRA/OVRB remains high until the analog input returns to within the input range and another conversion is completed. By logically AND-ing OVRA/OVRB with the MSB and its complement, overrange high or underrange low conditions can be detected.

VRA/OVRB

DATA OUTPUT S

1111

1

1111

0

1111

0

1111

0

0000

0

0000

1

0000

Figure 42. OVRA/OVRB Relation to Input Voltage and Output Data

1111 1111 1110

0001 0000 0000

OVRA/ OVRB

–FS + 1/2 L SB

–FS – 1/2 LSB

+FS – 1 LS B

+FS – 1/2 L SB

< 5 pF).

LOAD

Tabl e 11 .

Figure 2 and

+FS–FS

07100-017

Rev. 0 | Page 18 of 32

AD9601

TIMING—SINGLE PORT MODE

In single port mode, the CMOS output data is available from Data Port A (DA0 to DA9). The outputs for Port B (DB0 to DB9) are unused, and are high impedance in this mode. The Port A outputs and the differential output data clock (DCO+/DCO−) switch nearly simultaneously during the rising edge of DCO+. In this mode, it is recommended to use the rising edge of DCO− to capture the data from Port A. The setup and hold time depends on the input sample clock period, and is approximately 1/f

CLK

± t

SKEW

.

TIMING—INTERLEAVED MODE

In interleaved mode, the output data of the AD9601 is demultiplexed onto two data port buses, Port A (DA0 to DA9) and Port B (DB0 to DB9). The output data and differential data capture clock switch at one-half the rate of the sample clock input (CLK+/CLK−), increasing the setup and hold time for the external data capture circuit relative to single port mode (see Figure 3, interleaved mode timing diagram). The two ports switch on alternating sample clock cycles, with the data for Port A being valid during the rising edge of DCO+, and the data for Port B being valid during the rising edge of DCO−. The pipeline latency for both ports is six sample clock cycles. Due to the random nature of the ÷2 circuit that generates the timing for the output stage in interleaved mode, the first data sample during power-up can be assigned to either Data Port A or Port B. The user cannot control the polarity of the output data clock relative to the input sample clock. In this mode, it is recom-

mended to use the rising edge of DCO+ to capture the data from Port A, and the rising edge of DCO− to capture the data from Port B. In both cases, the setup and hold time depends on the input sample clock period, and both are approximately 2/f

± t

.

S

SKEW

fS/2 Spurious

Because the AD9601 output data rate is at one-half the sampling frequency in interleaved output mode, there is significant f

/2

S

energy in the outputs of the part, and there is significant energy in the ADC output spectrum at f certain that this f

/2 energy does not couple into either the clock

S

circuit or the analog inputs of the AD9601. When f

/2. Care must be taken to be

S

/2 energy is

S

coupled in this fashion, it appears as a spurious tone reflected around f

/4, 3fS/4, 5fS/4, and so on. For example, in a 125 MSPS

S

sampling application with a 90 MHz single-tone analog input, this energy generates a tone at 97.5 MHz.

[(3 × 125 MSPS/4 − 90 MHz) + 3 × 125 MSPS/4]

Depending on the relationship of the IF frequency to the center of the Nyquist zone, this spurious tone may or may not be in the user’s band of interest. Some residual f

/2 energy is present in

S

the AD9601, and the level of this spur is typically below the level of the harmonics at clock rates. the f

/2 spur level vs. the analog input frequency for the

S

AD9601-250. For the specifications provided in

Figure 20 shows a plot of

Tabl e 2, the fS/2 spur effect is not a factor, as the device is specified in single port output mode.

Rev. 0 | Page 19 of 32

AD9601

LAYOUT CONSIDERATIONS

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9601, it is recommended that two separate supplies be used: one for analog (AVDD, 1.8 V nominal) and one for digital (DRVDD, 1.8 V nominal). If only a single 1.8 V supply is available, it is routed to AVDD first, then tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding connection to DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length.

A single PC board ground plane is sufficient when using the AD9601. With proper decoupling and smart partitioning of analog, digital, and clock sections of the PC board, optimum performance is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9601. An exposed, continuous copper plane on the PCB should mate to the AD9601 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged.

To maximize the coverage and adhesion between the ADC and PCB, partition the continuous plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and PCB. See

Figure 43 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see Application Note AN-772,

A Design and Manufacturing Guide for the Lead Frame Chip Scale Package.

SILKSCREEN PARTITION

PIN 1 INDICATOR

07100-018

Figure 43. Typical PCB Layout

CML

The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in

Figure 45.

RBIAS

The AD9601 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance.

AD9601 CONFIGURATION USING THE SPI

The AD9601 SPI allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC. This gives the user added flexibility to customize device operation depending on the application. Addresses are accessed (programmed or read back) serially in one-byte words. Each byte can be further divided down into fields, which are documented in the

There are three pins that define the serial port interface or SPI to this particular ADC. They are the SPI SCLK/DFS, SPI SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used to synchronize the read and write data presented the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB is an active low control that enables or disables the read and write cycles (see

Table 8. Serial Port Pins

Mnemonic Function

SCLK

SDIO

CSB

RESET

SCLK (Serial Clock) is the serial shift clock in. SCLK is used to synchronize serial interface reads and writes.

SDIO (Serial Data Input/Output) is a dual-purpose pin. The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame.

CSB (Chip Select Bar) is an active low control that gates the read and write cycles.

Master Device Reset. When asserted, device assumes default settings. Active low.

The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in and

Tabl e 10 .

During an instruction phase, a 16-bit instruction is transmitted. Data then follows the instruction phase and is determined by the W0 and W1 bits, which is 1 or more bytes of data. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether this is a read or write command. This allows the serial data input/output (SDIO) pin to change direction from an input to an output.

Data can be sent in MSB or in LSB first mode. MSB first is default on power-up and can be changed by changing the configuration register. For more information about this feature and others, see Interfacing to High Speed ADCs via SPI at

www.analog.com.

Memory Map section.

Tabl e 8).

Figure 44

Rev. 0 | Page 20 of 32

AD9601

HARDWARE INTERFACE

The pins described in Ta b l e 8 comprise the physical interface between the user’s programming device and the serial port of the AD9601. All serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 kΩ).

This interface is flexible enough to be controlled by either PROMS or PIC microcontrollers as well. This provides the user with an alternate method to program the ADC other than a SPI controller.

If the user chooses not to use the SPI interface, some pins serve a dual function and are associated with a specific function when strapped externally to AVDD or ground during device poweron. The strappable functions supported on the AD9601.

Configuration Without the SPI section describes the

t

DS

CSB

t

S

t

DH

t

HI

t

CLK

t

LO

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers, the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer. In this mode, the SPI CSB chip select should be connected to ground, which disables the serial port interface.

Table 9. Mode Selection

External

Mnemonic

Voltage

Configuration

AVDD Duty cycle stabilizer enabled SPI SDIO/DCS AGND Duty cycle stabilizer disabled AVDD Twos complement enabled SPI SCLK/DFS AGND Offset binary enabled

t

H

SCLK

SDIO

DON’T CARE

R/W W1 W0 A12 A11 A10 A9 A8 A7

Figure 44. Serial Port Interface Timing Diagram

D5 D4 D3 D 2 D1 D0

DON’T CARE

DON’T C AREDON’T CARE

07100-019

Rev. 0 | Page 21 of 32

AD9601

Table 10. Serial Timing Definitions

Parameter Timing (minimum, ns) Description

t

DS

t

DH

t

CLK

t

S

t

H

t

HI

t

LO

t

EN_SDIO

t

DIS_SDIO

Table 11. Output Data Format

Input (V) Condition (V)

VIN+ − VIN− < 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 VIN+ − VIN− = 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = 0.62 1111 1111 1111 1111 1111 1111 0000 0000 0000 0 VIN+ − VIN− > 0.62 + 0.5 LSB 1111 1111 1111 1111 1111 1111 0000 0000 0000 1

5 Setup time between the data and the rising edge of SCLK 2 Hold time between the data and the rising edge of SCLK 40 Period of the clock 5 Setup time between CSB and SCLK 2 Hold time between CSB and SCLK 16 Minimum period that SCLK should be in a logic high state 16 Minimum period that SCLK should be in a logic low state 1

5

Offset Binary Output Mode D11 to D0

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in

Figure 44)

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in

Figure 44)

Twos Complement Mode D11 to D0

Gray Code Mode (SPI Accessible)

D11 to D0

OR

Rev. 0 | Page 22 of 32

AD9601

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer register map (Address 0xFF), and program register map (Address 0x08 to Address 0x2A).

The Addr (Hex) column of the memory map indicates the register address in hexadecimal, and the Default Value (Hex) column shows the default hexadecimal value that is already written into the register. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The default value enables the duty cycle stabilizer. Overwriting this default so that Bit 0 = 0 disables the duty cycle stabilizer. For more information on this and other functions, consult the Inter facing to High Speed ADCs via SPI user manual at

Table 12. Memory Map Register

Addr (Hex)

Chip Configuration Registers

00 chip_port_config 0 LSB

01 chip_id 8-bit chip ID, Bits[7:0]

02 chip_grade 0 0 0 Speed grade:

Transfer Register

FF device_update 0 0 0 0 0 0 0 SW

ADC Functions

08 modes 0 0 PDWN:

Parameter Name

Bit 7 (MSB)

www.analog.com.

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles

first

AD9601 = 0x36

01 = 200 MSPS 10 = 250 MSPS

0 0 Internal power-down mode: 0 = full (default) 1 =

standby

RESERVED LOCATIONS

Undefined memory locations should not be written to other than their default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

Coming out of reset, critical registers are preloaded with default values. These values are indicated in

Tabl e 12 . Other registers do not have default values and retain the previous value when exiting reset.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”

Default Bit 0 (LSB)

X X X Read-

transfer

000 = normal (power-up, default)

001 = full power-down

010 = standby

011 = normal (power-up)

Note: external PDWN pin overrides

this setting

Value

(Hex)

Read-

only

0x00 Synchronously

0x00 Determines

Default Notes/ Comments

should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode.

Default is unique chip ID, different for each device. This is a readonly register.

Child ID used to differentiate graded devices.

transfers data from the master shift register to the slave.

various generic modes of chip operation.

Rev. 0 | Page 23 of 32

AD9601

Default Addr (Hex)

Parameter Name

09 clock 0 0 0 0 0 0 0 Duty cycle

OD test_io Reset

OF ain_config 0 0 0 0 0 Analog

14 output_mode 0 0 Interleave

16 output_phase Output

17 flex_output_delay Output

18 flex_vref Input voltage range setting:

Bit 7 (MSB)

clock polarity 1 = inverted 0 = normal (default)

delay enable: 0 = enable 1 = disable

Bit 0

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Reset PN23 gen: 1 = on 0 = off (default)

output mode: 1 = enabled 0 = disabled (default)

0 0 0 0x03

Output clock delay:

PN9 gen:

1 = on

0 = off

(default)

Output

enable:

0 =

enable

(default)

1 =

disable

(Format determined by output_mode)

0 Output

Output test mode:

0000 = off (default)

0001 = midscale short

0010 = +FS short 0011 = −FS short

0100 = checker board output

0101 = PN 23 sequence

0110 = PN 9

0111 = one/zero word toggle

1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused

CML input disable:

1 = on 0 = off (default)

invert: 1 = on 0 = off (default)

00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns

11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns

10000 = 0.98 V

10001 =1.00 V

10010 = 1.02 V

10011 =1.04 V

11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V

01110 = 1.48 V 01111 = 1.50 V

enable:

1 = on

0 = off

(default)

Data format select:

00 = offset binary

…

(LSB)

stabilizer: 0 = disabled 1 = enabled (default)

0 0x00

(default)

01 = twos

complement

10 = Gray code

Value (Hex)

0x01

0x00 When set, the

0x00

Default Notes/ Comments

test data is placed on the output pins in place of normal data.

Rev. 0 | Page 24 of 32

AD9601

A

EVALUATION BOARD

D8B

D6B

D4B

D10B

DORB

49

D9

D10

P7

GNDCD10

C10

CONNECTS TO J 2

DOR

GND

CSB

E33

E32

VSPI

P17

GND

P5

P4P3P2

GND

GNDCD9

E31

CSB_DUT

59

P16

GND

C9

D10

RN1

GNDCD8

39

GNDCD5

GNDCD6

GNDCD7

D8

DOR

16

50_OHMS

1

P10

P9

GND

P1

GND

D2B

D0B

415042434445464748

D1

D2D3D4D5D6D7D8

GNDCD1

GNDCD2

GNDCD3

GNDCD4

D2D4D6

DORB

15

GNDAB10

C1

C2C3C4C5C6C7C8

314032333435363738

516052535455565758

D0

D10

D11B

D11

121314

11

2345678

VSPI

E3

R10

1K

E1

SDIO_ODM SCLK_DTP

E4

E10

R13

1K

E5

GND

VSPI

D11B

B9

B10

GNDAB9

A10

A9

10

29

D11

D9BD9D10B

9

10

GND

E2

AVDD

R11

D9B

19

GNDAB8

9

D9

D1B

D7B

D5B

D3B

DCOBDCO

112012131415161718

B1

B2B3B4B5B6B7B8

GNDAB1

GNDAB2

GNDAB3

GNDAB4

GNDAB5

GNDAB6

GNDAB7

A1

A2A3A4A5A6A7A8

2345678

213022232425262728

D1

D3D5D7

1

P11

CONNECTS TO J 1

HEADERM1469169_1

GND

D8BD8D7BD7D6B

D6

9

10

121314

152

RN2

50_OHMS

116

15

D9B

16

D9

17

D10B

18

D10

19

D11B

20

D11

21

DORB

22

DOR

GND

23 48

DGND1

DRVDD

24 47

DVDD1

25

SPSDIO/DCS

26

SPSCLK/DFS

CSB

27

SPCSB

28

RESETB

1K

E7

SW3

EVQ-Q2

12

IN OUT

GND

10K R12

GND

T3

Alternate Options

ADT1-1WT

34567

13

PDN

RBIAS

AVDD_REF

30

29

31

AVDD

E8

E9

GND

VSPI

TOUTBTINB

TOUTGND

6

1234

5

T5

PRI SEC

nc

CML CML

DNP

R4

11

50_OHMS

8

DRVDD

GND

109121114

8

7

D6

D5

D6BD7D7BD8D8B

DVDD

DGND

U4

AD9601_CSP

AIN

AINB

AVDD_PIPE2

AVDD_PIPE3

AVDD_PIPE4

AVDD_PIPE5

343332

35

36

AVDD

33 R7

0

R9

DNP

L8

C21

0.1UF

AMPOUT+

36

R6

R5

CML

C19

0.1UF

T6

5

1

2

34

GND

PRI SEC

GND

ETC1-1-13

C22

0.1UF

TOUT

CML

1

GND

C16

0.1UF

TOUTB

425

E6

3

PRI SEC

ETC1-1-13

TINB

L1

10NH

49

D9

D10

GNDCD8

GNDCD9

GNDCD10

C10

C9

39

59

D5

D5B

15

16

RN3

2345678

1

6

D5B

AVDD_CLK1

AVDD_PIPE

AVDD_PIPE1

CML

393837

AVDD

C17 DNP

33

optional

R16

0

GND

36

GND

40

L9

AMPOUT-

0.1UF

GNDCD7

21435

D3

DCO

DCOB

DGND2 DVDD2

CLKB

AVDD_FL1

41

AVDD

C18

GNDCD6

D4BD4D3B

D3BD4D4B

D2

D2B

D1

D1B

D0

D0B

CLK

AVDD_FL

42

AVDD

121314

PAD

GNDCD5

D3

57 56 55 54 53

52 51 50 49

46 45 44 43

CMLX

07100-045

SDO_CHA

SDI_CHA

GNDCD4

GNDCD3

GNDCD2

D2D3D4D5D6D7D8

GNDCD1

C2C3C4C5C6C7C8

SCLK_CH

19

415042434445464748

B9

D1

B10

GNDAB4

GNDAB5

GNDAB6

GNDAB7

GNDAB8

GNDAB9

GNDAB10

A10

A9

C1

9

314032333435363738

29

516052535455565758

112012131415161718

B1

B2B3B4B5B6B7B8

GNDAB1

GNDAB2

GNDAB3

A1

A2A3A4A5A6A7A8

1102345678

213022232425262728

HEADERM1469169_1

CSB1_CHA

D1

D1BD0D0B

D2B

RN4

50_OHMS

D2

152

34567

116

9

10

11

DCOB

DCO

9

10

121314

11

8

GND

C61

0.1UF

GND

R86

10K

GND

VCLK

GND

E20

E19

E18

C74

0.1UF

3

GND

TRI_STATE

VCLK

NC

5

VCLK

CR2

3

CR3

1

2

DNP

GND

C23

CLKCT

0.1UF

6

1234

5

PRI SEC

nc

R15

CLKCT

0.1UF C15

R3

R87

GND

VCLK

R85

10K

VOLT_CONTROL

162

U6

VOLT_CONTROL

CVHD_956 Crystek Crystal

OUTPUT

4

OPTIO NAL ENCODE CIRCUITS

00

R90

XTALINPUT

DNP

GND

50

GND

XTALINPUT

0

GND

J4

GND DRVDD AVDD

AVDD

AVDD_CLK

R17

0 DNP

CML

CLK

50

R1

CLK

2 1

GND

0.1UF C75

3

00

R89

T2

ADT1-1WT

00

R8

GND

C20

DNP

R14

GND

J3

GND

Input

ANALOG

GND

J2

CR2 TO MAKE LAYOUT AND PARASI T I C L O ADING SYMMETRI CAL

ENCODE

Figure 45. AD9601 Evaluation Board Schematic Page 1

Rev. 0 | Page 25 of 32

AD9601

0

0.1UF

C71

0.1UF

C70

0.1UF

C650.1UF

0.1UF

C64

0.1UF

C63

0.1UF

C62

0.1UF

C27

C28

0.1UF

C29

0.1UF

C30

0.1UF

C31

0.1UF

C32

0.1UF

C33

+

C8

10UF

AVDD

GND

POWER OPTIONS

100PF

C73

0.1UF

C72

0.1UF

C69

C68

0.1UF

C67

0.1UF

C66

0.1UF

C13

0.1UF

C59

0.1UF

C60

+

C54

10UF

VCLK

0.1UF

C24

0.1UF

C25

0.1UF

C26

+

C9

10UF

DRVDD

GND

P8

GND

U8

3

21

4

EGND

123

PJ-102A

0.1UF

C56

0.1UF

C57

0.1UF

C58

+

C14

10UF

VAMP

VSPIEXT

GND

VSPI

VIN

R2

T1

U7

C11

10UF

+

GND

0.1UF

C34

+

C12

10UF

0.1UF

C39

C35

0.1UF

C36

0.1UF

499

EGND

H4

MTHOLE6

H3

MTHOLE6

H2

MTHOLE6H1MTHOLE6

GND

VSPIEXTX

DRVDDX1

AVDDX

VAMPX

C3

1UF

GND

C1

1UF

GND

4

C7

1UF

GND

4

C5 1UF

GND

EGND

P6

VSPIEXTX

OUT

4

OUT

4

1.8V 3.3V

OUT

1.8V

OUT

+5V

1.8V

3.3V

DRVDD

VSPIEXT

L14

L15

FERRITE

GND

VSPIEXT1

DRVDD1

GND

1

OUT1

2

VSPIEXTX

IN

3

C4

U11

1UF

ADP3338

GND

1

OUT1

2

IN

3

C2

U12

1UF

ADP3338

GND

1

AVDDX

OUT1

2

IN

3

C10

U9

1UF

ADP3338

GND

1

VAMPX

OUT1

2

IN

3

C6

U10

1UF

ADP3338

GND

FERRITE

AVDD1

VIN

DRVDDX1

VIN

+5.0V

1.8V

AVDD

VAMP

L12

L13

FERRITE

GND

VAMP1

21345678

L6

FERRITE

L2

FERRITE

0

R88

DRVDDX

L4

VIN

FERRITE

L7

FERRITE

7100-046

VCLK

VSPIEXT1

L3

VSPI

FERRITE

L5

DRVDD1

FERRITE

AVDD1

VAMP1

Figure 46. AD9601 Evaluation Board Schematic Page 2

Rev. 0 | Page 26 of 32

AD9601

GND

00

R65

R63

00

R66

AMPOUT-

AMPOUT+

DNP

C76

DNP L11

C44

DNP

GND

10K

R42

GND

10K

R43

VAMP

GND

CML

C46.1UF

VAMP

00

R91

E13

E14

E12

C37.1UF

VCC

13

VCMENB

15

16 14

VIP

GND

00

R46

00

R41

12

10

11

GND

VOP

VON

Z1

RGN

RGP

RDP

2

L10 DNP

C45 DNP

AD9515 Logic Setup

GND

9

GND

8

VCC

AD8352

GND

67

5

VIN

RDN 413

R64

S1

S0

VCLK

VAMP

GND

00

00 R67

00 R68

S2

VCLK

S3

VCLK

R71

R69

00

R72

R70

S4

VCLK

CLK

C53

0.1UF

S5

VCLK

CLK

C50

0.1UF

R59

100

240

R75

R73

00

R76

R74

S6

S7

VCLK

E17

R60

C51

0.1UF

GND

R61

100

R79

R77

00

R80

R78

S8

VCLK

E16

C52

R58

S9

VCLK

0.1UF

07100-047

GND

00

R83

R81

00

R84

R82

S10

VCLK

00

R44

C43

R37

R94

DNP

P13

TOUT2

00

TINB1

DNP C40

R36 00

SMBMST

DNP

R40

DNP

R33

49.9

GND

6

T4

1234

5

ADT1-1WT

nc

GND

R34

PRI SEC

DNP

P12

5

R45

C47

.1UF

25

GND

Operat ional Amplifier

GND

R35

5

R39

C42

.1UF

R38

25

TOUTB2

TINB2

DNP C41

R47 00

SMBMST

TINB1

TOUT2

5

T7

1

GND

2

34

PRI SEC

TOUTB2

ETC1-1-13

TINB2

VCLK

AD9515(Opt_Clk Circuit)

GND

33

R62

31

4.12K

32

R54

10K

R52

00

R53

00

GND GN D

DNP R49

U1

R51

SMBMST

22

23

OUT0

OUT0B

GND_PAD

GND

RSET

CLK

CLKB

235

DNP C49

P15

19

SYNCB

R57

18

S10

OUT1

25

S0

OUT1B

S9

16

S1

S8

15

S2

S7

14

S3

S6

13

S4

S5

12

S5

S4

11

S6

S3

10

S7

AD9515

S2

9

S8

S1

8

S9

S0

7

S10

VREF

6

E15

DNC; 27, 28

VCLK; 1, 4, 17, 20, 21, 24 , 26, 29, 30

00

R55

00

R56

00

DNP

R50

0.1UF C48

50

R48

SMBMST

P14

GND

GND GND

Figure 47. AD9601 Evaluation Board Schematic Page 3

Rev. 0 | Page 27 of 32

AD9601

T

1K

SPI CIRCUITRY

R24

VSPIEXT

SDO_CHA

CSB1_CHA

SDI_CHA

SCLK_CHA

VSPI

1K

R25

VSPI

4

5

Y2

Y1

VCCGND

1K

U5

R27

NC7WZ07

A1

3

2

16

GND

10K

R26

SDIO_ODM

U3

NC7WZ16

A2

10K

R18

GND

CSB_DU

SCLK_DTP

VSPI

4

5

Y2

Y1

VCCGND

A2

A1

3

2

16

GND

07100-048

10K

R19

VSPIEXT

Figure 48. AD9601 Evaluation Board Schematic Page 4

Table 13. Bill of Materials

Reference Designator

Qty

Package Description Vendor Part Number

1 PCB PCB, AD9230 customer evaluation board, Rev. G Moog AD9230revG 7

C1, C3, C4, C5,

603 Capacitor, 1 F, 0603, X5R, ceramic, 6.3 V, 10% Panasonic ECJ-1VB0J105K

C6, C7, C10

6

C8, C9, C11,

6032-28 Capacitor, 10 F, tantalum, 16 V, 10% Kemet T491C106K016AS

C12, C14, C55 1 C17 402 Capacitor, 2.0 pF, 50 V, ceramic, 0402, SMD Murata GRM1555C1H2R0GZ01D 7

C27, C32, C33,

402 Capacitor, 0.33 F, ceramic, X5R, 10 V, 10% Murata GRM155R61A334KE15D C62, C63, C64, C71

6

C28, C29, C30,

402 Capacitor, 120 pF, ceramic, C0G, 25 V, 5% Murata GRM1555C1H121JA01J C31, C65, C70

10

C21, C22, C23,

402 Capacitor, 0.1 F, ceramic, X5R, 10 V, 10% Murata GRM155R71C104KA88D C24, C25, C26, C34, C35, C36, C39

1 CR4 603 LED green, SMT, 0603, SS-TYPE Panasonic LNJ314G8TRA 1 CR2 Mini 3P Diode, 30 V, 20 mA Agilent HSMS2812 1 F1 1210 Fuse, 6.0 V, 2.2 A trip current resettable fuse Tyco/Raychem NANOSMDC110F-2 15

E1, E2, E3, E4,

Connector, header, 0.1" Samtec TSW-150-08-G-S E5, E7, E8, E9, E10, E12, E13, E14, E31, E32, E33

2 J2, J3

10

L2, L3, L4, L5,

SMA end

launch

Connector, SMA PCB coax end launch, Johnson 142

1206 Ferrite bead, BLM, 3 A, 50 Ω @ 100 MHz Murata BLM31PG500SN1L

Johnson 142-0701-851

L7, L12, L13, L14, L15, R88

1 P8 Power jack, male, 2.1 mm power jack dc CUI Inc CP-102A-ND 1 R1 201 Resistor, 100 Ω, 0201, 1/20 W, 1% NIC Components NRC02F1000TRF 1 R2 603 Resistor, 499 Ω, 0603, 1/10 W, 1% NIC Components NRC06F4990TRF

Rev. 0 | Page 28 of 32

AD9601

Reference

Qty

2 R5, R6 402 Resistor, 36 Ω, 0402, 1/16 W, 1% Panasonic ERJ-2GEJ360X 2 R7, R16 402 Resistor, 15 Ω, 0402, 1/16 W, 5% Panasonic ERJ-2RKF15R0X 6

4

7

4

3 L1, L8, L9 603 Resistor, 0 Ω, 0603, 1/10 W, 5% NIC Components NRC06ZOTRF 1 P9, P10 805 Resistor, 0 Ω, 0805, 1/8 W, 1% NIC Components NRC10ZOTRF 1 SW3

1 T1 2020 Ferrite bead, 5 A, 50 V, 190 Ω @ 100 MHz Murata DLW5BSN191SQ2L 2 T2,T3 CD542 Transformer, 0.5 W, 30 mA Mini-Circuits ADT1-1WT+ 1 U3 6-SC70 IC, buffer, inverter, UHS dual SC70-6 Fairchild NC7WZ16P6X 1 U5 6-SC70 IC, buffer, inverter, UHS dual OD out SC70-6 Fairchild NC7WZ07P6X 1 U7 DO-214AA Diode, 50 V, 2 A Micro Commercial S2A-TPMSTR-ND 1 U8 DO-214AB Diode, 30 V, 3 A (SMC) Micro Commercial SK33-TPMSCT-ND 1 U11 SOT-223 Voltage regulator, 3.3 V, 1.5 A Analog Devices ADP3339AKCZ-3.3 2 U9, U12 SOT-223 Voltage regulator, 1.8 V, 1.5 A Analog Devices ADP3339AKCZ-1.8 1 U4 LFCSP56

2 P7, P11 HM-Zd PCB

Do not install the following:

0 C2, C54 TAJD Capacitor, tantalum, SMT 6032, 10 F, 16 V, 10% Kemet T491C106K016AS 0

0 CR1 Led_ss LED green, USS type 0603 Panasonic LNJ314G8TRA 0 CR3 Diode Schottky diode Agilent HSMS2812 0 805 Tyco/Raychem NANOSMDC110F-2 0

0 J1

0 J4 SMA

0 L6 1206 Inductor, 10 nH Murata BLM31P500S 0

Designator Package Description Vendor Part Number

R10, R11, R13, R24, R25, R27

R12, R18, R19, R26,

R15, C16, C18, C19, C20, R89, R90

RN1, RN2, RN3, RN4

C15, C37, C38, C40, C41, C61, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, C39, C56, C57, C58, C59, C74, C75, C60, C66, C67, C68, C69, C72

E6, E15, E16, E17, E18, E19, E20

P12, P13, P14, P15

402 Resistor, 1 kΩ, 0402, 1/16 W, 1% NIC Components NRC04F1001TRF

402 Resistor, 10 kΩ, 0402, 1/16 W, 5% NIC Components NRC04J103TRF

402 Resistor, 0 Ω, 0402, 1/16 W, 5% NIC Components NRC04ZOTRF

0402x8

EVQQ2F03W

402 Capacitor, 0.1 F, ceramic, 10% Murata GRM155R71C104KA88D

Connector, header, 0.1" Samtec TSW-150-08-G-S

10-pin header

SMA Amphenol RF ARFX1231-ND

Resistor array, SMT 0402; 0 Ω, ¼ W, 5%, RESNEXB-2HV

Switch, light touch SMD Panasonic P12937SCT-ND

AD9230 12-bit, 170 MSPS/210 MSPS/250 MSPS,

1.8 V ADC, LFCSP-56 Connector, 2-Pr, 10-column, high speed, HM-Zd,

PCB-mounted

TSW-110-08-G-D Samtec TSW-110-08-G-D

Connector, PCB coax SMA end launch, Johnson 142

Panasonic EXB2HV050JV

Analog Devices AD9230BCPZ-xxx

Tyco 6469169-1

Johnson 142-0701-851

Rev. 0 | Page 29 of 32

AD9601

Reference

Qty

Designator Package Description Vendor Part Number

0

R3, R14, R33, R34, R35, R48, R49

0

R42, R43, R54, R85, R86

0

R28, R29, R30, R31, R32

0 R37, R38 402 Resistor, 25 Ω NIC Components NRC04F24R9TRF 0 R39, R45 402 Resistor, 5 Ω NIC Components NRC04J5R1TRF 0 R58, R59 402 Resistor, 100 Ω NIC Components NRC04F1000TRF 0 R60, R61 402 Resistor, 240 Ω NIC Components NRC04J241TRF 0

R8, R9, R17, R36, R40, R41, R44, R46, R47, R87, R50, R51, R52, R53, R55, R56, R57, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84

0 P1, P2, P16, P17 805 Resistor, 0 Ω NIC Components NRC10ZOTRF 0 SW1

0 T4

0 T5, T6 sm-22 Balun M/A-Com MABA007159-0000 0 U2 SOIC-8 PIC12F629 Microchip Tech PIC12F629-I/SN 0 U6 Crystal Cvhd_956 crystal CVHD_956 0 U10 SOT-223 Regulator ADP3339AKCZ-5.0 0 Z1 16CSP4X4 AD8352 0 U1 16CSP8X8 AD9515 0 P6 8-pin power connector post Wieland Z5.530.0825.0 0 P6 8-pin power connector top Wieland 25.602.2853.0

402 Resistor, 49.9 Ω Susumu RR0510R-49R9-D

402 Resistor, 10 kΩ NIC Components NRC04J103TRF

402 Resistor, 5 kΩ NIC Components NRC04F4991TRF

402 Resistor, 0 Ω NIC Components NRC04ZOTRF

EVQ-

Q2F03W

Switch, light touch SMD Panasonic P12937SCT-ND

Transformer, RF, 0.4 MHz to 800 MHz, SMD case style CD542

Mini-Circuits ADT1-1WT+

Rev. 0 | Page 30 of 32

AD9601

0

OUTLINE DIMENSIONS

0.30

0.23

0.18

PIN 1

56

INDICATOR

1

BSC SQ

PIN 1 INDICATO R

8.00

0.60 MAX

43

42

0.60 MAX

4.45

4.30 SQ

4.15

14

0.30 MIN

112805-0

1.00 .85 .80

SEATING

PLANE

12° MAX

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VLL D-2

7.75

BSC SQ

0.20 REF

0.50

0.40

0.30

0.05 MAX

0.02 NOM COPLANARITY

0.08

29

28

EXPOSED

PAD

(BOTTOM VIEW)

6.50 REF

15

Figure 49. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm Body, Very Thin Quad

(CP-56-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9601BCPZ-200 AD9601BCPZ-250 AD9601-250EBZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2

−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-2 CMOS Evaluation Board with AD9601BCPZ-250

Rev. 0 | Page 31 of 32

AD9601

NOTES

Rev. 0 | Page 32 of 32

Datasheet AD9601 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ANALOG INPUT AND VOLTAGE REFERENCE

Differential Input Configurations

CLOCK INPUT CONSIDERATIONS

Clock Duty Cycle Considerations

Clock Jitter Considerations

POWER DISSIPATION AND POWER-DOWN MODE

DIGITAL OUTPUTS

Digital Outputs and Timing

Out-of-Range

TIMING—SINGLE PORT MODE

TIMING—INTERLEAVED MODE

fS/2 Spurious

LAYOUT CONSIDERATIONS

POWER AND GROUND RECOMMENDATIONS

Exposed Paddle Thermal Heat Slug Recommendations

RBIAS

AD9601 CONFIGURATION USING THE SPI

HARDWARE INTERFACE

CONFIGURATION WITHOUT THE SPI

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

DEFAULT VALUES

LOGIC LEVELS

EVALUATION BOARD

OUTLINE DIMENSIONS

ORDERING GUIDE