Datasheet AD9572 Datasheet (ANALOG DEVICES)

Fiber Channel/Ethernet Clock Generator IC,

FEATURES

Fully integrated dual VCO/PLL cores

0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz

0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz Input crystal or clock frequency of 25 MHz

Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,

100 MHz, and 125 MHz Choice of LVPECL or LVDS output format Integrated loop filters Copy of reference clock output Rates configured via strapping pins

0.71 W power dissipation (LVDS operation)

1.07 W power dissipation (LVPECL operation)

3.3 V operation Space saving, 6 mm × 6 mm, 40-lead LFCSP

APPLICATIONS

Fiber channel line cards, switches, and routers Gigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation

GENERAL DESCRIPTION

The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed

7 Clock Outputs

AD9572

FUNCTIONAL BLOCK DIAGRAM

REFSEL

XTAL

OSC

REFCLK

PFD/CP

AD9572

LDO

VCO

ORDER

LPF THIRD

LDO

VCO

LPF

3RD ORDER

Figure 1.

feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to

156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for the required output rates.

A second PLL also operates as an integer-N synthesizer and drives two LVPECL or LVDS output buffers for 106.25 MHz operation. No external loop filter components are required, thus conserving valuable design time and board space.

The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP) and can be operated from a single

3.3 V supply. The temperature range is −40°C to +85°C.

DIVIDE RS

DIVIDERS

FREQSEL

CMOS

LVPECL

OR LVDS

LVPECL

OR LVDS

LVPECL

OR LVDS

CMOS

1 × 25MHz

2 × 106.25MHz

1 × 156.25MHz

2 × 100MHz OR 125MHz

1 × 33.33MHz

FORCE_LO W

7498-001

16-PORT FIBRE CHANNEL ASIC

QUAD SFP

PHY

QUAD SFP

PHY

10G SFP+

QUAD SFP

PHY

ISLAND

QUAD SFP

Figure 2. Typical Application

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

CPU

PHY

1 × 156.25MHz 2 × 106.25MHz 1 × 100MHz/125MHz 1 × 25MHz 1 × 33.33MHz

AD9572

7498-002

AD9572

REVISION HISTORY

/11—Rev. A to Rev. B

C

hanges to Output Rise Time, t

Time, t

11/10—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Table 2............................................................................ 4

Changes to Table 3 and Table 4....................................................... 5

Changes to Table 7............................................................................ 6

Added Figure 7 and Figure 8......................................................... 11

Added Figure 14, Figure 15, and Figure 16................................. 13

Deleted Original Figure 16 and Figure 19................................... 16

Parameter in Table 7....................................................... 6

FC2

Parameter and Output Fall

RC2

Renumbered Figures Sequentially............................... Throughout

Changes to CMOS Clock Distribution Section.......................... 17

Changes to LVPECL Clock Distribution Section, Added

Figure 23 and Figure 24................................................................. 18

Changes to LVDS Clock Distribution Section, Added

Figure 26 .......................................................................................... 18

Changes to Reference Input Section ............................................ 18

Changes to Power and Grounding Considerations and Power

Supply Rejection Section ............................................................... 19

7/09—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD9572

SPECIFICATIONS

PLL CHARACTERISTICS

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE NOISE CHARACTERISTICS

PLL Noise (106.25 MHz LVDS Output)

At 1 kHz −123 dBc/Hz 33.33 MHz output disabled At 10 kHz −127 dBc/Hz 33.33 MHz output disabled At 100 kHz −129 dBc/Hz 33.33 MHz output disabled At 1 MHz −150 dBc/Hz 33.33 MHz output disabled At 10 MHz −152 dBc/Hz 33.33 MHz output disabled At 30 MHz −153 dBc/Hz 33.33 MHz output disabled

PLL Noise (156.25 MHz LVDS Output)

At 1 kHz −118 dBc/Hz 33.33 MHz output disabled At 10 kHz −125 dBc/Hz 33.33 MHz output disabled At 100 kHz −126 dBc/Hz 33.33 MHz output disabled At 1 MHz −145 dBc/Hz 33.33 MHz output disabled At 10 MHz −151 dBc/Hz 33.33 MHz output disabled At 30 MHz −151 dBc/Hz 33.33 MHz output disabled

PLL Noise (125 MHz LVDS Output)

At 1 kHz −119 dBc/Hz 33.33 MHz output disabled At 10 kHz −127 dBc/Hz 33.33 MHz output disabled At 100 kHz −128 dBc/Hz 33.33 MHz output disabled At 1 MHz −147 dBc/Hz 33.33 MHz output disabled At 10 MHz −151 dBc/Hz 33.33 MHz output disabled At 30 MHz −152 dBc/Hz 33.33 MHz output disabled

PLL Noise (100 MHz LVDS Output)

At 1 kHz −121 dBc/Hz 33.33 MHz output disabled At 10 kHz −128 dBc/Hz 33.33 MHz output disabled At 100 kHz −130 dBc/Hz 33.33 MHz output disabled At 1 MHz −147 dBc/Hz 33.33 MHz output disabled At 10 MHz −150 dBc/Hz 33.33 MHz output disabled At 30 MHz −150 dBc/Hz 33.33 MHz output disabled

PLL Noise (106.25 MHz LVPECL Output)

At 1 kHz −121 dBc/Hz 33.33 MHz output disabled At 10 kHz −128 dBc/Hz 33.33 MHz output disabled At 100 kHz −129 dBc/Hz 33.33 MHz output disabled At 1 MHz −151 dBc/Hz 33.33 MHz output disabled At 10 MHz −154 dBc/Hz 33.33 MHz output disabled At 30 MHz −155 dBc/Hz 33.33 MHz output disabled

PLL Noise (156.25 MHz LVPECL Output)

At 1 kHz −119 dBc/Hz 33.33 MHz output disabled At 10 kHz −125 dBc/Hz 33.33 MHz output disabled At 100 kHz −126 dBc/Hz 33.33 MHz output disabled At 1 MHz −147 dBc/Hz 33.33 MHz output disabled At 10 MHz −152 dBc/Hz 33.33 MHz output disabled At 30 MHz −153 dBc/Hz 33.33 MHz output disabled

Rev. B | Page 3 of 20

AD9572

Parameter Min Typ Max Unit Test Conditions/Comments

PLL Noise (125 MHz LVPECL Output)

At 1 kHz −122 dBc/Hz 33.33 MHz output disabled At 10 kHz −127 dBc/Hz 33.33 MHz output disabled At 100 kHz −128 dBc/Hz 33.33 MHz output disabled At 1 MHz −148 dBc/Hz 33.33 MHz output disabled At 10 MHz −152 dBc/Hz 33.33 MHz output disabled At 30 MHz −153 dBc/Hz 33.33 MHz output disabled

PLL Noise (100 MHz LVPECL Output)

At 1 kHz −122 dBc/Hz 33.33 MHz output disabled At 10 kHz −128 dBc/Hz 33.33 MHz output disabled At 100 kHz −130 dBc/Hz 33.33 MHz output disabled At 1 MHz −148 dBc/Hz 33.33 MHz output disabled At 10 MHz −150 dBc/Hz 33.33 MHz output disabled At 30 MHz −151 dBc/Hz 33.33 MHz output disabled

PLL Noise (33.33 MHz CMOS Output)

At 1 kHz −130 dBc/Hz At 10 kHz −138 dBc/Hz At 100 kHz −139 dBc/Hz At 1 MHz −152 dBc/Hz At 5 MHz −152 dBc/Hz

Phase Noise (25 MHz CMOS Output)

At 1 kHz −133 dBc/Hz At 10 kHz −142 dBc/Hz At 100 kHz −148 dBc/Hz At 1 MHz −148 dBc/Hz

At 5 MHz −148 dBc/Hz Spurious Content1 −70 dBc Dominant amplitude, all outputs active PLL Figure of Merit −217.5 dBc/Hz

1

When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content might be presented on Pin 21 and Pin 22 only.

LVDS CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 2.

Jitter Integration Bandwidth (Typ) 100 MHz 106.25 MHz

12 kHz to 20 MHz 0.51 0.44 0.42/0.88 0.42

1.875 MHz to

0.19

20 MHz

637 kHz to 10 MHz 0.22

200 kHz to 10 MHz 0.32 0.25/0.78

12 kHz to 35 MHz 0.50 (off only)

1

The typical 125 MHz rms jitter data is collected from the differential pair, Pin 21 and Pin 22, unless otherwise noted.

125 MHz 33M = Off/On

1

156.25 MHz Unit Test Conditions/Comments

Rev. B | Page 4 of 20

ps rms

LVDS output frequency combinations are 1 × 156.25 MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz

LVDS output frequency combinations are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×

106.25 MHz

AD9572

LVPECL CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 3.

125 MHz Jitter Integration Bandwidth (Typ)

12 kHz to 20 MHz (Typ) 0.61 0.45 0.44/2.2 0.46 ps rms

12 kHz to 20 MHz (Max) 0.87 0.81

1.875 MHz to 20 MHz (Typ) 0.28 ps rms

637 kHz to 10 MHz (Typ) 0.23 ps rms

200 kHz to 10 MHz (Typ) 0.38 0.24/2.2 ps rms

12 kHz to 35 MHz (Typ)

12 kHz to 35 MHz (Max)

CMOS CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

100 MHz

106.25 MHz

33M =

Off/On

0.56 (off

only)

0.52 (off

only)

0.66 (off

only)

156.25 MHz Unit Test Conditions/Comments

LVPECL output frequency combinations are 1 × 156.25 MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz

0.56 ps rms

ps rms

LVPECL output frequency combinations are 1 × 156.25 MHz, 1 × 100 MHz, 1 × 125 MHz, 2 × 106.25 MHz

LVPECL output frequency combinations are 156.25 MHz unterminated, 2 × 125 MHz, 2 × 106.25 MHz

Table 4.

Jitter Integration Bandwidth 25 MHz 33.3 MHz Unit Test Conditions/Comments

12 kHz to 5 MHz (Typ) 0.78 0.41 ps rms 12 kHz to 5 MHz (Max) 1.1 N/A ps rms 200 kHz to 5 MHz (Typ) 0.76 0.52 ps rms 200 kHz to 5 MHz (Max) 1.0 N/A ps rms

REFERENCE INPUT

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

CLOCK INPUT (REFCLK)

Input Frequency 25 MHz Input High Voltage 2.0 V Input Low Voltage 0.8 V Input Current −1.0 +1.0 μA Input Capacitance 2 pF

and TA (−40°C to +85°C) variation.

S

Rev. B | Page 5 of 20

AD9572

CLOCK OUTPUTS

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS

Output Frequency 156.25 MHz Output High Voltage (VOH) VS − 1.24 VS − 1.05 VS − 0.83 V Output Low Voltage (VOL) VS − 2.07 VS − 1.87 VS − 1.62 V Output Differential Voltage (VOD) 700 825 950 mV Duty Cycle 45 55 %

LVDS CLOCK OUTPUTS

Output Frequency 156.25 MHz Differential Output Voltage (VOD) 250 350 475 mV Delta VOD 25 mV Output Offset Voltage (VOS) 1.125 1.25 1.375 V Delta VOS 25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND Duty Cycle 45 55 %

CMOS CLOCK OUTPUTS

Output Frequency 33.33 MHz Output High Voltage (VOH) VS − 0.1 V Sourcing 1.0 mA current Output Low Voltage (VOL) 0.1 V Sinking 1.0 mA current Duty Cycle 42 58 %

and TA (−40°C to +85°C) variation.

S

TIMING CHARACTERISTICS

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL

Output Rise Time, tRP 480 625 810 ps 20% to 80%, measured differentially Output Fall Time, tFP 480 625 810 ps 80% to 20%, measured differentially

LVDS

Output Rise Time, tRL 160 350 540 ps 20% to 80%, measured differentially Output Fall Time, tFL 160 350 540 ps 80% to 20%, measured differentially

CMOS

Output Rise Time, tRC 0.25 0.50 2.5 ns

Output Fall Time, tFC 0.25 0.70 2.5 ns

Output Rise Time, t

Output Fall Time, t

and TA (−40°C to +85°C) variation.

S

1.3 2.1 2.6 ns

RC2

1.4 2.3 3.0 ns

FC2

Termination = 200 Ω to 0 V; C

= 0 pF; CAC = 100

LOAD

nF; oscilloscope set to 50 Ω termination

Termination = 100 Ω differential; C

= 0 pF; CAC =

LOAD

100 nF; oscilloscope set to 50 Ω termination

20% to 80%; termination = 50 Ω to 0 V; C

= 100 nF

C

AC

80% to 20%; termination = 50 Ω to 0 V; C

= 100 nF

C

AC

LOAD

20% to 80%; active probe measurement, C 1 pF, R

probe

=20 kΩ, C

LOAD

= 3.9 pF

80% to 20%; active probe measurement, C 1 pF, R

probe

=20 kΩ, C

LOAD

= 3.9 pF

= 5 pF;

=

probe

=

probe

Rev. B | Page 6 of 20

AD9572

CONTROL PINS

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS

REFSEL Pin REFSEL has a 30 kΩ pull-up resistor.

FREQSEL Pin

FORCE_LOW Pin FORCE_LOW has a 16 kΩ pull-down resistor.

and TA (−40°C to +85°C) variation.

S

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 1.0 μA Logic 0 Current 155 μA

Logic 1 Voltage

2/3(V

S

) +

V

0.2

Logic 0 Voltage

1/3(V

V

) −

S

0.2 Logic 1 Current 45 μA Logic 0 Current 30 μA

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 240 μA Logic 0 Current 2.0 μA

FREQSEL has a 150 kΩ pull-up resistor and a 100 kΩ pull-down resistor.

POWER

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

and TA (−40°C to +85°C) variation.

S

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

Power Supply 3.0 3.3 3.6 V LVDS Power Dissipation 715 870 mW LVPECL Power Dissipation 1075 1305 mW

CRYSTAL OSCILLATOR

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

CRYSTAL SPECIFICATION Fundamental mode

Frequency 25 MHz ESR 50 Ω Load Capacitance 14 pF Phase Noise −135 dBc/Hz At 1 kHz offset Stability −30 +30 ppm

and TA (−40°C to +85°C) variation.

S

Rev. B | Page 7 of 20

AD9572

TIMING DIAGRAMS

DIFFERENTIAL

80%

0%

20%

DIFFERENTIAL

80%

0%

20%

V

OD

LVPECL

t

RP

t

FP

Figure 3. LVPECL Timing, Differential

V

OD

LVDS

t

RL

t

FL

Figure 4. LVDS Timing, Differential

SINGLE-E NDED

80%

CMOS

5pF LO AD

20%

t

7498-022

RC

t

FC

7498-006

Figure 5. CMOS Timing, Single-Ended, 5 pF Load

7498-023

Rev. B | Page 8 of 20

AD9572

ABSOLUTE MAXIMUM RATINGS

Table 11.

Parameter Rating

VS to GND −0.3 V to +3.6 V REFCLK to GND −0.3 V to VS + 0.3 V BYPASSx to GND −0.3 V to VS + 0.3 V XO to GND −0.3 V to VS + 0.3 V FREQSEL, FORCE_LOW, and

REFSEL to GND 25M, 33M, 100M/125M, 106M, and

156M to GND Junction Temperature1 150°C Storage Temperature Range −65°C to +150°C

1

See Table 12 for θJA.

−0.3 V to VS + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7.

Table 12. Thermal Resistance

Package Type θJA Unit

40-Lead LFCSP 27.5 °C/W

ESD CAUTION

Rev. B | Page 9 of 20

AD9572

2

4

L

W

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

*

VS

BYPASS1

FORCE_LO

38

39

40

36

37

106M

VS

GND

VS

106M

32

31

33

34

35

1GND 2VS 3NC 425M 5VS 6XO 7XO 8REFCLK 9REFSEL

10GND

NOTES

1. * = SHORT TO PIN 36. . ** = SHORT TO PI N 14.

3. NC = NO CONNECT . . NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICA

CONNECTION AS WELL AS A T HERMAL ENHANCEMENT . FOR THE DEVICE TO FUNCTION PROPERLY, T HE PADDLE MUST BE ATTACHED TO GROUND (GND).

PIN 1 INDICAT OR

AD9572

TOP VIEW

(Not to Scale)

11

12

13

**

VS

30 106M 29 106M 28 VS 27 FREQSEL 26 VS 25 VS 24 VS 23 33M 22 100M/125M 21 100M/125M

15

17

16

18

19

14

VS

BYPASS2

20

VS

156M

/125M

100M/125M

100M

Figure 6. Pin Configuration

Table 13. Pin Function Descriptions1

Pin No. Mnemonic Description

1, 10, 34 GND Ground. Includes external paddle (EPAD). 2 VS Power Supply Connection for the 25M CMOS Buffer. 3 NC 4 25M 5 VS 6, 7 XO 8 REFCLK 9 REFSEL 11 VS 12, 13 N/A 14, 36 BYPASS2, BYPASS1 15 VS 16 VS 17 156M 18

156M

19, 21 100M/125M 20, 22

100M

/125M 23 33M 24 VS 25 VS 26 VS 27 FREQSEL 28 VS 29, 31

106M

No Connect. This pin should be left floating. CMOS 25 MHz Output. Power Supply Connection for the Crystal Oscillator. External 25 MHz Crystal. 25 MHz Reference Clock Input. Tie low when not in use. Logic Input. Used to select the reference source. Power Supply Connection for the GbE PLL. Short to Pin 14. These pins are for bypassing each LDO to ground with a 220 nF capacitor. Power Supply Connection for the GbE VCO. Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers. LVPECL/LVDS Output at 156.25 MHz. Complementary LVPECL/LVDS Output at 156.25 MHz.

LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping. Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz.

CMOS 33.33 MHz Output. Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers. Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers. Power Supply Connection for the GbE PLL Feedback Divider. Logic Input. Used to configure output drivers. Power Supply Connection for the FC PLL Feedback Divider. LVPECL/LVDS Output at 106.25 MHz.

30, 32 106M Complementary LVPECL/LVDS Output at 106.25 MHz.

07498-007

Rev. B | Page 10 of 20

AD9572

T

Pin No. Mnemonic Description

33 VS Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers. 35 VS Power Supply Connection for the FC VCO. 37 FORCE_LOW 38 N/A 39 VS 40 VS Power Supply Connection for Miscellaneous Logic.

1

The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to

ground (GND).

= 100nF|| 10nF

C

D

Forces the 33.33 MHz output into a low state. Short to Pin 36. Power Supply Connection for the FC PLL.

V

S

C

D

0.22µF

V

S

C

D

V

S

C

D

RT= 100Ω

50Ω

GND

156M

50Ω

RT = 100Ω

VS

156M

50Ω

106M

100M/125M

50Ω

RT = 100Ω

106M

FREQSEL

100M/125M

50Ω

33M

VS

50Ω

RT = 100Ω

V

S

C

D

V

S

C

D

V

S

C

D

V

S

C

D

50Ω

RT = 100Ω

O CMOS

INPUT

C

= 22pF

X

= 22pF

X

BYPASS1

AD9572

VS

C

D

V

S

VS

D

V

S

VS

GND

V

S

C

50Ω

V

S

C

25MHz

VS

D

NC

25M

VS

D

XO

REFCLK

REFSEL

GND

VS

C

D

V

S

TEST

0.22µF

FORCE_LOW

BYPASS2

C

Figure 7. Typical Application Schematic, LVDS Format Outputs, 1 × 25 MHz, 1 × 156.25 MHz, 2 × 125 MHz, and 2 × 106.25 MHz

TO CMOS INPUT

07498-024

Rev. B | Page 11 of 20

AD9572

T

VSV

= 100nF|| 10nF

C

D

V

S

C

D

0.22µF

V

S

C

D

V

S

C

D

50Ω

S

127Ω 127Ω

50Ω

O CMOS

INPUT

C

= 22pF

X

= 22pF

X

VS

GND

V

S

C

VS

D

TEST

FORCE_LO W

VS

BYPASS1

NC

50Ω

V

S

C

25M

VS

D

XO

AD9572

25MHz

XO

REFCLK

REFSEL

GND

VS

GND

106M

VS

50Ω

C

V

S

D

FREQSEL

VS

33M

100M/125M

C

50Ω

V

S

D

V

S

D

V

S

D

50Ω

83Ω 83Ω

TO CMOS INPUT

VS VS

127Ω 127Ω

83Ω 83Ω

VS VS

127Ω 127Ω

83Ω 83Ω

VS VS

VS

TEST

C

D

VS

BYPASS2

C

VS

C

D

0.22µF

V

S

V

S

156M

50Ω

156M

50Ω

100M/125M

V

100M/125M

S

50Ω

127Ω 127Ω

83Ω

127Ω

V

S

07498-025

Figure 8. Typical Application Schematic, LPECL Format Outputs, 1 × 25 MHz, 1 × 156.25 MHz, 2 × 125 MHz, and 2 × 106.25 MHz

Rev. B | Page 12 of 20

AD9572

–

V

TYPICAL PERFORMANCE CHARACTERISTICS

Phase noise plots taken with 100 MHz and 125 MHz outputs enabled; 33.3 MHz output disabled.

100

–110

–120

–130

–140

PHASE NOISE (d Bc/Hz)

–150

–160

1k 10k 100k 1M 100M10M

FREQUENCY (Hz)

Figure 9. 106.25 MHz Phase Noise

100

–110

–120

–130

–140

PHASE NOISE (d Bc/Hz)

–150

–110

–120

–130

–140

PHASE NOISE (d Bc/Hz)

–150

–160

1k 10k 100k 1M 100M10M

07498-008

FREQUENCY (Hz)

07498-011

Figure 12. 156.25 MHz Phase Noise

100

–110

–120

–130

–140

PHASE NOISE (d Bc/Hz)

–150

–160

1k 10k 100k 1M 100M10M

FREQUENCY (Hz)

Figure 10. 125 MHz Phase Noise

100

–110

–120

–130

–140

PHASE NOISE (d Bc/Hz)

–150

–160

1k 10k 100k 1M 100M10M

FREQUENCY (Hz)

Figure 11. 25 MHz Phase Noise

07498-009

07498-010

–160

1k 10k 100k 1M 100M10M

FREQUENCY (Hz)

Figure 13. 100 MHz Phase Noise

500mV/DI

10ns/DIV

07498-026

Figure 14. 25 MHz CMOS Output, 3.9 pF Load Capacitance on Evaluation

Board, Active-Probe Measurement, R

probe

=20 kΩ, C

probe

=1 pF

07498-012

Rev. B | Page 13 of 20

AD9572

V

200mV/DI

2ns/DIV

07498-027

Figure 15. 156.25 MHz LVPECL Output, Differential Plot, 200 Ω Termination

to GND on Evaluation Board, AC-Coupled via 0.1 μF Capacitors to

Oscilloscope Set to 50 Ω Input Termination

100mV/DI

2ns/DIV

07498-028

Figure 16. 125 MHz LVDS Output, Differential Plot, AC-Coupled via 0.1 μF

Capacitors to Oscilloscope Set to 50 Ω Input Termination

Rev. B | Page 14 of 20

AD9572

TERMINOLOGY

Phase Jitter

An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from the ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as Gaussian (normal) in distribution.

This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given.

Phase Noise

When the total power contained within some interval of offset frequencies (for example, 12 kHz to 20 MHz) is integrated, it is called the integrated phase noise over that frequency offset interval, and it can be readily related to the time jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillator or clock source has been subtracted. This makes it possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

Rev. B | Page 15 of 20

AD9572

V

THEORY OF OPERATION

REFSEL

SVSGNDBYPASS1

REFCLK

XTAL

OSC

1

0

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

V

LDO

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

V

LDO

VCO

LDO

VCO

AD9572

Figure 17. Detailed Block Diagram

Figure 17 shows a block diagram of the AD9572. The chip combines dual PLL cores, which are configured to generate the specific clock frequencies required for networking applications without any user programming. This PLL is based on proven Analog Devices synthesizer technology, noted for its exceptional phase noise performance. The AD9572 is highly integrated and includes loop filters, regulators for supply noise immunity, all the necessary dividers with multiple output buffers in a choice of formats, and a crystal oscillator. A user need only supply a 25 MHz reference clock or an external crystal to implement an entire line card clocking solution that does not require any processor intervention. A copy of the 25 MHz reference source is also available.

DIVIDE

BY 17

DIVIDE

BY 5

DIVIDE

BY 25

DIVIDE

BY 4

DIVIDE

BY 5

DIVIDE

BY 4

DIVIDE

BY 4

DIVIDE

BY 4

DIVIDE

BY 5

DIVIDE

BY 3

156.25MHz

LVPECL/

125MHz/100MHz

0

1

LVPECL/

LEVEL

DECODE

125MHz/100MHz

0

1

LVPECL/

FORCE_LOW

106.25MHz

LVPECL/

LVDS

33.33MHz

CMOS

LVDS

CMOS

25M

106M

BYPASS2

156M

100M/125M

FREQSEL

100M/125M

33M

07498-013

OUTPUTS

Tabl e 1 4 provides a summary of the outputs available.

Table 14. Output Formats

Frequency Format Copies

25 MHz CMOS 1

106.25 MHz LVPECL/LVDS 2

156.25 MHz LVPECL/LVDS 100 MHz or 125 MHz LVPECL/LVDS

33.33 MHz CMOS 1

Note that the pins labeled 100M/125M can provide 100 MHz or 125 MHz by strapping the FREQSEL pin as shown in Tabl e 1 5 .

1 2

Rev. B | Page 16 of 20

AD9572

V

Table 15. FREQSEL (Pin 27) Definition

FREQSEL

Frequency Available from Pin 19 and Pin 20 (MHZ)

Frequency Available from Pin 21 and Pin 22 (MHZ)

0 125 125 1 100 100 NC 125 100

frequency difference between them. Figure 20 shows a simplified schematic.

3.3

CHARGE

HIGH

REFCLK

D1 Q 1

CLR1

UP

PUMP

The simplified equivalent circuits of the LVDS and LVPECL outputs are shown in Figure 18 and Figure 19.

3.5mA

OUT

OUTB

3.5mA

Figure 18. LVDS Output Simplified Equivalent Circuit

3.3

GND

Figure 19. LVPECL Output Simplified Equivalent Circuit

OUT

OUTB

07498-014

07498-015

The differential outputs are factory programmed to either LVPECL or LVDS format, and either option can be sampled on request.

CMOS drivers tend to generate more noise than differential outputs and, as a result, the proximity of the 33.33 MHz output to Pin 21 and Pin 22 does affect the jitter performance when FREQSEL = 0 (that is, when the differential output is generating 125 MHz). For this reason, the 33 MHz pin can be forced to a low state by asserting the FORCE_LOW signal on Pin 37 (see Tabl e 1 6 ). An internal pull-down enables the 33.33 MHz output if the pin is not connected.

Table 16. FORCE_LOW (Pin 37) Definition

FORCE_LOW 33.33 MHz Output (Pin 23)

0 or NC 33.33 MHz 1 0

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP

The PFD takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and

CP

CLR2

D2 Q 2

DOWN

GND

7498-016

HIGH

FEEDBACK

DIVIDER

Figure 20. PFD Simplified Schematic

POWER SUPPLY

The AD9572 requires a 3.3 V ± 10% power supply for VS. The tables in the Specifications section give the performance expected from the AD9572 with the power supply voltage within this range. The absolute maximum range of −0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VS pin.

Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 µF). The AD9572 should be bypassed with adequate capacitors (0.1 µF) at all power pins as close as possible to the part. The layout of the AD9572 evaluation board is a good example.

The exposed metal paddle on the AD9572 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The PCB acts as a heat sink for the AD9572; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB.

CMOS CLOCK DISTRIBUTION

The AD9572 provides two CMOS clock outputs (one 25 MHz and one 33.33 MHz) that are dedicated CMOS levels. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be followed.

Point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and signal integrity.

Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9572 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 21. The far-end

Rev. B | Page 17 of 20

AD9572

V

termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.

= 3.3

PULLUP

CMOS

10Ω

50Ω

100Ω

5pF

7498-018

Figure 21. CMOS Output with Far-End Termination

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs, which are open emitter, require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 19 shows the LVPECL output stage.

In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 22. The resistor network is designed to match the transmission line impedance (50 Ω) and establish a dc bias of (V LVPECL termination network with a reduced number of components is also possible as shown in Figure 23.

3.3V

LVPECL

VT = VCC – 2.0V V

Figure 22. LVPECL Far-End Termination

LVPECL

CC

SINGLE- ENDED (NOT COUPL ED)

= 3.3V

CC

– 2 V). An alternative dc-coupled

3.3

3.3V

50Ω

127Ω127Ω

83Ω83Ω

LVPECL

07498-029

50Ω

TERM

50Ω50Ω

LVPECL

07498-031

LVPECL

0.1µF

50Ω

0.1µF

50Ω

200Ω200Ω

Figure 24. LVPECL AC- Coupled Termination

LVDS CLOCK DISTRIBUTION

The AD9572 is also available with low voltage differential signaling (LVDS) output s . LVDS use s a c urrent mode output stage with a factory programmed current level. The normal value (default) for this current is 3.5 mA, which yields a 350 mV output swing across a 100 Ω resistor. The LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is shown in Figure 25.

50Ω

LVDS

100Ω

50Ω

LVDS

07498-032

Figure 25. LVDS Output Termination

See the AN-586 Application Note on the Analog Devices website at www.analog.com for more information about LVDS.

REFERENCE INPUT

By default, the crystal oscillator is enabled and used as the reference source, which requires the connection of an external 25 MHz crystal cut to resonate in fundamental mode. The total load capacitance presented to the oscillator should sum to 14 pF. In the example shown in Figure 26, parasitic trace capacitance of 1.5 pF, and an AD9572 input pin capacitance of 1.5 pF are assumed, with the series combination of the two 22 pF capacitances providing a further 11 pF. The REFSEL pin is pulled high internally by about 30 k to support default operation.

XTAL

OSC

REFSEL

TO PLLs

07498-033

50Ω

07498-030

Figure 23. LVPECL Y Termination

An ac- coupled LVPECL termination scheme is shown in Figure 24.

22pF

REFCLK

Figure 26. Reference Input section

When REFSEL is tied low, the crystal oscillator is powered down, and the REFCLK pin must provide a good quality 25 MHz reference clock instead. This single-ended input can be driven by either a dc-coupled LVCMOS level signal or an ac-coupled

Rev. B | Page 18 of 20

AD9572

sine wave or square wave, provided that an external divider is used to bias the input at V

Table 17. REFSEL (Pin 9) Definition

REFSEL Reference Source

0 REFCLK input 1 Internal crystal oscillator

S

/2.

POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION

Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important

as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance. Each power supply pin should have independent decoupling and connections to the power supply plane. It is recommended that the device exposed paddle be directly connected to the ground plane by a grid of at least nine vias. Care should be taken to ensure that the output traces cannot couple onto the reference or crystal input circuitry. Traces should not be routed under the crystal. Output signal traces should be kept on the top PCB layer; these traces have very high edge rates, and the use of PCB vias will result in signal integrity problems.

Rev. B | Page 19 of 20

AD9572

OUTLINE DIMENSIONS

PIN 1

INDICATOR

6.10

6.00 SQ

5.90

0.50

BSC

0.30

0.25

0.18

31

N

1

P

30

EXPOSED

PAD

40

1

I

N

I

*

4.70

4.60 SQ

4.50

O

R

T

D

C

I

A

0.80

0.75

0.70

SEATING

PLANE

21

0.08

20

BOTTOM VIEWTOP VIEW

0.45

0.40

0.35

0.05 MAX

0.02 NOM COPLANARITY

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION.

10

11

0.20 MIN

FORPROPERCONNECTIONOF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

02-02-2010-A

Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad

(CP-40-7)

Dimensions shown in millimeters

ORDERING GUIDE

1, 2, 3

Model

AD9572ACPZLVD −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-7 AD9572ACPZLVD-RL −40°C to +85°C

AD9572ACPZLVD-R7 −40°C to +85°C

AD9572ACPZPEC −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-7 AD9572ACPZPEC-RL −40°C to +85°C

AD9572ACPZPEC-R7 −40°C to +85°C

AD9572-EVALZ-LVD Evaluation Board AD9572-EVALZ-PEC Evaluation Board

1

Z = RoHS Compliant Part.

2

LVD indicates LVDS-compliant, differential clock outputs.

3

PEC indicates LVPECL-compliant, differential clock outputs.

Temperature Range Package Description Package Option

40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],

CP-40-7

13” Tape and Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],

CP-40-7

7” Tape and Reel, 750 Pieces

40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],

CP-40-7

13” Tape and Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],

CP-40-7

7” Tape and Reel, 750 Pieces

Rev. B | Page 20 of 20

Datasheet AD9572 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

PLL CHARACTERISTICS

LVDS CLOCK OUTPUT JITTER

LVPECL CLOCK OUTPUT JITTER

CMOS CLOCK OUTPUT JITTER

REFERENCE INPUT

CLOCK OUTPUTS

TIMING CHARACTERISTICS

CONTROL PINS

POWER

CRYSTAL OSCILLATOR

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

OUTPUTS

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP

POWER SUPPLY

CMOS CLOCK DISTRIBUTION

LVPECL CLOCK DISTRIBUTION

LVDS CLOCK DISTRIBUTION

REFERENCE INPUT

POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION

OUTLINE DIMENSIONS

ORDERING GUIDE