Datasheet AD9548 Datasheet (ANALOG DEVICES)

Page 1

Quad/Octal Input Network Clock

FEATURES

Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Auto/manual holdover and reference switchover 4 pairs of reference input pins with each pair configurable as

a single differential input or as 2 independent single-

ended inputs Input reference frequencies from 1 Hz to 750 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 30-bit programmable input reference divider 4 pairs of clock output pins with each pair configurable as a

single differential LVDS/LVPECL output or as 2 single-

ended CMOS outputs Output frequencies up to 450 MHz 30-bit integer and 10-bit fractional programmable feedback

divider Programmable digital loop filter covering loop bandwidths

from 0.001 Hz to 100 kHz Optional low noise LC-VCO system clock multiplier Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles Software controlled power-down 88-lead LFCSP package

Generator/Synchronizer

AD9548

APPLICATIONS

Network synchronization Cleanup of reference clock jitter GPS 1 pulse per second synchronization SONET/SDH clocks up to OC-192, including FEC Stratum 2 holdover, jitter cleanup, and phase transient

control Stratum 3E and Stratum 3 reference clocks Wireless base station controllers Cable infrastructure Data communications

GENERAL DESCRIPTION

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

The AD9548 operates over an industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

STABLE

SOURCE

CLOCK

MULTIPLIER

DIGITAL

REFERENCE INPU TS

AND

MONITOR MUX

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

PLL

SERIAL CONT ROL INT ERFACE

(SPI or I

AD9548

DAC

Figure 1.

ANALOG

FILTER

CLOCK DISTRI BUTION

CHANNEL 0

DIVIDER

CHANNEL 1

DIVIDER

CHANNEL 2

DIVIDER

CHANNEL 3

DIVIDER

SYNC

EEPROM

STATUS AND

CONTROL PINS

08022-001

Page 2

AD9548

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Supply Voltage............................................................................... 4

Supply Current.............................................................................. 4

Power Dissipation......................................................................... 4

Logic Inputs (M7 to M0, RESET, TDI, TCLK, TMS).............. 5

Logic Outputs (M7 to M0, IRQ, TDO) ..................................... 5

System Clock Inputs (SYSCLKP/SYSCLKN) ........................... 5

Distribution Clock Inputs (CLKINP/CLKINN)...................... 6

Reference Inputs (REFA/REFAA to REFD/REFDD) .............. 7

Reference Monitors...................................................................... 7

Reference Switchover Specifications.......................................... 8

Distribution Clock Outputs (OUT0 to OUT3)........................ 8

DAC Output Characteristics (DACOUTP/DACOUTN) .......9

Time Duration of Digital Functions........................................ 10

Digital PLL .................................................................................. 10

Digital PLL Lock Detection ...................................................... 10

Holdover Specifications............................................................. 10

Serial Port Specifications—SPI Mode...................................... 11

Serial Port Specifications—I2C Mode...................................... 11

Jitter Generation .........................................................................12

Absolute Maximum Ratings.......................................................... 14

ESD Caution................................................................................ 14

Pin Configuration and Function Descriptions........................... 15

Typical Performance Characteristics ........................................... 18

Input/Output Termination Recommendations .......................... 23

Getting Started................................................................................ 24

Power-On Reset .......................................................................... 24

Initial Pin Programming ...........................................................24

Device Register Programming.................................................. 24

Theory of Operation ...................................................................... 26

Overview...................................................................................... 26

Reference Clock Inputs.............................................................. 27

Reference Monitors .................................................................... 27

Reference Profiles....................................................................... 28

Reference Switchover ................................................................. 30

Rev. B | Page 2 of 112

Digital PLL (DPLL) Core .......................................................... 32

Direct Digital Synthesizer ......................................................... 34

Tuning Word Processing ........................................................... 35

Loop Control State Machine..................................................... 36

System Clock Inputs................................................................... 37

SYSCLK PLL Multiplier............................................................. 38

Clock Distribution ..................................................................... 39

Status and Control.......................................................................... 44

Multifunction Pins (M0 to M7) ............................................... 44

IRQ Pin........................................................................................ 45

Watchdog Timer......................................................................... 46

EEPROM ..................................................................................... 46

Serial Control Port ......................................................................... 51

SPI/IC Port Selection................................................................ 51

SPI Serial Port Operation.......................................................... 51

IC Serial Port Operation.......................................................... 55

I/O Programming Registers.......................................................... 58

Buffered/Active Registers.......................................................... 58

Autoclear Registers..................................................................... 58

Serial Port Configuration (Register 0000 to Register 0005). 70

System Clock (Register 0100 to Register 0108)...................... 71

General Configuration (Register 0200 to Register 0214) ..... 72

DPLL Configuration (Register 0300 to Register 031B)......... 75

Clock Distribution Output Configuration (Register 0400 to

Reference Input Configuration (Register 0500 to Register

0507)............................................................................................. 81

Profile Registers (Register 0600 to Register 07FF) ................ 83

Operational Controls (Register 0A00 to Register 0A10)...... 92

Status Readback (Register 0D00 to Register 0D19)............... 97

Nonvolatile Memory (EEPROM) Control (Register 0E00 to

EEPROM Storage Sequence (Register 0E10 to Register 0E3F)

..................................................................................................... 101

Power Supply Partitions............................................................... 105

3.3 V Supplies............................................................................ 105

1.8 V Supplies............................................................................ 105

Thermal Performance.................................................................. 106



Page 3

AD9548

Calculating Digital Filter Coefficients....................................... 107

Calculation of the α Register Values ..................................... 108

Calculation of the β Register Values...................................... 108

Calculation of the γ Register Values ...................................... 109

REVISION HISTORY

7/11—Rev. A to Rev. B

Changed AD9584 to AD9548........................................................32

Changed 437,749,988,378,041 to 43,774,988,378,041................34

Change to Calculating Digital Filter Coefficients Section.......107

10/10—Rev. 0 to Rev. A

Changes to Timing Parameter, Table 17.......................................11

Added Low Loop Bandwidth Applications Using a TCXO/OCXO Section and Choosing a System Clock Oscillator Frequency

Section ..............................................................................................37

Moved System Clock Period Section ............................................39

Changes to Addr 0002, Table 35....................................................60

Changes to Addr 0600, Table 35....................................................62

Changes to Addr 0632, Table 35....................................................63

Calculation of the δ Register Values.......................................109

Outline Dimensions......................................................................110

Ordering Guide.........................................................................110

Changes to Addr 0680, Table 35....................................................64

Changes to Addr 06B2, Table 35...................................................65

Changes to Address 0002 Description, Table 38.........................70

Changes to Bit 7 and Bit 6, Table 78 .............................................83

Changes to Address 0629 and Address 062A, Table 87 and Bit 7

and Bit 6, Table 88...........................................................................85

Changes to Address 065B and Address 065C, Table 97 and Bit 7

and Bit 6, Table 98...........................................................................87

Changes to Address 06A9 and Address 06AA, Table 107 .........89

Changes to Bit 7 and Bit 6, Table 108 ...........................................90

Changes to Address 06DB and Address 06DC, Table 117.........92

4/09—Revision 0: Initial Version

Rev. B | Page 3 of 112

Page 4

AD9548

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD

SUPPLY VOLTAGE

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY VOLTAGE

DVDD3 3.135 3.30 3.465 V Pin 7, Pin 82 DVDD 1.71 1.80 1.89 V Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88 AVDD3 3.135 3.30 3.465 V Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73

3.3 V Supply (Typical) 3.135 3.30 3.465 V Pin 31, Pin 37, Pin 38, Pin 44

1.8 V Supply (Alternative) 1.71 1.80 1.89 V Pin 31, Pin 37, Pin 38, Pin 44

AVDD 1.71 1.80 1.89 V

SUPPLY CURRENT

The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Tab l e 3 . The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Ta ble 3 .

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY CURRENT

1.5 3 mA Pin 7, Pin 82

DVDD3

190 215 mA Pin 1, Pin 6, Pin 12, Pin 14, Pin 15, Pin 77, Pin 83, Pin 88

DVDD

52 75 mA Pin 21, Pin 22, Pin 47, Pin 60, Pin 66, Pin 67, Pin 73

AVDD3

3.3 V Supply (Typical) 24 110 mA Pin 31, Pin 37, Pin 38, Pin 44

1.8 V Supply (Alternative) 24 110 mA Pin 31, Pin 37, Pin 38, Pin 44

135 163 mA

AVDD

= 1.8 V; TA= 25°C; I

Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,

Pin 63, Pin 70, Pin 74

Pin 23, Pin 24, Pin 29, Pin 34, Pin 41, Pin 50, Pin 55, Pin 59,

Pin 63, Pin 70, Pin 74

= 20 mA (full scale), unless otherwise noted.

DAC

POWER DISSIPATION

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION

Typical Configuration 800 1100 mW

All Blocks Running 900 1400 mW

Full Power-Down 13 mW

Rev. B | Page 4 of 112

= 20 MHz1; fS = 1 GHz2; f

SYSCLK

= 122.88 MHz3; one

DDS

LVPECL clock distribution output running at 122.88 MHz

(all others powered down); one input reference running

at 100 MHz (all others powered down)

= 20 MHz1; fS = 1 GHz2; f

SYSCLK

= 399 MHz3; all clock

DDS

distribution outputs configured as LVPECL at 399 MHz; all

input references configured as differential at 100 MHz;

fractional-N active (R = 10, S = 39, U = 9, V = 10)

Conditions = typical configuration; no external pull-up or

pull-down resistors

Page 5

AD9548

Parameter Min Typ Max Unit Test Conditions/Comments

Incremental Power Dissipation

SYSCLK PLL Off −105 mW f Input Reference On

Differential 7 mW Single-Ended 13 mW

Output Distribution Driver On

LVDS 70 mW LVPECL 75 mW

CMOS 65 mW A single 3.3 V CMOS output with a 10 pF load.

is the frequency at the SYSCLKP and SYSCLKN pins.

SYSCLK

fS is the sample rate of the output DAC.

is the output frequency of the DDS.

DDS

LOGIC INPUTS (M7 TO M0, RESET, TDI, TCLK, TMS)

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (M7 to M0, RESET, TDI, TCLK, TMS)

Input High Voltage (VIH) 2.1 V Input Low Voltage (VIL) 0.8 V Input Current (I Input Capacitance (CIN) 3 pF

, I

) ±80 ±200 µA

INH

INL

Conditions = typical configuration; table values show the change in power due to the indicated operation.

= 1 GHz1; high frequency direct input mode.

SYSCLK

LOGIC OUTPUTS (M7 TO M0, IRQ, TDO)

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC OUTPUTS (M7 to M0, IRQ, TDO)

Output High Voltage (VOH) 2.7 V IOH = 1 mA Output Low Voltage (VOL) 0.4 V IOL = 1 mA IRQ Leakage Current Open-drain mode

Active Low Output Mode 1 A VOH = 3.3 V Active High Output Mode 1 A VOL =-0 V

SYSTEM CLOCK INPUTS (SYSCLKP/SYSCLKN)

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

SYSTEM CLOCK PLL BYPASSED

Input Frequency Range 500 1000 MHz Minimum Input Slew Rate 1000 V/s

Duty Cycle 40 60 % Common-Mode Voltage 1.2 V Internally generated Differential Input Voltage Sensitivity 100 mV p-p

Input Capacitance 2 pF Single-ended, each pin Input Resistance 2.5 kΩ

Minimum limit imposed for jitter performance

Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input

Rev. B | Page 5 of 112

Page 6

AD9548

Parameter Min Typ Max Unit Test Conditions/Comments

SYSTEM CLOCK PLL ENABLED

PLL Output Frequency Range 900 1000 MHz Phase-Frequency Detector (PFD) Rate 150 MHz Frequency Multiplication Range 6 255 Assumes valid system clock and PFD rates VCO Gain 70 MHz/V High Frequency Path

Input Frequency Range 100.1 500 MHz Minimum Input Slew Rate 200 V/s

Frequency Divider Range 1 8 Binary steps (M = 1, 2, 4, 8) Common-Mode Voltage Differential Input Voltage Sensitivity 100 mV p-p

Input Capacitance 3 pF Single-ended, each pin Input Resistance 2.5 kΩ

Low Frequency Path

Input Frequency Range 3.5 100 MHz Minimum Input Slew Rate 50 V/s

Common-Mode Voltage 1.2 V Internally generated Differential Input Voltage Sensitivity 100 mV p-p

Input Capacitance 3 pF Single-ended, each pin Input Resistance 4 kΩ

Crystal Resonator Path

Crystal Resonator Frequency Range 10 50 MHz Fundamental mode, AT cut Maximum Crystal Motional Resistance 100 Ω

1 V Internally generated

Minimum limit imposed for jitter performance

See the System Clock Inputs section for recommendations

DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)

Input Frequency Range 62.5 500 MHz Minimum Slew Rate 75 V/s

Common-Mode Voltage 700 mV Internally generated. Differential Input Voltage Sensitivity 100 mV p-p

Differential Input Power Sensitivity −15 dBm

Input Capacitance 3 pF Input Resistance 5 kΩ

Rev. B | Page 6 of 112

Minimum limit imposed for jitter performance.

Capacitive coupling required; can accommodate single-ended input by ac grounding unused input; the instantaneous voltage on either pin must not exceed the supply rails.

The same as voltage sensitivity but specified as power into a 50 Ω load.

Each pin has a 2.5 kΩ internal dcbias resistance.

Page 7

AD9548

REFERENCE INPUTS (REFA/REFAA TO REFD/REFDD)

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

DIFFERENTIAL OPERATION

Frequency Range

Sinusoidal Input 10 750 MHz LVPECL Input 1 750 × 106 Hz LVDS Input 1 750 × 106 Hz

Minimum Input Slew Rate 40 V/s

Common-Mode Input Voltage 2 V Internally generated Differential Input Voltage Sensitivity ±65 mV

Input Resistance 25 kΩ Input Capacitance 3 pF

Minimum Pulse Width High 620 ps Minimum Pulse Width Low 620 ps

SINGLE-ENDED OPERATION

Frequency Range (CMOS) 1 250 ×106 Hz Minimum Input Slew Rate 40 V/s

Input Voltage High (VIH)

1.2 V to 1.5 V Threshold Setting 0.9 V

1.8 V to 2.5 V Threshold Setting 1.2 V

3.0 V to 3.3 V Threshold Setting 1.9 V

Input Voltage Low (VIL)

1.2 V to 1.5 V Threshold Setting 0.27 V

1.8 V to 2.5 V Threshold Setting 0.5 V

3.0 V to 3.3 V Threshold Setting 1.0 V Input Resistance 45 kΩ Input Capacitance 3 pF Minimum Pulse Width High 1.5 ns Minimum Pulse Width Low 1.5 ns

Minimum limit imposed for jitter performance

Minimum differential voltage across pins required to ensure switching between logic levels; the instantaneous voltage on either pin must not exceed the supply rails

Minimum limit imposed for jitter performance

REFERENCE MONITORS

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE MONITORS

Reference Monitor

Loss of Reference Detection

Time

Frequency Out-of Range Limits 9.54 × 10−7 0.1 ∆f/f Validation Timer 0.001 65.535 sec Programmable in 1 ms increments Redetect Timer 0.001 65.535 sec Programmable in 1 ms increments

is the frequency of the active reference; R is the frequency division factor determined by the R-divider.

REF

1.2 sec

Calculated using the nominal phase detector period (NPDP = R/f

Programmable (lower bound subject to quality of SYSCLK)

REF

Rev. B | Page 7 of 112

REF

Page 8

AD9548

REFERENCE SWITCHOVER SPECIFICATIONS

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE SWITCHOVER SPECIFICATIONS

Maximum Output Phase Perturbation (Phase

Build-Out Switchover)

Maximum Time/Time Slope (Hitless

Switchover)

Time Required to Switch to a New Reference

Hitless Switchover 5 sec

Phase Build-Out Switchover 3 sec

is the frequency of the active reference; R is the frequency division factor determined by the R-divider.

REF

DISTRIBUTION CLOCK OUTPUTS (OUT0 TO OUT3)

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL MODE Using internal current setting resistor

Maximum Output Frequency 725 MHz Rise/Fall Time (20% to 80%) 180 315 ps 100 Ω termination across output pins Duty Cycle 45 55 % Differential Output Voltage Swing

Common-Mode Output Voltage

LVDS MODE

Maximum Output Frequency 725 MHz Rise/Fall Time1 (20% to 80%) 200 350 ps 100 Ω termination across the output pair Duty Cycle 40 60 % Differential Output Voltage Swing

Balanced, VOD 247 454 mV

Unbalanced, ∆VOD 50 mV

Offset Voltage

Common-Mode, VOS 1.125 1.375 V Output driver static Common-Mode Difference, ∆VOS 50 mV

Short-Circuit Output Current 13 24 mA Output driver static

CMOS MODE

Maximum Output Frequency

3.3 V Supply 10 pF load Strong Drive Strength Setting 250 MHz Weak Drive Strength Setting 25 MHz

1.8 V Supply 150 MHz

630 770 910 mV

AVDD3

− 1.5

40 200 ps

315 65,535 ns/sec

AVDD3 − 1.3

AVDD3 −

V Output driver static

1.05

Assumes a jitter-free reference; satisfies Telcordia GR-1244-CORE requirements

Minimum/maximum values are programmable upper bounds; a minimum value ensures <10% error; satisfies Telcordia GR-1244-CORE requirements

Calculated using the nominal phase detector period (NPDP = R/f

REF

Calculated using the nominal phase detector period (NPDP = R/f

REF

Magnitude of voltage across pins; output driver static

Using internal current setting resistor (nominal 3.12 kΩ)

Voltage swing between output pins; output driver static

Absolute difference between voltage swing of normal pin and inverted pin; output driver static

Voltage difference between pins; output driver static

Weak drive option not supported for operating the CMOS drivers using a 1.8 V supply

Rev. B | Page 8 of 112

Page 9

AD9548

Parameter Min Typ Max Unit Test Conditions/Comments

Rise/Fall Time1 (20% to 80%) 10 pF load

3.3 V Supply Strong Drive Strength Setting 0.5 2 ns Weak Drive Strength Setting 8 14.5 ns

1.8 V Supply 1.5 2.5 ns

Duty Cycle 40 60 % 10 pF load Output Voltage High (VOH)

AVDD3 = 3.3 V, IOH = 10 mA 2.6 V AVDD3 = 3.3 V, IOH = 1 mA 2.9 V AVDD3 = 1.8 V, IOH = 1 mA 1.5 V

Output Voltage Low (VOL)

AVDD3 = 3.3 V, IOL = 10 mA 0.3 V AVDD3 = 3.3 V, IOL = 1 mA 0.1 V AVDD3 = 1.8 V, IOL = 1 mA 0.1 V

OUTPUT TIMING SKEW 10 pF load

Between LVPECL Outputs 14 125 ps Rising edge only; any divide value Between LVDS Outputs 13 138 ps Rising edge only; any divide value Between CMOS 3.3 V Outputs

Strong Drive Strength Setting 23 240 ps

Weak Drive Strength Setting 24 ps Between CMOS 1.8 V Outputs 40 ps Weak drive not supported at 1.8 V Between LVPECL Outputs and LVDS

Outputs Between LVPECL Outputs and CMOS

Outputs

ZERO-DELAY TIMING SKEW ±5 ns

The listed values are for the slower edge (rise or fall).

14 140 ps

19 ps

Output driver static; strong drive strength setting

Output relative to active input reference; output distribution synchronization to active reference feature enabled; assumes manual phase offset compensation of deterministic latency

DAC OUTPUT CHARACTERISTICS (DACOUTP/DACOUTN)

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

DAC OUTPUT CHARACTERISTICS (DACOUTP/DACOUTN)

Frequency Range 62.5 450 MHz Output Offset Voltage 15 mV

Voltage Compliance Range VSS − 0.5 0.5 VSS + 0.5 V Output Resistance 50 Ω

Output Capacitance 5 pF Full-Scale Output Current 20 mA

Gain Error −12 +12 % FS

This is the single-ended voltage at either DAC output pin (no external load) when the internal DAC code implies that no current is delivered to that pin.

Single-ended, each pin has an internal 50 Ω termination to VSS.

Programmable (8 mA to 31 mA; see the DAC Output section).

Rev. B | Page 9 of 112

Page 10

AD9548

TIME DURATION OF DIGITAL FUNCTIONS

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

TIME DURATION OF DIGITAL FUNCTIONS

EEPROM-to-Register Download Time 25 ms

Minimum Power-Down Exit Time 10.5 s Dependent on loop-filter bandwidth Maximum Time from Assertion of the RESET

45 ns pin to the M0 to M7 Pins Entering High Impedance State

DIGITAL PLL

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL PLL

Phase-Frequency Detector (PFD)

1 10

Input Frequency Range

Loop Bandwidth 0.001 105 Hz

Phase Margin 30 89 Degrees Programmable design parameter Reference Input (R) Division Factor 1 230 1, 2, …, 1,073,741,824 Integer Feedback (S) Division Factor 8 230 8, 9, …, 1,073,741,824 Fractional Feedback Divide Ratio 0 0.999 Maximum value: 1022/1023.

is the frequency at the input to the phase-frequency detector.

PFD

fS is the sample rate of the output DAC.

is the frequency of the active reference; R is the frequency division factor determined by the R-divider.

REF

Hz Maximum f

Programmable design parameter; maximum

= f

LOOP

Using default EEPROM storage sequence (see Register 0E10 to Register 0E3F)

Using default EEPROM storage sequence (see Register 0E10 to Register 0E3F

: fS/1002

PFD

/(20R)3

REF

DIGITAL PLL LOCK DETECTION

Table 15.

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE LOCK DETECTOR

Threshold Programming Range 0.001 65.5 ns Threshold Resolution 1 ps

FREQUENCY LOCK DETECTOR

Threshold Programming Range 0.001 16,700 ns Reference-to-feedback period difference Threshold Resolution 1 ps

HOLDOVER SPECIFICATIONS

Table 16.

Parameter Min Typ Max Unit Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Frequency Accuracy <0.01 ppm

Excludes frequency drift of SYSCLK source; excludes frequency drift of input reference prior to entering holdover

Rev. B | Page 10 of 112

Page 11

AD9548

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 17.

Parameter Min Typ Max Unit Test Conditions/Comments

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 30 µA Input Logic 0 Current 110 µA Input Capacitance 2 pF

SCLK Internal 30 kΩ pull-down resistor

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 1 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF

SDIO

As an Input

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 1 µA Input Logic 0 Current 1 µA

Input Capacitance 2 pF As an Output Output Logic 1 Voltage 2.7 V 1 mA load current Output Logic 0 Voltage 0.4 V 1 mA load current

SDO

Output Logic 1 Voltage 2.7 V 1 mA load current Output Logic 0 Voltage 0.4 V 1 mA load current

TIMING

SCLK

Clock Rate, 1/t

40 MHz

CLK

Pulse Width High, tHI 10 ns

Pulse Width Low, tLO 12 ns SDIO to SCLK Setup, tDS 3 ns SCLK to SDIO Hold, tDH 0 ns SCLK to Valid SDIO and SDO, tDV 15 ns CS to SCLK Setup (tS)

CS to SCLK Hold (tC) CS Minimum Pulse Width High

Internal 30 kΩ pull-up resistor

10 ns 0 ns 6 ns

SERIAL PORT SPECIFICATIONS—I2C MODE

Table 18.

Parameter Min Typ Max Unit Test Conditions/Comments

SDA, SCL (AS INPUT) No internal pull-up/down resistor.

Input Logic 1 Voltage 0.7 × DVDD3 V Input Logic 0 Voltage 0.3 × DVDD3 V Input Current −10 +10 µA For VIN = 10% to 90% DVDD3 Hysteresis of Schmitt Trigger Inputs 0.015 × DVDD3 Pulse Width of Spikes That Must Be

Suppressed by the Input Filter, t

SDA (AS OUTPUT)

Output Logic 0 Voltage 0.4 V IO = 3 mA. Output Fall Time from V

IHmin

to V

20 + 0.1 C

ILmax

50 ns

250 ns 10 pF ≤ Cb ≤ 400 pF.

Rev. B | Page 11 of 112

Page 12

AD9548

Parameter Min Typ Max Unit Test Conditions/Comments

TIMING

SCL Clock Rate 400 kHz Bus-Free Time Between a Stop and Start

Condition, t

BUF

Repeated Start Condition Setup Time,

SU; STA

Repeated Hold Time Start Condition, t

Stop Condition Setup Time, t

SU; STO

HD; STA

0.6 µs Low Period of the SCL Clock, tLO 1.3 µs High Period of the SCL Clock, tHI 0.6 µs SCL/SDA Rise Time, t

SCL/SDA Fall Time, tF 20 + 0.1 C Data Setup Time, t Data Hold Time, t Capacitive Load for Each Bus Line, C

Cb is the capacitance (pF) of a single bus line.

100 ns

SU; DAT

100 ns

HD; DAT

400 pF

JITTER GENERATION

Table 19.

Parameter Min Typ Max Unit Test Conditions/Comments

JITTER GENERATION

= 1 Hz1; f

REF

Bandwidth: 100 Hz to 61 MHz 0.81 ps rms Random jitter Bandwidth: 5 kHz to 20 MHz 0.73 ps rms Random jitter Bandwidth: 20 kHz to 80 MHz 0.79 ps rms Random jitter Bandwidth: 50 kHz to 80 MHz 0.78 ps rms Random jitter Bandwidth: 4 MHz to 80 MHz 0.37 ps rms Random jitter

= 8 kHz1; f

REF

Bandwidth: 100 Hz to 77 MHz 0.71 ps rms Random jitter Bandwidth: 5 kHz to 20 MHz 0.34 ps rms Random jitter Bandwidth: 20 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 50 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 4 MHz to 80 MHz 0.31 ps rms Random jitter

= 19.44 MHz1; f

REF

Bandwidth: 100 Hz to 77 MHz 1.05 ps rms Random jitter Bandwidth: 5 kHz to 20 MHz 0.34 ps rms Random jitter Bandwidth: 20 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 50 kHz to 80 MHz 0.43 ps rms Random jitter Bandwidth: 4 MHz to 80 MHz 0.32 ps rms Random jitter

= 122.88 MHz2; f

DDS

= 155.52 MHz2; f

DDS

= 155.52 MHz2; f

DDS

= 0.01 Hz3

LOOP

= 100 Hz3

LOOP

1.3 µs

0.6 µs

20 + 0.1 C

300 ns

= 20 MHz4 OCXO; fS = 1 GHz5; Q-

SYSCLK

divider = 1; default SysClk PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types

= 50 MHz4 crystal;

SYSCLK

= 1 GHz5; Q-divider = 1; default SYSCLK

PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types

= 1 kHz3

= 50 MHz4 crystal;

SYSCLK

= 1 GHz5; Q-divider = 1; default SYSCLK

PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types

After this period, the first clock pulse is generated.

Rev. B | Page 12 of 112

Page 13

AD9548

Parameter Min Typ Max Unit Test Conditions/Comments

= 19.44 Hz1; f

REF

Bandwidth: 100 Hz to 100 MHz 0.67 ps rms Random jitter Bandwidth: 5 kHz to 20 MHz 0.31 ps rms Random jitter Bandwidth: 20 kHz to 80 MHz 0.33 ps rms Random jitter Bandwidth: 50 kHz to 80 MHz 0.33 ps rms Random jitter Bandwidth: 4 MHz to 80 MHz 0.16 ps rms Random jitter

is the frequency of the active reference.

REF

is the output frequency of the DDS.

DDS

is the DPLL digital loop filter bandwidth.

LOOP

is the frequency at the SYSCLKP and SYSCLKN pins.

SYSCLK

fS is the sample rate of the output DAC.

= 311.04 MHz2; f

DDS

= 1 kHz3

LOOP

= 50 MHz4 crystal;

SYSCLK

= 1 GHz5; Q-divider = 1; default SYSCLK

PLL charge pump current; results valid for LVPECL, LVDS, and CMOS output logic types

Rev. B | Page 13 of 112

Page 14

AD9548

ABSOLUTE MAXIMUM RATINGS

Table 20.

Parameter Rating

Analog Supply Voltage (AVDD) 2 V Digital Supply Voltage (DVDD) 2 V Digital I/O Supply Voltage (DVDD3) 3.6 V DAC Supply Voltage (AVDD3) 3.6 V Maximum Digital Input Voltage −0.5 V to DVDD3 + 0.5 V Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 14 of 112

Page 15

AD9548

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

M7M6M5M4DVDD

DVDD

SDIO

SDO

DVDD

DVDD3

TCLK

TMS TDO

TDI

DVDD

RESET

DVDD DVDD

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17VSS 18DACOUTP 19DACOUTN 20VSS 21AVDD3 22AVDD3

232425262728293031323334363735

AVDD

SCLK/SCL

CS/SDA

NOTES

1. NC = NO CONNECT .

2. THE EXPO SED PAD MUST BE CONNECTED TO GROUND (VSS ).

DVDD3

M3M2M1

798081828384858687

AD9548

TOP VIEW

(Not to Scale)

88-LEAD LFCSP

12mm × 12mm

0.5mm PIT CH

VSS

AVDD

OUT0P

AVDD3

CLKINP

CLKINN

OUT_RSET

AVDD

AVDD3

REFDD

383940

OUT2P

AVDD3

AVDD

REFCC

REFD

424344

AVDD

OUT3P

OUT2N

DVDD

IRQNCAVDD3

7877767574737271706968

AVDD

OUT1P

OUT1N

OUT0N

REFC

AVDD3

OUT3N

AVDD3

REFBB

REFB AVDD

63 62

REFAA

REFA AVDD3

AVDD

59 58

TDC_VRT

TDC_VRB NC

AVDD

VSS

SYSCLKP

SYSCLKN

VSS

AVDD

SYSCLK_LF

SYSCLK_VREG

AVDD3

47 46

08022-002

Figure 2. 88-Lead LFCSP Pin Configuration

Table 21. Pin Function Descriptions

Input/

Pin No. Mnemonic

1, 6, 12, 77,

DVDD I Power 1.8 V Digital Supply.

Output

Pin Type Description

83, 88 2 SCLK/SCL I 3.3 V CMOS Serial Programming Clock. Data clock for serial programming. 3 SDIO I/O 3.3 V CMOS

Serial Data Input/Output. When the device is in 4-wire mode, data is written via this pin. In 3-wire mode, both data reads and writes occur on this pin. There is no internal pull-up/pull-down resistor on this pin.

4 SDO O 3.3 V CMOS

Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There is no internal pull-up/pull-down resistor on this pin.

/SDA

I 3.3 V CMOS

Chip Select (SPI). Active low. When programming a device, this pin must be held low. In systems where more than one AD9548 is present, this pin enables individual programming of each AD9548 (in I

C® mode, this is a serial data pin).

This pin has an internal 10 kΩ pull-up resistor but only in SPI mode. 7, 82 DVDD3 I Power 3.3 V I/O Digital Supply. 8 TCLK I JTAG Clock. Internal pull-down resistor; no connection if JTAG is not used. 9 TMS I JTAG Mode. Internal pull-up resistor; no connection if JTAG is not used. 10 TDO O JTAG Output. No connection if JTAG is not used 11 TDI I JTAG Input. Internal pull-up resistor; no connection if JTAG is not used. 13 RESET I 3.3 V CMOS

Chip Reset. When this active high pin is asserted, the chip goes into reset.

This pin has an internal 50 kΩ pull-down resistor. 14, 15 DVDD I Power 1.8 V DAC Decode Digital Supply. Keep isolated from the 1.8 V core digital supply. 16, 45, 46 NC No Connect. 17, 20, 25,

VSS O Ground Analog Ground. Connect to ground.

28, 51, 54 18 DACOUTP O

Differential

DAC Output. DACOUTP contains an internal 50 Ω pull-down resistor.

output

19 DACOUTN O

Differential output

Complementary DAC Output. DACOUTN contains an internal 50 Ω pull-down

resistor.

Rev. B | Page 15 of 112

Page 16

AD9548

Input/

Pin No. Mnemonic

21, 22 AVDD3 I Power 3.3 V Analog (DAC) Power Supply. 23, 24 AVDD I Power 1.8 V Analog (DAC) Power Supply. 26 CLKINN I

27 CLKINP I

29 AVDD I Power 1.8 V Analog (Input Receiver) Power Supply. 30 OUT_RSET O

31, 37, 38, 44

32 OUT0P O

33 OUT0N O

34, 41 AVDD I Power 1.8 V Analog (Output Divider) Power Supply. 35 OUT1P O

36 OUT1N O

39 OUT2P O

40 OUT2N O

42 OUT3P O

43 OUT3N O

47 AVDD3 I Power 3.3 V Analog (System Clock) Power Supply. 48 SYSCLK_VREG I

49 SYSCLK_LF O

50, 55 AVDD I Power 1.8 V Analog (System Clock) Power Supply. 52 SYSCLKN I

AVDD3 I Power

Output Pin Type Description

Differential input

Current set resistor

LVPECL, LVDS, or CMOS

Differential input

Clock Distribution Input. In standard operating mode, this pin is connected to the filtered DACOUTN output. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal whose single-ended swing is at least 400 mV.

Clock Distribution Input. In standard operating mode, this pin is connected to the filtered DACOUTP output

Connect an optional 3.12 kΩ resistor from this pin to ground (see the Output Current Control with an External Resistor section).

Analog Supply for Output Driver. These pins are normally 3.3 V but can be 1.8 V. Pin 31 powers Out0x. Pin 37 powers OUT1x. Pin 38 powers OUT2x. Pin 44 powers OUT3x. Apply power to these pins even if the corresponding outputs (OUT0P/ OUT0N, OUT1P/ OUT1N, OUT2P/ OUT2N, and OUT3P/ OUT3N) are not used. See the Power Supply Partitions section.

Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply.

Complementary Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply.

Complementary Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

Output 2. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply.

Complementary Output 2. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

Output 3. This output can be configured as LVPECL, LVDS, or single-ended CMOS. LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output driver power supply.

Complementary Output 3. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

System Clock Loop Filter Voltage Regulator. Connect a 0.1 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated SYSCLK PLL multiplier’s external loop filter (see the SYSCLK PLL Multiplier section).

System Clock Multiplier Loop Filter. When using the frequency multiplier to drive the system clock, an external loop filter can be attached to this pin.

Complementary System Clock Input. Complementary signal to SYSCLKP. SYSCLKN contains internal dc biasing and should be ac-coupled with a 0.01 F capacitor, except when using a crystal, in which case connect the crystal across SYSCLKP and SYSCLKN.

Rev. B | Page 16 of 112

Page 17

AD9548

Input/

Pin No. Mnemonic

53 SYSCLKP I

56, 75 NC I No Connection. These pins should be left floating. 59 AVDD I Power 1.8 V Analog Power Supply. 57, 58

60, 66, 67, 73

61 REFA I

62 REFAA I

63, 70, 74 AVDD I Power 1.8 V Analog (Reference Input) Power Supply. 64 REFB I

65 REFBB I

68 REFC I

69 REFCC I

71 REFD I

72 REFDD I

76 IRQ O Logic Interrupt Request Line. 78, 79, 80,

81, 84, 85, 86, 87

EP VSS O

TDC_VRB, TDC_VRT

AVDD3 I Power 3.3 V Analog (Reference Input) Power Supply.

M0, M1, M2, M3, M4, M5, M6, M7

Output Pin Type Description

Differential input

I Use capacitive decoupling on these pins (see Figure 38).

Differential input

I/O 3.3 V CMOS Configurable I/O Pins. These pins are configured under program control.

Exposed pad

System Clock Input. SYSCLKP contains internal dc biasing and should be ac-

coupled with a 0.01 F capacitor, except when using a crystal, in which case

connect the crystal across SYSCLKP and SYSCLKN. Single-ended 1.8 V CMOS is

also an option but can introduce a spur if the duty cycle is not 50%. When using

SYSCLKP as a single-ended input, connect a 0.01 F capacitor from SYSCLKN to

ground.

Reference A Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

Complementary Reference A Input. Complementary signal to the input provided

on Pin 61. The user can configure this pin as a separate single-ended input.

Reference B Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

Complementary Reference B Input. Complementary signal to the input provided

on Pin 64. The user can configure this pin as a separate single-ended input.

Reference C Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

Complementary Reference C Input. Complementary signal to the input provided

on Pin 68. The user can configure this pin as a separate single-ended input.

Reference D Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

Complementary Reference D Input. Complementary signal to the input provided

on Pin 71. The user can configure this pin as a separate single-ended input.

The exposed pad must be connected to ground (VSS).

Rev. B | Page 17 of 112

Page 18

AD9548

–

TYPICAL PERFORMANCE CHARACTERISTICS

fR = input reference clock frequency; fO = clock frequency; f loop bandwidth; PLL off = SYSCLK PLL bypassed; PLL on = SYSCLK PLL enabled; I PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, f

–100

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

PHASE NOISE ( dBc/Hz)

–80

–90

–110

–80

–90

–100

–110

–120

–130

–140

–150

–160

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 173fs (–75.4d Bc) 20kHz TO 80MHz: 315fs (–70.2d Bc) (EXTRAPO LATED)

100 1k 10k 100k 1M 10M 100M

FREQUENCY O FFSET (Hz)

Figure 3. Additive Phase Noise (Output Driver = LVPECL),

= 19.44 MHz, fO = 155.52 MHz,

LBW = 1 kHz, f

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 333fs (–69.8d Bc) 20kHz TO 80MHz: 430fs (–67.6dBc) (EXTRAPO LATED)

100 1k 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

= 1 GHz, PLL Off

SYS

Figure 4. Additive Phase Noise (Output Driver = LVPECL),

= 19.44 MHz, fO = 155.52 MHz,

LBW = 1 kHz, f

= 50 MHz (Crystal), PLL On

SYS

= SYSCLK input frequency; fS = internal system clock frequency; LBW = DPLL

SYS

= 1 GHz, ICP = automatic mode, LF = internal, unless otherwise noted.

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

08022-068

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

08022-056

= SYSCLK PLL charge pump current; LF = SYSCLK

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 103fs (–74.0dBc) 20kHz TO 80MHz: 160fs (–70.1dBc)

100 1k 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

Figure 5. Additive Phase Noise (Output Driver = LVPECL),

= 19.44 MHz, fO = 311.04 MHz,

LBW = 1 kHz, f

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 310fs (–64.4dBc) 20kHz TO 80MHz: 330fs (–63.9d Bc)

100 1k 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

= 1 GHz, PLL Off

SYS

Figure 6. Additive Phase Noise (Output Driver = LVPECL),

= 19.44 MHz, fO = 311.04 MHz,

LBW = 1 kHz, f

= 50 MHz (Crystal), PLL On

SYS

08022-066

08022-067

Rev. B | Page 18 of 112

Page 19

AD9548

–

PHASE NOISE (dBc/Hz)

–80

–90

–100

–110

–120

–130

–140

–150

–160

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 361fs (–69.0d Bc) 20kHz TO 80MHz: 441fs (–67.3d Bc) (EXTRAPO LATED)

100 1k 10k 100k 1M 10M 100M

FREQUENCY O FFSET (Hz)

Figure 7. Additive Phase Noise (Output Driver = LVPECL),

= 19.44 MHz, fO = 155.52 MHz,

LBW = 1 kHz, f

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

10 100 1k 10k 100k 1M 10M 100M

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 10MHz: 717fs (–65.1d Bc) 12kHz TO 20MHz: 725fs (–65.0dBc) 20kHz TO 80MHz: 790fs (–64.3dBc)

FREQUENCY O FFSET (Hz)

= 50 MHz, PLL On

SYS

Figure 8. Additive Phase Noise (Output Driver = LVPECL),

= 1 Hz, fO = 122.88 MHz,

LBW = 0.05 Hz, f

–80

–90

–100

–110

–120

–130

PHASE NOISE ( dBc/Hz)

–140

–150

–160

100 1k 10k 100k 1M 10M 100M

= 20 MHz (OCXO), PLL On

SYS

INTEGRAT ED RMS JITT ER (PHASE NOI SE): 5kHz TO 20MHz : 336fs (–69.7d Bc) 20kHz TO 80MHz : 425fs (–67.6d Bc) (EXTRAP OLATED)

FREQUENCY O FFSET (Hz)

Figure 9. Additive Phase Noise (Output Driver = LVPECL),

= 8 kHz, fO = 155.52 MHz,

LBW = 100 Hz, f

= 50 MHz (Crystal), PLL On

SYS

08022-069

08022-044

08022-052

–80

–90

–100

–110

–120

–130

PHASE NOISE ( dBc/Hz)

–140

–150

–160

100 1k 10k 100k 1M 10M 100M

50MHz CRYSTAL

ROHDE & SCHWARZ SMA100 (50MHz)

ROHDE & SCHWARZ

SMA100 (1GHz)

FREQUENCY ( Hz)

Figure 10. Additive Phase Noise Comparison of SYSCLK Input Options

(Output Driver = LVPECL),

= 19.44 MHz, fO = 311.04 MHz, LBW = 1 kHz

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

–80

–90

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 356fs (–69.2dBc) 20kHz TO 80MHz: 435fs (–67.4dBc) (EXTRAPO LATED)

100 1k 10k 100k 1M 10M 100M

FREQUENCY O FFSET (Hz)

Figure 11. Additive Phase Noise (Output Driver = LVPECL),

= 1 Hz, fO = 155.52 MHz,

LBW = 0.05 Hz, f

–100

–110

–120

–130

PHASE NOISE ( dBc/Hz)

–140

–150

–160

–80

–90

INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 245fs (–72.4d Bc) 20kHz TO 80MHz: 300fs (–64.3dBc) (EXTRAPO LATED)

100 1k 10k 100k 1M 10M 100M

FREQUENCY O FFSET (Hz)

= 50 MHz, PLL On

SYS

Figure 12. Additive Phase Noise (Output Driver = LVPECL) ,

= 19.44 MHz, fO = 155.52 MHz,

LBW = 1 kHz, f

2x Frequency Multiplier, I

= 50 MHz (Crystal), PLL On with

SYS

= 375 μA, LF = External (350 kHz)

08022-058

08022-054

08022-051

Rev. B | Page 19 of 112

Page 20

AD9548

–

–100

CLOSED-LOOP PEAKING: 0.04dB

–110

–120

–130

–140

PHASE NOISE ( dBc/Hz)

–150

–160

–170

100 1k 10k 100k 1M 10M

ROHDE & SCHW ARZ

SMA100 (1GHz)

20MHz OCXO

ROHDE & SCHWARZ SMA100 (50MHz)

FREQUENCY OFFSET (Hz)

Figure 13. Phase Noise of SYSCLK Input Sources

1.0

0.8

LVPECL

0.6

0.4

AMPLITUDE (V)

0.2

LVDS

–10

–20

–30

–40

CLOSED-LOOP GAIN (dB)

–50

–60

–70

10 100 1k 10k 100k

08022-053

FREQUENCY OFFSET (Hz)

08022-047

Figure 16. Jitter Transfer Bandwidth, Output Driver = LVPECL,

= 19.44 MHz, fO = 155.52 MHz,

LBW = 100 Hz (Phase Margin = 88°), f

2.0

1.5

AMPLITUDE (V)

1.0

20pF LOAD

= 1 GHz, PLL Off

SYS

5pF LOAD

10pF LOAD

0 100 200 300 400 500 600 700

FREQUENCY ( MHz)

Figure 14. Amplitude vs. Toggle Rate,

LVPECL and LVDS

4.0

3.5

3.0

2.5

AMPLITUDE (V)

2.0

1.5

1.0 0 100 200 300 400 500

FREQUE NCY (MHz)

10pF LO AD

20pF LOAD

Figure 15. Amplitude vs. Toggle Rate,

3.3 V CMOS (Strong Mode)

0.5 0 50 100 150 250200

08022-049

FREQUENCY (MHz)

08022-062

Figure 17. Amplitude vs. Toggle Rate,

1.8 V CMOS

4.0

3.5

3.0

2.5

AMPLITUDE (V)

2.0

1.5

1.0

08022-055

0 1020304050

5pF LOAD

10pF LOAD

FREQUE NCY (MHz)

08022-063

Figure 18. Amplitude vs. Toggle Rate,

3.3 V CMOS (Weak Mode)

Rev. B | Page 20 of 112

Page 21

AD9548

140

130

120

110

100

POWER (mW)

0 100 200 300 400 500

LVPECL

LVDS

FREQUE NCY (MHz)

Figure 19. Power Consumption vs. Frequency,

LVPECL and LVDS

(Single Channel)

160

08022-064

POWER (mW)

0 50 100 150 200

10pF LOAD

20pF LO AD

5pF LOAD

FREQUENCY (MHz)

Figure 22. Power Consumption vs. Frequency,

1.8 V CMOS

08022-061

140

120

10pF LOAD

20pF LO AD

5pF LOAD

FREQUENCY (M Hz)

100

POWER (mW)

0 50 100 1 50 200 250 300 350

Figure 20. Power Consumption vs. Frequency,

3.3 V CMOS (Strong Mode)

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

DIFFERENTIAL AMPLITUDE (V)

–0.6

–0.8

–1.0

012345

TIME (ns)

Figure 21. Output Waveform,

LVPECL (400 MHz)

20pF LOAD 5p F LOAD

POWER (mW)

10 15 20 25 30 35 40

08022-060

10pF LOAD

FREQUENCY (MHz)

08022-059

Figure 23. Power Consumption vs. Frequency,

3.3 V CMOS (Weak Mode)

0.5

0.4

0.3

0.2

0.1

L AMPLITUDE (V)

–0.1

–0.2

DIFFERENTI

–0.3

–0.4

–0.5

012345

08022-050

TIME (ns)

08022-048

Figure 24. Output Waveform,

LVDS (400 MHz)

Rev. B | Page 21 of 112

Page 22

AD9548

3.5

3.0

2.5

20pF LOAD

10pF LOAD

3.5

3.0

2.5

5pF LO AD

AMPLITUDE (V)

2.0

1.5

1.0

0.5

–0.5

20 pF LOAD

0 1020304050607080

TIME (ns)

08022-046

Figure 27. Output Waveform,

3.3 V CMOS (20 MHz, Weak Mode)

2.0

1.5

1.0

AMPLITUDE ( V)

0.5

–0.5

0 2 4 6 8 10 12 14 16

TIME (ns)

Figure 25. Output Waveform,

3.3 V CMOS (100 MHz, Strong Mode)

2.0

1.5

20pF LOAD

1.0

10pF LOAD

08022-057

0.5

AMPLITUDE (V)

–0.5

0 2 4 6 8 10 12 14 16

TIME (ns)

Figure 26. Output Waveform,

1.8 V CMOS (100 MHz)

08022-065

Rev. B | Page 22 of 112

Page 23

AD9548

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

0.1µF

AD9548

3.3V LVDS OUTPUT

100Ω

IMPEDANCE

0.1µF

HIGH

INPUT

DOWNST REAM

Figure 28. AC-Coupled LVDS or LVPECL Output Driver

AD9548

3.3V

LVPECL-

COMPATIBL E

OUTPUT

100Ω

DOWNST REAM

Figure 29. DC-Coupled LVDS or LVPECL Output Driver

0.1µF

AD9548

(OPTIO NAL)

SELF-BIASED REFERENCE

INPUT

0.1µF

100Ω

Figure 30. Reference Input

DEVICE

08022-005

0.1µF

AD9548

SELF-BIASED

0.1µF

08022-003

100Ω

SYSCLK

INPUT

(OPTIO NAL)

08022-006

Figure 31. SYSCLKx Input

0.1µF

AD9548

(OPTIO NAL)

SELF-BIASED

CLKINx

INPUT

08022-007

100Ω

0.1µF

08022-004

Figure 32. CLKINx Input

Rev. B | Page 23 of 112

Page 24

AD9548

GETTING STARTED

POWER-ON RESET

The AD9548 monitors the voltage on the power supplies at power-up. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD (Pin 1, Pin 6, Pin 12, Pin 77, Pin 83, and Pin 88) is greater than 1.4 V ± 0.05 V, the device generates a 75 ns reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing. Within 45 ns after the leading edge of the internal reset pulse, the M0 to M7 multifunction pins behave as high impedance digital inputs and remain so until programmed otherwise.

INITIAL PIN PROGRAMMING

During a device reset (either via the power-up reset pulse or the RESET pin), the multifunction pins (M0 to M7) behave as high impedance inputs, but upon removal of the reset condition, level-sensitive latches capture the logic pattern present on the multifunction pins. The AD9548 requires that the user supply the desired logic state to the M0 to M7 pins by means of pull-up and/or pull-down resistors (nominally 10 k to 30 k).

The initial state of the M0 to M7 pins following a reset is referred to as FncInit, Bits[7:0]. Bits[7:0] of FncInit map directly to the logic states of M7:0, respectively. The three LSBs of FncInit (FncInit, Bits[2:0]) determine whether the serial port interface behaves according to the SPI or I Specifically, FncInit, Bits[2:0] = 000 selects the SPI interface, while any other value selects the I

the I

C bus address set to the value of FncInit, Bits[2:0].

The five MSBs of FncInit (FncInit, Bits[7:3]) determine the operation of the EEPROM loader. On the falling edge of RESET, if FncInit, Bits[7:3] = 00000, then the EEPROM contents are not transferred to the control registers and the device registers assume their default values. However, if FncInit, Bits[7:3] ≠ 00000, then the EEPROM controller transfers the contents of the EEPROM to the control registers with condition = FncInit, Bits[7:3] (see the EEPROM section).

DEVICE REGISTER PROGRAMMING

The initial state of the M0 to M7 pins establishes the serial I/O port protocol (SPI or I protocol, and assuming that an EEPROM download is not used, program the device according to the recommended sequence described in the Program the System Clock Functionality section through the Generate the Output Clock section.

Program the System Clock Functionality

The system clock parameters reside in the 0100 register address space. They include the following:

• System clock PLL controls

• System clock period

• System clock stability timer

C). Using the appropriate serial port

C protocol.

C port with the three LSBs of

Rev. B | Page 24 of 112

It is essential to program the system clock period because many of the AD9548 subsystems rely on this value. It is highly recommended to program the system clock stability timer, as well. This is especially important when using the system clock PLL but also applies if using an external system clock source, especially if the external source is not expected to be completely stable when power is applied to the AD9548.

Initialize the System Clock

After the system clock functionality is programmed, issue an I/O update using Register 0005, Bit 0 to invoke the system clock settings.

Calibrate the System Clock (Only if Using SYSCLK PLL)

Set the calibrate system clock bit in the sync/cal register (Address 0A02, Bit 0) and issue an I/O update. Then clear the calibrate system clock bit and issue another I/O update. This action allows time for the calibration to proceed while programming the remaining device registers.

Program the Multifunction Pins (Optional)

This step is required only if the user intends to use any of the multifunction pins for status or control. The multifunction pin parameters reside in the 0200 to 0207 register address space. The default configuration of the multifunction pins is as an undesignated high impedance input pin.

Program the IRQ Functionality (Optional)

This step is required only if the user intends to use the IRQ feature. IRQ control resides in the 0200 to 0207 register address space. It includes the following:

• IRQ pin mode control

• IRQ mask

The IRQ mask default values prevent interrupts from being generated. The IRQ pin mode default is open-drain NMOS.

Program the Watchdog Timer (Optional)

This step is required only if the user intends to use it. Watchdog timer control resides in the 0200 register address space. The watchdog timer is disabled by default.

Program the DAC Full-Scale Current (Optional)

This step is required only if the user intends to use a full-scale current setting other than the default value. DAC full-scale current control resides in the 0200 register address space.

Program the Digital Phase-Locked Loop (DPLL)

The DPLL parameters reside in the 0300 register address space. They include the following:

• Free-run frequency (DDS frequency tuning word)

• DDS phase offset

• DPLL pull-in range limits

• DPLL closed-loop phase offset

• Phase slew control (for hitless reference switching)

• Tuning word history control (for holdover operation)

Page 25

AD9548

Program the Clock Distribution Outputs

The clock distribution parameters reside in the 0400 register address space. They include the following:

• Output power-down control

• Output enable (disabled by default)

• Output synchronization

• Output mode control

• Output divider functionality

Program the Reference Inputs

The reference input parameters reside in the 0500 register address space. They include the following:

• Reference power-down

• Reference logic family

• Reference profile assignment control

• Phase build-out control

Program the Reference Profiles

The reference profile parameters reside in the 0600 to 0700 register address space. They include the following:

• Reference priority

• Reference period

• Reference period tolerance

• Reference validation timer

• Reference redetect timer

• Digital loop-filter coefficients

• Reference prescaler (R-divider)

• Feedback dividers (S, U, and V)

• Phase and frequency lock detector controls

Generate the Reference Acquisition

After the registers are programmed, issue an I/O update using Register 0005, Bit 0 to invoke all of the register settings programmed up to this point.

If the settings are programmed for manual profile assignment, the DPLL locks to the first available reference that has the highest priority. If the settings are programmed for automatic profile assignment, then write to the reference profile detect register (Address 0A0D) to select the state machines that require starting. Next, issue an I/O update (Address 0005, Bit 0) to start the selected state machines. Upon completion of the reference detection sequence, the DPLL locks to the first available reference with the highest priority.

Generate the Output Clock

If the registers are programmed for automatic clock distribution synchronization via DPLL phase or frequency lock, the synthesized output signal appears at the clock distribution outputs (assuming the output is enabled and that the DDS output signal has been routed to the CLKIN input pins). Otherwise, set and then clear the sync distribution bit (Address 0A02, Bit 1) or use a multifunction pin input (if programmed accordingly) to generate a clock distribution sync pulse, which causes the synthesized output signal to appear at the clock distribution outputs.

Rev. B | Page 25 of 112

Page 26

AD9548

THEORY OF OPERATION

REFA

REFAA

REFB

REFBB

REFC

REFCC

REFD

REFDD

M0 TO M7

IRQ

AD9548

DIFFERENTIAL

SINGLE-E NDED

4 OR 8

INPUT

REF

MONITOR

IRQ AND

STATUS

LOGIC

DIGITAL PLL CORE

÷R

TDC/PFD

PHASE

CONTROLL ER

PROG.

DIGITAL

LOOP

FILTER

CONTROL

LOGIC

÷S

TW CLAMP

AND

HISTORY

HOLDO VER

LOGIC

DDS/DAC

LOW NOISE

CLOCK

MULTIPLIER

SYSCLK PORT

POST

DIV

POST

DIV

POST

DIV

POST

DIV

CLOCK

DISTRIBUTI ON

AMP

OUT_R SET

OUT0P OUT0N

OUT1P OUT1N

OUT2P OUT2N

OUT3P OUT3N

CLKINP

CLKINN

EXTERNAL

ANALOG

FILTER

DIGITAL

INTERFACE

Figure 33. Detailed Block Diagram

OVERVIEW

The AD9548 provides clocking outputs directly related in phase and frequency to the selected (active) reference but with jitter characteristics primarily governed by the system clock. The AD9548 supports up to eight reference inputs and a wide range of reference frequencies. The core of this product is a digital phase-locked loop (DPLL). The DPLL has a programmable digital loop filter that greatly reduces jitter transferred from the active reference to the output. The AD9548 supports both manual and automatic holdover. While in holdover, the AD9548 continues to provide an output as long as the DAC sample clock is present. The holdover output frequency is a time average of the output frequency history just prior to the transition to the holdover condition.

The device offers manual and automatic reference switchover capability if the active reference is degraded or fails completely. A direct digital synthesizer (DDS) and integrated DAC constitute a digitally controlled oscillator (DCO). The DCO output is a sinusoidal signal (450 MHz maximum) at a frequency determined by the active reference frequency and the programmed values of the reference prescaler (R) and feedback divider (S). Although not explicitly shown in Figure 33, the S-divider has both an integer and fractional component, which is similar to a fractional-N synthesizer.

SYSCLK N SYSC LKP

The SYSCLKx input provides the sample clock for the DAC, which is either a directly applied high frequency source or a low frequency source coupled with the integrated PLL-based frequency multiplier. The low frequency option also allows for the use of a crystal resonator connected directly across the SYSCLKx inputs.

The DAC output routes directly off-chip, where an external filter removes the sampling artifacts before returning the signal on-chip at the CLKINx inputs. Once on-chip, an integrated comparator converts the filtered sinusoidal signal to a clock signal (square wave) with very fast rise and fall times.

The clock distribution section provides four output drivers. Each driver is programmable either as a single differential LVPECL/LVDS output or as a dual single-ended CMOS output. Furthermore, each of the four outputs has a dedicated 30-bit programmable postdivider. The clock distribution section operates at up to 725 MHz. This enables use of a band-pass reconstruction filter (for example, a SAW filter) to extract a Nyquist image from the DAC output spectrum, thereby allowing output frequencies that exceed the typical 450 MHz limit at the DAC output.

08022-009

Rev. B | Page 26 of 112

Page 27

AD9548

REFERENCE CLOCK INPUTS

Four pairs of pins provide access to the reference clock receivers. Each pair is configurable either as a single differential receiver or as two independent single-ended receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate spontaneously.

When configured for differential operation, the input receivers accommodate either ac- or dc-coupled input signals. The receiver is internally dc biased in order to handle ac-coupled operation.

When configured for single-ended operation, the input receivers exhibit a pull-down load of 45 kΩ (typical). Three user-programmable threshold voltage ranges are available for each single-ended receiver.

REFERENCE MONITORS

The reference monitors depend on a known and accurate system clock period. Therefore, the functioning of the reference monitors is not reliable until the system clock is stable. To avoid an incorrect valid indication, the reference monitors indicate fault status until the system clock stability timer expires (see the System Clock Stability Timer section).

Reference Period Monitor

Each reference input has a dedicated monitor that repeatedly measures the reference period. The AD9548 uses the reference period measurements to determine the validity of the reference based on a set of user provided parameters in the profile register area of the register map (see the Profile Registers (Register 0600 to Register 07FF) section). The AD9548 also uses the reference period monitor to assign a particular reference to a profile when the user programs the device for automatic profile assignment.

The monitor works by comparing the measured period of a particular reference input with the parameters stored in the profile register assigned to that same reference input. The parameters include the reference period, an inner tolerance, and an outer tolerance. A 50-bit number defines the reference period in units of femtoseconds. The 50-bit range allows for a reference period entry of up to 1.125 sec. However, an actual reference signal with a period in excess of 1 sec is beyond the recommended operating range of the device. A 20-bit number defines the inner and outer tolerances. The value stored in the register is the reciprocal of the tolerance specification. For example, a tolerance specification of 50 ppm yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000 (0x04E20).

The use of two tolerance values provides hysteresis for the monitor decision logic. The inner tolerance applies to a previously faulted reference and specifies the largest period tolerance that a previously faulted reference can exhibit before it qualifies as nonfaulted. The outer tolerance applies to an already nonfaulted reference. It specifies the largest period tolerance that a nonfaulted reference can exhibit before being faulted.

To produce decision hysteresis, the inner tolerance must be less than the outer tolerance. That is, a faulted reference must meet tighter requirements to become nonfaulted than a nonfaulted reference must meet to become faulted.

Reference Validation Timer

Each reference input has a dedicated validation timer. The validation timer establishes the amount of time that a previously faulted reference must remain fault free before the AD9548 declares it nonfaulted. The timeout period of the validation timer is programmable via a 16-bit register (see the validation register contained within each of the eight profile registers in the register map, Address 0600 to Address 07FF). The 16-bit number stored in the validation register represents units of milliseconds, which yields a maximum timeout period of 65,535 ms.

Note that a validation period of 0 must be programmed to disable the validation timer. With the validation timer disabled, the user must validate a reference manually via the force validation timeout register (Address 0A0E).

Reference Redetect Timer

Each reference input has a dedicated redetect timer. The redetect timer is useful only with the device programmed for automatic profile selection. The redetect timer establishes the amount of time that a reference must remain faulted before the AD9548 attempts to reassign it to a new profile. The timeout period of the redetect timer is programmable via a 16-bit register (see the redetect timeout register contained within each of the eight profile registers in the register map, Address 0600 to Address 07FF). The 16-bit number stored in the redetect timeout register represents units of milliseconds, which yields a maximum timeout period of 65,535 ms.

Note that a timeout period of 0 must be programmed to disable the redetect timer.

Reference Validation Override Control

Register 0A0E to Register 0A10 provide the user with the ability to override the reference validation logic enabling a certain level of troubleshooting capability. Each of the eight input references has a dedicated block of validation logic as shown in Figure 34. The state of the valid signal at the output is what defines a particular reference as valid (1) or not (0), which includes the validation period (if activated) as prescribed by the validation timer. The override controls are the three control bits on the left side of the diagram.

Rev. B | Page 27 of 112

Page 28

AD9548

FORCE VALI DATION

TIMEOUT

REF MONIT OR

BYPASS

REF MONIT OR

OVERRIDE

REFERENCE

MONITOR

REF FAULT

REFERENCE VALI DATION LO GIC

(8 COPIES, 1 PER REFERENCE INPUT)

FAULTED

Figure 34. Reference Validation Override

The main feature to note is that any time faulted = 1, the output latch is reset, which forces valid = 0 (indicating an invalid reference) regardless of the state of any other signal. Under the default condition (that is, all three control bits are 0), the reference monitor is the primary source of the validation process. This is because, under the default condition, the ref fault signal from the reference monitor is identically equal to the faulted signal.

The function of the faulted signal is fourfold.

• Any time faulted = 1, then valid = 0, regardless of the state

of any other control signal. Therefore, faulted = 1 indicates an invalid reference.

• Any time the faulted signal transitions from 0 to 1 (that is,

from nonfaulted to faulted), the validation timer is momentarily reset, which means that, once it is enabled, it must exhaust its full counting sequence before it expires.

• When faulted = 0 (that is, the reference is not faulted), the

validation timer is allowed to perform its timing sequence. When faulted = 1 (that is, the reference is faulted), the validation timer is reset and halted.

• The faulted signal passes through an inverter, converting it

to a nonfaulted signal, which appears at the input of the valid latch. This allows the valid latch to capture the state of the nonfaulted signal when the validation timer expires.

The ref monitor bypass control bit enables bypassing of the ref fault signal generated by the reference monitor. When ref monitor bypass = 1, the state of the faulted signal is dictated by the ref monitor override control bit. This is useful when the user relies on an external reference monitor rather than the internal monitor resident in the device. The user programs the ref monitor override bit based on the status of the external monitor. On the other hand, when ref monitor bypass = 0, the ref monitor override control bit allows the user to manually test the operation of both the valid latch and the validation timer. In this case, the user relies on the signal generated by the internal reference monitor (ref fault) but uses the ref monitor override bit to emulate a faulted reference. That is, when ref monitor override = 1, then faulted = 1, but when ref monitor override = 0, then faulted = ref fault.

In addition, the user has the ability to emulate a timeout of the validation timer via the appropriate force validation timeout control bit in Register 0A0E. Writing a Logic 1 to any of these

Rev. B | Page 28 of 112

VALIDATION TIMER

TIMEOUT

VALID

08022-010

autoclearing bits triggers the valid latch, which is identically equivalent to a timeout of the validation timer.

REFERENCE PROFILES

The AD9548 has eight independent profile registers. A profile register contains 50 bytes that establish a particular set of device parameters. Each of the eight input references can be assigned to any one of the eight profiles (that is, more than one reference can be assigned to the same profile). The profiles allow the user to prescribe the specific device functionality that should take effect when one of the input references (assigned to the profile) becomes the active reference. Each profile register has the same format and stores the following device parameters:

• Reference priority

• Reference period value (in femtoseconds)

• Inner tolerance value (1/tolerance)

• Outer tolerance value (1/tolerance)

• Validation timer value (milliseconds)

• Redetect timer value (milliseconds)

• Digital loop filter coefficients

• Reference prescaler setting (R-divider)

• Feedback divider settings (S, U, and V)

• DPLL phase lock detector threshold level

• DPLL phase lock detector fill rate

• DPLL phase lock detector drain rate

• DPLL frequency lock detector threshold level

• DPLL frequency lock detector fill rate

• DPLL frequency lock detector drain rate

Reference-to-Profile Assignment Control

The user can manually assign a reference to a profile or let the device make the assignment automatically. The manual reference profile selection register (Address 0503 to Address 0506) is where the user programs whether a reference-to-profile assignment is manual or automatic. The manual reference profile selection register is a 4-byte register partitioned into eight half bytes (or nibbles). The eight nibbles form a one-to-one correspondence with the eight reference inputs: one nibble for REF A, the next for REF AA, and so on. For a reference configured as a differential input, however, the device ignores the nibble associated with the two-letter input. For example, if the B reference is differential, then only the REFB nibble matters (the device ignores the REFBB nibble).

Page 29

AD9548

The MSB of each nibble is the manual profile bit, whereas the three LSBs of each nibble identify one of the eight profiles (0 to

7). A Logic 1 for the manual profile bit assigns the associated reference to the profile identified by the three LSBs of the nibble. A Logic 0 for the manual profile bit configures the associated reference for automatic reference-to-profile assignment (the three LSBs are ignored in this case). Note that references configured for automatic reference-to-profile assignment require activation (see the Reference-to-Profile Assignment State Machine section).

Reference-to-Profile Assignment State Machine

The functional flexibility of the AD9548 resides in the way that it assigns a particular input reference to one of the eight reference profiles. The reference-to-profile assignment state machine effectively builds a reference-to-profile table that maps the index of each input reference to a profile (see Table 2 2).

Each entry in the profile column consists of a profile number (0 to 7) or a null value. A null value appears when a referenceto-profile assignment does not exist for a particular reference input (following a reset, for example). The information in Tabl e 22 appears in the register map (Register 0D0C to Register 0D13) so that the user has access to the reference-to-profile assignments on a real-time basis. Register 0D0C contains the information for REF A, Register 0D0D contains the information for REF AA, and so on to Register 0D13 for REF DD. Bit 7 of each register is the null indicator for that particular reference. If Bit 7 = 0, then the profile assignment for that particular reference is null. If Bit 7 = 1, then that particular reference is assigned to the profile (0 to 7) identified by Bits[6:4]. Note that Bits[6:4] are meaningless unless Bit 7 = 1.

Table 22. Reference-to-Profile Table

Reference Input

A 0 Profile number (or null value) AA 1 Profile number (or null value) B 2 Profile number (or null value) BB 3 Profile number (or null value) C 4 Profile number (or null value) CC 5 Profile number (or null value) D 6 Profile number (or null value) DD 7 Profile number (or null value)

Reference Index

Profile

Following a reset, the reference-to-profile assignment state machine is inactive to avoid improperly assigning a reference to a profile before the system clock stabilizes. The reason is that the state machine relies on accurate information from the reference monitors, which, in turn, rely on a stable system clock. Because the reference-to-profile assignment state machine is inactive at power-up, the user must initiate it manually by writing to the reference profile detect register (Address 0A0D). The state machine activates immediately, unless the system clock is not stabilized, in which case, activation occurs upon

expiration of the system clock stability timer. Note that initialization of the state machine is on a per-reference basis. That is, each reference input is associated with an independent initialization control bit.

Once initialized for processing a reference, the state machine continuously monitors that reference until the occurrence of a device reset. This is true even when the user programs a reference for manual profile selection, in which case, the state machine associated with that particular reference operates with its activity masked. The masked background activity allows for seamless operation if the user subsequently reprograms the reference for automatic profile selection.

Reference-to-Profile Assignment

When a reference is programmed for manual profile assignment (see Register 0503 to Register 0506), the reference-to-profile assignment state machine simply puts the programmed manual profile number into the profile column of the reference-toprofile table (see Tab l e 2 2 ) in the row associated with the appropriate reference. However, when the user programs a reference for automatic profile assignment, the state machine must figure out which profile to assign to the reference.

As long as a null entry appears in the reference-to-profile table for a particular input reference, the validation logic for that reference enters a period estimation mode. Note that a null entry is the default state following a reset, but it also occurs when a reference redetect timer expires. The period estimation mode enables the validation logic to make a blind estimate of the period of the input reference with a tolerance of 0.1%. The validation logic remains in the period estimation mode until it successfully estimates the reference period.

Upon a successful reference period measurement by the validation logic, the state machine compares the measured period to the nominal reference period programmed into each of the eight profiles. The state machine assigns the reference to the profile with the closest match to the measured period. If more than one profile exactly matches the reference period, then the state machine chooses the profile with the lowest numeric index. For example, if the reference period in both Profile 3 and Profile 5 matches the measured period, then Profile 3 is given the assignment.

To safeguard against making a poor reference-to-profile assignment, the state machine ensures that the measured reference period is within 6.25% of the nominal reference period that appears in the closest match profile. Otherwise, the state machine does not make a profile assignment and leaves the null entry in the reference-to-profile table.

As long as there are input references programmed for automatic profile assignment, and for which the profile assignment is null, the state machine continues to cycle through those references searching for a profile match. Furthermore, unless an input reference is assigned to a profile, it is considered invalid and excluded as a candidate for a reference switchover.

Rev. B | Page 29 of 112

Page 30

AD9548

REFERENCE SWITCHOVER

An attractive feature of the AD9548 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm coupled with register-based controls. This scheme provides the user with maximum control over the state machine that handles reference switchover.

The main reference switchover control resides in the loop mode register (Address 0A01). The user selection mode bits (Register 0A01, Bits[4:3]) allow the user to select one of the reference switchover state machine’s four operating modes, as follows:

• Automatic mode (Address A01, Bits[4:3] = 00)

• Fallback mode (Address 0A01, Bits[4:3] = 01)

• Holdover mode (Address 0A01, Bits[4:3] = 10)

• Manual mode (Address 0A01, Bits[4:3] = 11)

In automatic mode, a fully automatic priority-based algorithm selects which reference is the active reference. When programmed for automatic mode, the device ignores the user selection reference bits (Register 0A01, Bits[2:0]). However, when programmed for any of the other three modes, the device makes use of the user reference bits. These bits specify a particular input reference (000 = REF A, 001 = REF AA ..., 111 = REF DD).

In fallback mode, the user reference is the active reference whenever it is valid. Otherwise, the device switches to a new reference using the automatic, priority-based algorithm.

In holdover mode, the user reference is the active reference whenever it is valid. Otherwise, the device switches to holdover mode.

In manual mode, the user reference is the active reference whether it is valid or not. Note that, when using this mode, the user must program the reference-to-profile assignment (see register 0503 to Register 0506) as manual for the particular reference declared as the user reference. The reason is that if the user reference fails and its redetect timer expires, then its profile assignment (shown in the active reference (user reference) does not have an assigned profile, which places the AD9548 into an undefined state.

The user also has the option to force the device directly into holdover or free-run operation via the user holdover and user free-run bits (Register 0A01, Bit 6 and Bit 5, respectively]). In free-run mode, the free running frequency tuning word register (Address 0300 to Address 0305) defines the DDS output frequency. In holdover mode, the DDS output frequency depends on the holdover control settings (see the Holdover section).

Automatic Priority-Based Reference Switchover

The AD9548 has a two-tiered, automatic, priority-based algorithm that is in effect for both automatic and fallback

Tabl e 22 ) becomes null. This means that

reference switchover. The algorithm relies on the fact that each reference profile contains both a selection priority and a promoted priority. The selection and promoted priority values range from 0 (highest priority) to 7 (lowest priority). The selection priority determines the order in which references are chosen as the active reference. The promoted priority is a separate priority value given to a reference only after it becomes the active reference.

An automatic reference switchover occurs on failure of the active reference or when a previously failed reference becomes valid and its selection priority is higher than the promoted priority of the currently active reference (assuming that the automatic or fallback reference switchover is in effect). When performing an automatic reference switchover, the AD9548 chooses a reference based on the priority settings within the profiles. That is, the device switches to the reference with the highest selection priority (lowest numeric priority value). It does so by using the reference-to-profile table (see Table 22) to determine the reference associated with the profile exhibiting the highest priority.

If multiple references share the same profile, then the device chooses the reference having the lowest index value. For example, if the A, B, and CC references (Index 0, Index 2, and Index 5, respectively) share the same profile, then a switchover to Reference A occurs because Reference A has the lowest index value. Note, however, that only valid references are included in switchover of the selection process. The switchover control logic ignores any reference with a status indication of invalid.

The promoted priority parameter allows the user to assign a higher priority to a reference after it becomes the active reference. For example, suppose four references have a selection priority of 3 and a promoted priority of 1, and the remaining references have a selection priority or 2 and a promoted priority of 2. Now, assume that one of the Priority 3 references becomes active because all of the Priority 2 references have failed. Someti me later, however, a Priority 2 reference becomes valid. T he switchover logic normally attempts to automatically switch over to the Priority 2 reference because it has higher priority than the presently active Priority 3 reference. However, because the Priority 3 reference is active, its promoted priority of 1 is in effect. This is a higher priority than the newly validated reference’s priority of 2, so the switchover does not occur. This mechanism enables the user to give references preferential treatment while they are selected as the active reference. An example of promoted vs. nonpromoted priority switching appears in state diagram form in block diagram of the interrelationship between the reference inputs, monitors, validation logic, profile selection, and priority selection functionality.

Figure 35. Figure 36 shows a

Rev. B | Page 30 of 112

Page 31

AD9548

INITIAL STATE

PRIORITY TABLE

INPUT PRIORIT Y PROMOTED

A0 0

B1 0

C2 1

D3 2

COMMON WITHOUT PROMOTION WITH PROMOTION

Figure 35. Example of Priority Promotion

A/AA

B/BB

C/CC

D/DD

PROFILE

SELECTION

………

…

VALIDATION

LOGIC

Figure 36. Reference Clock Block Diagram

Phase Build-Out Reference Switching

Phase build-out reference switching is the term given to a reference switchover that completely masks any phase difference between the previous reference and the new reference. That is, there is virtually no phase change detectable at the output when a phase build-out switchover occurs.

The AD9548 handles phase build-out switching based on whether the new reference is a phase master. A phase master is any reference with a selection priority value that is less than the phase master threshold priority value (that is, higher priority). The phase master threshold priority value resides in the phase build-out switching register (Address 0507), whereas the selection priority resides in the profile registers (Address 0600 to Address 07FF). By default, the phase master threshold priority is 0; therefore, no references can be phase masters until the user changes the phase master threshold priority.

Whenever the AD9548 switches from one reference to another, it compares the selection priority value stored in the profile assigned to the new reference with the phase master threshold priority. The AD9548 performs a phase build-out switchover only if the new reference is not a phase master.

Hitless Reference Switching (Phase Slew Control)

Hitless reference switching is the term given to a reference switchover that limits the rate of change of the phase of the output clock while the PLL is in the process of acquiring phase lock. This prevents the output frequency offset from becoming excessive.

Rev. B | Page 31 of 112

ALL VALID

A VALID

B VALID

ACTIVE

A FAULTED

ACTIVE

B FAULTED

ACTIVE

PRIORITY

SELECTION

A VALID

B VALID

CONTROLL ER

……

LOOP

08022-011

÷RMONITORS

TDC

08022-012

The all-digital nature of the DPLL core (see the Digital PLL (DPLL) Core section) gives the user numerical control of the rate at which phase changes occur at the DPLL output. When enabled, a phase slew controller monitors the phase difference between the feedback and reference inputs to the DPLL. The phase slew controller has the ability to place a user-specified limit on the rate of change of phase, thus providing a mechanism for hitless reference switching.

The user sets a limit on the rate of change of phase by storing the appropriate value in the 16-bit phase slew rate limit register (Address 0316 to Address 0317). The 16-bit word (representing ns/sec) puts an upper bound on the rate of change of the phase at the output of the DPLL during a reference switchover. A phase slew rate value of 0 (default) disables the phase slew controller.

The accuracy of the phase slew controller depends on both the phase slew limit value and the system clock frequency. Generally, an increase in the phase slew rate limit value or a decrease in the system clock frequency tends to reduce the error. As such, the accuracy is best for the largest phase slew limit value and the lowest system clock frequency. For example, assuming the use of a 1 GHz system clock, a phase slew limit value of 315 ns/sec (or more) ensures an error of less than 10%, whereas a phase slew rate limit value above ~3100 ns/sec ensures an error of less than 1%. On the other hand, assuming the use of a 500 MHz system clock, the same phase slew rate limit values ensure an error of less than 5% or 0.5%, respectively.

Page 32

AD9548

DIGITAL PLL (DPLL) CORE

DPLL Overview

A diagram of the digital PLL core of the AD9548 appears in Figure 37. The phase/frequency detector, feedback path, lock detectors, phase offset, and phase slew rate limiting that comprise this second generation DPLL are all digital implementations.

LOCK

DETECT

PHASE SLEW

REF A

REF DD

LIMIT

TDC

R+1

TDC

AND

PFD

Figure 37. Digital PLL Core

The start of the DPLL signal chain is the reference signal, fR, which is the frequency of the reference input. A reference prescaler reduces the frequency of this signal by an integer factor, R + 1, where R is the 30-bit value stored in the appropriate profile register and 0 ≤ R ≤ 1,073,741,823. Therefore, the frequency at the output of the R-divider (or the input to TDC) is

TDC

1+=R

A time-to-digital converter (TDC) samples the output of the R-divider. The TDC/PFD produces a time series of digital words and delivers them to the digital loop filter. The digital loop filter offers the following advantages:

Determination of the filter response by numeric

•

coefficients rather than by discrete component values

•

The absence of analog components (R/L/C), which

eliminates tolerance variations due to aging

•

The absence of thermal noise associated with analog

components

•

The absence of control node leakage current associated

with analog components (a source of reference feedthrough spurs in the output spectrum of a traditional analog PLL)

The digital loop filter produces a time series of digital words at its output and delivers them to the frequency tuning input of a DDS, with the DDS replacing the function of the VCO in an analog PLL. The digital words from the loop filter tend to steer the DDS frequency toward frequency and phase lock with the input signal (f

). The DDS provides an analog output signal

TDC

via an integrated DAC, effectively mimicking the operation of an analog VCO.

CLOSED-LOOP

PHASE OFFSET

DIGITAL

LOOP

FILTER

S + 1 + U/V

DPPL CORE

DDS/

DAC

DDS

DACOUT

The DPLL includes a feedback divider that causes the DDS to operate at an integer-plus-fractional multiple (S + 1 + U/V) of f

. S is the 30-bit value stored in the profile register and has

TDC

a range of 7 ≤ S ≤ 1,073,741,823. U and V are the 10-bit numerator and denominator values of the optional fractional divide component and are also stored in the profile register. Together they establish the nominal DDS frequency (f

DDS

⎜

⎝

⎛

⎞

⎟

⎠

), given by

DDS

Normally, fractional-N designs exhibit distinctive phase noise and spurious artifacts resulting from the modulation of the integer divider based on the fractional value. Such is not the case for the AD9548 because it uses a purely digital means to determine phase errors. Because the phase errors incurred by

08022-013

modulating the feedback divider are deterministic, it is possible to compensate for them digitally. The result is a fractional-N PLL with no discernable modulation artifacts.

TDC/PFD

The TDC is a highly integrated functional block that incorporates both analog and digital circuitry. There are two pins associated with the TDC that the user must connect to external components. Figure 38 shows the recommended component values and their connections.

For best performance, place components as close as possible to the device pins. Components with low effective series resistance (ESR) and low parasitic inductance yield the best results.

AD9548

10µF

TDC_VRTTDC_VRB

0.1µF

08022-014

0.1µF

Figure 38. TDC Pin Connections

The phase-frequency detector (PFD) is an all-digital block. It compares the digital output from the TDC (which relates to the active reference edge) with the digital word from the feedback block (which relates to the rollover edge of the DDS accumulator after division by the feedback divider). It uses a digital code pump and digital integrator (rather than a conventional charge pump and capacitor) to generate the error signal that steers the DDS frequency toward phase lock.

Closed-Loop Phase Offset

The all-digital nature of the TDC/PFD provides for numerical control of the phase offset between the reference and feedback edges. This allows the user to adjust the relative timing of the distribution output edges relative to the reference input edges by programming the 40-bit fixed phase lock offset register

Rev. B | Page 32 of 112

Page 33

AD9548

(Address 030F to Address 0313). The 40-bit word is a signed (twos complement) number that represents units of picoseconds.

In addition, the user can adjust the closed-loop phase offset (positive or negative) in incremental fashion. To do so, program the desired step size in the 16-bit incremental phase lock offset step size register (Address 0314 to Address 0315). This is an unsigned number that represents units of picoseconds. The programmed step size is added to the current closed-loop phase offset each time the user writes a Logic 1 to the increment phase offset bit (Register 0A0C, Bit 0). Conversely, the programmed step size is subtracted from the current closed-loop phase offset each time the user writes a Logic 1 to the decrement phase offset bit (Register 0A0C, Bit 1). The serial I/O port control logic clears both of these bits automatically. The user can remove the incrementally accumulated phase by writing a Logic 1 to the reset incremental phase offset bit (Register 0A0C, Bit 2), which is also cleared automatically. Alternatively, rather than using the serial I/O port, the multifunction pins can be set up to perform the increment, decrement, and clear functions.

Note that the incremental phase offset is completely independent of the offset programmed into the fixed phase lock offset register. However, if the phase slew limiter is active (see the Hitless Reference Switching (Phase Slew Control) section), then any instantaneous change in closed-loop phase offset (fixed or incremental) will be subject to possible slew limitation by the action of the phase slew limiter.

Programmable Digital Loop Filter

The AD9548 loop filter is a third order digital IIR filter that is analogous to the third order analog loop shown in Figure 39.

Figure 39. Third Order Analog Loop Filter

08022-015

The filter requires four coefficients as shown in Figure 40. The AD9548 evaluation board software automatically generates the required loop filter coefficient values based on the user’s design criteria. The Calculating Digital Filter Coefficients section contains the design equations for calculating the loop filter coefficients manually.

FRACTIONAL

(16-BIT)

1/2

(6-BIT)

(3-BIT)

(4-BIT)

IN OUT

FRACTIO NAL

(17-BIT)

Figure 40. Third Order Digital IIR Loop Filter

1/2

(6-BIT)

(THIRD ORDE R IIR)

LOOP FILTER

FRACTIO NAL (17-BIT)

1/2 (6-BIT)

FRACTIO NAL (15-BIT)

1/2 (5-BIT)

4851

Each coefficient has a fractional component representing a value from 0 up to, but not including, unity. Each coefficient

08022-016

also has an exponential component representing a power of 2 with a negative exponent. That is, the user enters a positive number (x) that the hardware interprets as a negative exponent

−x

of two (2

). Thus, the β, γ, and δ coefficients always represent

values less than unity. The α coefficient, however, has two additional exponential components, but the hardware interprets

these as a positive exponent of 2 (that is, 2

). This allows the α

coefficient to be a value greater than unity. The positive exponent appears as two separate terms in order to provide sufficient dynamic range.

DPLL Phase Lock Detector

The DPLL contains an all-digital phase lock detector. The user controls the threshold sensitivity and hysteresis of the phase detector via the profile registers.

The phase lock detector behaves in a manner analogous to water in a tub (see Figure 41). The total capacity of the tub is 4096 units with −2048 denoting empty, 0 denoting the 50% point, and +2048 denoting full. The tub also has a safeguard to prevent overflow. Furthermore, the tub has a low water mark at

−1024 and a high water mark at +1024. To change the water level, the user adds water with a fill bucket or removes water with a drain bucket. The user specifies the size of the fill and drain buckets via the 8-bit fill rate and drain rate values in the profile registers.

The water level in the tub is what the lock detector uses to determine the lock and unlock conditions. Whenever the water level is below the low water mark (−1024), the detector indicates an unlock condition. Conversely, whenever the water level is above the high water mark (+1024), the detector indicates a lock condition. While the water level is between the marks, the detector simply holds its last condition. This concept appears graphically in Figure 41, with an overlay of an example of the instantaneous water level (vertical) vs. time (horizontal) and the resulting lock/unlock states.

During any given PFD phase error sample, the detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). The decision of whether to add or remove water depends on the threshold level specified by the user. The phase lock threshold value is a 16-bit number stored in the profile registers and is expressed in picoseconds. Thus, the phase lock threshold extends from 0 ns to ±65.535 ns and represents the magnitude of the phase error at the output of the PFD.

The phase lock detector compares each phase error sample at the output of the PFD to the programmed phase threshold value. If the absolute value of the phase error sample is less than or equal to the programmed phase threshold value, then the detector control logic dumps one fill bucket into the tub. Otherwise, it removes one drain bucket from the tub. Notice that it is not the polarity of the phase error sample, but its magnitude relative to the phase threshold value, that determines whether to fill or drain. If more filling is taking place than

Rev. B | Page 33 of 112

Page 34

AD9548

draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the phase lock detector to indicate lock. If more draining is taking place than filling, then the water level in the tub eventually falls below the low water mark (−1024), which causes the phase lock detector to indicate unlock. The ability to specify the threshold level, fill rate, and drain rate enables the user to tailor the operation of the phase lock detector to the statistics of the timing jitter associated with the input reference signal.

STATE

2048

1024

–1024

–2048

Figure 41. Lock Detector Diagram

Note that whenever the AD9548 enters the free-run or holdover mode, the DPLL phase lock detector indicates unlocked. In addition, whenever the AD9548 performs a reference switchover, the state of the lock detector prior to the switch is preserved during the transition period.

DPLL Frequency Lock Detector

The operation of the frequency lock detector is identical to that of the phase lock detector. The only difference is that the fill or drain decision is based on the period deviation between the reference and feedback signals of the DPLL instead of the phase error at the output of the PFD.

The frequency lock detector uses a 24-bit frequency threshold register specified in units of picoseconds. Thus, the frequency threshold value extends from 0 s to ±16.777215 s. It represents the magnitude of the difference in period between the reference and feedback signals at the input to the DPLL. For example, if the reference signal is 1.25 MHz and the feedback signal is 1.38 MHz, then the period difference is approximately 75.36 ns (|1/1,250,000 − 1/1,380,000| ≈ 75.36 ns).

LOCKED UNLO CKED

FILL

DRAIN

RATE

FREQUENCY

UNING WORD

(FTW)

LOCK LEVEL

UNLOCK LEVEL

48-BIT ACCUMULAT O

4848

OFFSET

08022-017

PHASE

DIRECT DIGITAL SYNTHESIZER

DDS Overview

One of the primary building blocks of the digital PLL is a direct digital synthesizer (DDS). The DDS behaves like a sinusoidal signal generator. The frequency of the sinusoid generated by the DDS is determined by a frequency tuning word (FTW), which is a digital (that is, numeric) value. Unlike an analog sinusoidal generator, a DDS uses digital building blocks and operates as a sampled system. Thus, it requires a sampling clock (f serves as the fundamental timing source of the DDS. The

accumulator behaves as a modulo-2

counter with a programmable step size (FTW). A block diagram of the DDS appears in Figure 42.

The input to the DDS is the 48-bit FTW. The FTW serves as a step size value. On each cycle of f

, the accumulator adds the

value of the FTW to the running total at its output. For example, given FTW = 5, the accumulator counts by fives, incrementing on each f reaches the upper end of its capacity (2

cycle. Over time, the accumulator

in this case), at which point, it rolls over but retains the excess. The average rate at which the accumulator rolls over establishes the frequency of the output sinusoid. The average rollover rate of the accumulator establishes the output frequency (f

FTW

⎞

⎛

⎜ ⎝

⎟

SDDS

⎠

) of the DDS and is given by

DDS

Solving this equation for FTW yields

⎡

FTW

2round

⎢ ⎢

⎣

For example, given that f

⎤

⎛

⎞

DDS

⎜

⎟

⎥

⎜

⎟

⎥

⎝

⎠

⎦

= 1 GHz and f

= 155.52 MHz, then

DDS

FTW = 43,774,988,378,041 (0x27D028A1DFB9).

Note that the minimum DAC output frequency is 62.5 MHz; therefore, normal operation requires an FTW that yields an output frequency in excess of this lower bound.

ANGLE TO

AMPLI TUDE

CONVERSION

1419

DAC

(14-BIT)

DAC+

DAC–

) that

Figure 42. DDS Block Diagram

8022-018

Rev. B | Page 34 of 112

Page 35

AD9548

DDS Phase Offset

The relative phase of the sinusoid generated by the DDS is numerically controlled by adding a phase offset word to the output of the DDS accumulator. This is accomplished via the open loop phase offset register (Address 030D to Address 030E), which is a programmable 16-bit value (phase). The resulting phase offset, Φ (in radians), is given by

phase

⎛

=Δ

2Φ

⎜ ⎝

⎞ ⎟

⎠

Phase offset and relative time offset are directly related. The time offset is (Δphase/2

)/f

(in seconds), where f

DDS

is the

output frequency of the DDS (in hertz).

DAC Output

The output of the digital core of the DDS is a time series of numbers representing a sinusoidal waveform. The DAC translates the numeric values to an analog signal. The DAC output signal appears at two pins that constitute a balanced current source architecture (see Figure 43).

AVDD3

CURRENT

SCALE

CODE

IFS ( )

– 1

DACOUTP DACOUTN

GND

MIRROR

CURRENT

SWITCH ARRAY

SWITCH

CONTROL

CODE

Figure 43. DAC Output Pins

50Ω50Ω

GND

CODE

IFS (1– )

– 1

08022-019

The value of IFS is programmable via the 10-bit DAC full-scale current word in the DAC current register (Address 0213 to Address 0214). The value of the 10-bit word (I

SCALE

) sets IFS

according to the following formula:

I +×=

72μA120

()()

SCALE

TUNING WORD PROCESSING

The frequency tuning words that dictate the output frequency of the DDS come from one of three sources (see Figure 44).

•

The free running frequency tuning word register

•

The output of the digital loop filter

•

The output of the tuning word history processor

TUNING WO RD

HISTORY

FREE-RUN

TUNING WO RD

TUNING WORD

UPDATE

FROM DIGITAL

LOOP FILTER

TUNING

WORD

ROUTING

CONTROL

Figure 44. Tuning Word Processing

When the DPLL is in free-run mode, the DDS tuning word is the value stored in the free running frequency tuning word register (Address 0300 to Address 0305). When the DPLL is operating normally (closed loop), the DDS tuning word comes from the output of the digital loop filter, which changes dynamically in order to maintain phase lock with the input reference signal (assuming that the device has not performed an automatic switch to holdover mode). When the DPLL is in holdover mode, the DDS tuning word depends on a historical record of past tuning words during the time that the DPLL operated in closed-loop mode.

However, regardless of the operating mode, the DDS output frequency is ultimately subject to the boundary conditions imposed by the frequency clamp logic, as explained in the Frequency Clamp section.

Frequency Clamp

The user controls the frequency clamp boundaries via the pullin range limits registers (Address 0307 to Address 030C). These registers allow the user to fix the DDS output frequency between an upper and lower bound with a granularity of 24 bits. Note that these upper and lower bounds apply regardless of the frequency tuning word that appears at the input to the DDS. The register value relates to the absolute upper or lower frequency bound (f

= fS × (N/224)

CLAMP

) as

Where N is the value stored in the upper- or lower-limit register, and f

is the system sample rate.

Even though the frequency clamp limits put a bound on the DDS output frequency, the DPLL is still free to steer the DDS frequency within the clamp limits. The default register values set the clamp range from 0 Hz (dc) to f the frequency clamp functionality until the user alters the register values.

Frequency Tuning Word History

The AD9548 has the ability to track the history of the tuning word samples generated by the DPLL digital loop filter output. It does so by periodically computing the average tuning word value over a user-specified interval. The user programs the interval via the 24-bit history accumulation timer register (Address 0318 to Address 031A). This 24-bit value represents a time interval (T

) in milliseconds that extends from 1 ms to

AVG

a maximum of 4:39:37.215 (hr:min:sec).

TUNING WO RD

HISTORY

PROCESSOR

TUNING

WORD

CLAMP

LOWER TUNING

WORD

UPPER

TUNING

WORD

, effectively eliminating

TO DDS

08022-070

Rev. B | Page 35 of 112

Page 36

AD9548

Note that history accumulation timer = 0 should not be programmed because it may cause improper device operation.

The control logic performs a calculation of the average tuning word during the T holdover history register (Address 0D14 to Address 0D19). Computation of the average for each T independent of the previous interval (that is, the average is a memoryless average as opposed to a true moving average). In addition, at the end of each T an internal strobe pulse. The strobe pulse sets the history updated bit in the IRQ monitor register (assuming the bit is enabled via the IRQ mask register). Furthermore, the strobe pulse is available as an output signal via the multifunction pins (see the Multifunction Pins (M0 to M7) section).

History accumulation begins whenever the device switches to a new reference. By default, the device clears any previous history when it switches to a new reference. Furthermore, the user can clear the tuning word history under software control via Register 0A03, Bit 2, or under hardware control via the multifunction pins (see the Multifunction Pins (M0 to M7) section). However, the user has the option of programming the device to retain (rather than clear) the old history by setting the persistent history bit (Register 031B, Bit 3).

Whenever the tuning word history is nonexistent (that is, after a power-up, reset, or switchover to a new reference with the persistent history bit cleared), the device waits for the history accumulation timer (T history value in the holdover history register.

In cases where T problem arises in that the first averaged result does not become available until the full T that as much as 4½ hours can elapse before the first averaged result is available. If the device has to switch to holdover mode during this time, a tuning word history is not available.

To alleviate this problem, the user has access to the incremental average bits in the history mode register (Register 031B, Bits[2:0]). If the history has been cleared, then this 3-bit value, K (0 ≤ K ≤ 7), specifies the number of intermediate averages to take during the first, and only the first, T K = 0, no intermediate averages are calculated; therefore, the first average occurs after interval T mode). However, if K = 4, for example, four intermediate averages are taken during the first T

These average computations occur at T

/2, and T

AVG

sequence of powers of 2 beginning with T lation of intermediate averages occurs only during the first

interval. All subsequent average computations occur at

AVG

evenly spaced intervals of T

interval and stores the result in the

AVG

interval is

AVG

interval, the device generates

AVG

) to expire before storing the first

AVG

is quite large (4½ hours, for example), a

AVG

interval passes. Thus, it is possible

AVG

interval. When

AVG

(the default operating

AVG

interval.

AVG

/16, T

AVG

/8, T

(notice that the denominator exhibits a

/2K). The calcu-

AVG

/4,

LOOP CONTROL STATE MACHINE

The loop control state machine is responsible for monitoring, initiating, and sequencing changes to the DPLL loop. Generally, it automatically controls the transition between input references and the entry and exit of holdover mode. In controlling loop state changes, the state machine also arbitrates the application of new loop filter coefficients, divider settings, and phase detector offsets based on the profile settings. The user can manually force the device into holdover or free-run mode via the loop mode register (Address 0A01), as well as force the selection of a specific input reference.

Switchover

Switchover occurs when the loop controller switches directly from one input reference to another. Functionally, the AD9548 handles a reference switchover by briefly entering holdover mode and then immediately recovering. During the switchover event, however, the AD9548 preserves the status of the lock detectors to avoid phantom unlock indications.

Holdover

The holdover state of the DPLL is an open-loop operating mode. That is, the device no longer operates as a closed-loop system. Instead, the output frequency remains constant and is dependent on the device programming and availability of tuning word history.

If a tuning word history exists (see the Frequency Tuning Word History section), then the holdover frequency is the average frequency just prior to entering the holdover state. If there is no tuning word history, then the holdover frequency depends on the state of the single sample fallback bit in the history mode register (Register 031B, Bit 4). If the single sample fallback bit is Logic 0, then the holdover frequency is the frequency defined in the free running frequency tuning word register (Address 0300 to Address 0305). If the single sample fallback bit is Logic 1, then the holdover frequency is the last instantaneous frequency output by the DDS just prior to the device entering holdover mode (note that this is not the average frequency prior to holdover).

The initial holdover frequency accuracy depends on the loop bandwidth of the DPLL and the time elapsed to compute a tuning word history. The longer the historical average, the more accurate the initial holdover frequency (assuming a drift-free system clock). Furthermore, the stability of the system clock establishes the stability and long-term accuracy of the holdover output frequency. Another consideration is the 48-bit frequency tuning resolution of the DDS and its relationship to fractional frequency error,

, as follows:

∆f

O/fO

where, f output frequency.

is the sample rate of the output DAC, and fO is the DDS

Rev. B | Page 36 of 112

Page 37

AD9548

The worst-case scenario is maximum f (62.5 MHz), which yields ∆f

O/fO

(1 GHz) and minimum fO

= 2.8 × 10

−14

, less than one part

in 10 trillion.

Recovery from Holdover

When in holdover and a valid reference becomes available, the device exits holdover operation. The loop state machine restores the DPLL to closed-loop operation, locks to the selected reference, and sequences the recovery of all the loop parameters based on the profile settings for the active reference.

Note that, if the user holdover bit (Register 0A01, Bit 6) is set, the device does not automatically exit holdover when a valid reference is available. However, automatic recovery can occur after clearing the user holdover bit.

SYSTEM CLOCK INPUTS

Functional Description

The system clock circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. The user has the option of directly driving the SYSCLKx inputs with a high frequency clock source at the desired system clock rate. Alternatively, the SYSCLKx input can be configured to operate in conjunction with the internal SYSCLK PLL. The SYSCLK PLL can synthesize the system clock by means of a crystal resonator connected across the SYSCLKx input pins or by means of direct application of a low frequency clock source.

The SYSCLKx inputs are internally biased to a dc level of ~1 V. Take care to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. Generally, the recommendation is that the SYSCLKx inputs be ac-coupled to the signal source (except when using a crystal resonator).

Low Loop Bandwidth Applications Using a TCXO/OCXO

For many applications, the use of a crystal oscillator is a costeffective and simple choice. The stability is good enough to support loop bandwidths down to 50 Hz, and the holdover performance is good enough for all except the most demanding applications.

In cases where Stratum 2 or Stratum 3 holdover performance is needed, or in cases where the loop bandwidth must be <50 Hz, the user must use either a TCXO or OCXO. The user should choose a TCXO/OCXO with a high output frequency and CMOS output to achieve the best performance.

When interfacing the TCXO/OCXO, a voltage divider on the output should be used to reduce the voltage swing to 1 V p-p, and that signal should be ac-coupled to the SYSCLKP pin. The SYSCLKN pin can be bypassed to ground with a 0.01 µF capacitor.

Choosing the System Clock Oscillator Frequency

The best performance of the AD9548 is achieved when the system clock is not an integer multiple of the DDS output frequency.

As an example, using a 19.44 MHz oscillator for the system clock in a 156.25 MHz Ethernet application yields better performance than a 25 MHz oscillator.

Another good system clock choice for many communications applications is a 49.152 MHz crystal used in IEEE 1394 (FireWire) because nearly all output frequencies are not integer related to this frequency, and the crystal is readily available.

System Clock Details

A block diagram of the system clock appears in Figure 45. The signal at the SYSCLKx input pins becomes the internally buffered DAC sampling clock (f

High frequency direct (HF)

•

Low frequency synthesized (LF)

•

Crystal resonator synthesized (XTAL)

) via one of three paths.

Note that both the LF and XTAL paths require the use of the SYSCLK PLL (see the SYSCLK PLL Multiplier section).

The main purpose of the HF path is to allow the direct use of a high frequency (500 MHz to 1 GHz) external clock source for clocking the AD9548. This path is optimized for high frequency and low noise floor. Note that the HF input also provides a path to SYSCLK PLL (see the SYSCLK PLL Multiplier section), which includes an input divider (M) programmable for divide-by -1, -2, -4, or -8. The purpose of the divider is to limit the frequency at the input to the PLL to less than 150 MHz (the maximum PFD rate).

SYSCLK_VREG SYSCLK_LF

XTAL

SYSCLKP

SYSCLKN

2×

÷M

Figure 45. System Clock Block Diagram

Rev. B | Page 37 of 112

LOCK

DETECT

PFD

AND

CHARGE

PUMP

LOOP

FILTER

÷N

VCO

CALIBRATI ON

SYSTEM CLOCK

08022-020

Page 38

AD9548

The LF path permits the user to provide an LVPECL, LVDS, CMOS, or sinusoidal low frequency clock for multiplication by the integrated SYSCLK PLL. The LF path handles input frequencies from 3.5 MHz up to 100 MHz. However, when using a sinusoidal input signal, it is best to use a frequency in excess of 20 MHz. Otherwise, the resulting low slew rate can lead to substandard noise performance. Note that the LF path includes an optional 2× frequency multiplier to double the rate at the input to the SYSCLK PLL and potentially reduce the PLL in-band noise. However, to avoid exceeding the maximum PFD rate of 150 MHz, using the 2× frequency multiplier is valid only for input frequencies below 125 MHz.

The XTAL path enables the connection of a crystal resonator (typically 10 MHz to 50 MHz) across the SYSCLKx input pins. An internal amplifier provides the negative resistance required to induce oscillation. The internal amplifier expects a 3.2 mm ×

2.5 mm AT cut, fundamental mode crystal with a maximum motional resistance of 100 . The following crystals, listed in alphabetical order, may meet these criteria. Note that, whereas these crystals may meet the preceding criteria according to their data sheets, Analog Devices, Inc., does not guarantee their operation with the AD9548 nor does Analog Devices endorse one crystal manufacturer/supplier over another.

AVX/Kyocera CX3225SB

•

ECS ECX-32

•

Epson/Toyocom TSX-3225

•

Fox FX3225BS

•

NDK NX3225SA

•

Siward SX-3225

SYSCLK PLL MULTIPLIER

The SYSCLK PLL multiplier is an integer-N design and relies on an integrated LC tank and VCO. It provides a means to convert a low frequency clock input to the desired system clock frequency, f accepts input signals between 3.5 MHz and 500 MHz, but frequencies in excess of 150 MHz require the M-divider to ensure compliance with the maximum PFD rate (150 MHz). The PLL contains a feedback divider (N) that is programmable for divide values between 6 and 255. The nominal VCO gain is 70 MHz/V.

Lock Detector

The SYSCLK PLL has a built-in lock detector. Register 0100, Bit 2 determines whether the lock detector is active. When active (default), the user controls the sensitivity of the lock detector via the lock detect divider bits (Register 0100, Bits[1:0]).

(900 MHz to 1 GHz). The SYSCLK PLL multiplier

Note that 0 must be written to the system clock stability timer (Register 0106 to Register 0108) whenever the lock detector is disabled (Register 0100, Bit 2 = 1).

The SYSCLK PLL phase detector operates at the PFD rate, which is f

/N. Each PFD sample indicates whether the

VCO

reference and feedback signals are phase aligned (within a certain threshold range).

While the PLL is in the process of acquiring a lock condition, the PFD samples typically consist of an arbitrary sequence of in-phase and out-of-phase indications. As the PLL approaches complete phase lock, the number of consecutive in-phase PFD samples grows larger. Thus, one way of indicating a locked condition is to count the number of consecutive in-phase PFD samples and if it exceeds a certain value, then declare the PLL locked.

This is exactly the role of the lock detect divider bits. When the lock detector is enabled (Register 0100, Bit 2 = 0), the lock detect divider bits determine the number of consecutive in-phase decisions required (128, 256, 512, or 1024) before the lock detector declares a locked condition. The default setting is 128.

Charge Pump

The charge pump operates in either automatic or manual mode based on the charge pump mode bit (Register 0100, Bit 6).

When Register 0100, Bit 6 = 0, the AD9548 automatically selects the appropriate charge pump current based on the N-divider value. Note that the user cannot control the charge pump current bits (Register 0100, Bits[5:3]) in automatic mode. When Register 0100, Bit 6 = 1, the user determines the charge pump current via the charge pump current bits (Register 0100, Bits[5:3]). The charge pump current varies from 125 A to 1 mA in 125 A steps. The default setting is 500 A.

SYSCLK PLL Loop Filter

The AD9548 has an internal second order loop filter that establishes the loop dynamics for input signals between 12.5 MHz and 100 MHz. By default, the device uses the internal loop filter. However, an external loop filter option is available by setting the external loop filter enable bit (Register 0100, Bit 7). This bypasses the internal loop filter and allows the device to use an externally connected second order loop filter, as shown in Figure 46.

AD9548

SYSCLK_VREG

48 49

Figure 46. External Loop Filter Schematic

SYSCLK_LF

8022-021

Rev. B | Page 38 of 112

Page 39

AD9548

(

)

To determine the external loop filter components, the user decides on the desired open loop bandwidth (f

) and phase

margin (φ). These parameters allow calculation of the loop filter components, as follows:

φtan

−

()

φsin

()

φsin1

()

φcos

⎞ ⎟

⎟ ⎠

⎞ ⎟

⎟ ⎠

⎛

C1π=

where K

= 7 × 107 V/ns (typical), ICP is the programmed

VCO

⎜ ⎜

VCOCP

⎝

VCOCP

()

VCOCP

()

⎛ ⎜

⎜ ⎝

charge pump current (amperes), N is the programmed feedback divider value, f

is the desired open-loop bandwidth (in hertz),

and Φ is the desired phase margin (in radians).

For example, assuming that N = 40, I

= 0.5 mA, f

= 400 kHz,

and Φ = 50°, then the loop filter calculations yield R1 = 3.31 k, C1 = 330 pF, and C2 = 50.4 pF.

System Clock Period

Many of the user-programmable parameters of the AD9548 have absolute time units. To make this possible, the AD9548 requires a priori knowledge of the period of the system clock. To accommodate this requirement, the user programs the 21-bit nominal system clock period in the nominal SYSCLK period register (Address 0106 to Address 0108). The contents of this register reflect the actual period of the system clock in femtoseconds. The user must properly program this register to ensure proper operation of the device because many of its subsystems rely on this value.

System Clock Stability Timer

The system clock stability timer (Register 0106 to Register 0108) is a 20-bit value programmed in milliseconds. If the programmed timer value is 0, then the timer immediately indicates that it has timed out. If the programmed timer value is a nonzero value and the SYSCLK PLL is enabled, then the timer starts timing when the SYSCLK PLL lock detector indicates lock and times out after the prescribed period. However, when the user disables the SYSCLK PLL, then the timer ignores the SYSCLK PLL lock detector and starts timing as soon as the SYSCLK PLL is disabled. The user can monitor the status of the stability timer via Register 0D01, Bit 4, via the multifunction pins or via the IRQ pin.

Note that the system clock stability timer must be programmed before the SYSCLK PLL is either activated or disabled.

SYSCLK PLL Calibration

When using the SYSCLK PLL, it is necessary to calibrate the LC VCO to ensure that the PLL can remain locked to the system clock input signal. Assuming the presence of either an external SYSCLK input signal or a crystal resonator, the calibration process executes after the user sets and then clears the calibrate

system clock bit in the cal/sync register (Register 0A02, Bit 0). During the calibration process, the device calibrates the VCO amplitude and frequency. The status of the system clock calibration process is user accessible via the system clock register (Register 0D01, Bit 1). It is also available via the IRQ monitor register (Register 0D02, Bit 1) provided the status bit is enabled via the IRQ mask register.

When the calibration sequence is complete, the SYSCLK PLL eventually attains a lock condition, at which point the system clock stability timer begins its countdown sequence. Expiration of the timer indicates that the SYSCLK PLL is stable, which is reflected in the system clock register (Register 0D01, Bit 4).

Note that the monitors/detectors associated with the input references (REFA/AA – REFD/DD) are internally disabled until the SYSCLK PLL indicates that it is stable.

CLOCK DISTRIBUTION

The clock distribution block of the AD9548 provides an integrated solution for generating multiple clock outputs based on frequency dividing the DPLL output. The distribution output consists of four channels (OUT0 to OUT3). Each of the four output channels has a dedicated divider and output driver, as appears in Figure 47.

CLKINP

CLKINN

SYNC

CONTROL

ENABLE

4 4 4

Figure 47. Clock Distribution

Clock Input (CLKINx)

The clock input handles input signals from a variety of logic families (assuming proper terminations and sufficient voltage swing). It also handles sine wave input signals such as those delivered by the DAC reconstruction filter. Its default operating frequency range is 62.5 MHz to 500 MHz.

RESET

OUT0

OUT1

OUT2

OUT3

SYNC SOURCE

ENABLEn/MODE

OUT_RSET

OUT0P

OUT0N

OUT1P

OUT1N

OUT2P

OUT2N

OUT3P

OUT3N

08022-022

Rev. B | Page 39 of 112

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AD9548

Super-Nyquist Operation

Typically, the maximum usable frequency at the DAC output is about 45% of the system clock frequency. However, because it is a sampled DAC, its output spectrum contains Nyquist images. Of particular interest are the images appearing in the first Nyquist zone (50% to 100% of the system clock frequency). SuperNyquist operation takes advantage of these higher frequencies, but this implies that the CLKINx input operates in excess of 500 MHz, which is outside of its default operating limits.

The CLKINx receiver actually consists of two separate receivers: the default receiver and an optional high frequency receiver, which handles input signals up to 800 MHz. To select the high frequency receiver, write a Logic 1 to Register 0400, Bit 4.

Super-Nyquist operation requires a band-pass filter at the DAC output instead of the usual low-pass reconstruction filter. SuperNyquist operation is viable as long as the image frequency does not exceed the 800 MHz input range of the receiver. Furthermore, to provide acceptable jitter performance, which is a consideration for image signals with low amplitude, the signal at the CLKINx input must meet the minimum slew rate requirements.

Clock Dividers

The output clock distribution dividers are referred to as Q0 to Q3, corresponding to the OUT0 to OUT3 output channels, respectively. Each divider is programmable with 30 bits of division depth. The actual divider ratio is one more than the programmed register value; therefore, a register value of 3, for example, results in a divide ratio of 4. Thus, each divider offers a range of divide ratios from 1 to 2

With an even divide ratio, the output signal always exhibits a 50% duty cycle. When the clock divider is bypassed (a divide ratio of 1), the output duty cycle is the same as the input duty cycle. Odd output divide ratios (excluding 1) exhibit automatic duty cycle correction given by

where N (which must be an odd number) is the divide ratio and X is the normalized fraction of the high portion of the input period (that is, 0 < X < 1).

For example, if N = 5 and the input duty cycle is 20% (X = 0.2), then the output duty cycle is 44%. Note that, when the user programs an output as noninverting, then the device adjusts the falling edge timing to accomplish the duty cycle correction. Conversely, the device adjusts the rising edge timing for an inverted output.

Output Power-Down

Each of the output channels offers independent control of power-down functionality via the distribution settings register (Address 0400). Each output channel has a dedicated powerdown bit for powering down the output driver. However, if all four outputs are powered down, the entire distribution output enters a deep sleep mode.

(1 to 1,073,741,824).

CycleDutyOutput

12 −+

Even though each channel has a channel power-down control signal, it may sometimes be desirable to power down an output driver while maintaining the divider’s synchronization with the other channel dividers. This is accomplished by either of the following methods:

•

In CMOS mode, use the divider output enable control bit

to stall an output. This provides power savings while maintaining dc drive at the output.

•

In LVDS/LVPECL mode, place the output in tristate mode

(this works in CMOS mode as well).

Output Enable

Each of the output channels offers independent control of enable/ disable functionality via the distribution enable register (Address 0401). The distribution outputs use synchronization logic to control enable/disable activity to avoid the production of runt pulses and ensure that outputs with the same divide ratios become active/inactive in unison.

Output Mode

The user has independent control of the operating mode of each of the four output channels via the distribution channel modes register (Address 0404 to Address 0407). The operating mode control includes

•

Logic family and pin functionality Output drive strength

•

Output polarity

•

The three least significant bits of each of the four distribution channel mode registers comprise the mode bits. The mode value selects the desired logic family and pin functionality of an output channel, as given in Table 23 .

Table 23. Output Channel Logic Family and Pin Functionality

Mode Bits [2:0] Logic Family and Pin Functionality

000 CMOS (both pins) 001 CMOS (positive pin); tristate (negative pin) 010 Tristate (positive pin); CMOS (negative pin) 011 Tristate (both pins) 100 101 110 111 Unused

LVDS LVPECL Unused

Regardless of the selected logic family, each is capable of dc operation. However, the upper frequency is limited by the load conditions, drive strength, and impedance matching inherent in each logic family. Practical limitations set the maximum CMOS frequency to approximately 250 MHz, whereas LVPECL and LVDS are capable of 725 MHz.

Rev. B | Page 40 of 112

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AD9548

In addition to the three mode bits, each of the four distribution channel mode registers includes the following control bits:

•

Polarity invert CMOS phase invert

•

Drive strength

•

The polarity invert bit enables the user to choose between normal polarity and inverted polarity. Normal polarity is the default state. Inverted polarity reverses the representation of Logic 0 and Logic 1 regardless of the logic family.

The CMOS phase invert bit applies only when the mode bits select the CMOS logic family. In CMOS mode, both output pins of the channel have a dedicated CMOS driver. By default, both drivers deliver identical signals. However, setting the CMOS phase invert bit causes the signal on an OUTxN pin to be the opposite of the signal appearing on the OUTxP pin.

The drive strength bit allows the user to control whether the output uses weak (0) or strong (1) drive capability (applies to CMOS and LVDS but not LVPECL). For the CMOS family, the strong setting implies normal CMOS drive capability, whereas the weak setting implies low capacitive loading and allows for reduced EMI. For the LVDS family, the weak setting provides 3.5 mA drive current for standard LVDS operation, whereas the strong setting provides 7 mA for double terminated or double voltage LVDS operation. Note that 3.5 mA and 7 mA are the nominal drive current values when using the internal current setting resistor.

Output Current Control with an External Resistor

By default, the output drivers have an internal current setting resistor (3.12 k nominal) that establishes the nominal drive current for the LVDS and LVPECL operating modes. Instead of using the internal resistor, the user can set the external distribution resistor bit (Register 0400, Bit 5) and connect an external resistor to the OUT_RSET pin. Note that this feature supports an external resistor value of 3.12 k only, allowing for tighter control of the output current than is possible by using the internal current setting resistor. However, if the user elects to use a nonstandard external resistance, the following equations provide the output drive current as a function of the external resistance (R):

8325.10

LVDS

LVPECL

665.21

76.24

The numeric subscript associated with the LVDS output current corresponds to the logic state of the drive strength bit in the distribution channel modes register (Address 0404 to Address 0407). For R = 3.12 k, the equations yield I and I

= 8.0 mA. Note that the device maintains a constant

LVP EC L

= 3.5 mA, I

LVD S 0

= 7.0 mA,

LVD S 1

1.238 V (nominal) across the external resistor.

Clock Distribution Synchronization

A block diagram of the distribution synchronization functionality appears in Figure 48. The synchronization sequence begins with the primary synchronization signal, which ultimately results in delivery of a synchronization strobe to the clock distribution logic.

As indicated, the primary synchronization signal originates from four possible sources.

•

Direct sync source via the sync distribution bit (Register

0A02, Bit 1)

•

Automatic sync source based on frequency or phase lock

detection as controlled via the automatic synchronization register (Address 0403)

•

Multifunction pin sync source via one of the multifunction

pins (M0 to M7)

•

EEPROM sync source via the EEPROM

All four sources of the primary synchronization signal are logic OR’ed, so any one of them can synchronize the clock distribution output at any time. When using the multifunction pins, the synchronization event is the falling edge of the selected signal. When using the sync distribution bit, the user sets and then clears the bit. The synchronization event is the clearing operation; that is, the Logic 1 to Logic 0 transition of the bit.

The primary synchronization signal can synchronize the distribution output directly or it can enable a secondary synchronization signal. This functionality depends on the two sync source bits in the distribution synchronization register (Register 0402, Bits[5:4]).

When sync source = 00 (direct), the falling edge of the primary synchronization signal synchronizes the distribution output directly.

When sync source = 01, the rising edge of the primary synchronization signal triggers the circuitry that detects a rising edge of the active input reference. The detection of the rising edge is what synchronizes the distribution output.

When sync source = 10, the rising edge of the primary synchronization signal triggers the circuitry that detects a rollover of the DDS accumulator (after processing by the DPLL feedback divider). This corresponds to the zero crossing of the output of the phase-to-amplitude converter in the DDS (less the openloop phase offset stored in Register 030D to Register 030E). The detection of the DPLL feedback edge is what synchronizes the distribution output.

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AD9548

Active Reference Synchronization (Zero Delay)

Active reference synchronization is the term applied to the case when sync source = 01 (Register 0402, Bits[5:4]). Referring to Figure 48, this means that the active reference sync path is active because Bit 4 = 1, enabling the lower AND gate and disabling the upper AND gate. The edge detector in the active reference sync block monitors the rising edges of the active reference (the mux selects the active reference automatically). The edge detector is armed via the primary synchronization signal, which is one of the four inputs to the OR gate (typically the direct sync source). As soon as the edge detector is armed, its output goes high, which stalls the output dividers in the clock distribution block. Furthermore, once armed, a rising edge from the active reference forces the output of the edge detector low. This restarts the output dividers, thereby synchronizing the clock distribution block.

The term zero delay applies because it provides a means to edge align the output signal with the active input reference signal. Typically, zero-delay architectures use the output signal in the feedback loop of a PLL to track input/output edge alignment. Active reference synchronization, however, operates open loop. That is, synchronization of the output via the distribution synchronization logic occurs on a single edge of the active reference.

The fact that an active reference edge triggers the falling edge of the synchronization pulse means that the falling edge is asynchronous to the signal that clocks the distribution output dividers (CLKINx). Therefore, the output clock distribution logic reclocks the internal synchronization pulse to synchronize it with the CLKINx signal. This means that the output dividers restart after a deterministic delay associated with the reclocking circuitry. This deterministic delay has two components. The first deterministic delay component is four or five periods of the CLKINx signal. The one period uncertainty is due to the unknown position of the asynchronous reference clock edge relative to the CLKINx signal. The second deterministic delay component is one output period of the distribution divider.

DIRECT SYNC

SOURCE

(REGISTER 0A02[1])

AUTOMATIC S YNC

SOURCE

(REGIST ER 0403)

MULTIFUNCT ION PIN

SYNC SOURCE

EEPROM SYNC

SOURCE

PRIMARY

SYNCHRONIZAT ION

SIGNAL

0402[5]

EDGE

DETECT

DPLL

FEEDBACK

EDGE

DPLL EDGE SYNC

DIRECT SYNC

ARM

DETECT

SYSCLK/4

EDGE

0402[4]

REF A

REF AA

REF D

REF DD

ACTIVE REFERENCE SYNC

Figure 48. Output Synchronization Block Diagram

RESET

ARM

DETECT

EDGE

TO MULTIFUNCTIO N PIN STATUS LOGIC

TO CLOCK DISTRIBUTI ON SYNCHRONIZATI ON CONTRO L

STALL

DIVIDERS

SYNC OUTPUT DISTRIBUTI ON

08022-023

Rev. B | Page 42 of 112

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AD9548

The deterministic delay, expressed as t equation is a function of the frequency division factor (Q

in the following

LATENCY

) of

the channel divider associated with the zero-delay channel.

= (Qn + 4) × t

LATENCY

CLK_IN

= (Qn + 5) × t

LATENCY

In addition to deterministic delay, there is random delay (t

CLK_IN

PROP

associated with the propagation of the reference signal through the input reference receiver, as well as the propagation of the clock signal through the clock distribution logic. The total delay is

= t

DELAY

The user can compensate for t

LATENCY

+ t

PROP

by using the phase offset

DELAY

controls of the device to move the edge timing of the distribution output signal relative to the input reference edge. One method is to use the open-loop phase offset registers (Address 030D to Address 030E) for timing adjustment. However, be sure to use sufficiently small phase increments to make the adjustment. Too large a phase step can result in the clock distribution logic missing a CLKINx edge, thus ruining the edge alignment process. The appropriate phase increment depends on the transient response of any external circuitry connected between the DACOUTx and CLKINx pins.

)

The other method is to use the closed-loop phase offset registers (Address 030F to Address 0315) for timing adjustment. However, be sure to use a sufficiently small phase vs. time profile. Changing the phase too quickly can cause the DPLL to lose lock, thus ruining the edge alignment process. Note that the AD9548 phase slew limit register (Address 0316 to Address 0317) can be used to limit the rate of change of phase automatically, thereby mitigating the potential loss-of-lock problem.

To guarantee synchronization of the output dividers, it is important to make any edge timing adjustments after the synchronization event. Furthermore, when making timing adjustments, the distribution outputs can be disabled and then enabled after the adjustment is complete. This prevents the device from generating output clock signals during the timing adjustment process.

Note that the form of zero-delay synchronization described here does not track propagation time variations within the distribution clock input path or the reference input path (on or off chip) over temperature, supply, and so on. It is strictly a one-time synchronization event.

Synchronization Mask

Each output channel has dedicated synchronization mask bits (Register 0402, Bits[3:0]). When the mask bit associated with a particular channel is set, then that channel does not respond to the synchronization signal. This allows the device to operate with the masked channels active and the unmasked channels stalled while they wait for a synchronization pulse.

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AD9548

STATUS AND CONTROL

MULTIFUNCTION PINS (M0 TO M7)

The AD9548 has eight digital CMOS I/O pins (M0 to M7) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions based on the contents of Register 0200 to Register 0207. To monitor an internal function with a multifunction pin, write a Logic 1 to the most significant bit of the register associated with the desired multifunction pin. The value of the seven least significant bits of the register defines the control function, as shown in Tabl e 24 .

Table 24. Multifunction Pin Output Functions, Register 0200 to Register 0207 (Bit 7 = 1)

Bits[6:0] Value Output Function Source Proxy

0 Static Logic 0 1 Static Logic 1 2

6 EEPROM fault detected Register 0D00, Bit 2 7

9 Unused 10 Unused 11 SYSCLK PLL stable Register 0D01, Bit 4 12 to 15 Unused 16 DPLL free running Register 0D0A, Bit 0 17 DPLL active Register 0D0A, Bit 1 18 DPLL in holdover Register 0D0A, Bit 2 19

21 DPLL phase locked Register 0D0A, Bit 4 22 DPLL frequency locked Register 0D0A, Bit 5 23

27 to 31 Unused 32 Reference A fault Register 0D0C, Bit 2 33 Reference AA fault Register 0D0D, Bit 2 34 Reference B fault Register 0D0E, Bit 2

System clock divided by 32

Watchdog timer output

EEPROM upload in progress

EEPROM download in progress

SYSCLK PLL lock detected

SYSCLK PLL calibration in progress

DPLL in reference switchover

Active reference: phase master

DPLL phase slew limited

DPLL frequency clamped

Tuning word history available

Tuning word history updated

Rev. B | Page 44 of 112

Bits[6:0] Value Output Function Source Proxy

35 Reference BB fault Register 0D0F, Bit 2 36 Reference C fault Register 0D10, Bit 2 37 Reference CC fault Register 0D11, Bit 2 38 Reference D fault Register 0D12, Bit 2 39 Reference DD fault Register 0D13, Bit 2 40 to 47 Unused 48 Reference A valid Register 0D0C, Bit 3 49 Reference AA valid Register 0D0D, Bit 3 50 Reference B valid Register 0D0E, Bit 3 51 Reference BB valid Register 0D0F, Bit 3 52 Reference C valid Register 0D10, Bit 3 53 Reference CC valid Register 0D11, Bit 3 54 Reference D valid Register 0D12, Bit 3 55 Reference DD valid Register 0D13, Bit 3 56 to 63 Unused 64

72 to 79 Unused 80

81 to 127 Unused

Reference A active reference

Reference AA active reference

Reference B active reference

Reference BB active reference

Reference C active reference

Reference CC active reference

Reference D active reference

Reference DD active reference

Clock distribution sync pulse

To control an internal function with a multifunction pin, write a Logic 0 to the most significant bit of the register associated with the desired multifunction pin. The monitored function depends on the value of the seven least significant bits of the register, as shown in Tab l e 2 5.

Table 25. Multifunction Pin Input Functions, Register 0200 to Register 0207 (Bit 7 = 0)

Bits[6:0] Value Output Function Destination Proxy

0 Unused (default) 1 I/O update Register 0005, Bit 0 2 Full power-down Register 0A00, Bit 0 3 Watchdog reset Register 0A03, Bit 0 4 IRQ reset Register 0A03, Bit 1 5 Tuning word history reset Register 0A03, Bit 2 6 to 15 Unused

Page 45

AD9548

Bits[6:0] Value Output Function Destination Proxy

16 Holdover Register 0A01, Bit 6 17 Free run Register 0A01, Bit 5 18

21 to 31 Unused 32

40 to 47 Unused 48

56 to 63 Unused 64 Enable OUT0 Register 0401, Bit 0 65 Enable OUT1 Register 0401, Bit 1 66 Enable OUT2 Register 0401, Bit 2 67 Enable OUT3 Register 0401, Bit 3 68

70 to 127 Unused

Reset incremental phase offset

Increment incremental phase offset

Decrement incremental phase offset

Override Reference Monitor A

Override Reference Monitor AA

Override Reference Monitor B

Override Reference Monitor BB

Override Reference Monitor C

Override Reference Monitor CC

Override Reference Monitor D

Override Reference Monitor DD

Force validation Timeout A

Force validation Timeout AA

Force validation Timeout B

Force validation Timeout BB

Force validation Timeout C

Force validation Timeout CC

Force validation Timeout D

Force validation Timeout DD

Enable OUT0, OUT1, OUT2, OUT3

Sync clock distribution outputs

If more than one multifunction pin operates on the same control signal, then internal priority logic ensures that only one multifunction pin serves as the signal source. The selected pin is the one with the lowest numeric suffix. For example, if both M3 and M7 operate on the same control signal, then M3 is used as the signal source and the redundant pins are ignored.

At power-up, the multifunction pins can be used to force the device into certain configurations as defined in the initial pin programming section. This functionality, however, is valid only during power-up or following a reset, after which the pins can be reconfigured via the serial programming port or via the EEPROM.

IRQ PIN

The AD9548 has a dedicated interrupt request (IRQ) pin. The IRQ pin output mode register (Register 0208, Bits[1:0]) controls how the IRQ pin asserts an interrupt based on the value of the two bits, as follows:

00—The IRQ pin is high impedance when deasserted and active

low when asserted and requires an external pull-up resistor (this is the default operating mode).

01—The IRQ pin is high impedance when deasserted and active

high when asserted and requires an external pull-down resistor.

10—The IRQ pin is Logic 0 when deasserted and Logic 1 when

asserted.

11—The IRQ pin is Logic 1 when deasserted and Logic 0 when

asserted.

The AD9548 asserts the IRQ pin whenever any of the bits in the IRQ monitor register (Address 0D02 to Address 0D09) are Logic 1. Each bit in this register is associated with an internal function capable of producing an interrupt. Furthermore, each bit of the IRQ monitor register is the result of a logical AND of the associated internal interrupt signal and the corresponding bit in the IRQ mask register (Address 0209 to Address 0210). That is, the bits in the IRQ mask register have a one-to-one correspondence with the bits in the IRQ monitor register. Whenever an internal function produces an interrupt signal and the associated IRQ mask bit is set, then the corresponding bit in the IRQ monitor register is set. The user should be aware that clearing a bit in the IRQ mask register removes only the mask associated with the internal interrupt signal. It does not clear the corresponding bit in the IRQ monitor register.

The IRQ pin is the result of a logical OR of all the IRQ monitor register bits. Thus, the AD9548 asserts the IRQ pin so long as any of the IRQ monitor register bits are Logic 1. Note that it is possible to have multiple bits set in the IRQ monitor register. Therefore, when the AD9548 asserts the IRQ pin, it may indicate an interrupt from several different internal functions. The IRQ monitor register provides the user with a means to interrogate the AD9548 to determine which internal function(s) produced the interrupt.

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AD9548

Typically, when the AD9548 asserts the IRQ pin, the user interrogates the IRQ monitor register to identify the source of the interrupt request. After servicing an indicated interrupt, the user should clear the associated IRQ monitor register bit via the IRQ clearing register (Address 0A04 to Address 0A0B). The bits in the IRQ clearing register have a one-to-one correspondence with the bits in the IRQ monitor register. Note that the IRQ clearing register is autoclearing. The IRQ pin remains asserted until the user clears all of the bits in the IRQ monitor register that indicate an interrupt.

It is also possible to collectively clear all of the IRQ monitor register bits by setting the reset all IRQs bit in the reset function register (Register 0A03, Bit 1). Note that this is an autoclearing bit. Setting this bit results in deassertion of the IRQ pin. Alternatively, the user can program any of the multifunction pins to clear all IRQs. This allows the user to clear all IRQs by means of a hardware pin rather than by a serial I/O port operation.

WATCHDOG TIMER

The watchdog timer is a general-purpose programmable timer. To set the timeout period, the user writes to the 16-bit watchdog timer register (Address 0211 to Address 0212). A value of 0 in this register disables the timer. A nonzero value sets the timeout period in milliseconds, giving the watchdog timer a range of 1 ms to 65.535 sec. The relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms.

If enabled, the timer runs continuously and generates a timeout event whenever the timeout period expires. The user has access to the watchdog timer status via the IRQ mechanism and the multifunction pins (M0 to M7). In the case of the multifunction pins, the timeout event of the watchdog timer is a pulse that lasts 32 system clock periods.

There are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). The first is by writing a Logic 1 to the autoclearing reset watchdog bit in the reset function register (Register 0A03, Bit 0). Alternatively, the user can program any of the multifunction pins to reset the watchdog timer. This allows the user to reset the timer by means of a hardware pin rather than by a serial I/O port operation.

EEPROM

EEPROM Overview

The AD9548 contains an integrated 2048-byte, electrically erasable, programmable read-only memory (EEPROM). The AD9548 can be configured to perform a download at power-up via the multifunction pins (M3 to M7), but uploads and downloads can also be done on demand via the EEPROM control register (Address 0E00 to Address 0E03).

The EEPROM provides the ability to upload and download configuration settings to and from the register map. Figure 49 shows a functional diagram of the EEPROM.

Register 0E10 to Register 0E3F represent a 48-byte scratch pad that enables the user to store a sequence of instructions for transferring data to the EEPROM from the device settings portion of the register map. Note that the default values for these registers provide a sample sequence for saving/retrieving all of the AD9548 EEPROM-accessible registers. Figure 49 shows the connectivity between the EEPROM and the controller that manages data transfer between the EEPROM and the register map.

The controller oversees the process of transferring EEPROM data to and from the register map. There are two modes of operation handled by the controller: saving data to the EEPROM (upload mode) or retrieving data from the EEPROM (download mode). In either case, the controller relies on a specific instruction set.

M7 M6 M5 M4 M3

DEVICE SETTINGS ADDRESS

POINTER

DATA

DEVICE SETTINGS

(0100 TO 0A10)

Figure 49. EEPROM Functional Diagram

EEPROM

CONTROLLE R

(0E01 [4:0])

CONDITION

DATA

SCRATCH PA D (0E10 TO 0E3F )

DATA

EEPROM ADDRESS POINTER

SCRATCH PAD

ADDRESS

POINT ER

(000 TO 7FF)

SERIAL

INPUT/OUTPUT

PORT

EEPROM

08022-024

Rev. B | Page 46 of 112

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AD9548

Table 26. EEPROM Controller Instruction Set

Instruction Value (Hex)

00 to 7F Data 3

80 I/O update 1

A0 Calibrate 1

A1 Distribution sync 1

B0 to CF Condition 1

FE Pause 1

FF End 1

Instruction Type

EEPROM Instructions

Tabl e 26 lists the EEPROM controller instruction set. The controller recognizes all instruction types whether it is in upload or download mode, except for the pause instruction, which it only recognizes in upload mode.

The I/O update, calibrate, distribution sync, and end instructtions are mostly self-explanatory. The others, however, warrant further detail, as described in the following paragraphs.

Data instructions are those that have a value from 00 to 7F. A data instruction tells the controller to transfer data between the EEPROM and the register map. The controller needs the following two parameters to carry out the data transfer:

•

The number of bytes to transfer The register map target address

•

The controller decodes the number of bytes to transfer directly from the data instruction itself by adding one to the value of the instruction. For example, the data instruction, 1A, has a decimal value of 26; therefore, the controller knows to transfer 27 bytes (one more than the value of the instruction). Whenever the controller encounters a data instruction, it knows to read the next two bytes in the scratch pad because these contain the register map target address.

Bytes Required

Description

A data instruction tells the controller to transfer data to or from the device settings part of the register map. A data instruction requires two additional bytes that together indicate a starting address in the register map. Encoded in the data instruction is the number of bytes to transfer, which is one more than the instruction value.

When the controller encounters this instruction while downloading from the EEPROM, it issues a soft I/O update (see Register 0005 in Table 41).

When the controller encounters this instruction while downloading from the EEPROM, it initiates a system clock calibration sequence (see Register 0A02 in Table 120).

When the controller encounters this instruction while downloading from the EEPROM, it issues a sync pulse to the output distribution synchronization (see Register 0A02 in Table 120).

B1 to CF are condition instructions and correspond to Condition 1 through Condition 31, respectively. B0 is the null condition instruction. See the EEPROM Conditional Processing section for details.

When the controller encounters this instruction in the scratch pad while uploading to the EEPROM, it resets the scratch pad address pointer and holds the EEPROM address pointer at its last value. This allows storage of more than one instruction sequence in the EEPROM. Note that the controller does not copy this instruction to the EEPROM during upload.

When the controller encounters this instruction in the scratch pad while uploading to the EEPROM, it resets both the scratch pad address pointer and the EEPROM address pointer and then enters an idle state.

When the controller encounters this instruction while downloading from the EEPROM, it resets the EEPROM address pointer and then enters an idle state.

Note that, in the EEPROM scratch pad, the two registers that comprise the address portion of a data instruction have the MSB of the address in the D7 position of the lower register address. The bit weight increases left to right, from the lower register address to the higher register address. Furthermore, the starting address always indicates the lowest numbered register map address in the range of bytes to transfer. That is, the controller always starts at the register map target address and counts upward regardless of whether the serial I/O port is operating in I

C, SPI LSB-first, or SPI MSB-first mode.

As part of the data transfer process during an EEPROM upload, the controller calculates a 1-byte checksum and stores it as the final byte of the data transfer. As part of the data transfer process during an EEPROM download, however, the controller again calculates a 1-byte checksum value but compares the newly calculated checksum with the one that was stored during the upload process. If an upload/download checksum pair does not match, the controller sets the EEPROM fault status bit. If the upload/download checksums match for all data instructions encountered during a download sequence, the controller sets the EEPROM complete status bit.

Condition instructions are those that have a value from B0 to CF. Condition instructions B1 to CF represent Condition 1 to Condition 31, respectively. The B0 condition instruction is special because it represents the null condition (see the EEPROM Conditional Processing section).

Rev. B | Page 47 of 112

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AD9548

A pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratch pad. When the controller encounters a pause instruction during an upload sequence, it keeps the EEPROM address pointer at its last value. This way the user can store a new instruction sequence in the scratch pad and upload the new sequence to the EEPROM. The new sequence is stored in the EEPROM address locations immediately following the previously saved sequence. This process is repeatable until an upload sequence contains an end instruction. The pause instruction is also useful when used in conjunction with condition processing. It allows the EEPROM to contain multiple occurrences of the same register(s), with each occurrence linked to a set of conditions (see the EEPROM Conditional Processing section).

EEPROM Upload

To upload data to the EEPROM, the user must first ensure that the write enable bit (Register 0E00, Bit 0) is set. Then, on setting the autoclearing save to EEPROM bit (Register 0E02, Bit 0), the controller initiates the EEPROM data storage process.

Uploading EEPROM data requires that the user first write an instruction sequence into the scratch pad registers. During the upload process, the controller reads the scratch pad data byte by byte, starting at Register 0E10 and incrementing the scratch pad address pointer as it goes until it reaches a pause or End instruction.

As the controller reads the scratch pad data, it transfers the data from the scratch pad to the EEPROM (byte by byte) and increments the EEPROM address pointer accordingly, unless it encounters a data instruction. A data instruction tells the controller to transfer data from the device settings portion of the register map to the EEPROM. The number of bytes to transfer is encoded within the data instruction, and the starting address for the transfer appears in the next two bytes in the scratch pad.

When the controller encounters a data instruction, it stores the instruction in the EEPROM, increments the EEPROM address pointer, decodes the number of bytes to be transferred, and increments the scratch pad address pointer. Then it retrieves the next two bytes from the scratch pad (the target address) and increments the scratch pad address pointer by 2. Next, the controller transfers the specified number of bytes from the register map (beginning at the target address) to the EEPROM.

When it completes the data transfer, the controller stores an extra byte in the EEPROM to serve as a checksum for the transferred block of data. To account for the checksum byte, the controller increments the EEPROM address pointer by one more than the number of bytes transferred. Note that, when the

controller transfers data associated with an active register, it actually transfers the buffered contents of the register (see the Buffered/Active Registers section for details on the difference between buffered and active registers). This allows for the transfer of nonzero autoclearing register contents.

Note that conditional processing (see the EEPROM Conditional Processing section) does not occur during an upload sequence.

EEPROM Download

An EEPROM download results in data transfer from the EEPROM to the device register map. To download data, the user sets the autoclearing load from EEPROM bit (Register 0E03, Bit 1). This commands the controller to initiate the EEPROM download process. During download, the controller reads the EEPROM data byte by byte, incrementing the EEPROM address pointer as it goes, until it reaches an end instruction. As the controller reads the EEPROM data, it executes the stored instructions, which includes transferring stored data to the device settings portion of the register map whenever it encounters a data instruction.

Note that conditional processing (see the EEPROM Conditional Processing section) is only applicable when downloading.

Automatic EEPROM Download

Following a power-up, an assertion of the RESET pin, or a soft reset (Register 0000, Bit 5 = 1), if FncInit[7:3] ≠ 0 (see the Initial Pin Programming section), then the instruction sequence stored in the EEPROM executes automatically with condition = FncInit[7:3]. In this way, a previously stored set of register values downloads automatically on power-up or with a hard or soft reset. See the EEPROM Conditional Processing section for details regarding conditional processing and the way it modifies the download process.

EEPROM Conditional Processing

The condition instructions allow conditional execution of EEPROM instructions during a download sequence. During an upload sequence, however, they are stored as is and have no effect on the upload process.

Note that, during EEPROM downloads, the condition instructions themselves and the end instruction always execute unconditionally.

Conditional processing makes use of two elements: the condition (from Condition 1 to Condition 31) and the condition tag board. The relationships among the condition, the condition tag board, and the EEPROM controller appear schematically in Figure 50.

Rev. B | Page 48 of 112

Page 49

AD9548

EXAMPLE

CONDIT ION 3 AND

CONDIT ION 13

ARE TAGGED

CONDITIO N

TAG BOARD

1 65432

111098

25 26 27 28 29

15141312

2322212019181716

30 3124

0E01, BITS[4:0]

5 5

M7 M3

FncInit, BITS[7:3]

IF B1 ≤ INSTRUCTION ≤ CF,

THEN TAG DECO DED CONDITION

EEPROM

WATCH FOR

OCCURRENCE OF

CONDITIO N

STORE CONDIT ION

INSTRUCTIONS AS

THEY ARE READ FROM

THE SCRATCH PAD.

SCRATCH

PAD

INSTRUCTIO NS

DOWNL OAD.

UPLOAD

PROCEDURE

EEPROM CONTROLLER

DURING

CONDITIO N

HANDLER

DOWNLOAD

PROCEDURE

Figure 50. EEPROM Conditional Processing

The condition is a 5-bit value with 32 possibilities. Condition = 0 is the null condition. When the null condition is in effect, the EEPROM controller executes all instructions unconditionally. The remaining 31 possibilities, condition = 1 through condition = 31, modify the EEPROM controller’s handling of a download sequence. The condition originates from one of two sources (see Figure 50), as follows:

•

FncInit, Bits[7:3], which is the state of the M3 to M7

multifunction pins at power-up (see the Initial Pin Programming section)

•

If Register 0E01, Bits[4:0] ≠ 0, then the condition is the value stored in Register 0E01, Bits[4:0]; otherwise, the condition is FncInit, Bits[7:3]. Note that a nonzero condition present in Register 0E01, Bits[4:0] takes precedence over FncInit, Bits[7:3].

The condition tag board is a table maintained by the EEPROM controller. When the controller encounters a condition instructtion, it decodes the B1 through CF instructions as condition = 1 through condition = 31, respectively, and tags that particular condition in the condition tag board. However, the B0 condition instruction decodes as the null condition, for which the controller clears the condition tag board, and subsequent download instructions execute unconditionally (until the controller encounters a new condition instruction).

IF {0E01, BITS[4:0] ≠ 0}

CONDITION = 0E01, BITS[4:0]

ELSE

CONDITION = Fn cInit, BITS[7:3]

IF INST RUCTION = B0,

THEN CLEAR ALL TAGS

EXE CUT E/SK IP

INST RUCT ION(S)

ENDIF

CONDITION

IF {NO TAGS} OR {CONDITION = 0} EXECUTE INST RUCTIONS ELSE IF {CONDITION IS TAGGED} EXECUTE INSTRUCTIONS ELSE SKIP INSTRUCTIONS ENDIF ENDIF

8022-025

During download, the EEPROM controller executes or skips instructions depending on the value of condition and the contents of the condition tag board. Note, however, that condition instructions and the end instruction always execute unconditionally during download. If condition = 0, then all instructions during download execute unconditionally. If condition ≠ 0 and there are any tagged conditions in the condition tag board, then the controller executes instructions only if the condition is tagged. If the condition is not tagged, then the controller skips instructions until it encounters a condition instruction that decodes as a tagged condition. Note that the condition tag board allows for multiple conditions to be tagged at any given moment. This conditional processing mechanism enables the user to have one download instruction sequence with many possible outcomes depending on the value of the condition and the order in which the controller encounters condition instructions.

Rev. B | Page 49 of 112

Page 50

AD9548

Tabl e 27 lists a sample EEPROM download instruction sequence. It illustrates the use of condition instructions and how they alter the download sequence. The table begins with the assumption that no conditions are in effect. That is, the most recently executed condition instruction is B0 or no conditional instructions have been processed.

Table 27. EEPROM Conditional Processing Example

Instruction Action

0x08 0x01 0x00 0xB1 Tag Condition 1 0x19 0x04 0x00 0xB2 Tag Condition 2 0xB3 Tag Condition 3 0x07 0x05 0x00 0x0A

0xB0 Clear the condition tag board 0x80

0x0A

Storing Multiple Device Setups in EEPROM

Conditional processing makes it possible to create a number of different device setups, store them in EEPROM, and download a specific setup on demand. To do so, first program the device control registers for a specific setup. Then, store an upload sequence in the EEPROM scratch pad with the following general form:

Condition instruction (B1 to CF) to identify the setup with

a specific condition (1 to 31)

Data instructions (to save the register contents) along with

any required calibrate and/or I/O update instructions

Pause instruction (FE)

With the upload sequence written to the scratch pad, perform an EEPROM upload (Register 0E02, Bit 0).

Transfer the system clock register contents regardless of the current condition.

Transfer the clock distribution register contents only if condition = 1

Transfer the reference input register contents only if condition = 1, 2, or 3

Calibrate the system clock only if condition = 1, 2, or 3

Execute an I/O update regardless of the value of the condition

Calibrate the system clock regardless of the value of the condition

Reprogram the device control registers for the next desired setup. Then store a new upload sequence in the EEPROM scratch pad with the following general form:

Condition instruction (B0)

The next desired condition instruction (B1 to CF, but

different than the one used during the previous upload to identify a new setup)

Data instructions (to save the register contents) along with

any required calibrate and/or I/O update instructions

Pause instruction (FE)

With the upload sequence written to the scratch pad, perform an EEPROM upload (Register 0E02, Bit 0).

Repeat the process of programming the device control registers for a new setup, storing a new upload sequence in the EEPROM scratch pad (Step 1 through Step 4), and executing an EEPROM upload (Register 0E02, Bit 0) until all of the desired setups have been uploaded to the EEPROM.

Note that, on the final upload sequence stored in the scratch pad, the pause instruction (FE) must be replaced with an end instruction (FF).

To download a specific setup on demand, first store the condition associated with the desired setup in Register 0E01, Bits[4:0]. Then perform an EEPROM download (Register 0E03, Bit 1). Alternatively, to download a specific setup at power-up, apply the required logic levels necessary to encode the desired condition on the M3 to M7 multifunction pins. Then power up the device; an automatic EEPROM download occurs. The condition (as established by the M3 to M7 multifunction pins) guides the download sequence and results in a specific setup.

Keep in mind that the number of setups that can be stored in the EEPROM is limited. The EEPROM can hold a total of 2048 bytes. Each nondata instruction requires one byte of storage. Each data instruction, however, requires N + 4 bytes of storage, where N is the number of transferred register bytes and the other four bytes include the data instruction itself (one byte), the target address (two bytes), and the checksum calculated by the EEPROM controller during the upload sequence (one byte).

Rev. B | Page 50 of 112

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AD9548

SERIAL CONTROL PORT

POWER-ON RESETSERIAL CONT ROL ARBITER

SCLK/SCL

CS/SDA

SDIO

SDO

EEPR OM

SPI

I2C

EEPROM

CONTROLL ER

400kHz

Figure 51. Serial Port Functional Diagram

The AD9548 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9548 serial control port is compatible with most synchronous transfer formats, including Philips IC, Motorola SPI, and Intel SSR protocols. The serial control port allows read/write access to the AD9548 register map.

In SPI mode, single or multiple byte transfers are supported. The SPI port configuration is programmable via Register 0000. This register is integrated into the SPI control logic rather than in the register map and is distinct from the I

C Register 0000. It

is also inaccessible to the EEPROM controller.

A functional diagram of the serial control port, including its relationship to the EEPROM, appears in Figure 51.

Although the AD9548 supports both the SPI and I

C serial port protocols, only one is active following power-up (as determined by the multifunction pins, M0 to M2, during the startup sequence). That is, the only way to change the serial port protocol is to reset the device (or cycle the device power supply). Both protocols use a common set of control pins as shown in Figure 52.

SCLK/SCL

SDIO

SDO

CSB/SDA

Figure 52. Serial Control Port

AD9548

SERIAL

CONTROL

PORT

08022-027

SPI/I²C PORT SELECTION

Because the AD9548 supports both SPI and IC protocols, the active serial port protocol depends on the logic state of the three multifunction pins, M0 to M2, at startup. If all three pins are set to Logic 0 at startup, then the SPI protocol is active. Otherwise, the IC protocol is active with seven different IC slave address settings based on the startup logic pattern on the M0 to M2 pins

Rev. B | Page 51 of 112

13-BIT ADDRESS

SPACE

READ ONLY

REGION

READ/WRITE

REGION

ANALOG BLO CKS AND

DIGITAL CORE

MULTI-

FUNCTION

PIN CONTROL

LOGIC

M7 M6 M5 M4 M3 M2 M1 M0

8022-026

(see Tabl e 28 ). Note that the four MSBs of the slave address are hardware coded as 1011.

Table 28. Serial Port Mode Selection

M2 M1 M0 Serial Port Mode

0 0 0 SPI 0 0 1 I²C (address = 1001001) 0 1 0 I²C (address = 1001010) 0 1 1 I²C (address = 1001011) 1 0 0 I²C (address = 1001100) 1 0 1 I²C (address = 1001101) 1 1 0 I²C (address = 1001110) 1 1 1 I²C (address = 1001111)

SPI SERIAL PORT OPERATION

Pin Descriptions

The SCLK (serial clock) pin serves as the serial shift clock. This pin is an input. SCLK synchronizes serial control port read and write operations. The rising edge SCLK registers write data bits, and the falling edge registers read data bits. The SCLK pin supports a maximum clock rate of 40 MHz.

The SDIO (serial data input/output) pin is a dual-purpose pin and acts as either an input only (unidirectional mode) or as both an input and an output (bidirectional mode). The AD9548 default SPI mode is bidirectional.

The SDO unidirectional I/O mode. It serves as the data output pin for read operations.

The and write operations. This pin is internally connected to a 30 kΩ pull-up resistor. When into a high impedance state.

(serial data output) pin is useful only in

(chip select) pin is an active low control that gates read

is high, the SDO and SDIO pins go

Page 52

AD9548

SPI Mode Operation

The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. By default, the AD9548 uses the bidirectional MSB-first mode. The reason that bidirectional is the default mode is so that the user can still write to the device, if it is wired for unidirectional operation, to switch to unidirectional mode.

Assertion (active low) of the operation to the AD9548 SPI port. For data transfers of three bytes or fewer (excluding the instruction word), the device

supports the

pin can be temporarily deasserted on any byte boundary,

the allowing time for the system controller to process the next byte. CS

can be deasserted only on byte boundaries, however. This

applies to both the instruction and data portions of the transfer.

During stall high periods, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort a transfer midstream, then the state machine must be reset by either completing the transfer or by asserting the pin for at least one complete SCLK cycle (but less than eight SCLK cycles). Deasserting the terminates the serial transfer and flushes the buffer.

In the streaming mode (see Tab l e 29 ), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented. deasserted at the end of the last byte transferred, thereby ending the stream mode.

Table 29. Byte Transfer Count

W1 W0 Bytes to Transfer

0 0 1 0 1 2 1 0 3 1 1 Streaming mode

stalled high mode (see ). In this mode,

Communication Cycle—Instruction Plus Data

The SPI protocol consists of a two-part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9548 serial control port with information regarding the payload. The instruction word includes the R/ bit that indicates the direction of the payload transfer (that is, a read or write operation). The instruction word also indicates the number of bytes in the payload and the starting register address of the first payload byte.

pin initiates a write or read

Tabl e 29

pin on a nonbyte boundary

must be

Write

If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9548. Data bits are registered on the rising edge of SCLK. The length of the transfer (1, 2, or 3 bytes or streaming mode) depends on the W0 and W1 bits (see Table 29) in the instruction byte. When not streaming, bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is stalled, the serial transfer resumes when CS

is asserted. Deasserting the CS pin on a nonbyte boundary resets the serial control port. Reserved or blank registers are not skipped over automatically during a write sequence. Therefore, the user must know what bit pattern to write to the reserved registers to preserve proper operation of the part. Generally, it does not matter what data is written to blank registers, but it is customary to write 0s.

Most of the serial port registers are buffered (see the Buffered/Active Registers section for details on the difference between buffered and active registers). Therefore, data written into buffered registers does not take effect immediately. An additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. This is accomplished with an I/O update operation, which is performed in one of two ways. One is by writing a Logic 1 to Register 0005, Bit 0 (this bit is self-clearing). The other is to use an external signal via an appropriately programmed multifunction pin. The user can change as many register bits as desired before executing an I/O update. The I/O update operation transfers the buffer register contents to their active register counterparts.

can be deasserted after each sequence of eight

Read

The AD9548 supports the long instruction mode only. If the instruction word indicates a read operation, the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word. N is the number of data bytes read and depends on the W0 and W1 bits of the instruction word. The readback data is valid on the falling edge of SCLK. Blank registers are not skipped over during readback.

A readback operation takes data from either the serial control port buffer registers or the active registers, as determined by Register 0004, Bit 0.

SPI Instruction Word (16 Bits)

The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits, W1 and W0, indicate the number of bytes in the transfer (see Tabl e 29 which indicates the starting register address of the read/write operation (see ).

). The final 13 bits are the register address (A12 to A0),

Table 3 1

Rev. B | Page 52 of 112

Page 53

AD9548

SPI MSB-/LSB-First Transfers

The AD9548 instruction word and payload can be MSB first or LSB first. The default for the AD9548 is MSB first. The LSB-first mode can be set by writing a 1 to Register 0000, Bit 6. Immediately after the LSB-first bit is set, subsequent serial control port operations are LSB first.

When MSB-first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant payload byte. Subsequent data bytes must follow in order from high address to low address. In MSB-first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle.

When Register 0000, Bit 6 = 1 (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant payload byte followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle.

For multibyte MSB-first (default) I/O operations, the serial control port register address decrements from the specified starting address toward Address 0000. For multibyte LSB-first I/O operations, the serial control port register address increments from the starting address toward Address 1FFF. Unused addresses are not skipped during multibyte I/O operations; therefore, the user should write the default value to a reserved register and 0s to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers.

Table 30. Streaming Mode (No Addresses Are Skipped)

Write Mode

Address Direction Stop Sequence

LSB First Increment 0x0000 ... 0x1FFF MSB First Decrement 0x1FFF ... 0x0000

Table 31. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB LSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

R/W

W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SCLK

DON'T CARE

SDIO A12W0W1R/ W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INST RUCTION HEADE R REGIST ER (N) DATA REGIST ER (N – 1) DATA

DON'T CARE

8022-029

Figure 53. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data

SCLK

SDIO

SDO

DON'T CARE

A12W0W1R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

REGISTE R (N) DATA16-BIT INST RUCTION HE ADER REGISTER (N – 1) DAT A REGISTER (N – 2) DAT A REGI STER (N – 3) DAT A

DON'T CARE

DON'T

CARE

08022-030

Figure 54. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data

CLK

SCLK

SDIO

DON'T CARE

W1W0A12A11A10A9A8A7A6A5D4D3D2D1D0

R/W

Figure 55. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

Rev. B | Page 53 of 112

DON'T CARE

8022-031

Page 54

AD9548

DON'T CARE

SCL

DON'T CARE

SDIO

SCLK

SDIO

SDO

DATA BIT N – 1DATA BIT N

08022-032

Figure 56. Timing Diagram for Serial Control Port Register Read

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A1 2 D1D0R/WW1W0 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INST RUCTION HEADE R REGISTE R (N) DATA REGISTER (N + 1) DATA

Figure 57. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

DON'T CARE

8022-033

SCLK

SDIO

CLK

BIT N BIT N + 1

Figure 58. Serial Control Port Timing—Write

Table 32. Serial Control Port Timing

Parameter Description

tDS Setup time between data and the rising edge of SCLK tDH Hold time between data and the rising edge of SCLK t

Period of the clock

CLK

t tC

Setup time between the CS Setup time between the SCLK rising edge and CS

falling edge and the SCLK rising edge (start of the communication cycle)

rising edge (end of the communication cycle) tHI Minimum period that SCLK should be in a logic high state tLO Minimum period that SCLK should be in a logic low state t

SCLK to valid SDIO and SDO (see Figure 56)

08022-034

Rev. B | Page 54 of 112

Page 55

AD9548

SDA

I²C SERIAL PORT OPERATION

The I2C interface has the advantage of requiring only two control pins and is a de facto standard throughout the I industry. However, its disadvantage is programming speed, which is 400 kbps maximum. The AD9548 IC port design is based on the IC fast mode standard from Philips, so it supports both the 100 kHz standard mode and 400 kHz fast mode. Fast mode imposes a glitch tolerance requirement on the control signals. That is, the input receivers ignore pulses of less than 50 ns duration.

The AD9548 IC port consists of a serial data line (SDA) and a serial clock line (SCL). In an IC bus system, the AD9548 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device; that is, no clock is generated by the AD9548. The AD9548 uses direct 16-bit memory addressing instead of traditional 8-bit memory addressing.

The AD9548 allows up to seven unique slave devices to occupy

the I

C bus. These are accessed via a 7-bit slave address

transmitted as part of an I

C packet. Only the device with a matching slave address responds to subsequent I The device slave address is 1001xxx (the three right bits are determined by the M0 to M2 pins). The four MSBs (1001) are hard-wired, while the three LSBs (xxx, determined by the M0 to M2 pins) are programmable via the power-up state of the multifunction pins (see the Initial Pin Programming section).

I2C Bus Characteristics

A summary of the various I2C protocols appears in Tab le 3 3.

C commands.

Table 33. I2C Bus Abbreviation Definitions

Abbreviation Definition

S Start Sr Repeated start P A A W

Stop Acknowledge Nonacknowledge Write

R Read

The transfer of data is shown in Figure 59. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCL line is low.

SCL

DATA LINE

STABLE;

DATA VALID

Figure 59. Valid Bit Transfer

CHANGE OF DATA

ALLOWED

Start/stop functionality is shown in Figure 60. The start condition is characterized by a high-to-low transition on the SDA line while SCL is high. The start condition is always generated by the master to initialize a data transfer. The stop condition is characterized by a low-to-high transition on the SDA line while SCL is high. The stop condition is always generated by the master to terminate a data transfer. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit; bytes are sent MSB first.

08022-035

SDA

SCL

MSB

START CONDITI ON STOP CONDITION

Figure 60. Start and Stop Conditions

ACK FROM

SLAVE-RECEI VER

Figure 61. Acknowledge Bit

Rev. B | Page 55 of 112

3 TO 73 TO 7 89

8022-036

ACK FROM

SLAVE-RECEIVER

08022-037

Page 56

AD9548

The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte.

The nonacknowledge bit ( bit data byte. A nonacknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. It is done by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte.

Data Transfer Process

The master initiates data transfer by asserting a start condition. This indicates that a data stream follows. All IC slave devices connected to the serial bus respond to the start condition.

The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/ This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/ master (transmitter) writes to the slave device (receiver). If the

bit is 1, the master (receiver) reads from the slave device

(transmitter).

The format for these commands is described in the Data Transfe r Format section

) is the ninth bit attached to any 8-

bit is 0, the

bit.

Data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted per transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. This addressing scheme gives a memory address of up to 2

− 1 = 65,535. The data bytes after these two memory address bytes are register data written to or read from the control registers. In read mode, the data bytes after the slave address byte are register data written to or read from the control registers.

When all data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10

clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull SDA low during the ninth clock pulse. This is known as a nonacknowledge bit. By receiving the nonacknowledge bit, the slave device knows the data transfer is finished and enters idle mode. The master then takes the data line low during the low period before the 10 high during the 10

clock pulse to assert a stop condition.

clock pulse, and

A start condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded.

SCL

MSB

ACK FROM

SLAVE-RECEIV ER

Figure 62. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

Figure 63. Data Transfer Process (Master Read Mode, 2-Byte Transfer)

ACK FROM

MASTER-RECEIVER

Rev. B | Page 56 of 112

3 TO 73 TO 7 8910

ACK FROM

SLAVE-RECEI VER

NON-ACK FROM

MASTER-RECEIVER

08022-038

08022-039

Page 57

AD9548

SDA

Data Transfer Format

Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.

S Slave

address

Send byte format—the send byte protocol is used to set up the register address for subsequent reads.

S Slave address W A RAM address high byte A RAM address low byte A P

Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.

S Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2

Read byte format—the combined format of the send byte and the receive byte.

S Slave

Address

I²C Serial Port Timing

A RAM address

high byte

A RAM

Address

High Byte

A RAM address

A RAM

Address

Low Byte

A RAM

low byte

A Sr Slave

Address

A RAM

Data 0

R A RAM

Data

Data 1

A RAM

Data

A RAM

Data 2

A RAM

Data

A P

SCL

SSr

HD; STA

HD; DAT

SU; DAT

SU; STA

Figure 64. I²C Serial Port Timing

HD; STA

Table 34. IC Timing Definitions

Parameter Description

Serial clock

SCL

Bus free time between stop and start conditions

BUF

Repeated hold time start condition

HD; STA

Repeated start condition setup time

SU; STA

Stop condition setup time

SU; STO

Data hold time

HD; DAT

Date setup time

SU; DAT

tLO SCL clock low period tHI SCL clock high period tR Minimum/maximum receive SCL and SDA rise time tF Minimum/maximum receive SCL and SDA fall time t

Pulse width of voltage spikes that must be suppressed by the input filter

SU; STO

BUF

08022-040

Rev. B | Page 57 of 112

Page 58

AD9548

I/O PROGRAMMING REGISTERS

The register map spans an address range from 0x0000 through 0x0E3F (0 to 3647, decimal). Each address provides access to 1 byte (eight bits) of data. Each individual register is identified by its four-digit hexadecimal address (for example, Register 0A10). In some cases, a group of addresses collectively define a register (for example, the IRQ mask register consists of Register 0209, Register 020A, Register 020B, Register 020C, Register 020D, Register 020E, Register 020F, and Register 0210).

In general, when a group of registers defines a control parameter, the LSB of the value resides in the D0 position of the register with the lowest address. The bit weight increases right to left, from the lowest register address to the highest register address. For example, the default value of the incremental phase lock offset step size register (Address 0314 to Address 0315) is the 16-bit hexadecimal number, 0x03E8 (not 0xE803).

Note that the EEPROM storage sequence registers (Address 0E10 to Address 0E3F) are an exception to the above convention (see the

EEPROM Instructions section).

An S or C in the Opt column of the register map identifies a register as an active register (otherwise, it is a buffer register). An S entry means that the I/O update signal to the active register is synchronized with the serial port clock or with an input signal driving one of the multifunction pins. On the other hand, a C entry means that the I/O update signal to the active register is synchronized with a clock signal derived from the internal system clock (f

/32), as shown in Figure 65.

When reading back a register that has both buffered and active contents, the user can use Register 0004, Bit 0 to select whether to read back the buffer or active contents. Readback of the active contents occurs when Register 0004, Bit 0 = 0, whereas readback of the buffer contents occurs when Register 0004, Bit 0 = 1. Note that a read-only active register requires an I/O update before reading its contents.

MULTIFUNCTION

FROM

PIN LOGIC

EDGE

DETECT

/32

BUFFERED/ACTIVE REGISTERS

There are two broad categories of registers in the AD9548, buffered and active (see Figure 65). Buffered registers are those that can be written to directly from the serial port. They do not need an I/O update to apply their contents to the internal device functions. In contrast, active registers require an I/O update to transfer data between the buffer registers and the internal device functions. In operation, the user programs as many buffer registers as desired and then issues an I/O update. The I/O update occurs by writing to Register 0005, Bit 0 = 1 (or by the external application of the necessary logic level to one of the multifunction pins previously programmed as an I/O update input). The contents of buffer registers connected directly to the internal device functions affect those functions immediately. The contents of buffer registers that connect to active registers do not affect the internal device functions until the I/O update event occurs.

Rev. B | Page 58 of 112

I/O UPDATE

SERIAL

CONTROL

PORT

CS/SDA

SDIO

SDO

SCLK/SCL

BUFFER REGISTERS

Figure 65. Buffered and Active Registers

ACTIVE C

REGISTERS

ACTIVE S

REGISTERS

TO INTERNAL DEVICE FUNCT IONS

AUTOCLEAR REGISTERS

An A in the Opt column of the register map identifies an autoclear register. Typically, the active value for an autoclear register takes effect following an I/O update. The bit is cleared by the internal device logic upon completion of the prescribed action.

08022-041

Page 59

AD9548

REGISTER ACCESS RESTRICTIONS

Read and write access to the register map may be restricted depending on the register in question, the source and direction of access, and the current state of the device. Each register can be classified into one or more access types. When more than one type applies, the most restrictive condition that applies at the moment is used.

Whenever access is denied to a register, all attempts to read the register return a 0 byte, and all attempts to write to the register are ignored. Access to nonexistent registers is handled in the same way as for a denied register.

Regular Access

Registers with regular access do not fall into any other category. Both read and write access to registers of this type can be from either the serial ports or EEPROM controller. However, only

one of these sources can have access to a register at any given time (access is mutually exclusive). Whenever the EEPROM controller is active, either in load or store mode, it has exclusive access to these registers.

Read-Only Access

An R in the Opt column of the register map identifies read-only registers. Access is available at all times, including when the EEPROM controller is active.

Exclusion from EEPROM Access

An E in the Opt column of the register map identifies a register with contents that are inaccessible to the EEPROM. That is, the contents of this type of register cannot be transferred directly to the EEPROM or vice versa. Note that read-only registers (R) are inaccessible to the EEPROM, as well.

Rev. B | Page 59 of 112

Page 60

AD9548

REGISTER MAP

Table 35.

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

Serial port control and part identification 0000 E SPI control Unidirec-

0000 Dup I2C control Unused Soft reset Unused 00 0001 E Reserved Unused 0002 R Silicon revision number C5 0003 R 0004 E Readback Unused Read

0005 A, E I/O update Unused I/O update 00 System clock 0100 S External

0101 S N-divider [7:0] 28 0102 S Unused M-divider

0103 C 40 0104 C 0105 C 0106 C 01 0107 C 0108 C General configuration 0200 S M0 M0 in/out M0 function [6:0] 00 0201 S M1 M1 in/out M1 function [6:0] 00 0202 S M2 M2 in/out M2 function [6:0] 00 0203 S M3 M3 in/out M3 function [6:0] 00 0204 S M4 M4 in/out M4 function [6:0] 00 0205 S M5 M5 in/out M5 function [6:0] 00 0206 S M6 M6 in/out M6 function [6:0] 00 0207 S M7 M7 in/out M7 function [6:0] 00 0208 C IRQ pin

0209 C Unused SYSCLK

020A C Unused Distribution

020B C Switching Closed Freerun Holdover Freq

020C C Unused History

020D C Ref AA

020E C Ref BB

020F C

Reserved

Nom SYSCLK period

System clock stability

output mode IRQ mask

tional

Device ID 48

loop filter enable

Nominal system clock period (femtoseconds) [15:0] [1 ns @ 1 ppm accuracy]

Unused Nominal system clock period [20:16] 0F System clock stability period (milliseconds) [15:0]

Unused System clock stability period (milliseconds) [19:16] 00

Unused IRQ pin output mode

new profile

Ref CC new profile

LSB first/ Inc Addr

Charge pump mode (auto/ man)

reset

Ref AA validated

Ref BB validated

Ref CC validated

Soft reset Long

Charge pump current [2:0] Lock

M-divider [1:0] 2×

unlocked

Ref AA fault cleared

Ref BB fault cleared

Ref CC fault cleared

instruction

SYSCLK locked

updated Ref AA

fault

Ref BB fault

Ref CC fault

Unused 10

detect timer disable

frequency multiplier enable

Unused Unused SYSCLK Cal

sync

unlocked

Frequency unclamped

Ref A new profile

Ref B new profile

Ref C new profile

PLL enable SYSCLK reference select

Watchdog timer

Freq locked

Frequency clamped

Ref A validated

Ref B validated

Ref C validated

buffer register

Lock detect divider [1:0] 18

[1:0]

complete EEPROM

fault Phase

unlocked Phase slew

unlimited Ref A

fault cleared

Ref B fault cleared

Ref C fault cleared

SYSCLK Cal started

EEPROM complete

Phase locked

Phase slew limited

Ref A fault

Ref B fault

Ref C fault

Rev. B | Page 60 of 112

Page 61

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

0210 C Ref DD

0211 C 00 0212 C 0213 S DAC full-scale current [7:0] FF 0214 S

DPLL 0300 C 00 0301 C 00 0302 C 00 0303 C 00 0304 C 00 0305 C 0306 A, C Update TW Unused Update TW 00 0307 C 00 0308 C 00 0309 C 030A C FF 030B C FF 030C C 030D C 00 030E C 030F C 00 0310 C 00 0311 C 00 0312 C 00 0313 C 0314 C E8 0315 C 0316 C 00 0317 C 0318 C 30 0319 C 75 031A C 031B C History

Clock distribution output 0400 S Distribution

0401 S Distribution

0402 S Distribution

0403 C Automatic

0404 S Unused OUT0

0405 S

Watchdog timer

DAC current

Free running frequency tuning word

Pull-in range limits

Open loop phase offset

Closed loop phase offset

Phase slew limit

History accumulation timer

mode

settings

enable

synchronization

Distribution channel modes

new profile

Watchdog timer (ms) [15:0] [up to 65.5 sec]

DAC shutdown

Free running frequency tuning word [47:0]

Pull-in range lower limit [23:0]

Pull-in range upper limit [23:0]

DDS phase offset word [15:0]

Fixed phase lock offset [39:0] (picoseconds; signed)

Incremental phase lock offset step size [15:0] (picoseconds)

Phase slew rate limit [15:0] (ns/sec)

History accumulation timer [23:0] (milliseconds)

Unused Single

Unused External

Unused OUT3

Unused Sync source [1:0] OUT3

Unused Automatic sync mode

Unused OUT1

Ref DD validated

Unused DAC full-scale current

Ref DD fault cleared

distribution resistor

CMOS phase invert

Ref DD fault

sample fallback

Receiver mode

OUT0 polarity invert

OUT1 polarity invert

Ref D new profile

Persistent history

OUT3 powerdown

enable

sync mask

OUT0 drive strength

OUT1 drive strength

Ref D validated

Incremental average [2:0] 00

OUT2 powerdown

OUT2 enable

OUT2 sync mask

OUT0 mode 03

OUT1 mode 03

Ref D fault cleared

[9:8]

OUT1 powerdown

OUT1 enable

OUT1 sync mask

[1:0]

Ref D fault

OUT0 powerdown

OUT0 enable

OUT0 sync mask

Rev. B | Page 61 of 112

Page 62

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

0406 S Unused OUT2

0407 S Unused OUT3

0408 S 00 0409 S 00 040A S 040B S Unused Q0 [29:24] 00 040C S 00 040D S 00 040E S 040F S Unused Q1 [29:24] 00 0410 S 00 0411 S 00 0412 S 0413 S Unused Q2 [29:24] 00 0414 S 00 0415 S 00 0416 S 0417 S Reference inputs 0500 S Reference

0501 S Ref BB logic family [1:0] Ref B logic family [1:0] Ref AA logic family [1:0] Ref A logic family [1:0] 00 0502 S 0503 C Enable Ref

0504 C Enable Ref

0505 C Enable Ref

0506 C

0507 C Phase build-

Profile 0 0600 Priorities Phase lock

0601 00 0602 00 0603 00 0604 00 0605 00 0606 0607 0608 00 0609 060A Unused Inner tolerance [19:16] 00 060B 00 060C 060D

Distribution channel dividers

power-down

Reference logic family

Manual reference profile selection

out switching

Reference period

Tolerance

Q0 [23:0]

Q1 [23:0]

Q2 [23:0]

Q3 [23:0]

Unused Q3 [29:24] 00

Ref DD powerdown

Ref DD logic family [1:0] Ref D logic family [1:0] Ref CC Logic Family [1:0] Ref C Logic Family [1:0] 00

AA manual profile

BB Manual Profile

CC Manual Profile

Enable Ref DD Manual Profile

Unused Phase master threshold priority [2:0] 00

scale Nominal period (femtoseconds) [47:0] (up to 1.125 sec)

Unused Nominal period [49:48] 00 Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm)

Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm)

Unused Outer tolerance [19:16] 00

Ref D powerdown

Ref AA manual profile [2:0] Enable Ref

Ref BB manual profile [2:0] Enable Ref

Ref CC manual profile [2:0] Enable Ref

Ref DD manual profile [2:0] Enable Ref

Unused Promoted priority [2:0] Selection priority [2:0] 00

CMOS phase invert

Ref CC powerdown

OUT2 polarity invert

OUT3 polarity invert

Ref C powerdown

OUT2 drive strength

OUT3 drive strength

Ref BB powerdown

A manual profile

B manual profile

C manual profile

D manual profile

OUT2 mode 03

OUT3 mode 03

Ref B powerdown

Ref A manual profile [2:0] 00

Ref B manual profile [2:0] 00

Ref C manual profile [2:0] 00

Ref D manual profile [2:0] 00

Ref AA powerdown

Ref A powerdown

Rev. B | Page 62 of 112

Page 63

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

060E 00 060F 0610 00 0611 0612 00 0613

0614 Alpha-2 exponent [1:0] Alpha-1 exponent [5:0] 00 0615 Beta-0 linear [6:0] Alpha-2

0616 Beta-0 linear [14:7] 00 0617 Unused Beta-1 exponent [4:0] Beta-0 linear [16:15] 00 0618 00 0619 061A Unused Gamma-1 exponent [4:0] Gamma-0

061B Delta-0 linear [7:0] 00 061C Delta-1

061D 061E 00 061F 00 0620 0621 Unused R [29:24] 00 0622 00 0623 00 0624 0625 Unused S [29:24] 00 0626 V [7:0] 00 0627 U [3:0] Unused V [9:8] 00 0628 0629 00 062A 062B Phase lock fill rate [7:0] 00 062C Phase lock drain rate [7:0] 00 062D 00 062E 00 062F 0630 Frequency lock fill rate [7:0] 00 0631 Profile 1 0632 Priorities Phase lock

0633 00 0634 00 0635 00 0636 00 0637 00 0638 0639 063A 00 063B 063C Unused Inner tolerance [19:16] 00 06CD 00 063E 063F

Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec)

Redetect timeout

Digital loop filter coefficients

Frequency multiplication

Lock detectors

Reference period

Tolerance

Redetect timer (milliseconds) [15:0] [up to 65.5 seconds]

Alpha-0 linear [15:0]

Gamma-0 linear [15:0]

Delta-0 linear [14:8] 00 exponent [0]

Alpha-3 exponent [3:0] Delta-1 exponent [4:1] 00 R [23:0]

S [23:0]

Unused U [9:4] 00 Phase lock threshold (picoseconds) [15:0]

Frequency lock threshold (picoseconds) [23:0]

Frequency lock drain rate [7:0] 00

Unused Promoted priority [2:0] Selection priority [2:0] 00

scale Nominal period (femtoseconds) [47:0] (up to 1.125 sec)

Unused Nominal period [49:48] 00 Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm)

Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm)

Unused Outer tolerance [19:16] 00

Rev. B | Page 63 of 112

00 exponent [2]

00 linear [16]

Page 64

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

0640 00 0641 0642 00 0643 0644 00 0645 0646 Alpha-2 exponent [1:0] Alpha-1 exponent [5:0] 00 0647 Beta-0 linear [6:0] Alpha-2

0648 Beta-0 linear [14:7] 00 0649 Unused Beta-1 exponent [4:0] Beta-0 linear [16:15] 00 064A 00 064B 064C Unused Gamma-1 exponent [4:0] Gamma-0

064D Delta-0 linear [7:0] 00 064E Delta-1 ex-

064F 0650 00 0651 00 0652 0653 Unused R [29:24] 00 0654 00 0655 00 0656 0657 Unused S [29:24] 00 0658 V [7:0] 00 0659 U [3:0] Unused V [9:8] 00 065A 065B 00 065C 065D Phase lock fill rate [7:0] 00 065E Phase lock drain rate [7:0] 00 065F 00 0660 00 0661 0662 Frequency lock fill rate [7:0] 00 0663 0664

to 067F

Profile 2 0680 Priorities Phase lock

0681 00 0682 00 0683 00 0684 00 0685 00 0686 0687 0688 00 0689 068A Unused Inner tolerance [19:16] 00 068B 00 068C

Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec)

Redetect timeout

Digital loop filter coefficients

Frequency multiplication

Lock detectors

Unused

Reference period

Tolerance

Redetect timer (milliseconds) [15:0] (up to 65.5 sec)

Alpha-0 linear [15:0]

exponent [2]

Gamma-0 linear [15:0]

linear [16]

Delta-0 linear [14:8] 00

ponent [0] Alpha-3 exponent [3:0] Delta-1 exponent [4:1] 00 R [23:0]

S [23:0]

Unused U [9:4] 00 Phase lock threshold (picoseconds) [15:0]

Frequency lock threshold (picoseconds) [23:0]

Frequency lock drain rate [7:0] 00

Unused Promoted priority [2:0] Selection priority [2:0] 00

scale Nominal period (femtoseconds) [47:0] (up to 1.125 sec)

Unused Nominal period [49:48] 00 Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm)

Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm)

Rev. B | Page 64 of 112

00 00

Page 65

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

068D Unused Outer tolerance [19:16] 00 068E 00 068F 0690 00 0691 0692 00 0693 0694 Alpha-2 exponent [1:0] Alpha-1 exponent [5:0] 00 0695 Beta-0 linear [6:0] Alpha-2

0696 Beta-0 linear [14:7] 00 0697 Unused Beta-1 exponent [4:0] Beta-0 linear [16:15] 00 0698 00 0699 069A Unused Gamma-1 exponent [4:0] Gamma-0

069B Delta-0 linear [7:0] 00 069C Delta-1

069D 069E 00 069F 00 06A0 06A1 Unused R [29:24] 00 06A2 00 06A3 00 06A4 06A5 Unused S [29:24] 00 06A6 V [7:0] 00 06A7 U [3:0] Unused V [9:8] 00 06A8 06A9 00 06AA 06AB Phase lock fill rate [7:0] 00 06AC Phase lock drain rate [7:0] 00 06AD 00 06AE 00 06AF 06B0 Frequency lock fill rate [7:0] 00 06B1 Profile 3 06B2 Priorities Phase lock

06B3 00 06B4 00 06B5 00 06B6 00 06B7 00 06B8 06B9 06BA 00 06BB 06BC Unused Inner tolerance [19:16] 00 06BD 00 06BE 06BF

Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec)

Redetect timeout

Digital loop filter coefficients

Frequency multiplication

Lock detectors

Reference period

Tolerance

Redetect timer (milliseconds) [15:0] (up to 65.5 seconds)

Alpha-0 linear [15:0]

Gamma-0 linear [15:0]

Delta-0 linear [14:8] 00 exponent [0]

Alpha-3 exponent [3:0] Delta-1 exponent [4:1] 00 R [23:0]

S [23:0]

Unused U [9:4] 00 Phase lock threshold (picoseconds) [15:0]

Frequency lock threshold (picoseconds) [23:0]

Frequency lock drain rate [7:0] 00

Unused Promoted priority [2:0] Selection priority [2:0] 00

scale Nominal period (femtoseconds) [47:0] (up to 1.125 sec)

Unused Nominal period [49:48] 00 Inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm)

Outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm)

Unused Outer tolerance [19:16] 00

Rev. B | Page 65 of 112

00 exponent [2]

00 linear [16]

Page 66

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

06C0 00 06C1 06C2 00 06C3 06C4 00 06C5 06C6 Alpha-2 exponent [1:0] Alpha-1 exponent [5:0] 00 06C7 Beta-0 linear [6:0] Alpha-2

06C8 Beta-0 linear [14:7] 00 06C9 Unused Beta-1 exponent [4:0] Beta-0

06CA 00 06CB 06CC Unused Gamma-1 exponent [4:0] Gamma-0

06CD Delta-0 linear [7:0] 00 06CE Delta-1

06CF 06D0 00 06D1 00 06D2 06D3 Unused R [29:24] 00 06D4 00 06D5 00 06D6 06D7 Unused S [29:24] 00 06D8 V [7:0] 00 06D9 U [3:0] Unused V [9:8] 00 06DA 06DB 00 06DC 06DD Phase lock fill rate [7:0] 00 06DE Phase lock drain rate [7:0] 00 06DF 00 06E0 00 06E1 06E2 Frequency lock fill rate [7:0] 00 06E3 06E4-

06FF Profile 4 through Profile 7 0700-

07FF

Operational controls 0A00 S General

0A01 C Loop

0A02 S Cal/sync Unused Sync

Validation Validation timer (milliseconds) [15:0] (up to 65.5 sec)

Redetect timeout

Digital loop filter coefficients

Frequency multiplication

Lock detectors

Unused

Profile 4

through Profile 7

power-down

mode

Redetect timer (milliseconds) [15:0] (up to 65.5 sec)

Alpha-0 linear [15:0]

exponent [2]

linear [16:15]

Gamma-0 linear [15:0]

exponent [0]

Alpha-3 exponent [3:0] Delta-1 exponent [4:1] 00 R [23:0]

S [23:0]

Unused U [9:4] 00 Phase lock threshold (picoseconds) [15:0]

Frequency lock threshold (picoseconds) [23:0]

Frequency lock drain rate [7:0] 00

The functionality of the Profile 4 through Profile 7 address locations (Address 0700 to Address 07FF) is identical to that of the Profile 0 through Profile 3 address locations (Address 0600 to Address 06FF).

Reset Sans regmap

Unused User

Delta-0 linear [14:8] 00

Unused SYSCLK

holdover

powerdown

User freerun

Reference powerdown

User selection mode [1:0] User reference selection [2:0] 00

TDC powerdown

DAC powerdown

Dist powerdown

distribution

linear [16]

Full powerdown

Calibrate system clock

00 00

Rev. B | Page 66 of 112

Page 67

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

0A03 A, C ResetFunc Unused Clear LF Clear CCI Clear

0A04 A, C Unused SYSCLK

0A05 A, C Unused Distribu-

0A06 A, C Switching Closed Freerun Holdover Freq

0A07 A, C Unused History

0A08 A, C Ref AA

0A09 A, C Ref BB

0A0A A, C Ref CC

0A0B A, C

0A0C A, C Incremental

0A0D A, C Reference

0A0E A, C Force

0A0F C Reference

0A10 C Reference

Status (read only; accessible during EEPROM transactions) 0D00 R EEPROM Unused Fault

0D01 R System clock Unused Stable Unused Unused Cal

0D02 R Unused SYSCLK

0D03 R Unused Distribu-

0D04 R Switching Closed Freerun Holdover Freq

0D05 R Unused History

0D06 R Ref AA

0D07 R Ref BB

0D08 R Ref CC

0D09 R

IRQ clearing

phase offset

profile detect

validation timeout

monitor override

monitor bypass

IRQ monitor

unlocked

new profile

Ref DD new profile

Unused Reset

Detect DD Detect D Detect CC Detect C Detect BB Detect B Detect AA Detect A 00

Force Timeout DD

Ref Mon Override DD

Ref Mon Bypass DD

new profile

Ref DD new profile

Ref AA validated

Ref BB validated

Ref CC validated

Ref DD validated

Force Timeout D

Ref Mon Override D

Ref Mon Bypass D

Ref AA validated

Ref BB validated

Ref CC validated

Ref DD validated

Ref AA fault cleared

Ref BB fault cleared

Ref CC fault cleared

Ref DD fault cleared

Force Timeout CC

Ref Mon Override CC

Ref Mon Bypass CC

unlocked

Ref AA fault cleared

Ref BB fault cleared

Ref CC fault cleared

Ref DD fault cleared

phase accumulator

SYSCLK locked

updated Ref AA

fault

Ref BB fault

Ref CC fault

Ref DD fault

Force Timeout C

Ref Mon Override C

Ref Mon Bypass C

SYSCLK locked

updated Ref AA

fault

Ref BB fault

Ref CC fault

Ref DD fault

Reset auto sync

Unused Unused SYSCLK Cal

tion sync

unlocked Freq un-

clamped Ref A

new profile

Ref B new profile

Ref C new profile

Ref D new profile

Force Timeout BB

Ref Mon Override BB

Ref Mon Bypass BB

Unused Unused SYSCLK Cal

tion sync

unlocked Freq un-

clamped Ref A

new profile

Ref B new profile

Ref C new profile

Ref D new profile

Reset TW history

Watchdog timer

Freq locked

Freq clamped

Ref A validated

Ref B validated

Ref C validated

Ref D validated

phase offset

Force Timeout B

Ref Mon Override B

Ref Mon Bypass B

detected

Watchdog timer

Freq locked

Freq clamped

Ref A validated

Ref B validated

Ref C validated

Ref D validated

Reset all IRQs

complete EEPROM

fault Phase

unlocked Phase slew

unlimited Ref A

fault cleared

Ref B fault cleared

Ref C fault cleared

Ref D fault cleared

Decrement phase offset

Force Timeout AA

Ref Mon Override AA

Ref Mon Bypass AA

Load in progress

in progress

complete EEPROM

fault Phase

unlocked Phase slew

unlimited Ref A

fault cleared

Ref B fault cleared

Ref C fault cleared

Ref D fault cleared

Reset watchdog

SYSCLK Cal started

EEPROM complete

Phase locked

Phase slew limited

Ref A fault

Ref B fault

Ref C fault

Ref D fault

Increment phase offset

Force Timeout A

Ref Mon Override A

Ref Mon Bypass A

Save in progress

Lock detected

SYSCLK Cal started

EEPROM complete

Phase locked

Phase slew limited

Ref A fault

Ref B fault

Ref C fault

Ref D fault

Rev. B | Page 67 of 112

Page 68

AD9548

Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

0D0A R, C Offset slew

0D0B R, C

0D0C R, C Ref A Profile

0D0D R, C Ref AA Profile

0D0E R, C Ref B Profile

0D0F R, C Ref BB Profile

0D10 R, C Ref C Profile

0D11 R, C Ref CC Profile

0D12 R. C Ref D Profile

0D13 R, C Ref DD Profile

0D14 R, C 0D15 R, C 0D16 R, C 0D17 R, C 0D18 R, C 0D19 R, C Nonvolatile memory (EEPROM) control 0E00 Write protect Unused Half rate

0E01 E Condition Unused Condition value [4:0] 00 0E02 A, E Save Unused Save to

0E03 A, E Load Unused Load from

EEPROM storage sequence 0E10 E Data: 9 bytes 08 0E11 E 01 0E12 E 0E13 E I/O update Action: IO_Update 80 0E14 E SYSCLK

0E15 E Data: 21 bytes 14 0E16 E 02 0E17 E 0E18 E Data: 28 bytes 1B 0E19 E 03 0E1A E 0E1B E Data: 26 bytes 19 0E1C E 04 0E1D E 0E1E E I/O update Action: IO_Update 80 0E1F E Data: 8 bytes 07 0E20 E 05 0E21 E 0E22 E Data: 100 bytes 63 0E23 E 06 0E24 E

DPLL status

Holdover history

System clock

calibrate General

DPLL

Clock distribution

Reference inputs

Profile 0 and Profile 1

limiting Frequency

clamped

selected

selected Tuning word readback [47:0]

Address: 0x0100

Action: calibrate system clock A0

Address: 0x0200

Address: 0x0300

Address: 0x0400

Address: 0x0500

Address: 0x0600

Phase build-out

History available

Selected profile [2:0] Valid Fault Fast Slow

Freq lock Phase lock Loop

switching

Active reference priority [3:0] Active reference [3:0]

Holdover Active Free

mode

EEPROM

running

Write enable

EEPROM Unused 00

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Addr Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def

0E25 E Data: 100 bytes 63 0E26 E 06 0E27 E 0E28 E Data: 100 bytes 63 0E29 E 07 0E2A E 0E2B E Data: 100 bytes 63 0E2C E 07 0E2D E 0E2E E I/O update Action: IO_Update 80 0E2F E Data: 17 bytes 10 0E30 E 0A 0E31 E 0E32 E I/O update Action: IO_Update 80 0E33 E End of data Action: end of data FF 0E34

to 0E3F

Profile 2 and Profile 3

Profile 4 and Profile 5

Profile 6 and Profile 7

Operational controls

E Continuation of scratch pad area

Address: 0x0680

Address: 0x0700

Address: 0x0780

Address: 0x0A00

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REGISTER MAP BIT DESCRIPTIONS

SERIAL PORT CONFIGURATION (REGISTER 0000 TO REGISTER 0005)

Table 36. Serial Configuration

Address Bits Bit Name Description

0000 [7] Unidirectional Select SPI port SDO pin operating mode.

0 (default) = 3-wire. 1 = 4-wire (SDO pin enabled).

[6] LSB first Bit order for SPI port.

0 (default) = most significant bit and byte first. 1 = least significant bit and byte first.

[5] Soft reset Device reset (invokes an EEPROM download if M[7:3] ≠ 0).

0 (default) = normal operation. 1 = reset.

[4] Long instruction

[0] Unused

Table 37. Reserved Register

Address Bits Bit Name Description

0001 [7:0] Unused

Table 38. Silicon Revision Level (Read-Only)

Address Bits Bit Name Description

0002 [7:0] Reserved Default = 0xC5 = 0b11000101

16-bit mode (the only mode supported by the device). This bit is read only and reads back as Logic

Table 39. Device ID (Read Only)

Address Bits Bit Name Description

0003 [7:0] Reserved Default = 0x48 = 0b01001000

Table 40. Register Readback Control

Address Bits Bit Name Description

0004 [7:1] Unused

0 Read buffer register

For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer. 0 (default) = reads values currently applied to the internal logic of the device. 1 = reads buffered values that take effect on the next assertion of the I/O update.

Table 41. Soft I/O Update

Address Bits Bit Name Description

0005 [7:1] Unused

0 I/O update

Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the internal control registers of the device. This is an autoclearing bit.

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SYSTEM CLOCK (REGISTER 0100 TO REGISTER 0108)

Table 42. Charge Pump and Lock Detect Control

Address Bits Bit Name Description

0100

[7]

[6] Charge pump mode Charge pump current control

[5:3] Charge pump current Selects charge pump current when Bit 6 = 1

[2]

[1:0] Lock detect timer Select lock detect timer depth

External loop filter enable

Lock detect timer disable

Enables use of an external SYSCLK PLL loop filter 0 (default) = internal loop filter 1 = external loop filter

0 (default) = automatic 1 = manual

000 = 125 A 001 = 250 A 010 = 375 A 011 (default) = 500 A 100 = 625 A 101 = 750 A 110 = 875 A 111 = 1000 A

Enable the SYSCLK PLL lock detect timer 0 (default) = enable 1 = disable

00 (default) = 128 01 = 256 10 = 512 11 = 1024

Table 43. N Divider

Address Bits Bit Name Description

0101 [7:0] N-divider System clock PLL feedback divider value: 6 ≤ N ≤ 255 (default = 0x28 = 40)

Table 44. SYSCLK Input Options

Address Bits Bit Name Description

0102

[7] Unused [6] M-divider reset Reset the M-divider

0 = normal operation 1 (default) = reset When not using the M-divider, program this bit to Logic 1.

[5:4] M-divider System clock input divider

00 (default) = 1 01 = 2 10 = 4 11 = 8

[3]

[2] PLL enable Enable the SYSCLK PLL

[1:0] System clock source Input mode select for SYSCLKx pins

2× frequency multiplier enable

Enable the 2× frequency multiplier 0 (default) = disable 1 = enable

0 = disable 1 (default) = enable

00 = crystal resonator 01 (default) = low frequency clock source 10 = high frequency (direct) clock source 11 = input receiver power-down

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Table 45. Nominal System Clock (SYSCLK) Period1

Address Bits Bit Name Description

0103 [7:0] System clock period, Bits[7:0]

0104 [7:0]

[7:5] Unused 0105 [4:0] System clock period System clock period, Bits[20:16]

Units are femtoseconds. The default value is 0x0F424 = 1,000,000 (1 ns) and implies a system clock frequency of 1 GHz.

Table 46. System Clock Stability Period1

Address Bits Bit Name Description

0106 [7:0] System clock stability period, Bits[7:0] (default = 0x01) 0107 [7:0]

[7:4] Unused 0108 [3:0]

Units are milliseconds. The default value is 0x000001 = 1 (1 ms).

GENERAL CONFIGURATION (REGISTER 0200 TO REGISTER 0214)

Register 0200 to Register 0207—Multifunction Pin Control (M0 to M7)

System clock period (expressed in

femtoseconds)

System clock stability period

System clock period, Bits[15:8]

System clock stability period, Bits[15:8] (default = 0x00)

System clock stability period, Bits[19:16] (default = 0x0) (default period = 0x00001, or 1 ms)

Table 47. Multifunction Pin (M0 to M7) Control1

Address Bits Bit Name Description

0200

[7] M0 in/out In/out control for the M0 pin

0 (default) = input (control pin)

1 = output (status pin) [6:0] M0 function See Table 24 and Table 25 (default = 0xb0000000) [7] M1 in/out In/out control for the M1 pin (same as M0) 0201 [6:0] M1 function See Table 24 and Table 25 (default = 0xb0000000) [7] M2 in/out In/out control for the M2 pin (same as M0) 0202 [6:0] M2 function See Table 24 and Table 25 (default = 0xb0000000) [7] M3 in/out In/out control for the M3 pin (same as M0) 0203 [6:0] M3 function See Table 24 and Table 25 (default = 0xb0000000) [7] M4 in/out In/out control for the M4 pin (same as M0) 0204 [6:0] M4 function See Table 24 and Table 25 (default = 0xb0000000) [7] M5 in/out In/out control for the M5 pin (same as M0) 0205 [6:0] M5 function See Table 24 and Table 25 (default = 0xb0000000) [7] M6 in/out In/out control for the M6 pin (same as M0) 0206 [6:0] M6 function See Table 24 and Table 25 (default = 0xb0000000) [7] M7 in/out In/out control for the M7 pin (same as M0) 0207 [6:0] M7 function See Table 24 and Table 25 (default = 0xb0000000)

The default setting for all the multifunction pins is as an unused control input pin.

Table 48. IRQ Pin Output Mode

Address Bits Bit Name Description

[7:2] Unused 0208 [1:0] IRQ pin output mode Select the output mode of the IRQ pin

00 (default) = NMOS, open drain (requires an external pull-up resistor)

01 = PMOS, open drain (requires an external pull-down resistor)

10 = CMOS, active high

11 = CMOS, active low

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Register 0209 to Register 0210—IRQ Mask

The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0D02 to Address 0D09). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.

Table 49. IRQ Mask for SYSCLK

Address Bits Bit Name Description

0209

Table 50. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM

Address Bits Bit Name Description

020A

[7:6] Unused [5] SYSCLK unlocked Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked [4] SYSCLK locked Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked [3:2] Unused [1] SYSCLK Cal complete Enables IRQ for indicating that SYSCLK calibration has completed [0] SYSCLK Cal started Enables IRQ for indicating that SYSCLK calibration has begun

[7:4] Unused [3] Distribution sync Enables IRQ for indicating a distribution sync event [2] Watchdog timer Enables IRQ for indicating expiration of the watchdog timer [1] EEPROM fault Enables IRQ for indicating a fault during an EEPROM load or save operation [0] EEPROM complete

Enables IRQ for indicating successful completion of an EEPROM load or save operation

Table 51. IRQ Mask for the Digital PLL

Address Bits Bit Name Description

020B

[7] Switching Enables IRQ for indicating that the DPLL is switching to a new reference [6] Closed Enables IRQ for indicating that the DPLL has entered closed-loop operation [5] Freerun Enables IRQ for indicating that the DPLL has entered free-run mode [4] Holdover Enables IRQ for indicating that the DPLL has entered holdover mode [3] Freq unlocked Enables IRQ for indicating that the DPLL lost frequency lock [2] Freq locked Enables IRQ for indicating that the DPLL has acquired frequency lock [1] Phase unlocked Enables IRQ for indicating that the DPLL lost phase lock [0] Phase locked Enables IRQ for indicating that the DPLL has acquired phase lock

Table 52. IRQ Mask for History Update, Frequency Limit, and Phase Slew Limit

Address Bits Bit Name Description

020C

[7:5] Unused [4] History updated Enables IRQ for indicating the occurrence of a tuning word history update [3] Frequency unclamped

[2] Frequency clamped

[1] Phase slew unlimited

[0] Phase slew limited

Enables IRQ for indicating a state transition frequency limiter from clamped to unclamped

Enables IRQ for indicating a state transition of the frequency limiter from unclamped to clamped

Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to not slew limiting

Enables IRQ for indicating a state transition of the phase slew limiter from not slew limiting to slew limiting

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Table 53. IRQ Mask for Reference Inputs

Address Bits Bit Name Description

020D

020E

020F

0210

[7] Ref AA new profile Enables IRQ for indicating that Ref AA has switched to a new profile [6] Ref AA validated Enables IRQ for indicating that Ref AA has been validated [5] Ref AA fault cleared Enables IRQ for indicating that Ref AA has been cleared of a previous fault [4] Ref AA fault Enables IRQ for indicating that Ref AA has been faulted [3] Ref A new profile Enables IRQ for indicating that Ref A has switched to a new profile [2] Ref A validated Enables IRQ for indicating that Ref A has been validated [1] Ref A fault cleared Enables IRQ for indicating that Ref A has been cleared of a previous fault [0] Ref A fault Enables IRQ for indicating that Ref A has been faulted [7] Ref BB new profile Enables IRQ for indicating that Ref BB has switched to a new profile [6] Ref BB validated Enables IRQ for indicating that Ref BB has been validated [5] Ref BB fault cleared Enables IRQ for indicating that Ref BB has been cleared of a previous fault [4] Ref BB fault Enables IRQ for indicating that Ref BB has been faulted [3] Ref B new profile Enables IRQ for indicating that Ref B has switched to a new profile [2] Ref B validated Enables IRQ for indicating that Ref B has been validated [1] Ref B fault cleared Enables IRQ for indicating that Ref B has been cleared of a previous fault [0] Ref B fault Enables IRQ for indicating that Ref B has been faulted [7] Ref CC new profile Enables IRQ for indicating that Ref CC has switched to a new profile [6] Ref CC validated Enables IRQ for indicating that Ref CC has been validated [5] Ref CC fault cleared Enables IRQ for indicating that Ref CC has been cleared of a previous fault [4] Ref CC fault Enables IRQ for indicating that Ref CC has been faulted [3] Ref C new profile Enables IRQ for indicating that Ref C has switched to a new profile [2] Ref C validated Enables IRQ for indicating that Ref C has been validated [1] Ref C fault cleared Enables IRQ for indicating that Ref C has been cleared of a previous fault [0] Ref C fault Enables IRQ for indicating that Ref C has been faulted [7] Ref DD new profile Enables IRQ for indicating that Ref DD has switched to a new profile [6] Ref DD validated Enables IRQ for indicating that Ref DD has been validated [5] Ref DD fault cleared Enables IRQ for indicating that Ref DD has been cleared of a previous fault [4] Ref DD fault Enables IRQ for indicating that Ref DD has been faulted [3] Ref D new profile Enables IRQ for indicating that Ref D has switched to a new profile [2] Ref D validated Enables IRQ for indicating that Ref D has been validated [1] Ref D fault cleared Enables IRQ for indicating that Ref D has been cleared of a previous fault [0] Ref D fault Enables IRQ for indicating that Ref D has been faulted

Table 54. Watchdog Timer1

Address Bits Bit Name Description

0211 [7:0] Watchdog timer, Bits[7:0] (default = 0x00) 0212 [7:0]

The watchdog timer is expressed in milliseconds. The default value is 0 (disabled).

Watchdog timer

Watchdog timer, Bits[15:8] (default = 0x00)

Table 55. Auxiliary DAC1

Address Bits Bit Name Description

0213 [7:0] Full-scale current Full scale current, Bits[7:0] (default = 0xFF)

[7] DAC shutdown Shut down the DAC current sources.

0 (default) = normal operation

0214

[6:2] Unused

1 = shut down

[1:0] Full-scale current Full-scale current, Bits[9:8] (default = 0b01)

(default current = 0x1FF, or 20.1 mA)

The default DAC full-scale current value is 0x01FF = 511, which equates to 20.1375 mA.

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DPLL CONFIGURATION (REGISTER 0300 TO REGISTER 031B)

Table 56. Free Running Frequency Tuning Word1

Address Bits Bit Name Description

0300 [7:0] Free running frequency tuning word, Bits[7:0] 0301 [7:0] Free running frequency tuning word, Bits[15:8] 0302 [7:0] Free running frequency tuning word, Bits[23:9] 0303 [7:0] Free running frequency tuning word, Bits[31:24] 0304 [7:0] Free running frequency tuning word, Bits[39:32] 0305 [7:0]

The default free running tuning word is 0x000000 = 0, which equates to 0 Hz.

Table 57. Update TW

Address Bits Bit Name Description

[7:1] Unused 0306 [0] Update TW

Table 58. Pull-In Range Lower Limit1

Address Bits Bit Name Description

0307 [7:0] Lower limit pull-in range, Bits[7:0]

0308 [7:0] Lower limit pull-in range, Bits[15:8]

0309 [7:0]

Frequency (expressed as a 48-bit

frequency tuning word)

Free running frequency tuning word, Bits[47:40]

A Logic 1 written to this bit transfers the free running frequency tuning word (Register 0300 to Register 0305) to the register imbedded in the tuning word processing logic. Note that it is not necessary to write the update TW bit when the device is in free-run mode. This is an autoclearing bit.

Pull-in range lower limit (expressed as a 24-bit frequency tuning word)

Lower limit pull-in range, Bits[23:9]

030A [7:0] Upper limit pull-in range, Bits[7:0]

Pull-in range upper limit (expressed as a

030B [7:0] Upper limit pull-in range, Bits[15:8]

24-bit frequency tuning word)

030C [7:0]

The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.

Upper limit pull-in range, Bits[23:9]

Table 59. DDS Phase Offset1

Address Bits Bit Name Description

030D [7:0] DDS phase offset, Bits[7:0]

030E [7:0]

The default DDS phase offset is 0.

Open-loop phase offset (expressed in

π/2

radians)

DDS phase offset, Bits[15:8]

Table 60. Fixed Closed-Loop Phase Lock Offset1

Address Bits Bit Name Description

030F [7:0] Fixed phase lock offset, Bits[7:0] 0310 [7:0] Fixed phase lock offset, Bits[15:8] 0311 [7:0] Fixed phase lock offset, Bits[23:16]

Fixed phase lock offset (expressed in pico-seconds)

0312 [7:0] Fixed phase lock offset, Bits[31:24] 0313 [7:0]

The default fixed closed loop phase lock offset is 0.

Fixed phase lock offset, Bits[39:32]

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Table 61. Incremental Closed-Loop Phase Lock Offset Step Size1

Address Bits Bit Name Description

0314 [7:0] Incremental phase lock offset step size, Bits[7:0]

0315 [7:0]

The default incremental closed-loop phase lock offset step size value is 0x03E8 = 1000 (1 ns).

Table 62. Phase Slew Rate Limit1

Address Bits Bit Name Description

0316 [7:0] Phase slew rate limit, Bits[7:0]

0317 [7:0]

The default phase slew rate limit is 0 (or disabled).

Table 63. History Accumulation Timer1

Address Bits Bit Name Description

0318 [7:0] History accumulation timer, Bits[7:0]

0319 [7:0] History accumulation timer, Bits[15:8]

031A [7:0]

Do not program a timer value of 0. The history accumulation timer default value is 0x007530 = 30,000 (30 sec).

Incremental phase lock offset step size (expressed in picoseconds per step)

Phase slew limit (expressed in nano-

seconds per second)

History accumulation timer (expressed in milliseconds)

Incremental phase lock offset step size, Bits[15:8]

Phase slew rate limit, Bits[15:8]

History accumulation timer, Bits[23:16]

Table 64. History Mode

Address Bits Bit Name Description

031B

[7:5] Unused [4] Single-sample fallback

Controls the holdover history. If tuning word history is not available for the reference that was active just prior to holdover, then

0 (default) = use the free running frequency tuning word register value. 1 = use the last tuning word from the DPLL.

[3] Persistent history Controls the holdover history initialization. When switching to a new reference

0 (default) = clear the tuning word history. 1 = retain the previous tuning word history.

[2:0] Incremental average History mode value from 0 to 7 (default = 0).

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CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0400 TO REGISTER 0419)

Table 65. Distribution Settings1

Address Bits Bit Name Description

0400

When Bits[3:0] = 1111, the clock distribution output enters a deep sleep mode.

[7:6] Unused [5]

[4] Receiver mode Clock distribution receiver mode

[3] OUT3 power-down Power-down clock distribution output OUT3

[2] OUT2 power-down Power-down clock distribution output OUT2

[1] OUT1 power-down Power-down clock distribution output OUT1

[0] OUT0 power-down Power-down clock distribution output OUT0

External distribution resistor

Output current control for the clock distribution outputs 0 (default) = internal current setting resistor 1 = external current setting resistor

0 (default) = normal operation 1 = high frequency mode (super-Nyquist)

0 (default) = normal operation 1 = power-down

Table 66. Distribution Enable

Address Bits Bit Name Description

0401

[7:4] Unused [3] OUT3 enable Enable the OUT3 driver.

0 (default) = disable. 1 = enable.

[2] OUT2 enable Enable the OUT2 driver.

0 (default) = disable. 1 = enable.

[1] OUT1 enable Enable the OUT1 driver.

0 (default) = disable. 1 = enable.

[0] OUT0 enable Enable the OUT0 driver.

0 (default) = disable. 1 = enable.

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Table 67. Distribution Synchronization

Address Bits Bit Name Description

0402

Table 68. Automatic Synchronization

Address Bits Bit Name Description

[7:6] Unused [5:4] Sync source Select the sync source for the clock distribution output channels.

00 (default) = direct.

01 = active reference.

10 = DPLL feedback edge.

11 = reserved. [3] OUT3 sync mask Mask the synchronous reset to the OUT3 divider.

0 (default) = unmasked

1 = masked. [2] OUT2 sync mask Mask the synchronous reset to the OUT2 divider.

0 (default) = unmasked.

1 = masked. [1] OUT1 sync mask Mask the synchronous reset to the OUT1 divider.

0 (default) = unmasked.

1 = masked. [0] OUT0 sync mask Mask the synchronous reset to the OUT0 divider.

0 (default) = unmasked.

1 = masked.

[7:2] Unused 0403 [1:0] Automatic sync mode Autosync mode

00 (default) = disabled 01 = sync on DPLL frequency lock 10 = sync on DPLL phase lock 11 = reserved

Table 69. Distribution Channel Modes

Address Bits Bit Name Description

0404

[7:6] Unused [5]

[4] OUT0 polarity invert Invert the polarity of OUT0.

[3] OUT0 drive strength OUT0 output drive capability control.

[2:0] OUT0 mode OUT0 operating mode select.

OUT0 CMOS phase invert

When the output mode is CMOS, the bit inverts the relative phase between the two

CMOS output pins. Otherwise, this bit is nonfunctional.

0 (default) = not inverted.

1 = inverted.

0 (default) = not inverted.

1 = inverted.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength; LVDS: 7 mA nominal.

000 = CMOS (both pins)

001 = CMOS (positive pin), tristate (negative pin).

010 = tristate (positive pin), CMOS (negative pin).

011 (default) = tristate (both pins).

100 = LVDS.

101 = LVPECL.

110 = reserved.

111 = reserved.

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Address Bits Bit Name Description

0405

0406

[7:6] Unused [5]

[4] OUT1 polarity invert Invert the polarity of OUT1.

[3] OUT1 drive strength OUT1 output drive capability control.

[2:0] OUT1 mode OUT1 operating mode select.

[7:6] Unused [5]

[4] OUT2 polarity invert Invert the polarity of OUT2.

[3] OUT2 drive strength OUT2 output drive capability control.

[2:0] OUT2 mode OUT2 operating mode select.

OUT1 CMOS phase invert

OUT2 CMOS phase invert

When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional.

0 (default) = not inverted. 1 = inverted.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength; LVDS: 7 mA nominal.

000 = CMOS (both pins). 001 = CMOS (positive pin), tristate (negative pin). 010 = tristate (positive pin), CMOS (negative pin). 011 (default) = tristate (both pins). 100 = LVDS. 101 = LVPECL. 110 = reserved. 111 = reserved.

When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted.

0 (default) = not inverted. 1 = inverted.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal. 1 = CMOS: normal drive strength; LVDS: 7 mA nominal.

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Address Bits Bit Name Description

0407

Register 0408 to Register 0417—Distribution Channel Dividers

[7:6] Unused [5]

OUT3 CMOS phase invert

When the output mode is CMOS, the bit inverts the relative phase between the two

CMOS output pins. Otherwise, this bit is nonfunctional.

0 (default) = not inverted.

1 = inverted. [4] OUT3 polarity invert Invert the polarity of OUT3.

0 (default) = not inverted.

1 = inverted. [3] OUT3 drive strength OUT3 output drive capability control.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength; LVDS: 7 mA nominal. [2:0] OUT3 mode OUT3 operating mode select.

000 = CMOS (both pins).

001 = CMOS (positive pin), tristate (negative pin).

010 = tristate (positive pin), CMOS (negative pin).

011 (default) = tristate (both pins).

100 = LVDS.

101 = LVPECL.

110 = reserved.

111 = reserved.

Table 70. Q0 Divider1

Address Bits Bit Name Description

0408 [7:0] Q0 divider, Bits[7:0]

Q0 0409 [7:0] Q0 divider, Bits[15:8] 040A [7:0]

Q0 divider, Bits[23:16] [7:6] Unused 040B [5:0] Q0 Q0 divider, Bits[29:24]

The default value is 0 (or divide by 1).

Table 71. Q1 Divider1

Address Bits Bit Name Description

040C [7:0] Q1 divider, Bits[7:0]

Q1 040D [7:0] Q1 divider, Bits[15:8] 040E [7:0]

Q1 divider, Bits[23:16] [7:6] Unused 040F [5:0] Q1 Q1 divider, Bits[29:24]

The default value is 0 (or divide by 1).

Table 72. Q2 Divider1

Address Bits Bit Name Description

0410 [7:0] Q2 divider, Bits[7:0]

Q2 0411 [7:0] Q2 divider, Bits[15:8] 0412 [7:0]

Q2 divider, Bits[23:16] [7:6] Unused 0413 [5:0] Q2 Q2 divider, Bits[29:24]

The default value is 0 (or divide by 1).

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Table 73. Q3 Divider1

Address Bits Bit Name Description

0414 [7:0] Q3 divider, Bits[7:0] 0415 [7:0] Q3 divider, Bits[15:8] 0416 [7:0]

[7:6] Unused 0417 [5:0] Q3 Q3 divider, Bits[29:24]

The default value is 0 (or divide by 1).

REFERENCE INPUT CONFIGURATION (REGISTER 0500 TO REGISTER 0507)

Table 74. Reference Power-Down

When all bits are set, the reference receiver section enters a deep sleep mode.

Address Bits Bit Name Description

0500

[7] Ref DD power-down REF DD input receiver power-down

[6] Ref D power-down REF D input receiver power-down

[5] Ref CC power-down REF CC input receiver power-down

[4] Ref C power-down REF C input receiver power-down

[3] Ref BB power-down REF BB input receiver power-down

[2] Ref B power-down REF B input receiver power-down

[1] Ref AA power-down REF AA input receiver power-down

[0] Ref A power-down REF A input receiver power-down

Q3 divider, Bits[23:16]

0 (default) = normal operation 1 = power-down

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Table 75. Reference Logic Family

Address Bits Bit Name Description

0501

0502

Table 76. Manual Reference Profile Selection

Address Bits Bit Name Description

0503

0504

0505

0506

[7:6] Ref BB logic family Select the logic family for the REF BB input receiver (ignored if Bits[5:4] = 00)

00 (default) = disabled

01 = 1.2 V to 1.5 V CMOS

10 = 1.8 V to 2.5 V CMOS

11 = 3.0 V to 3.3 V CMOS [5:4] Ref B logic family Select logic family for REF B input receiver.

00 (default) = differential (REFB/BB is positive/negative input)

01 = 1.2 V to 1.5 V CMOS

10 = 1.8 V to 2.5 V CMOS

11 = 3.0 V to 3.3 V CMOS [3:2] Ref AA logic family The same as Register 0501, Bits[7:6] but for REF AA [1:0] Ref A logic family The same as Register 0501, Bits[5:4] but for REF A [7:6] Ref DD logic family The same as Register 0501, Bits[7:6] but for REF DD [5:4] Ref D logic family The same as Register 0501, Bits[5:4] but for REF D [3:2] Ref CC logic family The same as Register 0501, Bits[7:6] but for REF CC [1:0] Ref C logic family The same as Register 0501, Bits[5:4] but for REF C

[7]

[6:4] Ref AA manual profile Manual profile assignment

[3]

[2:0] Ref A manual profile Same as Register 0503, Bits[6:4] but for REF A [7]

[6:4] Ref BB manual profile Same as Register 0503, Bits[6:4] but for REF BB [3]

[2:0] Ref B manual profile Same as Register 0503, Bits[6:4] but for REF B [7]

[6:4] Ref CC manual profile Same as Register 0503, Bits[6:4] but for REF CC [3]

[2:0] Ref C manual profile Same as Register 0503, Bits[6:4] but for REF C [7]

[6:4] Ref DD manual profile Same as Register 0503, Bits[6:4] but for REF DD [3]

[2:0] Ref D manual profile Same as Register 0503, Bits[6:4] but for REF D

Enable Ref AA manual profile

Enable Ref A manual profile

Enable Ref BB manual profile

Enable Ref B manual profile

Enable Ref CC manual profile

Enable Ref C manual profile

Enable Ref DD M manual profile

Enable Ref D manual profile

Select manual or automatic reference profile assignment for REF AA

0 (default) = automatic

1 = manual

000 (default) = Profile 0

001 = Profile 1

010 = Profile 2

011 = Profile 3

100 = Profile 4

101 = Profile 5

110 = Profile 6

111 = Profile 7

Same as Register 0503, Bit 7 but for REF A

Same as Register 0503, Bit 7 but for REF B

Same as Register 0503, Bit 7 but for REF CC

Same as Register 050, Bit 7 but for REF C

Same as Register 0503, Bit 7 but for REF DD

Same as Register 0503, Bit 7 but for REF D

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Table 77. Phase Build-Out Switching

Address Bits Bit Name Description

[7:3] Unused 0507 [2:0]

PROFILE REGISTERS (REGISTER 0600 TO REGISTER 07FF)

Note that the default value of every bit is 0 for Profile 0 to Profile 7.

Register 0600 to Register 0631—Profile 0

Table 78. Priorities—Profile 0

Address Bits Bit Name Description

0600

[7] Phase lock scale Controls the phase lock threshold unit scaling.

[6] Unused [5:3] Promoted priority

[2:0] Selection priority

Phase master threshold priority

Threshold priority level (a value of 0 to 7, with 0 (default) being the highest priority level). References with a selection priority value lower than this value are treated as phase masters (see the Profile Registers (Register 0600 to Register 07FF) section for the selection priority value).

0 = picoseconds. 1 = nanoseconds.

User-assigned priority level (0 to 7) of the reference associated with Profile 0 while that reference is the active reference. The numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority.

User-assigned priority level (0 to 7) of the reference associated with Profile 0, which ranks that reference relative to the others.

Table 79. Reference Period—Profile 0

Address Bits Bit Name Description

0601 [7:0] Nominal reference period, Bits[7:0] 0602 [7:0] Nominal reference period, Bits[15:8] 0603 [7:0] Nominal reference period, Bits[23:16] 0604 [7:0] Nominal reference period, Bits[31:24] 0605 [7:0] Nominal reference period, Bits[39:32] 0606 [7:0]

[7:2] Unused 0607 [1:0] Reference period Nominal reference period, Bits[49:48]

Reference period (in femtoseconds)

Nominal reference period, Bits[47:40]

Table 80. Tolerance—Profile 0

Address Bits Bit Name Description

0608 [7:0] Inner tolerance, Bits[7:0] 0609 [7:0]

060A

060B [7:0] Outer tolerance, Bits[7:0] 060C [7:0]

060D

[7:4] Unused [3:0] Inner tolerance Inner tolerance, Bits[19:16]

[7:4] Unused [3:0] Outer tolerance Outer tolerance, Bits[19:16]

Inner tolerance

Inner tolerance, Bits[15:8]

Outer tolerance

Outer tolerance, Bits[5:8]

Table 81. Validation Timer—Profile 0

Address Bits Bit Name Description

060E [7:0] Validation timer, Bits[7:0] 060F [7:0]

Validation timer (in milliseconds)

Validation timer, Bits[15:8]

Table 82. Redetect Timer—Profile 0

Address Bits Bit Name Description

0610 [7:0] Redetect timer, Bits[7:0] 0611 [7:0]

Redetect timer (in milliseconds)

Redetect timer, Bits[15:8]

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Table 83. Digital Loop Filter Coefficients—Profile 01

Address Bits Bit Name Description

0612 [7:0] Alpha-0 coefficient linear, Bits[7:0] 0613 [7:0]

[7:6] Alpha-2 exponent Alpha-2 coefficient exponent, Bits[1:0] 0614 [5:0] Alpha-1 exponent Alpha-1 coefficient exponent, Bits[5:0] [7:1] Beta-0 linear Beta-0 coefficient linear, Bits[6:0] 0615

[0] Alpha-2 exponent Alpha-2 coefficient exponent, Bit 2 0616 [7:0] Beta-0 linear Beta-0 coefficient linear, Bits[14:7] 0617

[7] Unused

[6:2] Beta-1 exponent Beta-1 coefficient exponent, Bits[4:0]

[1:0] Beta-0 linear Beta-0 coefficient linear, Bits[16:15] 0618 [7:0] Gamma-0 coefficient linear, Bits[7:0] 0619 [7:0] 061A

[7:6] Unused

[5:1] Gamma-1 exponent Gamma-1 coefficient exponent, Bits[4:0]

[0] Gamma-0 linear Gamma-0 coefficient linear, Bit 16 061B [7:0] Delta-0 linear Delta-0 coefficient linear, Bits[7:0]

[7] Delta-1 exponent Delta-1 coefficient exponent, Bit 0 061C

[6:0] Delta-0 linear Delta-0 coefficient linear, Bits[14:8]

[7:4] Alpha-3 exponent Alpha-3 coefficient exponent, Bits[3:0] 061D

[3:0] Delta-1 exponent Delta-1 coefficient exponent, Bits[4:1]

The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.

The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.

Alpha-0 linear

Alpha-0 coefficient linear, Bits[15:8]

Gamma-0 linear

Gamma -0 coefficient linear, Bits[15:8]

Table 84. R-Divider—Profile 01

Address Bits Bit Name Description

061E [7:0] R, Bits[7:0]

R 061F [7:0] R, Bits[15:8] 0620 [7:0]

R, Bits[23:16] [7:6] Unused 0621 [5:0] R R, Bits[29:24]

The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.

Table 85. S-Divider—Profile 01

Address Bits Bit Name Description

0622 [7:0] S, Bits[7:0]

S 0623 [7:0] S, Bits[15:8] 0624 [7:0]

S, Bits[23:16] [7:6] Unused 0625 [5:0] S S, Bits[29:24]

The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.

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Table 86. Fractional Feedback Divider—Profile 0

Address Bits Bit Name Description

0626 [7:0] V V, Bits[7:0] 0627

Table 87. Lock Detectors—Profile 0

Address Bits Bit Name Description

0629 [7:0] Phase lock threshold, Bits[7:0] 062A [7:0]

062B [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] 062C [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] 062D [7:0] Frequency lock threshold, Bits[7:0] 062E [7:0] Frequency lock threshold, Bits[15:8] 062F [7:0] 0630 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] 0631 [7:0]

[7:4] U U, Bits[3:0] [3:2] Unused [1:0] V V, Bits[9:8] [7:6] Unused 0628 [5:0] U U, Bits[9:4]

Phase lock threshold (units determined by Register 0x0600[7])

Frequency lock thresh-old (in picoseconds)

Frequency lock drain rate

Phase lock threshold, Bits[15:8]

Frequency lock threshold, Bits[23:16]

Frequency lock drain rate, Bits[7:0]

Register 0632 to Register 067F—Profile 1

Table 88. Priorities—Profile 1

Address Bits Bit Name Description

0632

[7] Phase lock scale Controls the phase lock threshold unit scaling.

0 = picoseconds.

1 = nanoseconds. [6] unused [5:3] Promoted priority

[2:0] Selection priority

User-assigned priority level (0 to 7) of the reference associated with Profile 1 while

that reference is the active reference. The numeric value of the promoted priority

must be less than or equal to the numeric value of the selection priority.

User-assigned priority level (0 to 7) of the reference associated with Profile 1, which

ranks that reference relative to the others.

Table 89. Reference Period—Profile 1

Address Bits Bit Name Description

0633 [7:0] Nominal reference period, Bits[7:0] 0634 [7:0] Nominal reference period, Bits[15:8] 0635 [7:0] Nominal reference period, Bits[23:16] 0636 [7:0] Nominal reference period, Bits[31:24] 0637 [7:0] Nominal reference period, Bits[39:32] 0638 [7:0]

[7:2] Unused 0639 [1:0] Reference period Nominal reference period, Bits[49:48]

Reference period (in femtoseconds)

Nominal reference period, Bits[47:40]

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Table 90. Tolerance—Profile 1

Address Bits Bit Name Description

063A [7:0] Inner tolerance, Bits[7:0] 063B [7:0]

[7:4] Unused 063C

[3:0] Inner tolerance Inner tolerance, Bits[19:16] 063D [7:0] Outer tolerance, Bits[7:0] 063E [7:0]

[7:4] Unused 063F

[3:0] Outer tolerance Outer tolerance, Bits[19:16]

Table 91. Validation Timer—Profile 1

Address Bits Bit Name Description

0640 [7:0] Validation timer, Bits[7:0] 0641 [7:0]

Table 92. Redetect Timer—Profile 1

Address Bits Bit Name Description

0642 [7:0] Redetect timer, Bits[7:0] 0643 [7:0]

Table 93. Digital Loop Filter Coefficients—Profile 11

Address Bits Bit Name Description

0644 [7:0] Alpha-0 coefficient linear, Bits[7:0] 0645 [7:0]

[7:6] Alpha-2 exponent Alpha-2 coefficient exponent, Bits[1:0] 0646

[5:0] Alpha-1 exponent Alpha-1 coefficient exponent, Bits[5:0]

[7:1] Beta -0 linear Beta-0 coefficient linear, Bits[6:0] 0647

[0] Alpha-2 exponent Alpha-2 coefficient exponent, Bit 2 0648 [7:0] Beta-0 linear Beta-0 coefficient linear, Bits[14:7] 0649

[7] Unused

[6:2] Beta-1 exponent Beta-1 coefficient exponent, Bits[4:0]

[1:0] Beta-0 linear Beta-0 coefficient linear, Bits[16:15] 064A [7:0] Gamma-0 coefficient linear, Bits[7:0] 064B [7:0] 064C

[7:6] Unused

[5:1] Gamma-1 exponent Gamma-1 coefficient exponent, Bits[4:0]

[0] Gamma-0 linear Gamma-0 coefficient linear, Bit 16 064D [7:0] Delta-0 linear Delta-0 coefficient linear, Bits[7:0]

[7] Delta-1 exponent Delta-1 coefficient exponent, Bit 0 064E

[6:0] Delta-0 linear Delta-0 coefficient linear, Bits[14:8]

[7:4] Alpha-3 exponent Alpha-3 coefficient exponent, Bits[3:0] 064F

[3:0] Delta-1 exponent Delta-1 coefficient exponent, Bits[4:1]

The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.

The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.

Inner tolerance

Outer tolerance

Validation timer (in milliseconds)

Redetect timer (in milliseconds)

Alpha-0 linear

Gamma-0 linear

Inner tolerance, Bits[15:8]

Outer tolerance, Bits[15:8]

Validation timer, Bits[15:8]

Redetect timer, Bits[15:8]

Alpha-0 coefficient linear, Bits[15:8]

Gamma-0 coefficient linear, Bits[15:8]

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Table 94. R-Divider—Profile 11

Address Bits Bit Name Description

0650 [7:0] R, Bits[7:0] 0651 [7:0] R, Bits[15:8] 0652 [7:0]

[7:6] Unused 0653 [5:0] R R, Bits[29:24]

The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.

Table 95. S-Divider—Profile 11

Address Bits Bit Name Description

0654 [7:0] S, Bits[7:0] 0655 [7:0] S, Bits[15:8] 0656 [7:0]

0657

The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.

[7:6] Unused [5:0] S S, Bits[29:24]

Table 96. Fractional Feedback Divider—Profile 1

Address Bits Bit Name Description

0658 [7:0] V V, Bits[7:0] 0659

[7:4] U U, Bits[3:0] [3:2] Unused [1:0] V V, Bits[9:8] [7:6] Unused 065A [5:0] U U, Bits[9:4]

R, Bits[23:16]

S, Bits[23:16]

Table 97. Lock Detectors—Profile 1

Address Bits Bit Name Description

065B [7:0] Phase lock threshold, Bits[7:0] 065C [7:0]

Phase lock threshold (units determined by Register 0x0632[7])

Phase lock threshold, Bits[15:8]

065D [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] 065E [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] 065F [7:0] Frequency lock threshold, Bits[7:0] 0660 [7:0] Frequency lock threshold, Bits[15:8] 0661 [7:0]

Frequency lock threshold

(in picoseconds)

Frequency lock threshold, Bits[23:16] 0662 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] 0663 [7:0]

Frequency lock drain

Frequency lock drain rate, Bits[7:0]

rate

0664 to 067F [7:0] Unused

Register 0680 to Register 06B1—Profile 2

Table 98. Priorities—Profile 2

Address Bits Bit Name Description

0680

[7] Phase lock scale Controls the phase lock threshold unit scaling.

0 = picoseconds.

1 = nanoseconds. [6] Unused [5:3] Promoted priority

User-assigned priority level (0 to 7) of the reference associated with Profile 2 while

that reference is the active reference. The numeric value of the promoted priority

must be less than or equal to the numeric value of the selection priority. [2:0] Selection priority

User-assigned priority level (0 to 7) of the reference associated with Profile 2, which

ranks that reference relative to the others.

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Table 99. Reference Period—Profile 2

Address Bits Bit Name Description

0681 [7:0] Nominal reference period, Bits[7:0] 0682 [7:0] Nominal reference period, Bits[15:8] 0683 [7:0] Nominal reference period, Bits[23:16] 0684 [7:0] Nominal reference period, Bits[31:24] 0685 [7:0] Nominal reference period, Bits[39:32] 0686 [7:0]

[7:2] Unused 0687 [1:0] Reference period Nominal reference period, Bits[49:48]

Table 100. Tolerance—Profile 2

Address Bits Bit Name Description

0688 [7:0] Inner tolerance, Bits[7:0] 0689 [7:0]

[7:4] Unused 068A

[3:0] Inner tolerance Inner tolerance, Bits[19:16] 068B [7:0] Outer tolerance, Bits[7:0] 068C [7:0]

[7:4] Unused 068D

[3:0] Outer tolerance Outer tolerance, Bits[19:16]

Reference period (in femtoseconds)

Nominal reference period, Bits[47:40]

Inner tolerance

Inner tolerance, Bits[15:8]

Outer tolerance

Outer tolerance, Bits[15:8]

Table 101. Validation Timer—Profile 2

Address Bits Bit Name Description

068E [7:0] Validation timer, Bits[7:0] 068F [7:0]

Validation timer (in milliseconds)

Validation timer, Bits[15:8]

Table 102. Redetect Timer—Profile 2

Address Bits Bit Name Description

0690 [7:0] Redetect timer, Bits[7:0] 0691 [7:0]

Redetect timer (in milliseconds)

Redetect timer, Bits[15:8]

Table 103. Digital Loop Filter Coefficients—Profile 21

Address Bits Bit Name Description

0692 [7:0] Alpha-0 coefficient linear, Bits[7:0] 0693 [7:0]

[7:6] Alpha-2 exponent Alpha-2 coefficient exponent, Bits[1:0] 0694

[5:0] Alpha-1 exponent Alpha-1 coefficient exponent, Bits[5:0]

[7:1] Beta-0 linear Beta-0 coefficient linear, Bits[6:0] 0695

[0] Alpha-2 exponent Alpha-2 coefficient exponent, Bit 2 0696 [7:0] Beta 0-linear Beta-0 coefficient linear, Bits[14:7] 0697

0698 [7:0] Gamma-0 coefficient linear, Bits[7:0] 0699 [7:0] 069A

069B [7:0] Delta-0 linear Delta-0 coefficient linear, Bits[7:0]

[7] Unused

[6:2] Beta-1 exponent Beta-1 coefficient exponent, Bits[4:0]

[1:0] Beta-0 linear Beta-0 coefficient linear, Bits[16:15]

[7:6] Unused

[5:1] Gamma-1 exponent Gamma-1 coefficient exponent, Bits[4:0]

[0] Gamma-0 linear Gamma-0 coefficient linear, Bit 6

Alpha-0 linear

Alpha-0 coefficient linear, Bits[15:8]

Gamma-0 linear

Gamma-0 coefficient linear, Bits[15:8]

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Bits Address Bit Name Description

[7] Delta-1 exponent Delta-1 coefficient exponent, Bit 0 069C [6:0] Delta-0 linear Delta-0 coefficient linear, Bits[14:8] [7:4] Alpha-3 exponent Alpha-3 coefficient exponent, Bits[3:0] 069D [3:0] Delta-1 exponent Delta-1 coefficient exponent, Bits[4:1]

The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.

The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.

Table 104. R-Divider—Profile 21

Address Bits Bit Name Description

069E [7:0] R, Bits[7:0] 069F [7:0] R, Bits[15:8] 06A0 [7:0]

[7:6] Unused 06A1 [5:0] R R, Bits[29:24]

The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.

Table 105. S-Divider—Profile 21

Address Bits Bit Name Description

06A2 [7:0] S, Bits[7:0] 06A3 [7:0] S, Bits[15:8] 06A4 [7:0]

[7:6] Unused 06A5 [5:0] S S, Bits[29:24]

The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.

R, Bits[23:16]

S, Bits[23:16]

Table 106. Fractional Feedback Divider—Profile 2

Address Bits Bit Name Description

06A6 [7:0] V V, Bits[7:0] 06A7

[7:4] U U, Bits[3:0] [3:2] Unused [1:0] V V, Bits[9:8] [7:6] Unused 06A8 [5:0] U U, Bits[9:4]

Table 107. Lock Detectors—Profile 2

Address Bits Bit Name Description

06A9 [7:0] Phase lock threshold, Bits[7:0] 06AA [7:0]

Phase lock threshold (units determined by Register 0x0680[7])

Phase lock threshold, Bits[15:8]

06AB [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] 06AC [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] 06AD [7:0] Frequency lock threshold, Bits[7:0] 06AE [7:0] Frequency lock threshold, Bits[15:8] 06AF [7:0]

Frequency lock thresh-old (in picoseconds)

Frequency lock threshold, Bits[23:16] 06B0 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] 06B1 [7:0]

Frequency lock drain

Frequency lock drain rate, Bits[7:0]

rate

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Register 06B2 to Register 07FF—Profile 3

Table 108. Priorities—Profile 3

Address Bits Bit Name Description

06B2

Table 109. Reference Period—Profile 3

Address Bits Bit Name Description

06B3 [7:0] Nominal reference period, Bits[7:0] 06B4 [7:0] Nominal reference period, Bits[15:8] 06B5 [7:0] Nominal reference period, Bits[23:16] 06B6 [7:0] Nominal reference period, Bits[31:24] 06B7 [7:0] Nominal reference period, Bits[39:32] 06B8 [7:0]

[7] Phase lock scale Controls the phase lock threshold unit scaling.

0 = picoseconds.

1 = nanoseconds. [6] Unused [5:3] Promoted priority

[2:0] Selection priority

Reference period (in femtoseconds)

[7:2] Unused 06B9 [1:0] Reference period Nominal reference period, Bits[49:48]

User-assigned priority level (0 to 7) of the reference associated with Profile 3 while

that reference is the active reference. The numeric value of the promoted priority

must be less than or equal to the numeric value of the selection priority.

User-assigned priority level (0 to 7) of the reference associated with Profile 3, which

ranks that reference relative to the others.

Nominal reference period, Bits[47:40]

Table 110. Tolerance—Profile 3

Address Bits Bit Name Description

06BA [7:0] Inner tolerance, Bits[7:0] 06BB [7:0]

[7:4] Unused 06BC [3:0] Inner tolerance Inner tolerance, Bits[19:16]

06BD [7:0] Outer tolerance, Bits[7:0] 06BE [7:0]

[7:4] Unused 06BF [3:0] Outer tolerance Outer tolerance, Bits[19:16]

Inner tolerance

Inner tolerance, Bits[15:8]

Outer tolerance

Outer tolerance, Bits[15:8]

Table 111. Validation Timer—Profile 3

Address Bits Bit Name Description

06C0 [7:0] Validation timer, Bits[7:0] 06C1 [7:0]

Validation timer (in milliseconds)

Validation timer, Bits[15:8]

Table 112. Redetect Timer—Profile 3

Address Bits Bit Name Description

06C2 [7:0] Redetect timer, Bits[7:0] 06C3 [7:0]

Redetect timer (in milliseconds)

Redetect timer, Bits[15:8]

Table 113. Digital Loop Filter Coefficients—Profile 31

Address Bits Bit Name Description

06C4 [7:0] Alpha-0 coefficient linear, Bits[7:0] 06C5 [7:0]

[7:6] Alpha-2 exponent Alpha-2 coefficient exponent, Bits[1:0] 06C6 [5:0] Alpha-1 exponent Alpha-1 coefficient exponent, Bits[5:0] [7:1] Beta-0 linear Beta-0 coefficient linear, Bits[6:0] 06C7 [0] Alpha-2 exponent Alpha-2 coefficient exponent, Bit 2

06C8 [7:0] Beta-0 linear Beta-0 coefficient linear, Bits[14:7]

Alpha-0 linear

Alpha-0 coefficient linear, Bits[15:8]

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Address Bits Bit Name Description

06C9

06CA [7:0] Gamma-0 coefficient linear, Bits[7:0] 06CB [7:0] 06CC

06CD [7:0] Delta-0 linear Delta-0 coefficient linear, Bits[7:0]

The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.

The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer. See the Calculating Digital Filter Coefficients section for details.

Table 114. R Divider—Profile 31

Address Bits Bit Name Description

06D0 [7:0] R, Bits[7:0] 06D1 [7:0] R, Bits[15:8] 06D2 [7:0]

The value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.

[7] Unused [6:2] Beta-1 exponent Beta-1 coefficient exponent, Bits[4:0] [1:0] Beta-0 linear Beta-0 coefficient linear, Bits[16:15]

Gamma-0 linear

Gamma-0 coefficient linear, Bits[15:8] [7:6] Unused [5:1] Gamma-1 exponent Gamma-1 coefficient exponent, Bits[4:0] [0] Gamma-0 linear Gamma-0 coefficient linear, Bit 16

[7] Delta-1 exponent Delta-1 coefficient exponent, Bit 0 06CE [6:0] Delta-0 linear Delta-0 coefficient linear, Bits[14:8] [7:4] Alpha-3 exponent Alpha-3 coefficient exponent, Bits[3:0] 06CF [3:0] Delta-1 exponent Delta-1 coefficient exponent, Bits[4:1]

R, Bits[23:16] [7:6] Unused 06D3 [5:0] R R, Bits[29:24]

Table 115. S Divider—Profile 31

Address Bits Bit Name Description

06D4 [7:0] S, Bits[7:0]

S 06D5 [7:0] S, Bits[15:8] 06D6 [7:0]

S, Bits[23:16] [7:6] Unused 06D7 [5:0] S S, Bits[29:24]

The value stored in the S-divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.

Table 116. Fractional Feedback Divider—Profile 3

Address Bits Bit Name Description

06D8 [7:0] V V, Bits[7:0] 06D9

[7:4] U U, Bits[3:0] [3:2] Unused [1:0] V V, Bits[9:8] [7:6] Unused 06DA [5:0] U U, Bits[9:4]

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Table 117. Lock Detectors—Profile 3

Address Bits Bit Name Description

06DB [7:0] Phase lock threshold, Bits[7:0] 06DC [7:0]

06DD [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] 06DE [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] 06DF [7:0] Frequency lock threshold, Bits[7:0] 06E0 [7:0] Frequency lock threshold, Bits[15:8] 06E1 [7:0] 06E2 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] 06E3 [7:0]

06E4 to 06FF

[7:0] Unused

Register 0700 to Register 07FF—Profile 4 to Profile 7

Profile 4 (Register 0700 to Register 0731) is identical to Profile 0 (Register 0600 to Register0631).

Profile 5 (Register 0732 to Register 077F) is identical to Profile 1 (Register 0632 to Register 067F).

Profile 6 (Register 0780 to Register 07B1) is identical to Profile 2 (Register 0680 to Register 06B1).

Profile 7 (Register 07B2 to Register 07FF) is identical to Profile 3 (Register 06B2 to Register 06FF).

Phase lock threshold (units determined by Register 0x06B2[7])

Frequency lock thresh-old (in picoseconds)

Frequency lock drain rate

Phase lock threshold, Bits[15:8]

Frequency lock threshold, Bits[23:16]

Frequency lock drain rate, Bits[7:0]

OPERATIONAL CONTROLS (REGISTER 0A00 TO REGISTER 0A10)

Table 118. General Power-Down

Address Bits Bit Name Description

0A00

[7] Reset sans reg map Reset internal hardware but retain programmed register values.

0 (default) = normal operation.

1 = reset. [6] Unused [5] SYSCLK power-down Place SYSCLK input and PLL in deep sleep mode.

0 (default) = normal operation.

1 = power-down. [4]

[3] TDC power-down Place the time-to-digital converter in deep sleep mode.

[2] DAC power-down Place the DAC in deep sleep mode.

[1] Dist power-down Place the clock distribution outputs in deep sleep mode.

[0] Full power-down Place the entire device in deep sleep mode.

Reference powerdown

Place reference clock inputs in deep sleep mode.

0 (default) = normal operation.

1 = power-down.

0 (default) = normal operation.

1 = power-down.

0 (default) = normal operation.

1 = power-down.

0 (default) = normal operation.

1 = power-down.

0 (default) = normal operation.

1 = power-down.

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Table 119. Loop Mode

Address Bits Bit Name Description

0A01

[7] Unused [6] User holdover Force the device into holdover mode.

0 (default) = normal operation. 1 = force device into holdover mode. The device behaves as though all input references are faulted.

[5] User freerun Force the device into free-run mode.

0 (default) = normal operation. 1 = force device into free-run mode. The free running frequency tuning word register specifies the DDS output frequency. Note that, when the user freerun bit is set, it overrides the user holdover bit.

[4:3] User selection mode Select the operating mode of the reference switching state machine.

00 (default) = automatic mode. The fully automatic priority-based algorithm selects the active reference (Bits[2:0] are ignored).

01 = fallback mode. The active reference is the user reference (Bits[2:0]) as long as it is valid. Otherwise, use the fully automatic priority-based algorithm to select the active reference. 10 = holdover mode. The active reference is the user reference (Bits[2:0]) as long as it is valid. Otherwise, enter holdover mode. 11 = manual mode. The active reference is always the user reference (Bits[2:0]). When using manual mode, be sure that the reference declared as the user reference (Bits[2:0]) is programmed for manual reference-to-profile assignment in the appropriate manual reference profile selection register (Address 0503 to Address

0506).

[2:0]

User reference selection

Input reference when user selection mode = 01, 10, or 11. 000 (default) = Input Reference A 001 = Input Reference AA 010 = Input Reference B 011 = Input Reference BB 100 = Input Reference C 101 = Input Reference CC 110 = Input Reference D 111 = Input Reference DD

Table 120. Cal/Sync

Address Bits Bit Name Description

0A02

[7:2] unused [1] Sync distribution

[0]

Calibrate system clock

Setting this bit (default = 0) initiates synchronization of the clock distribution output. While this bit = 1, the clock distribution output stalls. Synchronization occurs on the 1 to 0 transition of this bit.

Setting this bit (default = 0) initiates an internal calibration of the SYSCLK PLL (assuming it is enabled). The calibration routine automatically selects the proper VCO frequency band and signal amplitude. The internal system clock stalls during the calibration procedure, disabling the device until the calibration is complete (a few milliseconds).

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Register 0A03—ResetFunc

Table 121. Reset Functions1

Address Bits Bit Name Description

0A03

All bits in this register are autoclearing.

[7] Unused [6] Clear LF Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool). [5] Clear CCI Setting this bit (default = 0) clears the CCI filter (intended as a debug tool). [4]

[3] Reset auto sync

[2] Reset TW history

[1] Reset all IRQs

[0] Reset watchdog

Clear phase accumulator

Setting this bit (default = 0) clears DDS phase accumulator (not a recommended

action).

Setting this bit (default = 0) resets the automatic synchronization logic

(see Register 0403).

Setting this bit (default = 0) resets the tuning word history logic (part of holdover

functionality).

Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0D02 to

(Register 0A04 to Register 0A0B).

Setting this bit (default = 0) resets the watchdog timer (see Register 0211 to Register

0212). If the timer had timed out, it simply starts a new timing cycle. If the timer has

not yet timed out, it restarts at time zero without causing a timeout event.

Continuously resetting the watchdog timer at intervals less than its timeout period

prevents the watchdog timer from generating a timeout event.

Register 0A04 to Register 0A0B—IRQ Clearing

The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0D02 to Address 0D09). When set to Logic 1, an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ clearing register is an autoclearing register.

Table 122. IRQ Clearing for SYSCLK

Address Bits Bit Name Description

0A04

[7:6] Unused [5] SYSCLK unlocked Clears SYSCLK unlocked IRQ [4] SYSCLK locked Clears SYSCLK locked IRQ [3:2] Unused [1] SYSCLK Cal complete Clears SYSCLK calibration complete IRQ [0] SYSCLK Cal started Clears SYSCLK calibration started IRQ

Table 123. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM

Address Bits Bit Name Description

0A05

[7:4] Unused [3] Distribution sync Clears distribution sync IRQ [2] Watchdog timer Clears watchdog timer IRQ [1] EEPROM fault Clears EEPROM fault IRQ [0] EEPROM complete Clears EEPROM complete IRQ

Table 124. IRQ Clearing for the Digital PLL

Address Bits Bit Name Description

0A06

[7] Switching Clears switching IRQ [6] Closed Clears closed IRQ [5] Freerun Clears freerun IRQ [4] Holdover Clears holdover IRQ [3] Freq unlocked Clears frequency unlocked IRQ [2] Freq locked Clears frequency locked IRQ [1] Phase unlocked Clears phase unlocked IRQ [0] Phase locked Clears phase locked IRQ

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Table 125. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit

Address Bits Bit Name Description

0A07

Table 126. IRQ Clearing for Reference Inputs

Address Bits Bit Name Description

0A08

0A09

0A0A

0A0B

[7:5] Unused [4] History updated Clears history updated IRQ [3] Frequency unclamped Clears frequency unclamped IRQ [2] Frequency clamped Clears frequency clamped IRQ [1] Phase slew unlimited Clears phase slew unlimited IRQ [0] Phase slew limited Clears phase slew limited IRQ

[7] Ref AA new profile Clears Ref AA new profile IRQ [6] Ref AA validated Clears Ref AA validated IRQ [5] Ref AA fault cleared Clears Ref AA fault cleared IRQ [4] Ref AA fault Clears Ref AA fault IRQ [3] Ref A new profile Clears Ref A new profile IRQ [2] Ref A validated Clears Ref A validated IRQ [1] Ref A fault cleared Clears Ref A fault cleared IRQ [0] Ref A fault Clears Ref A fault IRQ [7] Ref BB new profile Clears Ref BB new profile IRQ [6] Ref BB validated Clears Ref BB validated IRQ [5] Ref BB fault cleared Clears Ref BB fault cleared IRQ [4] Ref BB fault Clears Ref BB fault IRQ [3] Ref B new profile Clears Ref B new profile IRQ [2] Ref B validated Clears Ref B validated IRQ [1] Ref B fault cleared Clears Ref B fault cleared IRQ [0] Ref B fault Clears Ref B fault IRQ [7] Ref CC new profile Clears Ref CC new profile IRQ [6] Ref CC validated Clears Ref CC validated IRQ [5] Ref CC fault cleared Clears Ref CC fault cleared IRQ [4] Ref CC fault Clears Ref CC fault IRQ [3] Ref C new profile Clears Ref C new profile IRQ [2] Ref C validated Clears Ref C validated IRQ [1] Ref C fault cleared Clears Ref C fault cleared IRQ [0] Ref C fault Clears Ref C fault IRQ [7] Ref DD new profile Clears Ref DD new profile IRQ [6] Ref DD validated Clears Ref DD validated IRQ [5] Ref DD fault cleared Clears Ref DD fault cleared IRQ [4] Ref DD fault Clears Ref DD fault IRQ [3] Ref D new profile Clears Ref D new profile IRQ [2] Ref D validated Clears Ref D validated IRQ [1] Ref D fault cleared Clears Ref D fault cleared IRQ [0] Ref D fault Clears Ref D fault IRQ

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Table 127. Incremental Phase Offset Control

Address Bits Bit Name Description

0A0C

Table 128. Reference Profile Selection State Machine Startup1

Address Bits Bit Name Description

0A0D

All bits in this register are autoclearing.

[7:3] Unused [2] Reset phase offset Resets the incremental phase offset to 0.

This is an autoclearing bit.

[1] Decr phase offset

Decrements the incremental phase offset by the amount specified in the incremental phase lock offset step size register (Register 0314 to Register 0315).

This is an autoclearing bit.

[0] Incr phase offset

Increments the incremental phase offset by the amount specified in the incremental phase lock offset step size register (Register 0314 to Register 0315). This is an autoclearing bit.

[7] Detect DD Setting this bit starts the profile selection state machine for Input Reference DD. [6] Detect D Setting this bit starts the profile selection state machine for Input Reference D. [5] Detect CC Setting this bit starts the profile selection state machine for Input Reference CC. [4] Detect C Setting this bit starts the profile selection state machine for Input Reference C. [3] Detect BB Setting this bit starts the profile selection state machine for Input Reference BB. [2] Detect B Setting this bit starts the profile selection state machine for Input Reference B. [1] Detect AA Setting this bit starts the profile selection state machine for Input Reference AA. [0] Detect A Setting this bit starts the profile selection state machine for Input Reference A.

Table 129. Reference Validation Override Controls1

Address Bits Bit Name Description

0A0E

[7] Force Timeout DD Setting this bit emulates a timeout of the validation timer for Reference DD.

This is an autoclearing bit.

[6] Force Timeout D Setting this bit emulates a timeout of the validation timer for Reference D.

This is an autoclearing bit.

[5] Force Timeout CC Setting this bit emulates a timeout of the validation timer for Reference CC.

This is an autoclearing bit.

[4] Force Timeout C Setting this bit emulates a timeout of the validation timer for Reference C.

This is an autoclearing bit.

[3] Force Timeout BB Setting this bit emulates a timeout of the validation timer for Reference BB.

This is an autoclearing bit.

[2] Force Timeout B Setting this bit emulates a timeout of the validation timer for Reference B.

This is an autoclearing bit.

[1] Force Timeout AA Setting this bit emulates a timeout of the validation timer for Reference AA.

This is an autoclearing bit.

[0] Force Timeout A Setting this bit emulates a timeout of the validation timer for Reference A.

This is an autoclearing bit.

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Address Bits Bit Name Description

0A0F

0A10

See Figure 34 for details.

STATUS READBACK (REGISTER 0D00 TO REGISTER 0D19)

All bits in Register 0D00 to Register 0D19 are read only.

[7] Ref Mon Override DD

[6] Ref Mon Override D

[5] Ref Mon Override CC

[4] Ref Mon Override C

[3] Ref Mon Override BB

[2] Ref Mon Override B

[1] Ref Mon Override AA

[0] Ref Mon Override A

[7] Ref Mon Bypass DD Bypasses the reference monitor for Reference DD (default = 0, not bypassed). [6] Ref Mon Bypass D Bypasses the reference monitor for Reference D (default = 0, not bypassed). [5] Ref Mon Bypass CC Bypasses the reference monitor for Reference CC (default = 0, not bypassed). [4] Ref Mon Bypass C Bypasses the reference monitor for Reference C (default = 0, not bypassed). [3] Ref Mon Bypass BB Bypasses the reference monitor for Reference BB (default = 0, not bypassed). [2] Ref Mon Bypass B Bypasses the reference monitor for Reference B (default = 0, not bypassed). [1] Ref Mon Bypass AA Bypasses the reference monitor for Reference AA (default = 0, not bypassed). [0] Ref Mon Bypass A Bypasses the reference monitor for Reference A (default = 0, not bypassed).

Overrides the reference monitor REF fault signal for Reference DD (default = 0, not overridden).

Overrides the reference monitor REF fault signal for Reference D (default = 0, not overridden).

Overrides the reference monitor REF fault signal for Reference CC (default = 0, not overridden).

Overrides the reference monitor REF fault signal for Reference C (default = 0, not overridden).

Overrides the reference monitor REF fault signal for Reference BB (default = 0, not overridden).

Overrides the reference monitor REF fault signal for Reference B (default = 0, not overridden).

Overrides the reference monitor REF fault signal for Reference AA (default = 0, not overridden).

Overrides the reference monitor REF fault signal for Reference A (default = 0, not overridden).

Table 130. EEPROM Status

Address Bits Bit Name Description

0D00

[7:3] Unused [2] Fault detected An error occurred while saving data to or loading data from the EEPROM. [1] Load in progress The control logic sets this bit while data is being read from the EEPROM. [0] Save in progress The control logic sets this bit while data is being written to the EEPROM.

Table 131. SYSCLK Status

Address Bits Bit Name Description

0D01

[7:5] Unused [4] Stable

[3:2] Unused [1] Cal in progress The control logic holds this bit set while the system clock calibration is in progress. [0] Lock detected Indicates the status of the system clock PLL.

The control logic sets this bit when the device considers the system clock to be stable (see the System Clock Stability Timer section).

0 = unlocked. 1 = locked (or the PLL is disabled).

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Register 0D02 to Register 0D09—IRQ Monitor

If not masked via the IRQ mask register (Address 0209 to Address 0210), then the appropriate IRQ monitor bit is set to a Logic 1 when the indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0A04 to Address 0A0B), the reset all IRQs bit (Register 0A03, Bit 1), or a device reset.

Table 132. IRQ Monitor for SYSCLK

Address Bits Bit Name Description

0D02

Table 133. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM

Address Bits Bit Name Description

0D03

[7:6] Unused [5] SYSCLK unlocked Indicates a SYSCLK PLL state transition from locked to unlocked [4] SYSCLK locked Indicates a SYSCLK PLL state transition from unlocked to locked [3:2] Unused [1] SYSCLK Cal complete Indicates that SYSCLK calibration has completed [0] SYSCLK Cal started Indicates that SYSCLK calibration has begun

[7:4] Unused [3] Distribution sync Indicates a distribution sync event [2] Watchdog timer Indicates expiration of the watchdog timer [1] EEPROM fault Indicates a fault during an EEPROM load or save operation [0] EEPROM complete Indicates successful completion of an EEPROM load or save operation

Table 134. IRQ Monitor for the Digital PLL

Address Bits Bit Name Description

0D04

[7] Switching Indicates that the DPLL is switching to a new reference [6] Closed Indicates that the DPLL has entered closed-loop operation [5] Freerun Indicates that the DPLL has entered free-run mode [4] Holdover Indicates that the DPLL has entered holdover mode [3] Freq unlocked Indicates that the DPLL lost frequency lock [2] Freq locked Indicates that the DPLL has acquired frequency lock [1] Phase unlocked Indicates that the DPLL lost phase lock [0] Phase locked Indicates that the DPLL has acquired phase lock

Table 135. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit

Address Bits Bit Name Description

0D05

[7:5] Unused [4] History updated Indicates the occurrence of a tuning word history update [3] Freq unclamped Indicates a frequency limiter state transition from clamped to unclamped [2] Freq clamped Indicates a frequency limiter state transition from unclamped to clamped [1] Phase slew unlimited

[0] Phase slew limited

Indicates a phase slew limiter state transition from slew limiting to not slew limiting

Indicates a phase slew limiter state transition from not slew limiting to slew limiting

Table 136. IRQ Monitor for Reference Inputs

Address Bits Bit Name Description

0D06

[7] Ref AA new profile Indicates that Ref AA has switched to a new profile [6] Ref AA validated Indicates that Ref AA has been validated [5] Ref AA fault cleared Indicates that Ref AA has been cleared of a previous fault [4] Ref AA fault Indicates that Ref AA has been faulted [3] Ref A new profile Indicates that Ref A has switched to a new profile [2] Ref A validated Indicates that Ref A has been validated [1] Ref A fault cleared Indicates that Ref A has been cleared of a previous fault [0] Ref A fault Indicates that Ref A has been faulted

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Address Bits Bit Name Description

0D07

0D08

0D09

[7] Ref BB new profile Indicates that Ref BB has switched to a new profile [6] Ref BB validated Indicates that Ref BB has been validated [5] Ref BB fault cleared Indicates that Ref BB has been cleared of a previous fault [4] Ref BB fault Indicates that Ref BB has been faulted [3] Ref B new profile Indicates that Ref B has switched to a new profile [2] Ref B validated Indicates that Ref B has been validated [1] Ref B fault cleared Indicates that Ref B has been cleared of a previous fault [0] Ref B fault Indicates that Ref B has been faulted [7] Ref CC new profile Indicates that Ref CC has switched to a new profile [6] Ref CC validated Indicates that Ref CC has been validated [5] Ref CC fault cleared Indicates that Ref CC has been cleared of a previous fault [4] Ref CC fault Indicates that Ref CC has been faulted [3] Ref C new profile Indicates that Ref C has switched to a new profile [2] Ref C validated Indicates that Ref C has been validated [1] Ref C fault cleared Indicates that Ref C has been cleared of a previous fault [0] Ref C fault Indicates that Ref C has been faulted [7] Ref DD new profile Indicates that Ref DD has switched to a new profile [6] Ref DD validated Indicates that Ref DD has been validated [5] Ref DD fault cleared Indicates that Ref DD has been cleared of a previous fault [4] Ref DD fault Indicates that Ref DD has been faulted [3] Ref D new profile Indicates that Ref D has switched to a new profile [2] Ref D validated Indicates that Ref D has been validated [1] Ref D fault cleared Indicates that Ref D has been cleared of a previous fault [0] Ref D fault Indicates that Ref D has been faulted

Table 137. DPLL Status

Address Bits Bit Name Description

0D0A

0D0B

[7] Offset slew limiting The current closed-loop phase offset is rate limited. [6] Phase build-out A phase build-out transition was made to the currently active reference. [5] Freq lock The DPLL has achieved frequency lock. [4] Phase lock The DPLL has achieved phase lock. [3] Loop switching The DPLL is in the process of a reference switchover. [2] Holdover The DPLL is in holdover mode. [1] Active The DPLL is active (that is, operating in a closed-loop condition) [0] Free running The DPLL is free running (that is, operating in an open-loop condition) [7] Frequency clamped The upper or lower frequency tuning word clamp is in effect. [6] History available There is sufficient tuning word history available for holdover operation. [5:3]

[2:0] Active reference Index of the currently active reference.

Active reference priority

Priority value of the currently active reference. 000 = highest priority. 111 = lowest priority.

000 = Reference A. 001 = Reference AA. 010 = Reference B. 011 = Reference BB. 100 = Reference C. 101 = Reference CC. 110 = Reference D. 111 = Reference DD.

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Table 138. Input Reference Status

Address Bits Bit Name Description

0D0C

0D0D [7:0] Same as 0D0C but for REF AA instead of REF A. 0D0E [7:0] Same as 0D0C but for REF B instead of REF A. 0D0F [7:0] Same as 0D0C but for REF BB instead of REF A. 0D10 [7:0] Same as 0D0C but for REF C instead of REF A. 0D11 [7:0] Same as 0D0C but for REF CC instead of REF A. 0D12 [7:0] Same as 0D0C but for REF D instead of REF A. 0D13 [7:0] Same as 0D0C but for REF DD instead of REF A.

[7] Profile selected The control logic sets this bit when it assigns Ref A to one of the eight profiles. [6:4] Selected profile The index (0 to 7) of the profile assigned to Ref A.

Note that these bits are meaningless unless Bit 7 = 1. [3] Valid Ref A is valid for use (it is unfaulted and its validation timer has expired). [2] Fault Ref A is not valid for use. [1] Fast

[0] Slow

If Bit 7 = 1, then this bit indicates that the frequency of Ref A is higher than allowed

by its profile settings.

If Bit 7 = 0, then this bit indicates that the frequency of Ref A is above the maximum

input reference frequency supported by the device.

If Bit 7 = 1, then this bit indicates that the frequency of Ref A is lower than allowed by

its profile settings.

If Bit 7 = 0, then this bit indicates that the frequency of Ref A is below the minimum

input reference frequency supported by the device.

Table 139. Holdover History1

Address Bits Bit Name Description

0D14 [7:0] Tuning word readback, Bits[7:0] 0D15 [7:0] Tuning word readback, Bits[15:8] 0D16 [7:0] Tuning word readback, Bits[23:9] 0D17 [7:0] Tuning word readback, Bits[31:24] 0D18 [7:0] Tuning word readback, Bits[39:32] 0D19 [7:0]

These registers contain the current 48-bit DDS frequency tuning word generated by the tuning word history logic.

Holdover history

Tuning word readback, Bits[47:40]

NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0E00 TO REGISTER 0E03)

Table 140. EEPROM Control

Address Bits Bit Name Description

0E00

0E03

[7:2] Unused [1] Half rate mode EEPROM serial communication rate.

0 (default) = 400 kHz (normal).

1 = 200 kHz. [0] Write enable EEPROM write enable/protect.

0 (default) = EEPROM write protected.

1 = EEPROM write enabled. [7:5] Unused 0E01 [4:0] Condition value

[7:1] Unused 0E02 0 Save to EEPROM

[7:2] Unused [1] Load from EEPROM Download data from the EEPROM. This is an autoclearing bit. [0] Unused

When set to a nonzero value (default = 0), these bits establish the condition for

EEPROM downloads.

Upload data to the EEPROM based on the EEPROM storage sequence. This is an

autoclearing bit.

Rev. B | Page 100 of 112

Datasheet AD9548 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

SUPPLY VOLTAGE

SUPPLY CURRENT

POWER DISSIPATION

LOGIC INPUTS (M7 TO M0, RESET, TDI, TCLK, TMS)

LOGIC OUTPUTS (M7 TO M0, IRQ, TDO)

SYSTEM CLOCK INPUTS (SYSCLKP/SYSCLKN)

DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)

REFERENCE INPUTS (REFA/REFAA TO REFD/REFDD)

REFERENCE MONITORS

REFERENCE SWITCHOVER SPECIFICATIONS

DISTRIBUTION CLOCK OUTPUTS (OUT0 TO OUT3)

DAC OUTPUT CHARACTERISTICS (DACOUTP/DACOUTN)

TIME DURATION OF DIGITAL FUNCTIONS

DIGITAL PLL

DIGITAL PLL LOCK DETECTION

HOLDOVER SPECIFICATIONS

SERIAL PORT SPECIFICATIONS—SPI MODE

SERIAL PORT SPECIFICATIONS—I2C MODE

JITTER GENERATION

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

GETTING STARTED

POWER-ON RESET

INITIAL PIN PROGRAMMING

DEVICE REGISTER PROGRAMMING

Program the System Clock Functionality

Initialize the System Clock

Calibrate the System Clock (Only if Using SYSCLK PLL)

Program the Multifunction Pins (Optional)

Program the IRQ Functionality (Optional)

Program the Watchdog Timer (Optional)

Program the DAC Full-Scale Current (Optional)

Program the Digital Phase-Locked Loop (DPLL)

Program the Clock Distribution Outputs

Program the Reference Inputs

Program the Reference Profiles

Generate the Reference Acquisition

Generate the Output Clock

THEORY OF OPERATION

OVERVIEW

REFERENCE CLOCK INPUTS

REFERENCE MONITORS

Reference Period Monitor

Reference Validation Timer

Reference Redetect Timer

Reference Validation Override Control

REFERENCE PROFILES

Reference-to-Profile Assignment Control

Reference-to-Profile Assignment State Machine

Reference-to-Profile Assignment

REFERENCE SWITCHOVER

Automatic Priority-Based Reference Switchover

Phase Build-Out Reference Switching

Hitless Reference Switching (Phase Slew Control)

DIGITAL PLL (DPLL) CORE

DPLL Overview

TDC/PFD

Closed-Loop Phase Offset

Programmable Digital Loop Filter

DPLL Phase Lock Detector

DPLL Frequency Lock Detector

DIRECT DIGITAL SYNTHESIZER

DDS Overview

DDS Phase Offset

DAC Output

TUNING WORD PROCESSING