On-chip VCO tunes from 2.05 GHz to 2.33 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Autorecover from holdover
Accepts references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each pair shares 1 to 32 dividers with coarse phase delay
Additive output jitter 225 fs rms
Channel-to-channel skew paired outputs <10 ps
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
Serial control port
48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
AT E
GENERAL DESCRIPTION
The AD9518-21 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz
to 2.33 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz may be used.
The AD9518-2 emphasizes low jitter and phase noise to
max
imize data converter performance, and can benefit other
applications with demanding phase noise and jitter requirements.
Integrated 2.2 GHz VCO
AD9518-2
FUNCTIONAL BLOCK DIAGRAM
PLL
LF
VCO
LVPECL
LVPECL
LVPECL
AD9518-2
STATUS
MONITOR
CP
REF1
REFIN
REF2
SWITCHOVER
AND MONITOR
CLK
SERIAL CONT ROL PORT
DIVIDER
AND MUXs
DIV/Φ
DIV/Φ
DIV/Φ
AND
DIGITAL LOGIC
Figure 1.
The AD9518-2 features six LVPECL outputs (in three pairs).
The LVPECL outputs operate to 1.6 GHz.
Each pair of outputs has dividers that allow both the divide
r
atio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32.
The AD9518-2 is available in a 48-lead LFCSP and can be
op
erated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5.5 V. A
separate LVPECL power supply can be from 2.375 V to 3.6 V.
The AD9518-2 is specified for operation over the industrial
ra
nge of −40°C to +85°C.
1
AD9518 is used throughout to refer to all the members of the AD9518
family. However, when AD9518-2 is used, it is referring to that specific
member of the AD9518 family.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
6431-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
VCO (ON-CHIP)
Frequency Range 2050 2335 MHz See Figure 11
VCO Gain (K
Tunin g Volt age (VT) 0.5 VCP − 0.5 V
Frequency Pushing (Open-Loop) 1 MHz/V
Phase Noise @ 100 kHz Offset −107 dBc/Hz f = 2175 MHz
Phase Noise @ 1 MHz Offset −124 dBc/Hz f = 2175 MHz
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency 0 250 MHz
Input Sensitivity 250 mV p-p
Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs
Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs
Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels
Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p
Input Logic High 2.0 V
Input Logic Low 0.8 V
Input Current −100 +100 μA
Input Capacitance 2 pF
) 50 MHz/V See Figure 6
VCO
= 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; R
S_LVPECL
V This is nominally 2.5 V to 3.3 V ± 5%
S
SET
5.25 V This is nominally 3.3 V to 5.0 V ± 5%
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
tual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground
ac
1.30 1.50 1.60 V
4.4 5.3 6.4 kΩ Self-biased
= 4.12 kΩ; CP
and TA (−40°C to +85°C) variation.
S
≤ VS when using internal VCO; outside of
V
CP
= 5.1 kΩ,
RSET
this range, the CP spurs may increase due to CP
up/down mismatch
Differential mode (can accommodate singleended input by ac grounding undriven input)
Frequencies below about 1 MHz should be
coupled; be careful to match V
dc-
(self-bias voltage)
CM
PLL figure of merit increases with increasing
te; see Figure 10
slew ra
Self-bias voltage of REFIN
1
1
Each pin, REFIN/REFIN
1
1
(REF1/REF2)
Rev. 0 | Page 4 of 64
Page 5
AD9518-2
www.BDTIC.com/ADI
Parameter Min Typ Max Unit Test Conditions/Comments
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Means Within the LBW
of the PLL)
PLL Figure of Merit (FOM) −220 dBc/Hz
V
P = 1 FD 300 MHz
P = 2 FD 600 MHz
P = 3 FD 900 MHz
P = 2 DM (2/3) 600 MHz
P = 4 DM (4/5) 1000 MHz
P = 8 DM (8/9) 2400 MHz
P = 16 DM (16/17) 3000 MHz
P = 32 DM (32/33) 3000 MHz
@ 500 kHz PFD Frequency −165 dBc/Hz
@ 1 MHz PFD Frequency −162 dBc/Hz
@ 10 MHz PFD Frequency −151 dBc/Hz
@ 50 MHz PFD Frequency −143 dBc/Hz
1.5 % 0.5 < CPV < VCP − 0.5 V
A, B counter input frequency (prescaler
input fr
The PLL in-band phase noise floor is estimated
by measuring the in-band phase noise at the
output of the VCO and subtracting 20 log(N)
(where N is the value of the N divider)
Reference slew rate > 0.25 V/ns; FOM + 10 log(f
is an approximation of the PFD/CP in-band
phase noise (in the flat region) inside the PLL
loop bandwidth; when running closed loop,
the phase noise, as observed at the VCO output,
is increased by 20 log(N)
= 5.1 kΩ
RSET
equency divided by P)
PFD
)
Rev. 0 | Page 5 of 64
Page 6
AD9518-2
www.BDTIC.com/ADI
Parameter Min Typ Max Unit Test Conditions/Comments
PLL DIGITAL LOCK DETECT WINDOW
Required to Lock (Coincidence of Edges) Selected by 0x17<1:0> and 0x18<4>
Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b
High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b
High Range (ABP 6 ns) 3.5 ns 0x17<1:0> = 10b; 0x18<4> = 0b
To Unlock After Lock (Hysteresis)
Low Range (ABP 1.3 ns, 2.9 ns) 7 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b
High Range (ABP 1.3 ns, 2.9 ns) 15 ns 0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b
High Range (ABP 6 ns) 11 ns 0x17<1:0> = 10b; 0x18<4> = 0b
1
REFIN and
2
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
REFIN
self-bias points are offset slightly to avoid chatter on an open input condition.
CLOCK INPUTS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK INPUTS (CLK, CLK)
Input Frequency 0
0
Input Sensitivity, Differential 150 mV p-p
Input Level, Differential 2 V p-p
Input Common-Mode Voltage, V
Input Common-Mode Range, V
Input Sensitivity, Single-Ended 150 mV p-p
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CMR
2
2
Signal available at LD, STATUS, and REFMON pins
when se
lected by appropriate register settings
Differential input
1
2.4 GHz High frequency distribution (VCO divider)
1
1.6 GHz Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
w rates > 1 V/ns
with sle
Larger voltage swings may turn on the protection
diodes and can degr
CM
1.3 1.57 1.8 V Self-biased; enables ac coupling
ade jitter performance
1.3 1.8 V With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK
ac-bypassed to RF ground
CLOCK OUTPUTS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Differential (OUT, OUT
Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 16
Output High Voltage (VOH) VS − 1.12 VS − 0.98 VS − 0.84 V
Output Low Voltage (VOL) VS − 2.03 VS − 1.77 VS − 1.49 V
Output Differential Voltage (VOD) 550 790 980 mV
Rev. 0 | Page 6 of 64
)
Page 7
AD9518-2
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TIMING CHARACTERISTICS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV
Output Rise Time, t
Output Fall Time, t
PROPAGATION DELAY, t
High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 27
Clock Distribution Configuration 773 933 1090 ps See Figure 29
Variation with Temperature 0.8 ps/°C
OUTPUT SKEW, LVPECL OUTPUTS
LVPECL Outputs That Share the Same Divider 5 15 ps
LVPECL Outputs on Different Dividers 13 40 ps
All LVPECL Outputs Across Multiple Parts 220 ps
1
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 245 fs rms Calculated from SNR of ADC method; DCC on
Distribution section only; does not include PLL
VCO; uses rising edge of clock signal
Calculated from SNR of ADC method; DCC not used
or even divides
f
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210 fs rms Calculated from SNR of ADC method
Distribution section only; does not include PLL and VCO;
ising edge of clock signal
uses r
and
Rev. 0 | Page 9 of 64
Page 10
AD9518-2
www.BDTIC.com/ADI
SERIAL CONTROL PORT
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
CS (INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 3 μA
Input Logic 0 Current 110 μA
Input Capacitance 2 pF
SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 μA
Input Logic 0 Current 1 μA
Input Capacitance 2 pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current 20 nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, tS, t
CS Minimum Pulse Width High, t
) 25 MHz
SCLK
HI
LO
DS
DH
DV
H
PWH
16 ns
16 ns
2 ns
1.1 ns
8 ns
2 ns
3 ns
CS has an internal 30 kΩ pull-up resistor
PD, SYNC, AND RESET PINS
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 110 μA
Logic 0 Current 1 μA
Capacitance 2 pF
RESET TIMING
Pulse Width Low 50 ns
SYNC TIMING
Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK input signal
Rev. 0 | Page 10 of 64
Page 11
AD9518-2
www.BDTIC.com/ADI
LD, STATUS, AND REFMON PINS
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
Output Voltage High (VOH) 2.7 V
Output Voltage Low (VOL) 0.4 V
MAXIMUM TOGGLE RATE 100 MHz
ANALOG LOCK DETECT
Capacitance 3 pF
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range 1.02 MHz
Extended Range (REF1 and REF2 Only) 8 kHz
LD PIN COMPARATOR
Trip Point 1.6 V
Hysteresis 260 mV
When selected as a digital output (CMOS); there are other
in which these pins are not CMOS digital outputs;
modes
see Table 43, 0x17, 0x1A, and 0x1B
Applies when mux is set to any divid
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
On-chip capacitance; used to calculate RC time constant
or analog lock detect readback; use a pull-up resistor
f
Frequency above which the monitor indicates the
esence of the reference
pr
Frequency above which the monitor indicates the
esence of the reference
pr
er or counter output,
POWER DISSIPATION
Table 16.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled
VCO Divider 30 mW VCO divider not used
REFIN (Differential) 20 mW All references off to differential reference enabled
REF1, REF2 (Single-Ended) 4 mW
VCO 70 mW CLK input selected to VCO selected
PLL 75 mW PLL off to PLL on, normal operation; no reference enabled
Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32
LVPECL Channel (Divider Plus Output Driver) 160 mW No LVPECL output on to one LVPECL output on
LVPECL Driver 90 mW Second LVPECL output turned on, same channel
75 185 mW
31 mW
No clock; no programming; defa
does not include power dissipated in external resistors
PLL on; internal VCO = 2335 MHz; VCO divider = 2;
annel dividers on; six LVPECL outputs @ 584 MHz;
all ch
does not include power dissipated in external resistors
PD pin pulled low; does not include power dissipated
in terminations
All references off to REF1 or REF2 enabled; differential
ference not enabled
re
ult register values;
Rev. 0 | Page 11 of 64
Page 12
AD9518-2
K
www.BDTIC.com/ADI
TIMING DIAGRAMS
t
CLK
CL
DIFFERENTIAL
80%
LVPECL
20%
t
PECL
Figure 2. CLK/
CLK
to Clock Output Timing, DIV = 1
t
06431-060
RP
Figure 3. LVPECL Timing, Differential
t
FP
06431-061
Rev. 0 | Page 12 of 64
Page 13
AD9518-2
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 17.
With
Parameter or Pin
VS, VS_LVPECL GND −0.3 V to +3.6 V
VCP GND −0.3 V to +5.8 V
REFIN, REFIN
REFIN
RSET GND −0.3 V to VS + 0.3 V
CPRSET GND −0.3 V to VS + 0.3 V
CLK, CLK
CLK
SCLK, SDIO, SDO, CS
OUT0, OUT0, OUT1, OUT1,
OUT2, OUT2
OUT4, OUT4
SYNC
REFMON, STATUS, LD GND −0.3 V to VS + 0.3 V
Junction Temperature
Storage Temperature Range −65°C to +150°C
Lead Temperature (10 sec) 300°C
1
See Table 18 for θJA.
, OUT3, OUT3,
, OUT5, OUT5
Respec
t To Rating
GND −0.3 V to VS + 0.3 V
REFIN
GND −0.3 V to VS + 0.3 V
CLK
GND −0.3 V to VS + 0.3 V
GND −0.3 V to VS + 0.3 V
GND −0.3 V to VS + 0.3 V
1
150°C
−3.3 V to +3.3 V
−1.2 V to +1.2 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 18.
Package Type
48-Lead LFCSP 28.5 °C/W
1
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-7.
1
θ
JA
Unit
ESD CAUTION
Rev. 0 | Page 13 of 64
Page 14
AD9518-2
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
BYPASS
VS
CLK
CLK
C
N
=
N
REFIN (REF1)REFIN (REF2)CPRSETVSRSETVSOUT0
4847464544434241403938
1
2
3
4
5
6
7
8
LF
9
10
11
12
O
O
C
13141516171819
SCLK
N
N
T
C
E
PIN 1
INDICATO R
CS
SDO
AD9518-2
TOP VIEW
(Not to Scale)
SDIO
RESET
PD
OUT4
OUT0
VS_LVPECL
OUT1
OUT1
2021222324
OUT4
OUT5
OUT5
VS_LVPECL
Figure 4. Pin Configuration
Table 19. Pin Function Descriptions
Pin No. Mnemonic Description
10, 24 to 26,
VS 3.3 V Power Pins.
35, 37, 43, 45
21, 30, 31, 40 VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
EPAD, 27, 34 GND
1 REFMON
2 LD
3 VCP
4 CP
5 STATUS
6 REF_SEL
7
SYNC
Ground; External Paddle (EPAD).
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 43, 0x1B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 4 3 , 0x1A.
Power Supply for Charge Pump (CP); VS < VCP < 5.0 V.
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 43, 0x17.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is also used
for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor.
8 LF
9 BYPASS
11 CLK
12
CLK
13 SCLK
14
CS
Loop Filter (Input). Connects to VCO control voltage node internally.
This pin is for bypassing the LDO to ground with a capacitor.
Along with CLK, this is the differential input for the clock distribution section.
Along with CLK, this is the differential input for the clock distribution section.
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.
15 SDO Serial Control Port Unidirectional Serial Data Out.
16 SDIO
17
18
RESET
PD
42 OUT0
41
OUT0
39 OUT1
38
OUT1
Serial Control Port Bidirectional Serial Data In/Out.
Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
VS
37
VS
36
C
N
V
35
S
34
G
N
33
OUT2
32
OUT2
31
VS_LVPECL
30
VS_LVPECL
29
OUT3
28
OUT3
27
G
N
26
V
S
25
S
V
D
D
06431-003
Rev. 0 | Page 14 of 64
Page 15
AD9518-2
www.BDTIC.com/ADI
Pin No. Mnemonic Description
33 OUT2 LVPECL Output; One Side of a Differential LVPECL Output.
32
29 OUT3 LVPECL Output; One Side of a Differential LVPECL Output.
28
19 OUT4 LVPECL Output; One Side of a Differential LVPECL Output.
20
22 OUT5 LVPECL Output; One Side of a Differential LVPECL Output.
23
44 RSET Resistor Connected Here Sets Internal Bias Currents. Nominal value = 4.12 kΩ.
46 CPRSET Resistor Connected Here Sets the CP Current Range. Nominal value = 5.1 kΩ.
47
48 REFIN (REF1)
36 NC No Connection.
OUT2
OUT3
OUT4
OUT5
(REF2) Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended
REFIN
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
input for REF2.
Along with REFIN
input for REF1.
, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended
Rev. 0 | Page 15 of 64
Page 16
AD9518-2
–
–
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TYPICAL PERFORMANCE CHARACTERISTICS
300
280
260
240
220
200
180
CURRENT (mA)
160
140
120
100
050010001500200025003000
Figure 5. Current vs. Frequency, Di
3 CHANNELS—6 LVPECL
3 CHANNELS—3 LVPECL
2 CHANNELS—2 LVPECL
1 CHANNEL—1 LVPECL
FREQUENCY (MHz)
rect-to-Output, LVPECL Outputs
48
46
44
42
40
(MHz/V)
38
VCO
K
36
34
32
30
2.002.052.102.152.202.252.302.35
VCO FREQUENCY (GHz)
Figure 6. K
VCO
vs. VCO Frequency
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
CURRENT FROM CP PIN (mA)
1.0
0.5
PUMP DOWNPUMP UP
0
00.51.01.52.02.53.0
Figure 7. Charge Pump Characteristics @ V
VOLTAGE ON CP PIN (V)
= 3.3 V
CP
06431-007
06431-010
06431-011
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
CURRENT FROM CP PIN (mA)
1.0
0.5
0
PUMP DOWNPUMP UP
00.5 1.0 1.5 2.03.04.02.53.55. 04.5
Figure 8. Charge Pump Characteristics @ V
VOLTAGE ON CP PIN (V)
= 5.0 V
CP
140
–145
–150
–155
(dBc/Hz)
–160
–165
PFD PHASE NOI SE REFERRED T O PFD INP UT
–170
0.1110010
PFD FREQUENCY (MHz)
Figure 9. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
An ideal sine wave can be thought of as having a continuous
nd even progression of phase with time from 0° to 360° for
a
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sin
e wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
ome interval of offset frequencies (for example, 10 kHz to
s
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of
Cs, DACs, and RF mixers. It lowers the achievable dynamic
AD
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
do
main, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
C decreases the signal-to-noise ratio (SNR) and dynamic
AD
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
ttributable to the device or subsystem being measured. The
a
phase noise of any external oscillators or clock sources is
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise. When there are multiple contributors to phase
noise, the total is the square root of the sum of squares of the
individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is
ttributable to the device or subsystem being measured. The
a
time jitter of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction with
the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources dominates
the system time jitter.
Rev. 0 | Page 20 of 64
Page 21
AD9518-2
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DETAILED BLOCK DIAGRAM
REFIN (REF 1)
REFIN (REF 2)
BYPASS
CLK
CLK
SYNC
RESET
SCLK
SDIO
SDO
REF1
REF2
LF
PD
CS
REF_ SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPOUT
REGULATOR (LDO)
VCO
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
AD9518-2
SGNDRSET
DISTRIBUTI ON
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5, OR 6
01
N DIVIDER
A/B
COUNTERS
Figure 26. Detailed Block Diagram
REFMO N
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LOCK
DETECT
PHASE
FREQUENCY
DETECT OR
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
06431-002
Rev. 0 | Page 21 of 64
Page 22
AD9518-2
www.BDTIC.com/ADI
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9518 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Tabl e 41 and Ta bl e 42 through Tabl e 48 ). Each section
o
r function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
High Frequency Clock Distribution—CLK or External
VCO >1600 MHz
The AD9518 power-up default configuration has the PLL
powered off and the routing of the input set so that the
CLK
CLK/
through the VCO divider (divide-by-2/divide-by-3/divide-by-4/
divide-by-5/divide-by-6). This is a distribution-only mode that
allows for an external input up to 2.4 GHz (see
max
is 1600 MHz; therefore, higher input frequencies must be divided
down before reaching the channel dividers. This input routing
can also be used for lower input frequencies, but the minimum
divide is 2 before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL
2400 MHz. In this configuration, the internal VCO is not used
and is powered off. The external VCO/VCXO feeds directly into
the prescaler.
The register settings shown in Table 2 0 are the default values
f these registers at power-up or after a reset operation. If the
o
contents of the registers are altered by prior programming after
power-up or reset, these registers may also be set intentionally
to these values.
input is connected to the distribution section
Tabl e 3). The
imum frequency that can be applied to the channel dividers
with an external VCO or VCXO with a frequency less than
Table 20. Default Settings of Some PLL Registers
Register Function
0x10<1:0> = 01b PLL asynchronous power-down (PLL off)
0x1E0<2:0> = 010b Set VCO divider = 4
0x1E1<0> = 0b Use the VCO divider
0x1E1<1> = 0b CLK selected as the source
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 21. Settings When Using an External VCO
Register Function
0x10 to 0x1E PLL normal operation (PLL on)
0x1E1<1> = 0b
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 22. Setting the PFD Polarity
Register Function
0x10<7> = 0b
0x10<7> = 1b
PLL settings; select and enable a reference
input; set R, N
according to the intended loop configuration
PFD polarity positive (higher control
oltage produces higher frequency)
v
PFD polarity negative (higher control
oltage produces lower frequency)
v
(P, A, B), PFD polarity, and I
CP
Rev. 0 | Page 22 of 64
Page 23
AD9518-2
V
T
R
)
VCO
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REFIN ( REF1)
REFIN ( REF2)
BYPASS
CLK
CLK
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
LF
REF_ SELCPRSETVCP
REFERENCE
SWITCHOVER
REF1
REF2
STATUS
LOW DROPOU
EGULATOR (LDO
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
AD9518-2
STATUS
SGNDRSET
DISTRIBUTI ON
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5, OR 6
01
N DIVIDE R
A/B
COUNTERS
REFMO N
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
Figure 27. High Frequency Clock Distribution or External VCO >1600 MHz
LOCK
DETECT
PHASE
FREQUENCY
DETECT OR
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
06431-029
Rev. 0 | Page 23 of 64
Page 24
AD9518-2
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Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the
channel dividers does not exceed its specified maximum frequency
(1.6 GHz, see
ilter to set the loop bandwidth. The external loop filter is also
f
Table 3 ). The internal PLL uses an external loop
crucial to the loop stability.
When using the internal VCO, it is necessary to calibrate the
V
CO (0x18<0>) to ensure optimal performance.
For internal VCO and clock distribution applications, the
re
gister settings shown in Ta b le 2 3 should be used.
REFIN ( REF1)
REFIN ( REF2)
BYPASS
CLK
CLK
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
REF1
REF2
REGULATOR (LDO)
LF
REF_ SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPOUT
VCO
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
AD9518-2
SGNDRSET
DISTRIBUTI ON
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5, OR 6
01
N DIVIDE R
A/B
COUNTERS
Figure 28. Internal VCO and Clock Distribution
Table 23. Settings When Using Internal VCO
Register Function
0x10<1:0> = 00b PLL normal operation (PLL on)
0x10 to 0x1E
PLL settings; select and enable a reference
input; set R, N
(P, A, B), PFD polarity, and I
according to the intended loop configuration
0x18<0> = 0,
0x232<0> = 1
Reset VCO calibration (first time after
power-up, this does not have to be done
but must be done subsequently)
0x18<0> = 1,
Initiate VCO calibration
0x232<0> = 1
0x1E0<2:0>
0x1E1<0> = 0b
VCO divider set to divide-by-2, divide-by-3,
-by-4, divide-by-5, or divide-by-6
divide
Use the VCO divider as source for
istribution section
d
0x1E1<1> = 1b VCO selected as the source
REFMO N
LOCK
DETECT
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
PHASE
FREQUENCY
DETECT OR
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
CP
06431-030
Rev. 0 | Page 24 of 64
Page 25
AD9518-2
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Clock Distribution or External VCO <1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is <1600 MHz, a configuration that bypasses the
VCO divider can be used. This only differs from the
High Frequency Clock Distribution—CLK or External VCO
>1600 MHz section in that the VCO divider (divide-by-2/
divide-by-3/divide-by-4/divide-by-5/divide-by-6) is bypassed.
This limits the frequency of the clock source to <1600 MHz
(due to the maximum input frequency allowed at the channel
dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, the register settings shown in Tab le 2 4 should be used.
Table 24. Settings for Clock Distribution <1600 MHz
When using the internal PLL with an external VCO <1600 MHz,
the PLL must be turned on.
Table 25. Settings for Using Internal PLL with External VCO
<1600 MH
Register Function
0x1E1<0> = 1b
0x10<1:0> = 00b
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 26. Setting the PFD Polarity
Register Function
0x10<7> = 0
0x10<7> = 1
z
Bypass the VCO divider as source for
istribution section
d
PLL normal operation (PLL on) along with
other ap
PFD polarity positive (higher control voltage
pr
PFD polarity negative (higher control
v
propriate PLL settings in 0x10 to 0x1E
oduces higher frequency)
oltage produces lower frequency)
Rev. 0 | Page 25 of 64
Page 26
AD9518-2
V
LOW DROPOUT
REGULATOR (LDO)
VCO
DIVIDE BY
2, 3, 4
6
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REFIN ( REF1)
REFIN ( REF2)
BYPASS
CLK
CLK
SYNC
RESET
SCLK
SDIO
SDO
PD
CS
REF_ SELCPRSETVCP
REFERENCE
SWITCHOVER
REF1
STATUS
REF2
STATUS
LF
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
AD9518-2
SGNDRSET
DISTRIBUTI ON
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
, 5, OR
01
N DIVIDE R
A/B
COUNTERS
REFMO N
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LOCK
DETECT
PHASE
FREQUENCY
DETECT OR
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
06431-028
Figure 29. Clock Distribution or External VCO <1600 MHz
Rev. 0 | Page 26 of 64
Page 27
AD9518-2
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Phase-Locked Loop (PLL)
REF_SEL
SGND
RSET
REFMO N
CPRSET
N DIVIDER
DIST
REF
R DIVIDER
A/B
COUNTERS
0
1
Figure 30. PLL Functional Blocks
REFIN ( REF1)
REFIN ( REF2)
BYPASS
LF
CLK
CLK
REFERENCE
SWITCHOVER
REF1
REF2
LOW DROPOUT
REGULATOR (LDO)
STATUS
VCO
STATUS
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5, OR 6
01
The AD9518 includes an on-chip PLL with an on-chip VCO.
LL blocks can be used either with the on-chip VCO to
The P
create a complete phase-locked loop, or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9518 PLL is useful for generating clock frequencies
rom a supplied reference frequency. This includes conversion
f
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be exploited to
clean up jitter and phase noise on a noisy reference. The exact
choices of PLL parameters and loop dynamics are application
specific. The flexibility and depth of the AD9518 PLL allows
the part to be tailored to function in many different applications
and signal environments.
Configuration of the PLL
The AD9518 allows flexible configuration of the PLL,
accomodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
that include the R divider, the N divider, the PFD polarity (only
applicable to external VCO/VCXO), the antibacklash pulse
width, the charge pump current, the selection of internal VCO
or external VCO/VCXO, and the loop bandwidth. These are
managed through programmable register settings (see
nd Tabl e 43 ) and by the design of the external loop filter.
a
Tabl e 41
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
VCO STATUS
Su
are highly dependent upon proper configuration of the PLL
settings. The design of the external loop filter is crucial to the
proper operation of the PLL. A thorough knowledge of PLL
theory and design is helpful.
ADIsimCLK™ (V1.2 o
with the design and exploration of the capabilities and features
of the AD9518, including the design of the PLL loop filter. It is
available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD
transfer function and minimizes phase noise and reference
spurs. The antibacklash pulse width is set by 0x17<1:0>.
An important limit to keep in mind is the maximum frequency
a
PFD is a function of the antibacklash pulse setting, as specified
in the Phase/Frequency Detector section of
LOCK
DETECT
PHASE
FREQUENCY
DETECTOR
PLL
REF
CHARGE PUMP
HOLD
LD
CP
STATUS
06431-064
ccessful PLL operation and satisfactory PLL loop performance
r later) is a free program that can help
llowed into the PFD. The maximum input frequency into the
Tabl e 2.
Rev. 0 | Page 27 of 64
Page 28
AD9518-2
www.BDTIC.com/ADI
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs,
and tells the CP to pump up or pump down to charge or
discharge the integrating node (part of the loop filter). The
integrated and filtered CP current is transformed into a voltage
that drives the tuning node of the internal VCO through the LF
pin (or the tuning pin of an external VCO) to move the VCO
frequency up or down. The CP can be set (0x10<6:4>) for high
impedance (allows holdover operation), for normal operation
(attempts to lock the PLL loop), for pump up, or for pump
down (test modes). The CP current is programmable in eight
steps from (nominally) 600 μA to 4.8 mA. The exact value of
the CP current LSB is set by the CP_RSET resistor, which is
nominally 5.1 kΩ.
On-Chip VCO
The AD9518 includes an on-chip VCO covering the frequency
range shown in Tab le 2 . Achieving low VCO phase noise was a
riority in the design of the VCO.
p
To tune over the wide range of frequencies covered by this
V
CO, ranges are used. This is largely transparent to the user but
is the reason that the VCO must be calibrated when the PLL
loop is first set up. The calibration procedure ensures that the
VCO is operating within the correct band range for the frequency
that it is asked to produce. See the
itional information.
add
VCO Calibration section for
The on-chip VCO is powered by an on-chip, low dropout
(LD
O), linear voltage regulator. The LDO provides some
isolation of the VCO from variations in the power supply
voltage level. The BYPASS pin should be connected to ground
by a 220 nF capacitor to ensure stability. This LDO employs the
same technology used in the anyCAP® line of regulators from
Analog Devices, Inc., making it insensitive to the type of
capacitor used. Driving an external load from the BYPASS pin
is not supported.
PLL External Loop Filter
When using the internal VCO, the external loop filter should be
referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for the PLL
is shown in
desir
depend upon the VCO frequency, the K
Figure 31. A loop filter must be calculated for each
ed PLL configuration. The values of the components
, the PFD frequency,
VCO
the CP current, the desired loop bandwidth, and the desired
phase margin. The loop filter affects the phase noise, the loop
settling time, and the loop stability. A knowledge of PLL theory
is necessary for understanding the subject of loop filter design.
There are tools available, such as ADIsimCLK, that can help
with the calculation of a loop filter according to the application
requirements.
PLL Reference Inputs
The AD9518 features a flexible PLL reference input circuit that
allows either a fully differential input or two separate singleended inputs. The input frequency range for the reference
inputs is specified in Ta b le 2 . Both the differential and the
sin
gle-ended inputs are self-biased, allowing for easy ac
coupling of input signals.
The differential input and the single-ended inputs share the two
ns, REFIN (REF1)/
pi
type is selected and controlled by 0x1C (see Tab l e 4 1 and Tab l e 4 3).
When the differential reference input is selected, the self-bias
el of the two sides is offset slightly (~100 mV, see Ta b le 2 ) to
lev
p
revent chattering of the input buffer when the reference is slow
or missing. This increases the voltage swing required of the
driver and overcomes the offset.
The single-ended inputs can be driven by either a dc-coupled
C
MOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is p
is not selected. The single-ended buffers power down when the
PLL is powered down, and when their individual power-down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
In differential mode, the reference input pins are internally selfb
iased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by
a single-ended signal, the unused side (
decoupled via a suitable capacitor to a quiet ground. Figure 32
hows the equivalent circuit of REFIN.
s
AD9518-2
LF
VCO
CHARGE
PUMP
Figure 31. Example of External Loop Filter for PLL
CP
BYPASS
= 220nF
C
BP
REFIN
(REF2). The desired reference input
R2
R1
C1C2C3
6431-065
owered down, or when the differential reference input
REFIN
) should be
Rev. 0 | Page 28 of 64
Page 29
AD9518-2
V
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REF1
10kΩ 12kΩ
REFIN
REFIN
10kΩ 10kΩ
REF2
Figure 32. REFIN Equivalent C
85kΩ
85kΩ
S
150Ω
150Ω
V
S
ircuit
V
S
06431-066
Reference Switchover
The AD9518 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9518 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin
REFIN
). This feature supports networking
and other applications that require redundant references. When
using reference switchover, the single-ended reference inputs
should be dc-coupled CMOS levels and should never be allowed
to go to high impedance. If these inputs are allowed to go to high
impedance, noise may cause the buffer to chatter, causing a
false detection of the presence of a reference.
There are several configurable modes of reference switchover.
The s
witchover can be performed manually or automatically.
The manual switchover is done either through a register setting
(0x1C) or by using the REF_SEL pin. The automatic switchover
occurs when REF1 disappears. There is also a switchover deglitch
feature, which ensures that the PLL does not receive rising edges
that are far out of alignment with the newly selected reference.
There are two reference automatic switchover modes (0x1C):
• P
refer REF1: Switch from REF1 to REF2 when REF1
disappears. Return to REF1 from REF2 when REF1 returns.
tay on REF2: Automatically switch to REF2 if REF1 disappears,
• S
but do not switch back to REF1 if it reappears. The reference
can be set back to REF1 manually at an appropriate time.
In automatic mode, REF1 is monitored by REF2. If REF1
d
isappears (two consecutive falling edges of REF2 without an
edge transition on REF1), REF1 is considered missing. Upon
the next subsequent rising edge of REF2, REF2 is used as the
reference clock to the PLL. If 0x1C<3> = 0b (default), when
REF1 returns (four rising edges of REF1 without two falling
edges of REF2 between the REF1 edges), the PLL reference
switches back to REF1. If 0x1C<3> = 1b, the user can control
when to switch back to REF1. This is done by programming the
part to manual reference select mode (0x1C<4> = 0b) and by
ensuring that the registers and/or REF_SEL pin are set to select
the desired reference. Auto mode can be re-enabled once REF1
is reselected.
Manual switchover requires the presence of a clock on the
r
eference input that is being switched to, or that the deglitching
feature be disabled (0x1C<7>).
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16,383 by
writing to 0x11 and 0x12. (Both R = 0 and R = 1 give divide-by-1.)
The output of the R divider goes to one of the PFD inputs to be
compared with the VCO frequency divided by the N divider.
The frequency applied to the PFD must not exceed the maximum
allowable frequency, which depends on the antibacklash pulse
setting (see
Tabl e 2).
The R counter has its own reset. R counter can be reset using
he shared reset bit of the R, A, and B counters. It can also be
t
reset by a
SYNC
operation.
VCXO/VCO Feedback Divider N: P, A, B, R
The N divider is a combination of a prescaler (P) and two counters,
A and B. The total divider value is
N = (P ×
where P ca
B) + A
n be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9518 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3 and dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3, 4
and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of
operation are given in
ailable at all frequencies (see Tabl e 2).
av
Tabl e 43 , 0x16<2:0>. Not all modes are
When operating the AD9518 in dual modulus mode (P//P + 1),
t
he equation used to relate input reference frequency to VCO
output frequency is
= (f
f
VCO
/R) × (P × B + A) = f
REF
× N/R
REF
However, when operating the prescaler in FD mode 1, 2, or 3,
th
e A counter is not used (A = 0) and the equation simplifies to
f
= (f
VCO
/R) × (P × B) = f
REF
× N/R
REF
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
which case the previous equation also applies.
in
Rev. 0 | Page 29 of 64
Page 30
AD9518-2
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By using combinations of DM and FD modes, the AD9518 can
achieve values of N all the way down to N = 1. Tabl e 27 shows
h
ow a 10 MHz reference input may be locked to any integer
multiple of N.
Note that the same value of N may be derived in different ways,
as i
llustrated by the case of N = 12. The user may choose a fixed
divide mode P = 2 with B = 6, use the dual modulus mode 2/3
with A = 0, B = 6, or use the dual modulus mode 4/5 with
A = 0, B = 3.
A and B Counters
The AD9518 B counter can be bypassed (B = 1). This B counter
bypass mode is only valid when using the prescaler in FD mode.
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
Unlike the R counter, an A = 0 is actually a zero. The B counter
ust be ≥3 or bypassed.
m
The maximum input frequency to the A and B counter is
eflected in the maximum prescaler output frequency specified in
r
Tabl e 2. This is the prescaler input frequency (VCO or CLK)
vided by P.
di
Although manual reset is not normally required, the A/B counters
ha
ve their own reset bit. A and B counters can be reset using the
shared reset bit of the R, A, and B counters. They may also be
reset through a
R, A, and B Counters:
The R, A, and B counters may also be reset simultaneously
through the
(see Tabl e 43 ). The
SYNC
operation.
SYNC
Pin Reset
SYNC
pin. This function is controlled by 0x19<7:6>
SYNC
pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays may be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See 0x19 in
Tabl e 43 .
Table 27. How a 10 MHz Reference Input May Be Locked to Any Integer Multiple of N
FREF R P A B N FVCO Mode Notes
10 1 1 X 1 1 10 FD P = 1, B = 1 (bypassed)
10 1 2 X 1 2 20 FD P = 2, B = 1 (bypassed)
10 1 1 X 3 3 30 FD P = 1, B = 3
10 1 1 X 4 4 40 FD P = 1, B = 4
10 1 1 X 5 5 50 FD P = 1, B = 5
10 1 2 X 3 6 60 FD P = 2, B = 3
10 1 2 0 3 6 60 DM P and P + 1 = 2 and 3, A = 0, B = 3
10 1 2 1 3 7 70 DM P and P + 1 = 2 and 3, A = 1, B = 3
10 1 2 2 3 8 80 DM P and P + 1 = 2 and 3, A = 2, B = 3
10 1 2 1 4 9 90 DM P and P + 1 = 2 and 3, A = 1, B = 4
10 1 2 X 5 10 100 FD P = 2, B = 5
10 1 2 0 5 10 100 DM P and P + 1 = 2 and 3, A = 0, B = 5
10 1 2 1 5 11 110 DM P and P + 1 = 2 and 3, A = 1, B = 5
10 1 2 X 6 12 120 FD P = 2, B = 6
10 1 2 0 6 12 120 DM P and P + 1 = 2 and 3, A = 0, B = 6
10 1 4 0 3 12 120 DM P and P + 1 = 4 and 5, A = 0, B = 3
10 1 4 1 3 13 130 DM P and P + 1 = 4 and 5, A = 1, B = 3
Rev. 0 | Page 30 of 64
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DIGITAL LOCK DETECT (DLD)
By selecting the proper output through the mux on each pin, the
DLD function is available at the LD, STATUS, and REFMON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is
indicated when the time difference exceeds a specified value
(the unlock threshold). Note that the unlock threshold is wider
than the lock threshold, which allows some phase error in
excess of the lock window to occur without chattering on the
lock indicator.
The lock detect window timing depends on three settings: the
ital lock detect window bit (0x18<4>), the antibacklash pulse
dig
width setting (0x17<1:0>, see Tabl e 2), and the lock detect
co
unter (0x18<6:5>). A lock is not indicated until there is a
programmable number of consecutive PFD cycles with a time
difference less than the lock detect threshold. The lock detect
circuit continues to indicate a lock until a time difference
greater than the unlock threshold occurs on a single subsequent
cycle. For the lock detect to work properly, the period of the
PFD frequency must be greater than the unlock threshold.
The number of consecutive PFD cycles required for lock is
programmable (0x18<6:5>).
Analog Lock Detect (ALD)
The AD9518 provides an ALD function that may be selected for
use at the LD pin. There are two versions of ALD:
• N-cha
• P
The analog lock detect function requires an R-C filter to
p
Current Source Digital Lock Detect (DLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
nnel open-drain lock detect. This signal requires a
pull-up resistor to the positive supply, VS. The output is
normally high with short, low-going pulses. Lock is indicated
by the minimum duty cycle of the low-going pulses.
-channel open-drain lock detect. This signal requires a pulldown resistor to GND. The output is normally low with
short, high-going pulses. Lock is indicated by the minimum
duty cycle of the high-going pulses.
rovide a logic level indicating lock/unlock.
= 3.3
S
AD9518-2
ALD
Figure 33. Example of Analog Lock Detect Filter Using
N-Chann
LD
el Open-Drain Driver
R2
V
R1
OUT
C
6431-067
current source lock detect function. This function is set by
selecting it as the output from the LD pin control (0x1A<5:0>).
The current source lock detect provides a current of 110 μA
LD is true and shorts to ground when DLD is false.
when D
If a capacitor is connected to the LD pin, it charges at a rate
determined by the current source during the DLD true time
but is discharged nearly instantly when DLD is false. By
monitoring the voltage at the LD pin (top of the capacitor), it is
only possible to get a Logic High level after the DLD has been
true for a sufficiently long time. Any momentary DLD false
resets the charging. By selecting a properly sized capacitor, it is
possible to delay a lock detect indication until the PLL is stably
locked, and the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
co
mparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (0x1B<4:0>) or the STATUS pin control (0x17<7:2>)
as an active high signal. It is also available as an active low signal
(REFMON, 0x1B<4:0> and STATUS, 0x17<7:2>). The internal
LD pin comparator trip point and hysteresis are given in
AD9518-2
110µA
C
V
OUT
CLK
DLD
LD PIN
COMPARAT OR
Figure 34. Current Source Digital Lock Detect
LD
REFMON
OR
STATUS
External VCXO/VCO Clock Input (CLK/
)
Table 1 5.
06431-068
CLK is a differential input that can be used as an input to drive
the AD9518 clock distribution section. This input can receive
up to 2.4 GHz. The pins are internally self-biased, and the input
signal should be ac-coupled via capacitors.
CLOCK INPUT
STAGE
06431-032
The CLK/
VS
LK
LK
2.5kΩ2.5kΩ
5kΩ
5kΩ
Figure 35. CLK Equivalent Input Circuit
CLK
input can be used as a distribution-only
input (with the PLL off ) or as a feedback input for an external
VCO/VCXO using the internal PLL when the internal VCO is
not used. The CLK/
CLK
input can be used for frequencies
up to 2.4 GHz.
Rev. 0 | Page 31 of 64
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AD9518-2
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Holdover
The AD9518 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high impedance
state. This is useful when the PLL reference clock is lost.
Holdover mode allows the VCO to maintain a relatively
constant frequency even though there is no reference clock.
Without this function, the charge pump is placed into a
constant pump-up or pump-down state, resulting in a massive
VCO frequency shift. Because the charge pump is placed in a
high impedance state, any leakage that occurs at the charge
pump output or the VCO tuning node causes a drift of the
VCO frequency. This can be mitigated by using a loop filter
that contains a large capacitive component because this drift is
limited by the current leakage induced slew rate (I
/C) of the
LEAK
VCO control voltage.
SYNC
Both a manual holdover, using the
pin, and an automatic
holdover mode are provided. To use either function, the holdover
function must be enabled (0x1D<0> and 0x1D<2>).
[Note that the VCO cannot be calibrated with the holdover
ena
bled because the holdover resets the N divider during
calibration, which prevents proper calibration. Disable holdover
before issuing a VCO calibration.]
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC
pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump immediately enters a high
impedance state. To take the charge pump out of a high
impedance state, take the
SYNC
pin high. The charge pump
then leaves the high impedance state synchronously with the
next PFD rising edge from the reference clock. This prevents
extraneous charge pump events from occurring during the time
between
SYNC
going high and the next PFD event. This also
means that the charge pump stays in a high impedance state as
long as there is no reference clock present.
The B-counter (in the N divider) is reset synchronously with the
cha
rge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, the channel dividers should be set to
SYNC
nore the
ig
pin (at least after an initial
dividers are not set to ignore the
SYNC
SYNC
event). If the
pin, any time
SYNC
is
taken low to put the part into holdover, the distribution outputs
turn off.
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappears.
A flow chart of the automatic/internal holdover function
peration is shown in Figure 36.
o
PLL ENABLED
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEA VES LOCK AS DET ERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
NO
ANALOG LO CK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x1D<3> = 1: USE L D PIN VOLT AGE
WITH HOLDOVER.
0x1D<3> = 0: IGNO RE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
CHARGE PUMP IS MADE
HIGH IMPEDANCE .
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REM AINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
YES
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE . PLL CAN
NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES ( PROGRAMMING OF THE DLD
DELAY COUNTE R) WITH THE REFERENCE AND
FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT
THE PFD. THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK
BEFORE THE HOLDOVER F UNCTION CAN BE
RETRIGGE RED.
DLD == LOW
YES
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
YES
HIGH IMPEDANCE
CHARGE PUMP
YES
REFERENCE
EDGE AT PFD?
YES
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
YES
DLD == HIGH
NO
NO
NO
Figure 36. Flow Chart of Automatic/Internal Holdover Mode
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (0x1D<3>), which causes the holdover
function to always sense LD as high. If DLD is used, it is
possible for the DLD signal to chatter some while the PLL is
reacquiring lock. The holdover function may retrigger, thereby
preventing the holdover mode from terminating. Use of the
current source lock detect mode is recommended to avoid this
situation (see the
Current Source Digital Lock Detect section).
6431-069
Rev. 0 | Page 32 of 64
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Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
i
s reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps to
align the edges out of the R and N dividers for faster settling of
the PLL and to reduce frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close, resulting in a smaller phase difference for
the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD p
in must charge (if 0x1D<3> = 1b) before it can re-enter
holdover (CP high impedance).
The holdover function always responds to the state of the
urrently selected reference (0x1C). If the loop loses lock during
c
a reference switchover (see the Reference Switchover section),
oldover is triggered briefly until the next reference clock edge
h
at the PFD.
The following registers affect the automatic/internal holdover
nction:
fu
• 0x18<6:5>—lo
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge as well as the delay from the end of a holdover
event until the holdover function can be re-engaged.
• 0x18<3>—disable digital lock detect. This bit must be set to 0
to enable the DLD circuit. Automatic/internal holdover does
not operate correctly without the DLD function enabled.
• 0x1A<5:0>—L
the current source lock detect mode if using the LD pin
comparator. Load the LD pin with a capacitor of an
appropriate value.
ck detect counter. This changes how many
D pin control. Set this to 000100b to put it in
For example, to use automatic holdover with:
utomatic reference switchover, prefer REF1.
• A
• Dig
ital lock detect: five PFD cycles, high range window.
utomatic holdover using the LD pin comparator.
• A
The following registers are set (in addition to the normal PLL
gisters):
re
• 0x18<6:5> = 00b; lo
• 0x18<4> = 0b; l
• 0x18<3> = 0b;
• 0x1A<5
• 0x1C<
• 0x1C<3> = 0b;
• 0x1C<
• 0x1D<3> = 1b;
• 0x1D<2> = 1b;
• 0x1D<
• 0x1D<0> = 1b;
:0> = 000100b; current source lock detect mode.
4> = 1b; automatic reference switchover enabled.
2:1> = 11b; enable REF1 and REF2 input buffers.
1> = 0b; use internal/automatic holdover mode.
ck detect counter = five cycles.
ock detect window = high range.
DLD normal operation.
prefer REF1.
enable LD pin comparator.
enable the holdover function.
enable the holdover function.
Frequency Status Monitors
The AD9518 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 37.
The PLL reference monitors have two threshold frequencies:
n
ormal and extended (see Ta b le 1 5). The reference frequency
m
onitor thresholds are selected in 0x1F.
• 0x1D<3>—LD
disable. When disabled, the holdover function always senses
the LD pin as high.
• 0x1D<1>—ext
• 0x1D<0> an
disabled, both external and automatic/internal holdover are
disabled.
pin comparator enable. 1 = enable; 0 =
ernal holdover control.
d 0x1D<2>—holdover enable. If holdover is
Rev. 0 | Page 33 of 64
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AD9518-2
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REFIN ( REF1)
REFIN ( REF2)
BYPASS
CLK
CLK
REF1
REF2
REGULATOR ( LDO)
LF
REF_SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPOUT
VCO
SGNDRSET
DISTRIBUTI ON
REFERENCE
R
DIVIDER
N DIVIDE R
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5, OR 6
01
Figure 37. Reference and VCO Status Monitors
A/B
COUNTERS
VCO Calibration
The AD9518 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be
present. During the first initialization after a power-up or a
reset of the AD9518, a VCO calibration sequence is initiated by
setting 0x18<0> = 1b. This can be done as part of the initial
setup before executing update registers (0x232<0> = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting 0x18<0> = 0b, executing an update registers
operation, setting 0x18<0> = 1b, and executing another update
registers operation. A readback bit (0x1F<6>) indicates when a
VCO calibration is finished by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is:
• Pr
ogram the PLL registers to the proper values for the PLL loop.
or the initial setting of the registers after a power-up or
• F
reset, initiate VCO calibration by setting 0x18<0> = 1b.
Subsequently, whenever a calibration is desired, set 0x18<0> =
0b, update registers, and set 0x18<0> = 1b, update registers.
YNC operation is initiated internally, causing the outputs
• A S
to go to a static state determined by normal SYNC function
operation.
• V
CO calibrates to the desired setting for the requested VCO
frequency.
• I
nternally, the SYNC signal is released, allowing outputs to
continue clocking.
• P
LL loop is closed.
LL locks.
• P
Rev. 0 | Page 34 of 64
PROGRAMMABLE
PROGRAMMABLE
VCO STATUS
0
1
REFMO N
LD
CP
STATUS
R DELAY
N DELAY
LOCK
DETECT
PHASE
FREQUENCY
DETECT OR
PLL
REFERENCE
CHARGE
PUMP
HOLD
A SYNC is executed during the VCO calibration; therefore, the
o
utputs of the AD9518 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Tabl e 43
(0x18<2:1>).
The calibration divider divides the PFD frequency (reference
requency divided by R) down to the calibration clock. The
f
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
= f
f
CAL_CLOCK
/(R × cal_div)
REFIN
where:
f
is the frequency of the REFIN signal.
REFIN
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(0x18<2:1>).
The VCO calibration takes 4400 calibration clock cycles.
Ther
efore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_
div PLL Reference Clock Cycles
Table 28. Example Time to Complete a VCO Calibration
with Differe
f
(MHz) R Divider PFD Time to Calibrate VCO
REFIN
nt f
Frequencies
REFIN
100 1 100 MHz 88 μs
10 10 1 MHz 8.8 ms
10 100 100 kHz 88 ms
06431-070
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AD9518-2
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VCO calibration must be manually initiated. This allows for
flexibility in deciding what order to program registers and when
to initiate a calibration, instead of having it happen every time
certain PLL registers have their values changed. For example,
this allows for the VCO frequency to be changed by small
amounts without having an automatic calibration occur each
time; this should be done with caution and only when the user
knows the VCO control voltage is not going to exceed the nominal
best performance limits. For example, a few 100 kHz steps are
fine, but a few MHz might not be. Additionally, because the
calibration procedure results in rapid changes in the VCO
frequency, the distribution section is automatically placed in
SYNC until the calibration is finished. Therefore, this
temporary loss of outputs must be expected.
A VCO calibration should be initiated under the following
nditions:
co
ter changing any of the PLL R, P, B, and A divider settings,
• Af
or after a change in the PLL reference clock frequency. This,
in effect, means any time a PLL register or reference clock is
changed such that a different VCO frequency results.
henever system calibration is desired. The VCO is designed
• W
to operate properly over extremes of temperatures even when
it is first calibrated at the opposite extreme. However, a VCO
calibration can be initiated at any time, if desired.
CLOCK DISTRIBUTION
A clock channel consists of a pair of outputs that share a
common divider. The AD9518 has three channels, each with
two LVPECL outputs, for a total of six LVPECL outputs.
Each channel has its own programmable divider that divides the
lock frequency applied to its input by any integer from 1 to 32.
c
Because the internal VCO frequency is above the maximum
c
hannel divider input frequency (1600 MHz), the VCO divider
must be used after the on-chip VCO. The VCO divider can be
set to divide by 2, 3, 4, 5, or 6. External clock signals connected
to the CLK input also require the VCO divider if the frequency
of the signal is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
dep
ending on the currently set division; that is, for any specific
division, D, the output of the divider can be set to high for
N + 1 input clock cycles and low for M + 1 input clock cycles
(where D = N + M + 2). For example, a divide-by-5 can be high
for one divider input cycle and low for four cycles, or a divideby-5 can be high for three divider input cycles and low for two
cycles. Other combinations are also possible.
The channel dividers include a duty-cycle correction function
tha
t can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
y to be set. Depending on the division selected, the output
dela
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or to start low.
Internal VCO or External CLK as Clock Source
The clock distribution of the AD9518 has two clock input
sources: an internal VCO or an external clock connected to the
CLK
CLK/
chosen as the source of the clock signal to distribute. When the
internal VCO is selected as the source, the VCO divider must be
used. When CLK is selected as the source, it is not necessary to
use the VCO divider if the CLK frequency is less than the
maximum channel divider input frequency (1600 MHz);
otherwise, the VCO divider must be used to reduce the
frequency to one acceptable by the channel dividers.
s
hows how the VCO, CLK, and VCO divider are selected.
0x1E1<1:0> selects the channel divider source and determines
whether the VCO divider is used. It is not possible to select the
VCO without using the VCO divider.
Table 29. Selecting VCO or CLK as Source for Channel
Di
<1> <0>
0 0 CLK Used
0 1 CLK Not used
1 0 VCO Used
1 1 Not allowed Not allowed
pins. Either the internal VCO or CLK must be
Tabl e 29
vider, and Whether VCO Divider Is Used
0x1E1
Channel Divider Source VCO Divider
CLK or VCO Direct to LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs, OUT0 to OUT5. This configuration
can pass frequencies up to the maximum frequency of the VCO
directly to the LVPECL outputs. The LVPECL outputs may not
be able to provide a full voltage swing at the highest frequencies.
To connect the LVPECL outputs directly to the internal VCO or
he VCO divider must be selected as the source to the
CLK, t
distribution section, even if no channel uses it.
Either the internal VCO or the CLK can be selected as the
ource for the direct to output routing.
s
Table 30. Settings for Routing VCO Divider Input Directly
to LVPECL
Register Setting Selection
0x1E1<1:0> = 00b CLK is the source; VCO divider selected
0x1E1<1:0> = 10b VCO is the source; VCO divider selected
0x192<1> = 1b Direct to output OUT0, OUT1
0x195<1> = 1b Direct to output OUT2, OUT3
0x198<1> = 1b Direct to output OUT4, OUT5
Outputs
Rev. 0 | Page 35 of 64
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AD9518-2
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Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, or 6) and
the division of the channel divider.
f
requency division for a channel is set.
Table 3 1 indicates how the
Table 31. Frequency Division for Divider 0 to Divider 2
CLK or VCO
Selected
CLK/VCO 2 to 6 1 (bypassed) Yes 1
CLK/VCO 2 to 6 1 (bypassed) No (2 to 6) × (1)
CLK/VCO 2 to 6 2 to 32 No
CLK
CLK
VCO
Divider
Not
used
Not
used
Channel
Divider
1 (bypassed) No 1
2 to 32 No 2 to 32
Direct to
Output
Frequency
Division
(2 to 6) ×
(2 to 32)
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 1 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see
Tabl e 41 through Tab le 4 8).
VCO Divider
The VCO divider provides frequency division between the
internal VCO and the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Tab le 4 6 , 0x1E0<2:0>).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving six
LVPECL outputs (OUT0 to OUT5). Tab le 3 2 gives the register
l
ocations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting of
the DCCOFF bits.
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, D
, is set by the values of M and N
X
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The cycles are cycles of the clock signal currently routed to the
in
put of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, D
Otherwise, D
= (N + 1) + (M + 1) = N + M + 2. This allows
X
= 1.
X
each channel divider to divide by any integer from 1 to 32.
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
hat are the M and N values for the channel?
• W
• I
s the DCC enabled?
• I
s the VCO divider used?
at is the CLK input duty cycle? (The internal VCO has a
• Wh
50% duty cycle.)
The DCC function is enabled by default for each channel
divid
er. However, the DCC function can be disabled
individually for each channel divider by setting the
DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non50% d
uty cycle. A non-50% duty cycle can also result with an
even division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
n even division must be set as M = N.
• A
dd division must be set as M = N + 1.
• An o
When not bypassed or corrected by the DCC function, the duty
ycle of each channel divider output is the numerical value of
c
(N + 1)/(N + M + 2) expressed as a %.
The duty cycle at the output of the channel divider for various
co
nfigurations is shown in Tabl e 3 3 to Ta ble 35.
Table 33. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, Odd Even
Even, Odd Odd
N + M + 2 DCCOFF = 1 DCCOFF = 0
1 (divider
ypassed)
b
1 (divider
ypassed)
b
1 (divider
ypassed)
b
D
X
50% 50%
33.3% 50%
40% 50%
(N + 1)/
(N +
(N + 1)/
(N +
Output Duty Cycle
50%; requires M = N
M + 2)
50%; requires M = N + 1
M + 2)
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Table 34. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
D
VCO
Divider
Even
Odd = 3
Odd = 5
X
N + M + 2 DCCOFF = 1 DCCOFF = 0
1 (divider
ypassed)
b
1 (divider
ypassed)
b
1 (divider
ypassed)
b
Even Even
Odd
Odd = 3 Even
Odd = 3 Odd
Odd = 5 Even
Odd = 5 Odd
50% 50%
33.3% (1 + X%)/3
40% (2 + X%)/5
(N + 1)/
(N +
(N + 1)/
(N +
(N + 1)/
(N +
(N + 1)/
(N +
(N + 1)/
(N +
(N + 1)/
(N +
Output Duty Cycle
50%,
M + 2)
requires M = N
50%,
M + 2)
requires M = N + 1
50%,
M + 2)
requires M = N
(3N + 4 + X%)/(6N + 9),
M + 2)
requires M = N + 1
50%,
M + 2)
requires M = N
(5N + 7 + X%)/(10N + 15),
M + 2)
requires M = N + 1
Table 35. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
D
Input Clock
Duty Cycle
Any 1
X
N + M + 2 DCCOFF = 1 DCCOFF = 0
1 (divider
b
Any Even
50% Odd
X% Odd
(N + 1)/
M + N + 2)
(
(N + 1)/
M + N + 2)
(
(N + 1)/
M + N + 2)
(
ypassed)
Output Duty Cycle
Same as input
duty cycle
50%, requires M = N
50%, requires
M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected direct to output, the duty cycle is 50%. If the
CLK input is routed direct to output, the duty cycle of the output is
the same as the CLK input.
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Tabl e 36 ).
Th
ese settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M)
programmed for the divider.
It is necessary to use the SYNC function to make phase offsets
fective (see the Synchronizing the Outputs—SYNC Function
ef
secti
on).
Table 36. Setting Phase Offset and Division for Divider 0,
The channel divide-by is set as N = high cycles and M = low cycles.
Case 1
For Φ ≤ 15,
Δ
= Φ × TX
t
Δ
= Δt/TX = Φ
c
Case 2
For Φ ≥ 16,
Δ
= (Φ − 16 + M + 1) × T
t
Δc = Δt/T
X
X
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 38 shows the results of setting such a coarse
of
fset between outputs.
CHANNEL
DIVIDER I NPUT
DIVIDER 0
DIVIDER 1
DIVIDER 2
0123456789101112131415
Tx
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
Figure 38. Effect of Coarse Phase Offset (or Delay)
C
A
H
1 × Tx
2 × Tx
E
L
D
N
N
I
D
V
T
P
T
U
S
U
E
D
R
O
I
V
I
=
5
0
4
,
=
%
T
U
D
Y
Synchronizing the Outputs—SYNC Function
The AD9518 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
06431-071
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Synchronization of the outputs is executed in several ways:
SYNC
• The
• B
y setting and then resetting any one of the following three
pin is forced low and then released (manual SYNC).
bits: the soft SYNC bit (0x230<0>), the soft reset bit
(0x00<5> [mirrored]), or the power-down distribution
reference bit (0x230<1>).
ynchronization of the outputs can be executed as part of the
• S
chip power-up sequence.
RESET
• The
• Th
e
• W
henever a VCO calibration is completed, an internal SYNC
pin is forced low and then released (chip reset).
PD
pin is forced low and then released (chip power-down).
signal is automatically asserted at the beginning and released
upon the completion of a VCO calibration.
CHANNEL DIVIDE
OUTPUT CLOCKING
CHANNEL DIVIDER O UTPUT STAT IC
The most common way to execute the SYNC function is to use
SYNC
th
e
outputs. This requires a low-going signal on the
pin to execute a manual synchronization of the
SYNC
pin,
which is held low and then released when synchronization is
desired. The timing of the SYNC operation is shown in
using VCO divider) and Figure 40 (VCO divider not used).
(
Ther
e is an uncertainty of up to one cycle of the clock at the
Figure 39
input to the channel divider due to the asynchronous nature of
the SYNC signal with respect to the clock edges inside the
AD9518. The delay from the
SYNC
rising edge to the beginning of
synchronized output clocking is between 14 and 15 cycles of
clock at the channel divider input, plus either one cycle of the VCO
divider input (see
in
put (see Figure 40), depending on whether the VCO divider is
us
ed. Cycles are counted from the rising edge of the signal.
Figure 39), or one cycle of the channel divider
Another common way to execute the SYNC function is by
se
tting and resetting the soft SYNC bit at 0x230<0> (see Tabl e 42
th
rough Ta ble 4 8 for details). Both setting and resetting of the
oft SYNC bit requires an update all registers (0x232<0> = 1)
s
operation to take effect.
CHANNEL DIVIDE
OUTPUT CLOCKING
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
YNC PIN
OUTPUT OF
CHANNEL DIVIDER
123 456 78910
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER I NPUT
Figure 39. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
1
11
1314
12
06431-073
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CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER O UTPUT ST ATIC
CHANNEL DIVIDE
OUTPUT CLOCKING
INPUT TO CLK
IINPUT TO CHANNEL DIVI DER
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
12345678910
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 40. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
A SYNC operation brings all outputs that have not been
uded (by the nosync bit) to a preset condition before
excl
allowing the outputs to begin clocking in synchronicity. The
preset condition takes into account the settings in each of the
channel’s start high bit and its phase offset. These settings
govern both the static state of each output when the SYNC
operation is happening and the state and relative phase of the
outputs when they begin clocking again upon completion of the
SYNC operation. Between outputs and after synchronization,
this allows for the setting of phase offsets.
The AD9518 outputs are in pairs, sharing a channel divider
p
er pair. The synchronization conditions apply to both outputs
of a pair.
Each channel (a divider and its outputs) can be excluded from
ny SYNC operation by setting the nosync bit of the channel.
a
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
LVPECL Clock Outputs: OUT0 to OUT5
The LVPECL differential voltage (VOD) is selectable from
~400 mV to ~960 mV, see 0xF0:0xF5<3:2>. The LVPECL
outputs have dedicated pins for power supply (VS_LVPECL),
allowing for a separate power supply to be used. V
S_LVPECL
can be
from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
in
verting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
1
11
13 14
12
6431-074
For this reason, the LVPECL outputs have several power-down
odes. This includes a safe power-down mode that continues
m
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are not connected (unused),
it is acceptable to use the total power-down mode.
The AD9518 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is
Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Tab l e 4 1 . At
p
ower-on, the AD9518 also executes a SYNC operation, which
brings the outputs into phase alignment according to the default
settings.
Rev. 0 | Page 39 of 64
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Asynchronous Reset via the
An asynchronous hard reset is executed by momentarily pulling
RESET
low. A reset restores the chip registers to the default
settings.
RESET
Pin
Soft Reset via 0x00<5>
A soft reset is executed by writing 0x00<5> and 0x00<2> = 1b.
This bit is not self-clearing; therefore, it must be cleared by
writing 0x00<5> and 0x00<2> = 0b to reset it and complete the
soft reset operation. A soft reset restores the default values to
the internal registers. The soft reset bit does not require an
update registers command (0x232) to be issued.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9518 can be put into a power-down condition by
PD
pulling the
functions and currents inside the AD9518. The chip remains in
this power-down state until
When woken up, the AD9518 returns to the settings programmed
into its registers prior to the power-down, unless the registers
are changed by new programming while the
PD
The
except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9518 is in a
following state:
he PLL is off (asynchronous power-down).
• T
• The V
• The CL
l dividers are off.
• Al
• Al
l LVPECL outputs are in safe off mode.
• The s
commands.
pin low. Power-down turns off most of the
PD
is brought back to Logic High.
PD
pin is held low.
power-down shuts down the currents on the chip,
PD
power-down, the chip is in the
CO is off.
K input buffer is off.
erial control port is active, and the chip responds to
If the AD9518 clock outputs must be synchronized to each
o
ther, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section). A VCO
ca
libration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9518 can be selectively powered
down. There are three PLL operating modes set by 0x10<1:0>,
as shown in Tab l e 4 3 .
In asynchronous power-down mode, the device powers down as
oon as the registers are updated.
s
In synchronous power-down mode, the PLL power-down is
g
ated by the charge pump to prevent unwanted frequency
jumps. The device goes into power-down on the occurrence of
the next charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
0x230<1> = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and can be damaged
under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs may be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output.
The LVPECL outputs have multiple power-down modes
(see
Tabl e 44 ), which give some flexibility in dealing with the
va
rious output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
0x230<1> = 1b (see the
Distribution Power-Down section).
Individual Circuit Block Power-Down
Other AD9518 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
Rev. 0 | Page 40 of 64
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SERIAL CONTROL PORT
The AD9518 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9518 serial control port is compatible with most synchronous
transfer formats, including both the Motorola® SPI® and Intel®
SSR® protocols. The serial control port allows read/write access
to all registers that configure the AD9518. Single- or multiplebyte transfers are supported, as well as MSB first or LSB first
transfer formats. The AD9518 serial control port can be
configured for a single bidirectional I/O pin (SDIO only) or
for two unidirectional I/O pins (SDIO/SDO). By default, the
AD9518 is in bidirectional mode, long instruction (long
instruction is the only instruction mode supported).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
n input only (unidirectional mode) or as an input/output
as a
(bidirectional mode). The AD9518 defaults to the bidirectional
I/O mode (0x00<7> = 0).
SDO (s
erial data out) is used only in the unidirectional I/O mode
(0x00<7> = 1) as a separate output pin for reading back data.
CS
(chip select bar) is an active low control that gates the read
and write cycles. When
CS
is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to VS.
13
SCLK
SDO
SDIO
Figure 42. Serial Control Port
CS
AD9518-2
14
SERIAL
15
CONTROL
16
PORT
6431-036
GENERAL OPERATION OF SERIAL CONTROL PORT
A write or a read operation to the AD9518 is initiated by
CS
pulling
CS
bytes of data (plus instruction data) are transferred (see Tab le 37 ).
I
n these modes,
boundary, allowing time for the system controller to process the
next byte.
high during either part (instruction or data) of the transfer.
low.
stalled high is supported in modes where three or fewer
CS
can temporarily return high on any byte
CS
can go high on byte boundaries only and can go
During this period, the serial control port state machine enters
a wai
t state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset by either completing the remaining transfers or by
returning the
less than eight SCLK cycles). Raising the
CS
low for at least one complete SCLK cycle (but
CS
on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In the streaming mode (see Ta b l e 37 ), any number of data bytes
an be transferred in a continuous stream. The register address
c
is automatically incremented or decremented (see the MSB/LSB
Fi
rst Transfers section).
CS
must be raised at the end of the last
byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9518.
The first writes a 16-bit instruction word into the AD9518,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9518 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9518. Data bits are registered on the rising edge of SCLK.
The length of the transfer (1, 2, 3 bytes or streaming mode) is
cated by two bits (W1:W0) in the instruction byte. When
indi
the transfer is 1, 2, or 3 bytes, but not streaming,
CS
can be
raised after each sequence of eight bits to stall the bus (except
after the last byte, where it ends the cycle). When the bus is
stalled, the serial transfer resumes when
CS
is lowered. Raising CS
on a nonbyte boundary resets the serial control port. During a
write, streaming mode does not skip over reserved or blank
registers; therefore, the user must know what bit pattern to
write to the reserved registers to preserve proper operation of
the part. It does not matter what data is written to blank registers.
Because data is written into a serial control port buffer area and
ot directly into the actual control registers of the AD9518, an
n
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9518,
thereby causing them to become active. The update registers
operation consists of setting 0x232<0> = 1b (this bit is selfclearing). Any number of bytes of data can be changed before
executing an update registers. The update registers simultaneously
actuates all register changes that have been written to the buffer
since any previous update.
Rev. 0 | Page 41 of 64
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Read
If the instruction word is for a read operation, the next N × 8
SCLK c
ycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by W1:W0.
If N = 4, the read operation is in streaming mode, continuing
CS
until
is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling
edge of SCLK.
The default mode of the AD9518 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9518 to unidirectional mode (SDO enable register,
0x00<7> = 1). In unidirectional mode, the readback data
appears on the SDO pin.
A readback request reads the data that is in the serial control
po
rt buffer area, or the data in the active registers (see Figure 43).
Re
adback of the buffer or active registers is controlled by 0x04<0>.
The AD9518 supports only the long instruction mode; therefore,
0x00<4:3> m
ust be set to 11b (this register uses mirrored bits).
Long instruction mode is the default at power-up or reset.
The AD9518 uses Register Address 0x00 to Register
A
ddress 0x232.
SCLK
SDIO
SDO
CS
SERIAL
CONTROL
PORT
WRITE RE GISTE R 0x232 = 0x01
TO UDATE REG ISTERS
Figure 43. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9518
UPDATE
REGISTERS
BUFFER REGISTERS
ACTIVE REGISTERS
06431-037
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits,
W1:W0, indicate the length of the transfer in bytes. The final
13 bits are the address (A12:A0) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
b
ytes of data indicated by Bits W1:W0 (see Tab l e 3 7 ).
Table 37. Byte Transfer Count
W1
0 0 1
0 1 2
1
1 1 Streaming mode
W0 Bytes to Transfer
0 3
A12:A0: These 13 bits select the address within the register map
that is written to or read from during the data transfer portion
of the communication cycle. Only Bits<A9:A0> are needed to
cover the range of the 0x232 registers used by the AD9518.
Bits<A12:A10> must always be 0b. For multibyte transfers, this
address is the starting byte address. In MSB first mode,
subsequent bytes decrement the address.
MSB/LSB FIRST TRANSFERS
The AD9518 instruction word and byte data can be MSB first
r LSB first. Any data written to 0x00 must be mirrored; the
o
upper four bits (<7:4>) must mirror the lower four bits (<3:0>).
This makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, see the default setting
for 0x18, which mirrors Bit 4 and Bit 3. This sets the long
instruction mode (default, and is the only mode supported).
The default for the AD9518 is MSB first.
When LSB first is set by 0x00<1> and 0x00<6>, it takes effect
ediately, because it only affects the operation of the serial
imm
control port and does not require that an update be executed.
When MSB first mode is active, the instruction and data bytes
m
ust be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the low
address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the
multibyte transfer cycle.
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. The internal byte address generator of the serial
control port increments for each byte of the multibyte
transfer cycle.
The AD9518 serial control port register address decrements
f
rom the register address just written to 0x00 for multibyte I/O
operations if the MSB first mode is active (default). If the LSB
first mode is active, the register address of the serial control
port increments from the address just written to 0x232 for
multibyte I/O operations.
Streaming mode always terminates when it hits 0x232. Note
that unused addresses are not skipped during multibyte I/O
operations.
Table 38. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB first
MSB first Decrement 0x01, 0x00, 0x232, stop
Address Direction Stop Sequence
Increment 0x230, 0x231, 0x232, stop
Rev. 0 | Page 42 of 64
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Table 39. Serial Control Port, 16-Bit Instruction Word, MSB First
16-BIT INST RUCTION HEADE RREGISTER (N) DATAREGI STER (N + 1) DAT A
Figure 48. Serial Control Port Write—LSB First, 16
Rev. 0 | Page 43 of 64
DATA BIT N – 1DATA BIT N
-Bit Instruction, Two Bytes Data
06431-041
DON'T CARE
DON'T CARE
6431-042
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CS
SCLK
t
S
t
CLK
t
HI
t
DS
t
DH
t
LO
t
C
SDIO
BIT NBIT N + 1
Figure 49. Serial Control Port Timing—Write
Table 40. Serial Control Port Timing
Parameter Description
t
DS
t
DH
t
CLK
t
S
t
C
t
HI
t
LO
t
DV
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a Logic High state
Minimum period that SCLK should be in a Logic Low state
SCLK to valid SDIO and SDO (see Figure 47)
06431-043
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REGISTER MAP OVERVIEW
Table 41. Register Map Overview
Default
Addr
(Hex)
Serial Port Configuration
00 Serial Port
01 Blank
02 to
03
04 Readback
PLL
10 PFD and
11 R Counter 14-Bit R Divider Bits<7:0> (LSB) 01
12 Blank 14-Bit R Divider Bits<13:8> (MSB) 00
13 A Counter Blank 6-Bit A Counter 00
14 B Counter 13-Bit B Counter Bits<7:0> (LSB) 03
15 Blank 13-Bit B Counter Bits<12:8> (MSB) 00
16 PLL Control 1 Set CP Pin
17 PLL Control 2 STATUS Pin Control Antibacklash Pulse Width 00
18 PLL Control 3 Reserved Lock Detect Counter Digital Lock
19 PLL Control 4
1A PLL Control 5 Reserved Reference
1B PLL Control 6 VCO
1C PLL Control 7 Disable
1D PLL Control 8 Reserved PLL Status
1E PLL Control 9
1F PLL Readback Reserved VCO Cal
20 to
4F
A0 to
AB
AC to
EF
Parameter
Configuration
Control
Charge Pump
Bit 7
(MSB)
SDO
Active
PFD
Polarity
to V
/2
CP
R, A, B Counters
Pin Reset
Frequency
Monitor
Switchover
Deglitch
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
LSB First Soft Reset Long
Charge Pump Current Charge Pump Mode PLL Power-Down 7D
r
)
Reset A and
B Counters
REF1 (REFIN)
Fr
Monitor
Use
REF_SEL Pin
Holdover
Active
equency
Reset R
Counte
SYNC
Frequency
Monitor
Threshold
REF2
REFIN
(
Frequency
Monitor
Select
F2
RE
Finished
Instruction
Reset All
Counters
Detect
Window
R Path Delay N Path Delay 00
Automatic
Reference
Switchover
Register
Disable
REF2
Selected
Blank Readback
Long
Instruction
Reserved
B Counter
Bypass
Disable
Dig
Detect
Stay on
RE
LD Pin
Comparato
Enable
Reserved
VCO
Frequency
> Threshold
Blank
Reserved
Blank
Soft Reset LSB First SDO Active 18
Active
Registers
Prescaler P 06
ital Lock
LD Pin Control 00
F2
VCO Calibration Divider VCO Cal
REFMON Pin Control 00
r
REF2
Power On
Holdover
le
Enab
REF2
equency
Fr
> Threshold
REF1
Power On
External
Holdover
Control
REF1
equency
Fr
>Threshold
Now
Differential
Reference
Holdover
le
Enab
Digital
Lock
Detect
Value
(Hex)
00
06
00
00
00
--
Rev. 0 | Page 45 of 64
Page 46
AD9518-2
www.BDTIC.com/ADI
Default
Addr
(Hex)
LVPECL Outputs
F0 OUT0 Blank OUT0
F1 OUT1 Blank OUT1
F2 OUT2 Blank OUT2
F3 OUT3 Blank OUT3
F4 OUT4 Blank OUT4
F5 OUT5 Blank OUT5
F6 to
13F
140
to
143
144 to
18F
LVPECL Channel Dividers
190 Divider 0
191 Divider 0
192 Blank Reserved Divider 0
193 Divider 1
194 Divider 1
195 Blank Reserved Divider 1
196 Divider 2
197 Divider 2
198 Blank Reserved Divider 2
199
to
1A3
1A4
to
1DF
VCO Divider and CLK Input
1E0 VCO Divider Blank Reserved VCO Divider 02
Parameter
(PECL)
(PECL)
(PECL)
Bit 7
(MSB)
Bypass
Bypass
Bypass
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Invert
Invert
Invert
Invert
Invert
Invert
Blank
Reserved
Blank
Divider 0 Low Cycles Divider 0 High Cycles 00
Divider 0
Nosync
Divider 1 Low Cycles Divider 1 High Cycles BB
Divider 1
Nosync
Divider 2 Low Cycles Divider 2 High Cycles 00
Divider 2
Nosync
Divider 0
Force High
Divider 1
Force High
Divider 2
Force High
Divider 0
Start High
Divider 1
Start High
Divider 2
Start High
Reserved
Blank
OUT0 LVPECL
Differential Voltage
OUT1 LVPECL
Differential Voltage
OUT2 LVPECL
Differential Voltage
OUT3 LVPECL
Differential Voltage
OUT4 LVPECL
Differential Voltage
OUT5 LVPECL
Differential Voltage
Divider 0 Phase Offset 80
Divider 1 Phase Offset 00
Divider 2 Phase Offset 00
OUT0 Power-Down 08
OUT1 Power-Down 0A
OUT2 Power-Down 08
OUT3 Power-Down 0A
OUT4 Power-Down 08
OUT5 Power-Down 0A
Direct to
Output
Direct to
Output
Direct to
Output
Bit 0 (LSB)
Divider 0
DCCOFF
Divider 1
DCCOFF
Divider 2
DCCOFF
Value
(Hex)
00
00
00
1E1 Input CLKs Reserved Power-
Down
Clock
Input
Section
1E2
to
22A
Rev. 0 | Page 46 of 64
Power-Down
VCO C
Interface
Blank
lock
PowerDown VCO
and CLK
Select
VCO o
r CLK
Bypass
VCO
Divider
00
Page 47
AD9518-2
www.BDTIC.com/ADI
Default
Addr
(Hex)
System
230 Power-Down
231 Blank Reserved 00
Update All Registers
232 Update All
Parameter
and SYNC
Registers
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Reserved Power-
Down
SYNC
Blank Update All
PowerDown
Distr
Reference
Bit 0 (LSB)
Soft SYNC 00
ibution
Registers
(SelfClearing
Bit)
Value
(Hex)
00
Rev. 0 | Page 47 of 64
Page 48
AD9518-2
www.BDTIC.com/ADI
REGISTER MAP DESCRIPTIONS
Tabl e 42 through Tab le 4 8 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. Reference to a specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, and
<5:2> refers to the range of bits from Bit 5 through Bit 2.
Table 42. Serial Port Configuration
Reg. Addr (Hex) Bit(s) Name Description
00 <7> SDO Active Selects unidirectional or bidirectional data transfer mode.
<7> = 1; SDO used for read; SDIO used for write; unidirectional mode.
00 <6> LSB First MSB or LSB data orientation.
<6> = 0; data-oriented MSB first; addressing decrements.
<6> = 1; data-oriented LSB first; addressing increments.
00 <5> Soft Reset Soft Reset.
16 <7> Set CP Pin Sets the CP pin to one-half of the VCP supply voltage.
16 <6> Reset R Resets R counter (R divider).
Down
14-Bit
R Divider
Bits<7:0>
(LSB)
14-Bit
R Divider
Bits<13:8>
(MSB)
6-Bit
ounter
A C
13-Bit
ounter
B C
Bits<7:0>
(LSB)
13-Bit
ounter
B C
Bits<12:8>
(MSB)
to V
/2 <7> = 0; CP normal operation.
CP
Counter <6> = 0; normal.
Sets the PFD polarity. Negative polarity is for use
The on-chip VCO requires positive polarity <7> = 0.
<6> <5> <4> ICP (mA)
<3> <2> Charge Pump Mode
0 0 High impedance state.
0 1 Force source current (pump up).
1 0 Force sink current (pump down).
1 1 Normal operation.
<1> <0> Mode
0 0 Normal operation.
0 1 Asynchronous power-down.
1 0 Normal operation.
1 1 Synchronous power-down.
R divider LSBs—lower eight bits.
R divider MSBs—upper six bits.
A counter (part of N divider).
B counter (part of N divider)—lower eight bits.
B counter (part of N divider)—upper five bits.
<7> = 1; CP pin set to V
<6> = 1; reset R counter.
/2.
CP
(if needed) with external VCO/VCXO only.
Rev. 0 | Page 49 of 64
Page 50
AD9518-2
www.BDTIC.com/ADI
Reg.
Addr
(Hex) Bit(s) Name Description
16 <5> Reset A and B Resets A and B counters (part of N divider).
16 <4> Reset All Resets R, A, and B counters.
Counters <4> = 0; normal.
<4> = 1; resets R, A, and B counters.
16 <3> B Counter B counter bypass. This is valid only when operating the prescaler in FD mode.
Bypass <3> = 0; normal.
<3> = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
16 <2:0> Prescaler P Prescaler: DM = dual modulus and FD = fixed divide.
0 0 0 FD Divide-by-1.
0 0 1 FD Divide-by-2.
0 1 0 DM Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.
0 1 1 DM Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
1 0 0 DM Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
1 0 1 DM Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.
1 1 0 DM Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0.
1 1 1 FD Divide-by-3.
17 <7:2> STATUS Selects the signal that is connected to the STATUS pin.
Pin Control
0 0 0 0 0 0 LVL Ground (dc).
0 0 0 0 0 1 DYN N divider output (after the delay).
0 0 0 0 1 0 DYN R divider output (after the delay).
0 0 0 0 1 1 DYN A divider output.
0 0 0 1 0 0 DYN Prescaler output.
0 0 0 1 0 1 DYN PFD up pulse.
0 0 0 1 1 0 DYN PFD down pulse.
0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as REFMON.
1 0 0 0 0 0 LVL Ground (dc).
1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
1 0 0 0 1 0 DYN REF2 clock (not available in differential mode).
1 0 0 0 1 1 DYN
1 0 0 1 0 0 DYN
1 0 0 1 0 1 LVL
1 0 0 1 1 0 LVL
1 0 0 1 1 1 LVL Status of REF1 frequency (active high).
1 0 1 0 0 0 LVL Status of REF2 frequency (active high).
1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency).
1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
1 0 1 0 1 1 LVL Status of VCO frequency (active high).
1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
1 0 1 1 0 1 LVL Digital lock detect (DLD); active high.
1 0 1 1 1 0 LVL Holdover active (active high).
Counters <5> = 0; normal.
<5> = 1; resets A and B counters.
<2> <1> <0> Mode Prescaler
<7> <6> <5> <4> <3> <2>
Level or
Dynamic
Signal Signal at STATUS Pin
Selected reference to PLL (differential reference when in
erential mode).
diff
Unselected reference to PLL (not available in differential
mode).
Status of selected reference (status of differential reference);
tive high.
ac
Status of unselected reference (not available in differential
Window <4> = 0; high range.
<4> = 1; low range.
18 <3> Disable Digital lock detect operation.
Digital <3> = 0; normal lock detect operation.
Lock Detect <3> = 1; disables lock detect.
18 <2:1> VCO Cal VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
Divider
0 0 2
0 1 4
1 0 8
1 1 16 (default)
Lock Detect
unter
Co
Digital Lock
tect
De
<1> <0> Antibacklash Pulse Width (ns)
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates
a locked condition.
<6> <5> PFD Cycles to Determine Lock
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the
digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
<2> <1> VCO Calibration Clock Divider
Level or
Dynamic
Signal
Signal at STATUS Pin
REF1 clock
REF2 clock
Selected reference to PLL
differential mode).
Unselected reference to PLL
differential mode).
Status of selected reference (status of differential reference);
tive low.
ac
Status of unselected reference (not available in differential
mode); ac
(Status of REF1 frequency) AND (status of REF2 frequency)
(DLD) AND (status of selected reference) AND (status of VCO)
(differential reference when in differential mode).
(not available in differential mode).
(differential reference when in
(not available when in
tive low.
.
.
Rev. 0 | Page 51 of 64
Page 52
AD9518-2
www.BDTIC.com/ADI
Reg.
Addr
(Hex) Bit(s) Name Description
18 <0>
19 <7:6> R, A, B
Counters 0 0
Reset 1 0 Synchronous reset.
1 1
19 <5:3> R Path Delay <5:3> R Path Delay (see Tabl e 2).
19 <2:0> N Path Delay <2:0> N Path Delay (see Tabl e 2).
1A <6>
Monitor <6> = 0; frequency valid if frequency is above the higher frequency threshold.
Threshold <6> = 1; frequency valid if frequency is above the lower frequency threshold.
1A <5:0> LD Pin Selects the signal that is connected to the LD pin.
Control
0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock).
0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect).
0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect).
0 0 0 0 1 1 HIZ High-Z LD pin.
0 0 0 1 0 0 CUR Current source lock detect (110 μA when DLD is true).
0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as REFMON.
1 0 0 0 0 0 LVL Ground (dc).
1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
1 0 0 0 1 0 DYN REF2 clock (not available in differential mode).
1 0 0 0 1 1 DYN
1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
1 0 0 1 0 1 LVL
1 0 0 1 1 0 LVL
1 0 0 1 1 1 LVL Status of REF1 frequency (active high).
1 0 1 0 0 0 LVL Status of REF2 frequency (active high).
1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency).
1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
1 0 1 0 1 1 LVL Status of VCO frequency (active high).
1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
1 0 1 1 0 1 LVL Digital lock detect (DLD); active high.
1 0 1 1 1 0 LVL Holdover active (active high).
1 0 1 1 1 1 LVL Not available—do not use.
1 1 0 0 0 0 LVL VS (PLL supply).
1 1 0 0 0 1 DYN
1 1 0 0 1 0 DYN
1 1 0 0 1 1 DYN
1 1 0 1 0 0 DYN
VCO Cal
w
No
Pin
SYNC
Reference
requency
F
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The sequence
to initiate a calibration is: program to 0, followed by an update bit (0x232<0>); then program to 1, followed by
another update bit (0x232<0>). This sequence gives complete control over when the VCO calibration occurs
relative to the programming of other registers that can impact the calibration.
<7> <6> Action
Do nothing on SYNC
0 1 Asynchronous reset.
Do nothing on SYNC
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect
the VCO frequency monitor’s detection threshold (see Table 15 , REF1, REF2, and VCO Frequency Status Monitor).
<5> <4> <3> <2> <1> <0>
(default).
.
Level or
Dynamic
Signal Signal at LD Pin
Selected reference to PLL (differential reference when in
erential mode).
diff
Status of selected reference (status of differential reference);
tive high.
ac
Status of unselected reference (not available in differential
mode); ac
REF1 clock
REF2 clock
Selected reference to PLL
differential mode).
Unselected reference to PLL
mode).
tive high.
(differential reference when in differential mode).
(not available in differential mode).
(differential reference when in
(not available when in differential
Rev. 0 | Page 52 of 64
Page 53
AD9518-2
www.BDTIC.com/ADI
Reg.
Addr
(Hex) Bit(s) Name Description
<5> <4> <3> <2> <1> <0>
1 1 0 1 0 1 LVL
1 1 0 1 1 0 LVL
1 1 0 1 1 1 LVL Status of REF1 frequency (active low).
1 1 1 0 0 0 LVL Status of REF2 frequency (active low).
1 1 1 0 0 1 LVL
1 1 1 0 1 0 LVL
1 1 1 0 1 1 LVL Status of VCO frequency (active low).
1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1).
1 1 1 1 0 1 LVL Digital lock detect (DLD); active low.
1 1 1 1 1 0 LVL Holdover active (active low).
1 1 1 1 1 1 LVL Not available—do not use.
1B <7> VCO Enables or disables VCO frequency monitor.
Frequency <7> = 0; disables VCO frequency monitor.
Monitor <7> = 1; enables VCO frequency monitor.
1B <6>
Frequency <6> = 0; disables REF2 frequency monitor.
Monitor <6> = 1; enables REF2 frequency monitor.
1B <5>
Monitor <5> = 0; disable REF1 (REFIN) frequency monitor.
<5> = 1; enable REF1 (REFIN) frequency monitor.
1B <4:0> REFMON Pin Selects the signal that is connected to the REFMON pin.
Control
0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
0 0 1 0 1 LVL
0 0 1 1 0 LVL
0 0 1 1 1 LVL Status of REF1 frequency (active high).
0 1 0 0 0 LVL Status of REF2 frequency (active high).
0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency).
0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
0 1 0 1 1 LVL Status of VCO frequency (active high).
0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
0 1 1 0 1 LVL Digital lock detect (DLD); active low.
0 1 1 1 0 LVL Holdover active (active high).
0 1 1 1 1 LVL LD pin comparator output (active high).
1 0 0 0 0 LVL VS (PLL supply).
1 0 0 0 1 DYN
1 0 0 1 0 DYN
(REFIN)
REF2
REF1 (REFIN)
requency
F
Enables or disables REF2 frequency monitor.
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
Level or
Dynamic
<4> <3> <2> <1> <0>
Signal
Level or
Dynamic
Signal
Signal at LD Pin
Status of selected reference (status of differential reference);
tive low.
ac
Status of unselected reference (not available in differential
mode); ac
(Status of REF1 frequency) AND (status of REF2 frequency)
(DLD) AND (status of selected reference) AND (status of VCO)
Signal at REFMON Pin
Selected reference to PLL (differential reference when in
erential mode).
diff
Status of selected reference (status of differential reference);
tive high.
ac
Status of unselected reference (not available in differential mode);
tive high.
ac
REF1 clock
REF2 clock
tive low.
(differential reference when in differential mode).
(not available in differential mode).
.
.
Rev. 0 | Page 53 of 64
Page 54
AD9518-2
www.BDTIC.com/ADI
Reg.
Addr
(Hex) Bit(s) Name Description
<4> <3> <2> <1> <0>
1 0 0 1 1 DYN
1 0 1 0 0 DYN
1 0 1 0 1 LVL
1 0 1 1 0 LVL
1 0 1 1 1 LVL Status of REF1 frequency (active low).
1 1 0 0 0 LVL Status of REF2 frequency (active low).
1 1 0 0 1 LVL
1 1 0 1 0 LVL
1 1 0 1 1 LVL Status of VCO frequency (active low).
1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1).
1 1 1 0 1 LVL Digital lock detect (DLD); active low.
1 1 1 1 0 LVL Holdover active (active low).
1 1 1 1 1 LVL LD pin comparator output (active low).
1C <7> Disable Disables or enables the switchover deglitch circuit.
Switchover <7> = 0; enables switchover deglitch circuit.
Deglitch <7> = 1; disables switchover deglitch circuit.
1C <6> Select REF2 If 0x1C<5> = 0, selects reference for PLL.
<6> = 0; selects REF1.
<6> = 1; selects REF2.
1C <5> Use REF_SEL If 0x1C<4> = 0 (manual), set method of PLL reference selection.
Pin <5> = 0; use 0x1C<6>.
<5> = 1; use REF_SEL pin.
1C <4> Automatic Automatic or manual reference switchover. Single-ended reference mode must be selected by 0x1C<0> = 0.
Reference <4> = 0; manual reference switchover.
Switchover <4> = 1; automatic reference switchover.
1C <3> Stay on REF2 Stays on REF2 after switchover.
<3> = 0; return to REF1 automatically when REF1 status is good again.
<3> = 1; stay on REF2 after switchover. Do not automatically return to REF1.
1C <2> REF2 When automatic reference switchover is disabled, this bit turns the REF2 power on.
Power On <2> = 0; REF2 power off.
<2> = 1; REF2 power on.
1C <1> REF1 When automatic reference switchover is disabled, this bit turns the REF1 power on.
Power On <1> = 0; REF1 power off.
<1> = 1; REF1 power on.
1C <0>
<0> = 0; single-ended reference mode.
<0> = 1; differential reference mode.
1D <4> PLL Status Disables the PLL status register readback.
Register <4> = 0; PLL status register enable.
Disable <4> = 1; PLL status register disable.
Differential
ference
Re
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the
automatic switchover for REF1 and REF2 to work.
Level or
Dynamic
Signal
Signal at REFMON Pin
Selected reference to PLL
differential mode).
Unselected reference to PLL
differential mode).
Status of selected reference (status of differential reference);
tive low.
ac
Status of unselected reference (not available in differential mode);
tive low.
ac
(Status of REF1 frequency) AND (status of REF2 frequency)
(DLD) AND (Status of selected reference) AND (status of VCO)
(differential reference when in
(not available when in
.
.
Rev. 0 | Page 54 of 64
Page 55
AD9518-2
www.BDTIC.com/ADI
Reg.
Addr
(Hex) Bit(s) Name Description
1D <3>
<3> = 0; disable LD pin comparator; internal/automatic holdover controller treats this pin as true (high).
<3> = 1; enable LD pin comparator.
1D <2> Holdover Along with Bit 0, enables the holdover function.
Enable <2> = 0; holdover disabled.
<2> = 1; holdover enabled.
1D <1> External
Holdover <1> = 0; automatic holdover mode—holdover controlled by automatic holdover circuit.
Control
1D <0> Holdover Along with Bit 2, enables the holdover function.
Enable <0> = 0; holdover disabled.
<0> = 1; holdover enabled.
1F <6> VCO Cal Readback register; status of the VCO calibration.
Finished <6> = 0; VCO calibration not finished.
<6> = 1; VCO calibration finished.
1F <5>
<5> = 0; not in holdover.
<5> = 1; holdover state active.
1F <4> REF2 Readback register; indicates which PLL reference is selected as the input to the PLL.
Selected <4> = 0; REF1 selected (or differential reference if in differential mode).
<4> = 1; REF2 selected.
1F <3>
Threshold <3> = 0; VCO frequency is less than the threshold.
<3> = 1; VCO frequency is greater than the threshold.
1F <2>
Threshold <2> = 0; REF2 frequency is less than threshold frequency.
<2> = 1; REF2 frequency is greater than threshold frequency.
1F <1>
Threshold <1> = 0; REF1 frequency is less than threshold frequency.
<1> = 1; REF1 frequency is greater than threshold frequency.
1F <0> Digital Lock Readback register; digital lock detect.
Detect <0> = 0; PLL is not locked.
<0> = 1; PLL is locked.
LD Pin
mparator
Co
Enable
Holdover
tive
Ac
VCO
requency >
F
REF2
requency >
F
REF1
requency >
F
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
When in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to
determine if the PLL was previously in a locked state (see Figure 36). Otherwise, this function can be used with
MON and STATUS pins to monitor the voltage on the LD pin.
the REF
Enables the external hold control through the SYNC
<1> = 1; external holdover mode—holdover controlled by SYNC
Readback register; indicates if the part is in the holdover state (see Figure 36). This is not the same as holdover
enabled
Readback register; indicates if the VCO frequency is greater than the threshold (see Table 15, REF1, REF2, and VCO
F
Readback register; indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by 0x1A<6>.
Readback register; indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by 0x1A<6>.
.
requency Status Monitor).
pin. (This disables the internal holdover mode.)
pin.
Rev. 0 | Page 55 of 64
Page 56
AD9518-2
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Table 44. LVPECL Outputs
Reg.
Addr
(Hex)
Bit(s) Name Description
F0 <4> OUT0 Invert Sets the output polarity.
<4> = 0; noninverting.
<4> = 1; inverting.
F0 <3:2> OUT0 LVPECL Sets the LVPECL output differential voltage (VOD).
Differential
Voltage 0 0 400
0 1 600
1 0 780
1 1 960
F0 <1:0> OUT0 LVPECL power-down modes.
Power-Down
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external load resistors. Off
1 0 Partial power-down, reference on, safe LVPECL power-down. Off
1 1 Total power-down, reference off; use only if there are no external load resistors. Off
F1 <4> OUT1 Invert Sets the output polarity.
<4> = 0; noninverting.
<4> = 1; inverting.
F1 <3:2> OUT1 LVPECL Sets the LVPECL output differential voltage (VOD).
Differential
Voltage 0 0 400
0 1 600
1 0 780
1 1 960
F1 <1:0> OUT1 LVPECL power-down modes.
Power-Down
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external load resistors. Off
1 0 Partial power-down, reference on, safe LVPECL power-down. Off
1 1 Total power-down, reference off; use only if there are no external load resistors. Off
F2 <4> OUT2 Invert Sets the output polarity.
<4> = 0; noninverting.
<4> = 1; inverting.
F2 <3:2> OUT2 LVPECL Sets the LVPECL output differential voltage (VOD).
Differential
Voltage 0 0 400
0 1 600
1 0 780
1 1 960
F2 <1:0> OUT2 LVPECL power-down modes.
Power-Down
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external load resistors. Off
1 0 Partial power-down, reference on, safe LVPECL power-down. Off
1 1 Total power-down, reference off; use only if there are no external load resistors. Off
F3 <4> OUT3 Invert Sets the output polarity.
<4> = 0; noninverting.
<4> = 1; inverting.
<3> <2> VOD (mV)
<1> <0> Mode Output
<3> <2> VOD (mV)
<1> <0> Mode Output
<3> <2> V
<1> <0> Mode Output
(mV)
OD
Rev. 0 | Page 56 of 64
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AD9518-2
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Reg.
Addr
(Hex) Bit(s) Name Description
F3 <3:2> OUT3 LVPECL Sets the LVPECL output differential voltage (VOD).
Differential
Voltage 0 0 400
0 1 600
1 0 780
1 1 960
F3 <1:0> OUT3 LVPECL power-down modes.
Power-Down
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external load resistors. Off
1 0 Partial power-down, reference on, safe LVPECL power-down. Off
1 1 Total power-down, reference off; use only if there are no external load resistors. Off
F4 <4> OUT4 Invert Sets the output polarity.
<4> = 0; noninverting.
<4> = 1; inverting.
F4 <3:2> OUT4 LVPECL Sets the LVPECL output differential voltage (VOD).
Differential
Voltage 0 0 400
0 1 600
1 0 780
1 1 960
F4 <1:0> OUT4 LVPECL power-down modes.
Power-Down
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external load resistors. Off
1 0 Partial power-down, reference on, safe LVPECL power-down. Off
1 1 Total power-down, reference off; use only if there are no external load resistors. Off
F5 <4> OUT5 Invert Sets the output polarity.
<4> = 0; noninverting.
<4> = 1; inverting.
F5 <3:2> OUT5 LVPECL Sets the LVPECL output differential voltage (VOD).
Differential
Voltage 0 0 400
0 1 600
1 0 780
1 1 960
F5 <1:0> OUT5 LVPECL power-down modes.
Power-Down
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external load resistors. Off
1 0 Partial power-down, reference on, safe LVPECL power-down. Off
1 1 Total power-down, reference off; use only if there are no external load resistors. Off
<3> <2> V
<1> <0> Mode Output
<3> <2> VOD (mV)
<1> <0> Mode Output
<3> <2> V
<1> <0> Mode Output
OD
(mV)
OD
(mV)
Rev. 0 | Page 57 of 64
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Table 45. LVPECL Channel Dividers
Reg.
Addr
(Hex)
Bit(s) Name Description
190 <7:4> Divider 0 Low Cycles Number of clock cycles of the divider input during which divider output stays low.
190 <3:0> Divider 0 High Cycles Number of clock cycles of the divider input during which divider output stays high.
191 <7> Divider 0 Bypass Bypasses and powers down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
191 <6> Divider 0 Nosync Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
191 <5> Divider 0 Force High Forces divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
191 <4> Divider 0 Start High Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
191 <3:0> Divider 0 Phase Offset Phase offset.
192 <1> Divider 0 Direct to Output Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
<1> = 0; OUT0 and OUT1 are connected to Divider 0.
192 <0> Divider 0 DCCOFF Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
193 <7:4> Divider 1 Low Cycles Number of clock cycles of the divider input during which divider output stays low.
193 <3:0> Divider 1 High Cycles Number of clock cycles of the divider input during which divider output stays high.
194 <7> Divider 1 Bypass Bypasses and powers down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
194 <6> Divider 1 Nosync Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
194 <5> Divider 1 Force High Forces divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
194 <4> Divider 1 Start High Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
194 <3:0> Divider 1 Phase Offset Phase offset.
195 <1> Divider 1 Direct to Output Connect OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
<1> = 0; OUT2 and OUT3 are connected to Divider 1.
f 0x1E1<1:0> = 10b, the VCO is routed directly to OUT0 and OUT1.
I
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT0 and OUT1.
If 0x1E1<1:0> = 01b, there is no effect.
<1> = 1;
f 0x1E1<1:0> = 10b, the VCO is routed directly to OUT2 and OUT3.
I
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT2 and OUT3.
If 0x1E1<1:0> = 01b, there is no effect.
Rev. 0 | Page 58 of 64
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AD9518-2
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Reg.
Addr
(Hex) Bit(s) Name Description
196 <7:4> Divider 2 Low Cycles Number of clock cycles of the divider input during which divider output stays low.
196 <3:0> Divider 2 High Cycles Number of clock cycles of the divider input during which divider output stays high.
197 <7> Divider 2 Bypass Bypasses and powers down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
197 <6> Divider 2 Nosync Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
197 <5> Divider 2 Force High Forces divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
197 <4> Divider 2 Start High Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
197 <3:0> Divider 2 Phase Offset Phase offset.
198 <1> Divider 2 Direct to Output Connect OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
<1> = 0; OUT4 and OUT5 are connected to Divider 2.
f 0x1E1<1:0> = 10b, the VCO is routed directly to OUT4 and OUT5.
I
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT4 and OUT5.
If 0x1E1<1:0> = 01b, there is no effect.
Table 46. VCO Divider and CLK Input
Reg.
Addr
(Hex) Bit(s) Name Description
1E0 <2:0> VCO Divider
0 0 0 2
0 0 1 3
0 1 0 4
0 1 1 5
1 0 0 6
1 0 1 Output static
1 1 0 Output static
1 1 1 Output static
1E1 <4> Power-Down Clock Input Section Power down the clock input section (including CLK buffer, VCO divider, and CLK tree).
<4> = 0; normal operation.
<4> = 1; power-down.
1E1 <3> Power-Down VCO Clock Interface Power down the interface block between VCO and clock distribution.
<3> = 0; normal operation.
<3> = 1; power-down.
1E1 <2> Power-Down VCO and CLK Power down both VCO and CLK input.
<2> = 0; normal operation.
<2> = 1; power-down.
<2> <1> <0> Divide
Rev. 0 | Page 59 of 64
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AD9518-2
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Reg.
Addr
(Hex) Bit(s) Name Description
1E1 <1> Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider.
<1> = 0; select external CLK as input to VCO divider.
<1> = 1; selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
1E1 <0> Bypass VCO Divider Bypass or use the VCO divider.
<0> = 0; use VCO divider.
<0> = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Table 47. System
Reg.
Addr
(Hex) Bit(s) Name Description
230 <2> Power-Down SYNC Power down the SYNC function.
<2> = 0; normal operation of the SYNC function.
<2> = 1; power-down SYNC circuitry.
230 <1> Power-Down Distribution Reference Power down the reference for distribution section.
<1> = 0; normal operation of the reference for the distribution section.
<1> = 1; power down the reference for the distribution section.
230 <0> Soft SYNC
The soft SYNC bit works the same as the SYNC
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
<0> = 0; same as SYNC
<0> = 1; same as SYNC
high.
low.
pin, except that the polarity of the bit
Table 48. Update All Registers
Reg.
Addr
(Hex)
Bit(s) Name Description
232 <0>
<0> = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Update All
egisters
R
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.
Rev. 0 | Page 60 of 64
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AD9518-2
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V
V
V
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APPLICATION NOTES
USING THE AD9518 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
⎛
⎜
SNR
×=
log20(dB)
⎜
⎝
where:
is the highest analog frequency being digitized.
f
A
is the rms jitter on the sampling clock.
t
J
Figure 50 shows the required sampling clock jitter as a function
f the analog frequency and effective number of bits (ENOB).
o
110
100
90
80
70
SNR (dB)
60
50
40
30
101k100
Figure 50. SNR and ENOB vs. Analog Input Frequency
For more information, see Application Note AN-756, Sampled
Systems and the Effects of Clock Phase Noise and Jitter, and Application Note AN-501, Aperture Uncertainty and ADC System
Performance, at www.analog.com.
⎞
1
⎟
⎟
π
tf
2
J
A
⎠
18
2πf
1
AtJ
16
14
12
ENOB
10
8
6
f
A
(MHz)
SNR = 20log
t
J
=
1
0
2
0
0
f
s
4
0
0
f
s
1
p
s
2
p
s
1
0
p
s
0
f
s
06431-044
Many high performance ADCs feature differential clock inputs
o simplify the task of providing the required low jitter clock on
t
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9518 features LVPECL outputs that provide differential
clock outputs, which enable clock solutions that maximize
converter SNR performance. The input requirements of the
ADC (differential or single-ended, logic level termination)
should be considered when selecting the best clocking/
converter solution.
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9518 provide the lowest jitter
clock signals available from the AD9518. The LVPECL outputs
(because they are open-emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 41 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
is r
ecommended, as shown in Figure 51. The resistor network is
ned to match the transmission line impedance (50 Ω) and
desig
the switching threshold (V
S_LVPECL
LVPECL
S_LVPECL
LVPECL
200Ω200Ω
Figure 52. LVPECL with Parallel Transmission Line
(NOT CO UPLED)
V
Figure 51. LVPECL Far-End Thevenin Termination
0.1nF
0.1nF
− 1.3 V).
S
50Ω
SINGLE-E NDED
50Ω
= VS – 1.3V
T
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
S_LVPECL
100Ω
127Ω127Ω
83Ω83Ω
V
S
LVPECL
S_LVPECL
LVPECL
6431-045
06431-046
Rev. 0 | Page 61 of 64
Page 62
AD9518-2
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
0.30
0.23
0.18
PIN 1
48
INDICATOR
1
BSC SQ
PIN 1
INDICATOR
7.00
0.60 MAX
37
36
0.60 MAX
1.00
0.85
0.80
12° MAX
SEATING
PLANE
TOP
VIEW
0.80 MAX
0.65 TYP
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
6.75
BSC SQ
0.20 REF
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
25
24
EXPOSED
PAD
(BOTTOM VIEW)
5.50
REF
13
5.25
5.10 SQ
4.95
12
0.25 MIN
Figure 53. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7
mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9518-2BCPZ
AD9518-2BCPZ-REEL7
AD9518-2/PCBZ
1
Z = RoHS Compliant Part.
1
1
1
−40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
−40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
Evaluation Board