On-chip VCO tunes from 1.75 GHz to 2.25 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
64-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9516-31 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to
2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9516-3 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
Integrated 2.0 GHz VCO
AD9516-3
FUNCTIONAL BLOCK DIAGRAM
PLL
∆
∆
∆
∆
LF
VCO
LVPECL
LVPECL
LVPECL
t
LVDS/CMOS
t
t
LVDS/CMOS
t
AD9516-3
STATUS
MONITOR
CP
REF1
REFIN
REF2
SWITCHOVER
AND MONITO R
CLK
DIV/ΦDIV/Φ
DIV/ΦDIV/Φ
SERIAL CONT ROL PO RT
DIVIDER
AND MUXs
DIV/Φ
DIV/Φ
DIV/Φ
AND
DIGITAL LOGIC
Figure 1.
The AD9516-3 features six LVPECL outputs (in three pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9516-3 is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-3 is specified for operation over the standard
industrial range of −40°C to +85°C.
1
AD9516 is used throughout to refer to all the members of the AD9516 family.
However, when AD9516-3 is used, it refers to that specific member of the
AD9516 family.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
06422-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Typical i s g iven for VS = V
Minimum and maximum values are given over full V
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
VS 3.135 3.3 3.465 V 3.3 V ± 5%
V
2.375 VS V Nominally 2.5 V to 3.3 V ± 5%
S_LVPECL
VCP V
RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground
CPRSET Pin Resistor 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability;
PLL CHARACTERISTICS
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
VCO (ON-CHIP)
Frequency Range 1750 2250 MHz See Figure 15
VCO Gain (K
Tuning Voltage (VT) 0.5 VCP −
Frequency Pushing (Open-Loop) 1 MHz/ V
Phase Noise at 100 kHz Offset −108 dBc/Hz f = 2000 MHz
Phase Noise at 1 MHz Offset −126 dBc/Hz f = 2000 MHz
REFERENCE INPUTS
Differential Mode (REFIN,
Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc-coupled; be careful
Input Sensitivity 250 mV p-p PLL figure of merit (FOM) increases with increasing slew rate; see
Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1
Self-Bias Voltage,
Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1
Input Resistance,
Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs
Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs
Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels
Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p
Input Logic High 2.0 V
Input Logic Low 0.8 V
Input Current −100 +100 μA
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
The PLL in-band phase noise floor is estimated by measuring the
in-band phase noise at the output of the VCO and subtracting
20log(N) (where N is the value of the N divider)
At 500 kHz PFD Frequency −165 dBc/Hz
At 1 MHz PFD Frequency −162 dBc/Hz
At 10 MHz PFD Frequency −151 dBc/Hz
At 50 MHz PFD Frequency −143 dBc/Hz
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum 2950 MHz
Output High Voltage (VOH) VS − 1.12 VS − 0.98 VS − 0.84 V
Output Low Voltage (VOL) VS − 2.03 VS − 1.77 VS − 1.49 V
Output Differential Voltage (VOD) 550 790 980 mV
LVDS CLOCK OUTPUTS Differential termination 100 Ω at 3.5 mA
OUT6, OUT7, OUT8, OUT9
Output Frequency 800 MHz
Differential Output Voltage (VOD) 247 360 454 mV
Delta VOD 25 mV
Output Offset Voltage (VOS) 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair
Delta VOS 25 mV
Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND
CMOS CLOCK OUTPUTS
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B
Output Frequency 250 MHz See Figure 27
Output Voltage High (VOH) VS − 0.1 V At 1 mA load
Output Voltage Low (VOL) 0.1 V At 1 mA load
Differential input
1
1.6 GHz Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is
improved with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
1.3 1.8 V With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK
Differential (OUT, OUT
ac-bypassed to RF ground
)
Using direct to output; see Figure 25 for peak-topeak differential amplitude
− VOL for each leg of a differential pair for
V
OH
default amplitude setting with driver not toggling;
see Figure 25 for variation over frequency
Differential (OUT, OUT
)
The AD9516 outputs toggle at higher frequencies,
but the output amplitude may not meet the VOD
specification; see Figure 26
− VOL measurement across a differential pair at
V
OH
the default amplitude setting with output driver
not toggling; see Figure 26 for variation over
frequency
This is the absolute value of the difference
between V
when the normal output is high vs.
OD
when the complementary output is high
This is the absolute value of the difference
between V
when the normal output is high vs.
OS
when the complementary output is high
Single-ended; termination = 10 pF
Rev. B | Page 6 of 80
Page 7
Data Sheet AD9516-3
TIMING CHARACTERISTICS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV
Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially
Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially
PROPAGATION DELAY, t
High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 43
Clock Distribution Configuration 773 933 1090 ps See Figure 45
Variation with Temperature 0.8 ps/°C
OUTPUT SKEW, LVPECL OUTPUTS1
LVPECL Outputs That Share the Same Divider 5 15 ps
LVPECL Outputs on Different Dividers 13 40 ps
All LVPECL Outputs Across Multiple Parts 220 ps
LVDS Termination = 100 Ω differential; 3.5 mA
Output Rise Time, tRL 170 350 ps 20% to 80%, measured differentially2
Output Fall Time, tFL 160 350 ps 20% to 80%, measured differentially2
PROPAGATION DELAY, t
OUT6, OUT7, OUT8, OUT9
For All Divide Values 1.4 1.8 2.1 ns
Variation with Temperature 1.25 ps/°C
OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs
LVDS Outputs That Share the Same Divider 6 62 ps
LVDS Outputs on Different Dividers 25 150 ps
All LVDS Outputs Across Multiple Parts 430 ps
CMOS Termination = open
Output Rise Time, tRC 495 1000 ps 20% to 80%; C
Output Fall Time, tFC 475 985 ps 80% to 20%; C
PROPAGATION DELAY, t
For All Divide Values 1.6 2.1 2.6 ns
Variation with Temperature 2.6 ps/°C
OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off
CMOS Outputs That Share the Same Divider 4 66 ps
All CMOS Outputs on Different Dividers 28 180 ps
All CMOS Outputs Across Multiple Parts 675 ps
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 10.0 MHz; R = 20
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method; DCC not used
for even divides
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method; DCC not used
for even divides
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method; DCC not used
for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210 fs rms Calculated from SNR of ADC method
285 fs rms Calculated from SNR of ADC method
350 fs rms Calculated from SNR of ADC method
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Rev. B | Page 11 of 80
Page 12
AD9516-3 Data Sheet
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter
100 MHz Output
Delay (1600 μA, 0x1C) Fine Adj. 000000 0.54 ps rms
Delay (1600 μA, 0x1C) Fine Adj. 101111 0.60 ps rms
Delay (800 μA, 0x1C) Fine Adj. 000000 0.65 ps rms
Delay (800 μA, 0x1C) Fine Adj. 101111 0.85 ps rms
Delay (800 μA, 0x4C) Fine Adj. 000000 0.79 ps rms
Delay (800 μA, 0x4C) Fine Adj. 101111 1.2 ps rms
Delay (400 μA, 0x4C) Fine Adj. 000000 1.2 ps rms
Delay (400 μA, 0x4C) Fine Adj. 101111 2.0 ps rms
Delay (200 μA, 0x1C) Fine Adj. 000000 1.3 ps rms
Delay (200 μA, 0x1C) Fine Adj. 101111 2.5 ps rms
Delay (200 μA, 0x4C) Fine Adj. 000000 1.9 ps rms
Delay (200 μA, 0x4C) Fine Adj. 101111 3.8 ps rms
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
CS (INPUT)
CS has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 3 μA
Input Logic 0 Current 110 μA
Input Capacitance 2 pF
SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 μA
Input Logic 0 Current 1 μA
Input Capacitance 2 pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current 20 nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
) 25 MHz
SCLK
16 ns
HIGH
16 ns
LOW
SDIO to SCLK Setup, tDS 2 ns
SCLK to SDIO Hold, tDH 1.1 ns
SCLK to Valid SDIO and SDO, tDV 8 ns
CS to SCLK Setup and Hold, tS, tH
CS Minimum Pulse Width High, t
PWH
2 ns
3 ns
Rev. B | Page 12 of 80
Page 13
Data Sheet AD9516-3
,
RESET
PD
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 110 μA
Logic 0 Current 1 μA
Capacitance 2 pF
RESET TIMING
Pulse Width Low 50 ns
SYNC TIMING
Pulse Width Low 1.5
LD, STATUS, AND REFMON PINS
Table 16.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
Output Voltage High (VOH) 2.7 V
Output Voltage Low (VOL) 0.4 V
MAXIMUM TOGGLE RATE 100 MHz
ANALOG LOCK DETECT
Capacitance 3 pF
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range 1.02 MHz
Extended Range (REF1 and REF2 Only) 8 kHz
LD PIN COMPARATOR
Trip Point 1.6 V
Hysteresis 260 mV
, AND
SYNC
PINS
These pins each have a 30 kΩ internal pull-up
resistor
High speed
clock cycles
High speed clock is CLK input signal
When selected as a digital output (CMOS);
there are other modes in which these pins
are not CMOS digital outputs; see Table 54 ,
Register 0x017, Register 0x01A, and Register 0x01B
Applies when mux is set to any divider or
counter output or PFD up/down pulse; also
applies in analog lock detect mode; usually
debug mode only; beware that spurs may couple
to output when any of these pins are toggling
On-chip capacitance; used to calculate RC time
constant for analog lock detect readback; use a
pull-up resistor
Frequency above which the monitor always
indicates the presence of the reference
Frequency above which the monitor always
indicates the presence of the reference
Rev. B | Page 13 of 80
Page 14
AD9516-3 Data Sheet
POWER DISSIPATION
Table 17.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled
VCO Divider 30 mW VCO divider bypassed
REFIN (Differential) 20 mW All references off to differential reference enabled
REF1, REF2 (Single-Ended) 4 mW
VCO 70 mW CLK input selected to VCO selected
PLL 75 mW PLL off to PLL on, normal operation; no reference enabled
Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32
LVPECL Channel (Divider Plus Output Driver) 160 mW
LVPECL Driver 90 mW Second LVPECL output turned on, same channel
LVDS Channel (Divider Plus Output Driver) 120 mW
LVDS Driver 50 mW Second LVDS output turned on, same channel
CMOS Channel (Divider Plus Output Driver) 100 mW
CMOS Driver (Second in Pair) 0 mW Static; second CMOS output, same pair, turned on
CMOS Driver (First in Second Pair) 30 mW Static; first output, second pair, turned on
Fine Delay Block 50 mW
75 185 mW
31 mW
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 2250 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
eight CMOS outputs (10 pF load) at 225 MHz; all fine delay on,
maximum current; does not include power dissipated in
external resistors
PLL on; internal VCO = 2250 MHz, VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
four LVDS outputs at 225 MHz; all fine delay on, maximum
current; does not include power dissipated in external
resistors
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 19.
Package Type1 θ
64-Lead LFCSP 22 °C/W
1
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-2.
ESD CAUTION
REFMON, STATUS, LD to GND −0.3 V to VS + 0.3 V
Junction Temperature1 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (10 sec) 300°C
1
See Table 19 for θJA.
Unit
JA
Rev. B | Page 16 of 80
Page 17
Data Sheet AD9516-3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFIN (REF1)
REFIN (REF2)
CPRSETVSVS
GND
RSETVSOUT0
OUT0
VS_LVPECL
OUT1
OUT1VSVS
646362616059585756555453525150
VS
49
1
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
10
BYPASS
11
VS
12
VS
13
CLK
14
CLK
15
NC
16
SCLK
NC = NO CONNECT
NOTES
1. THE EXT ERNAL PADDL E ON THE BO TTO M OF THE PACKAGE MUS T BE
CONNECTED T O GROUND F OR PROPE R OPERATI ON.
2. NC = NO CONNECT. DO NOT CONNECT TO T HIS PIN.
PIN 1
INDICATOR
2
3
4
5
6
7
8
9
171819202122232425262728293031
CS
NCNCNC
SDO
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Input/
Pin No.
1, 11, 12, 30,
Output
Pin Type Mnemonic Description
I Power VS 3.3 V Power Pins.
31, 32, 38,
49, 50, 51,
57, 60, 61
2 I 3.3 V CMOS REFMON
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
3 O 3.3 V CMOS LD
Lock Detect (Output). This pin has multiple selectable outputs; see Table 54 ,
Register 0x1A.
4 I Power VCP
5 O 3.3 V CMOS CP
6 O 3.3 V CMOS STATUS
7 I 3.3 V CMOS REF_SEL
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V.
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 5 4, Register 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
8 I 3.3 V CMOS
SYNC
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
9 I Loop filter LF
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large (>500 kHz) loop bandwidths.
10 O Loop filter BYPASS
13 I
Differential
CLK
This pin is for bypassing the LDO to ground with a capacitor.
Along with CLK
clock input
14 I
Differential
CLK
Along with CLK, this is the differential input for the clock distribution section.
clock input
LVPECL LVPECL
AD9516-3
TOP VIEW
(Not to Scale)
LVPECL LVPECL
PD
SDIO
OUT4
RESET
OUT6 (OUT6A)
48
OUT6 (OUT6B)
47
OUT7 (OUT7A)
46
OUT7 (OUT7B)
45
LVDS/CMOS
w/FINE DEL AY ADJUST
LVDS/CMOS
w/FINE DELAY ADJUST
32
VSVSVS
OUT4
OUT5
OUT5
VS_LVPECL
LVPECL LVPECL
GND
44
OUT2
43
OUT2
42
VS_LVPECL
41
OUT3
40
OUT3
39
VS
38
GND
37
OUT9 (OUT9B)
36
OUT9 (OUT9A)
35
OUT8 (OUT8B)
34
OUT8 (OUT8A)
33
06422-003
, this is the differential input for the clock distribution section.
Rev. B | Page 17 of 80
Page 18
AD9516-3 Data Sheet
Input/
Pin No.
15, 18, 19, 20 N/A NC NC No Connect. Do not connect to this pin.
16 I 3.3 V CMOS SCLK Serial Control Port Data Clock Signal.
17 I 3.3 V CMOS
21 O 3.3 V CMOS SDO Serial Control Port Unidirectional Serial Data Out.
22 I/O 3.3 V CMOS SDIO Serial Control Port Bidirectional Serial Data In/Out.
23 I 3.3 V CMOS
24 I 3.3 V CMOS
27, 41, 54 I Power VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
37, 44, 59,
EPAD
56 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output.
55 O LVPECL
53 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output.
52 O LVPECL
43 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output.
42 O LVPECL
40 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output.
39 O LVPECL
25 O LVPECL OUT4 LVPECL Output; One Side of a Differential LVPECL Output.
26 O LVPECL
28 O LVPECL OUT5 LVPECL Output; One Side of a Differential LVPECL Output.
29 O LVPECL
48 O
47 O
46 O
45 O
33 O
34 O
35 O
36 O
58 O
62 O
63 I
64 I
Output Pin Type Mnemonic Description
Serial Control Port Chip Select, Active Low. This pin has an internal 30 kΩ pull-up
CS
resistor.
RESET
PD
N/A GND GND
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
Current set
resistor
Current set
resistor
Reference
input
Reference
input
OUT6
(OUT6A)
OUT6
(OUT6B)
OUT7
(OUT7A)
OUT7
(OUT7B)
OUT8
(OUT8A)
OUT8
(OUT8B)
OUT9
(OUT9A)
OUT9
(OUT9B)
RSET A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.
CPRSET A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ.
REFIN
(REF2)
REFIN
(REF1)
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Ground Pins, Including External Paddle (EPAD). The external paddle on the bottom of
the package must be connected to ground for proper operation.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
Along with REFIN
Alternatively, this pin is a single-ended input for REF1.
, this pin is the differential input for the PLL reference.
Rev. B | Page 18 of 80
Page 19
Data Sheet AD9516-3
TYPICAL PERFORMANCE CHARACTERISTICS
300
280
260
240
220
200
180
CURRENT (mA)
160
140
120
100
050010001500200025003000
3 CHANNELS—6 LVPE CL
3 CHANNELS—3 LVPE CL
2 CHANNELS—2 LVPE CL
1 CHANNEL—1 LVPECL
FREQUENCY (MHz)
Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs
06422-007
70
65
60
55
50
(MHz/V)
45
VCO
K
40
35
30
25
1.71.81.92.02.12. 22.3
VCO FREQUENCY ( GHz)
Figure 10. VCO K
vs. Frequency
VCO
06422-010
180
2 CHANNELS—4 LVDS
160
140
120
CURRENT (mA)
100
80
0200400600800
2 CHANNELS—2 LVDS
1 CHANNEL—1 LVDS
FREQUENCY (MHz )
Figure 8. Current vs. Frequency—LVDS Outputs
(Includes Clock Distribution Current Draw)
240
220
200
180
160
140
CURRENT (mA)
120
100
2 CHANNELS—8 CMOS
1 CHANNEL—2 CMOS
80
0220015010050
2 CHANNELS—2 CMOS
1 CHANNEL—1 CMOS
FREQUENCY (MHz )
Figure 9. Current vs. Frequency—CMOS Outputs
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
CURRENT FROM CP P IN (mA)
1.0
0.5
06422-008
PUMP DOWNPUMP UP
0
00.51.01.52.02.53.0
VOLTAGE ON CP PIN (V)
Figure 11. Charge Pump Characteristics at VCP = 3.3 V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
CURRENT FROM CP P IN (mA)
1.0
0.5
50
06422-009
0
PUMP DOWNPUMP UP
00.5 1.0 1.5 2.03.04.02.53.55.04.5
VOLTAGE ON CP PIN (V)
Figure 12. Charge Pump Characteristics at V
= 5.0 V
CP
06422-011
06422-012
Rev. B | Page 19 of 80
Page 20
AD9516-3 Data Sheet
–
–
140
–145
–150
–155
(dBc/Hz)
–160
–165
PFD PHASE NOI SE REFERRED TO PFD INPUT
–170
0.1110010
PFD FREQUENCY (MHz)
Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
210
–212
–214
–216
–218
–220
PLL FIGURE OF MERIT (dBc/ Hz)
–222
–224
022.01.51.00.5
SLEW RATE (V/n s)
Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/
1.9
1.7
1.5
1.3
VCO TUNING V OLTAGE (V)
1.1
0.9
1.71.81. 92. 02.12.22. 3
VCO FREQUENCY ( GHz)
Figure 15. VCO Tuning Voltage vs. Frequency
(Note that VCO calibration centers the dc tuning voltage
for the PLL setup that is active during calibration.)
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that can be
attributed to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
When there are multiple contributors to phase noise, the total
is the square root of the sum of squares of the individual
contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that can be
attributed to the device or subsystem being measured. The time
jitter of any external oscillators or clock sources is subtracted. This
makes it possible to predict the degree to which the device impacts
the total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contributes
its own time jitter to the total. In many cases, the time jitter of
the external oscillators and clock sources dominates the system
time jitter.
Rev. B | Page 25 of 80
Page 26
AD9516-3 Data Sheet
V
DETAILED BLOCK DIAGRAM
REFIN (REF1)
REFIN (REF2)
BYPASS
CLK
CLK
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
REF1
REF2
LF
REF_ SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPOUT
REGULATOR (LDO)
VCO
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
SGNDRSET
DISTRI BUTIO N
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
N DIVIDER
DIVIDE BY
2, 3, 4, 5, OR 6
01
A/B
COUNTERS
REFMON
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LOCK
DETECT
PHASE
FREQUENCY
DETECTO R
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
AD9516-3
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
Figure 42. Detailed Block Diagram
Rev. B | Page 26 of 80
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
∆
∆
∆
∆
t
t
t
t
LVDS/CMOS
LVDS/CMOS
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
6422-002
Page 27
Data Sheet AD9516-3
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9516 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Tabl e 52 and Ta bl e 53 through Tab l e 6 2 ). Each section
or function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
High Frequency Clock Distribution—CLK or External
VCO > 1600 MHz
The AD9516 power-up default configuration has the PLL
powered off and the routing of the input set so that the
CLK
CLK/
through the VCO divider (divide-by-2/ divide-by-3/divide-by4/divide-by-5/divide-by-6). This is a distribution only mode
that allows for an external input up to 2400 MHz (see ).
The maximum frequency that can be applied to the channel
dividers is 1600 MHz; therefore, higher input frequencies must
be divided down before reaching the channel dividers. This
input routing can also be used for lower input frequencies, but
the minimum divide is 2 before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency of less
than 2400 MHz. In this configuration, the internal VCO is not
used and is powered off. The external VCO/VCXO feeds
directly into the prescaler.
The register settings shown in Table 2 1 are the default values of
these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
input is connected to the distribution section
Tabl e 3
Table 21. Default Settings of Some PLL Registers
Register Function
0x010[1:0] = 01b PLL asynchronous power-down (PLL off).
0x1E0[2:0] = 010b Set VCO divider = 4.
0x1E1[0] = 0b Use the VCO divider.
0x1E1[1] = 0b CLK selected as the source.
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 22. Settings When Using an External VCO
Register Function
0x010[1:0] = 00b PLL normal operation (PLL on).
0x010 to 0x01D
0x1E1[1] = 0b CLK selected as the source.
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 23. Setting the PFD Polarity
Register Function
0x010[7] = 0b
0x010[7] = 1b
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
according to the intended loop configuration.
PFD polarity positive (higher control
voltage produces higher frequency).
PFD polarity negative (higher control
voltage produces lower frequency).
CP
,
Rev. B | Page 27 of 80
Page 28
AD9516-3 Data Sheet
V
REFIN (REF1)
REFIN (REF2)
BYPASS
CLK
CLK
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
REF1
REF2
REGULATOR (LDO)
LF
REF_SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
LOW DROPOUT
VCO
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
STATUS
SGNDRSET
DISTRI BUTIO N
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
N DIVIDER
DIVIDE BY
2, 3, 4, 5, OR 6
01
A/B
COUNTERS
REFMON
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LOCK
DETECT
PHASE
FREQUENCY
DETECTO R
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
06422-029
AD9516-3
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
∆
∆
∆
∆
t
LVDS/CMOS
t
t
LVDS/CMOS
t
Figure 43. High Frequency Clock Distribution or External VCO > 1600 MHz
Rev. B | Page 28 of 80
Page 29
Data Sheet AD9516-3
V
REFIN (REF 1)
REFIN (REF 2)
BYPASS
CLK
CLK
SYNC
RESET
SCLK
SDIO
SDO
REF1
REF2
LF
PD
CS
REF_SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPO UT
REGULATOR ( LDO)
VCO
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
SGNDRSET
DISTRIBUTI ON
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5 , OR 6
01
N DIVIDER
A/B
COUNTERS
REFMON
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LOCK
DETECT
PHASE
FREQUENCY
DETECTOR
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9516-3
Figure 44. Internal VCO and Clock Distribution
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the
channel dividers does not exceed their specified maximum
frequency of 1600 MHz (see Tabl e 3). The internal PLL uses an
external loop filter to set the loop bandwidth. The external loop
filter is also crucial to the loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, use the
register settings that are shown in Tab l e 2 4 .
Rev. B | Page 29 of 80
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
6422-030
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
∆
∆
∆
∆
t
LVDS/CMOS
t
t
LVDS/CMOS
t
Table 24. Settings When Using Internal VCO
Register Function
0x010[1:0] = 00b PLL normal operation (PLL on).
0x010 to 0x01E PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
CP
according to the intended loop configuration.
0x018[0] = 0b,
0x232[0] = 1b
Reset VCO calibration. This is not required
the first time after power-up, but it must
be performed subsequently.
0x1E0[2:0] Set VCO divider to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, and divide-by-6.
0x1E1[0] = 0b Use the VCO divider as source for the
distribution section.
0x1E1[1] = 1b Select VCO as the source.
0x018[0] = 1b,
Initiate VCO calibration.
0x232[0] = 1b
,
Page 30
AD9516-3 Data Sheet
V
REFIN (REF1)
REFIN (REF2)
BYPASS
CLK
CLK
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
REF1
REF2
LF
REF_SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPO UT
REGULATOR (LDO)
VCO
DIGIT AL
LOGIC
SERIAL
CONTROL
PORT
SGNDRSET
DISTRI BUTIO N
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
N DIVIDER
DIVIDE BY
2, 3, 4, 5, OR 6
01
A/B
COUNTERS
REFMON
PROGRAM MABLE
R DELAY
PROGRAM MABLE
N DELAY
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LOCK
DETECT
PHASE
FREQUENCY
DETECT OR
PLL
REFERENCE
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
LD
CP
STATUS
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
06422-028
AD9516-3
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
∆
∆
∆
∆
t
LVDS/CMOS
t
t
LVDS/CMOS
t
Figure 45. Clock Distribution or External VCO < 1600 MHz
Rev. B | Page 30 of 80
Page 31
Data Sheet AD9516-3
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
High Frequency Clock Distribution—CLK or External VCO >
1600 MHz section only in that the VCO divider (divide-by-2,
divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed.
This limits the frequency of the clock source to <1600 MHz (due
to the maximum input frequency allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, use the register settings that are shown in Table 25 .
Table 25. Settings for Clock Distribution < 1600 MHz
Bypass the VCO divider as source for
distribution section
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
Table 26. Settings for Using Internal PLL with External VCO <
1600 MHz
Register Function
0x1E1[0] = 1b
0x010[1:0] = 00b
Bypass the VCO divider as source for
distribution section
PLL normal operation (PLL on), along with
other appropriate PLL settings in Register 0x010
to Register 0x01E
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 27. Setting the PFD Polarity
Register Function
0x010[7] = 0b
0x010[7] = 1b
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control voltage
produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Rev. B | Page 31 of 80
Page 32
AD9516-3 Data Sheet
VCPV
Phase-Locked Loop (PLL)
REF_SEL
SGND
RSET
REFMO N
CPRSET
N DIVIDER
DIST
REF
R DIVIDER
A/B
COUNTERS
0
1
REFIN ( REF1)
REFIN ( REF2)
BYPASS
CLK
CLK
REGULATOR (LDO)
LF
REFERENCE
SWITCHOVER
REF1
REF2
LOW DROPOUT
VCO
STATUS
STATUS
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5, OR 6
01
Figure 46. PLL Functional Blocks
The AD9516 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop, or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9516 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be exploited to
clean up jitter and phase noise on a noisy reference. The exact
choices of PLL parameters and loop dynamics are very application
specific. The flexibility and depth of the AD9516 PLL allow the
part to be tailored to function in many different applications
and signal environments.
Configuration of the PLL
The AD9516 allows flexible configuration of the PLL,
accommodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
that include the R divider, the N divider, the PFD polarity (only
applicable to external VCO/VCXO), the antibacklash pulse
width, the charge pump current, the selection of internal VCO
or external VCO/VCXO, and the loop bandwidth.
Rev. B | Page 32 of 80
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
VCO STATUS
These are managed through programmable register settings (see
Tabl e 5 2 and Tabl e 54) and by the design of the external loop
filter. Successful PLL operation and satisfactory PLL loop
performance are highly dependent upon proper configuration of
the PLL settings. The design of the external loop filter is crucial
to the proper operation of the PLL. A thorough knowledge of
PLL theory and design is helpful.
ADIsimCLK™ (V1.2 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9516, including the design of the PLL loop filter. It is
available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD
transfer function and minimizes phase noise and reference
spurs. The antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD, which in turn determines the correct
antibacklash pulse setting. The antibacklash pulse setting is
specified in the phase/frequency detector parameter of Tabl e 2 .
LOCK
DETECT
PHASE
FREQUENCY
DETECTOR
PLL
REF
HOLD
CHARGE PUMP
LD
CP
STATUS
06422-064
Page 33
Data Sheet AD9516-3
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs,
and tells the CP to pump up or pump down to charge or discharge
the integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the internal VCO through the LF pin (or the tuning
pin of an external VCO) to move the VCO frequency up or down.
The CP can be set (Register 0x010[6:4]) for high impedance
(allows holdover operation), for normal operation (attempts to
lock the PLL loop), for pump up, or for pump down (test modes).
The CP current is programmable in eight steps from (nominally)
600 μA to 4.8 mA. The exact value of the CP current LSB is set
by the CPRSET resistor, which is nominally 5.1 kΩ. If the value
of the resistor connected to the CP_RSET pin is doubled, the
resulting charge pump current range becomes 300 μA to 2.4 mA.
On-Chip VCO
The AD9516 includes an on-chip VCO covering the frequency
range shown in Tab le 2 . The calibration procedure ensures that
the VCO operating voltage is centered for the desired VCO
frequency. The VCO must be calibrated when the VCO loop is first
set up, as well as any time the nominal VCO frequency changes.
However, once the VCO is calibrated, the VCO has sufficient
operating range to stay locked over temperature and voltage
extremes without needing additional calibration. See the VCO
Calibration section for more information.
The on-chip VCO is powered by an on-chip, low dropout
(LDO), linear voltage regulator. The LDO provides some
isolation of the VCO from variations in the power supply
voltage level. The BYPASS pin should be connected to ground
by a 220 nF capacitor to ensure stability. This LDO employs the
same technology used in the anyCAP® line of regulators from
Analog Devices, Inc., making it insensitive to the type of
capacitor used. Driving an external load from the BYPASS pin
is not supported.
Note that the reference input signal must be present and the
VCO divider must not be static during VCO calibration.
PLL External Loop Filter
When using the internal VCO, the external loop filter should
be referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for a PLL
that uses the internal VCO is shown in Figure 47. The thirdorder design shown in Figure 47 usually offers best performance.
A loop filter must be calculated for each desired PLL configuration.
The values of the components depend upon the VCO frequency,
the K
, the PFD frequency, the CP current, the desired loop
VCO
bandwidth, and the desired phase margin. The loop filter affects
the phase noise, the loop settling time, and loop stability. A basic
knowledge of PLL theory is helpful for understanding loop filter
design. ADIsimCLK can help with calculation of a loop filter
according to the application requirements.
Rev. B | Page 33 of 80
Figure 47. Example of External Loop Filter for a PLL Using the Internal VCO
When using an external VCO, the external loop filter should be
referenced to ground. See Figure 48 for an example of an
external loop filter for a PLL using an external VCO.
Figure 48. Example of External Loop Filter for a PLL Using an External VCO
PLL Reference Inputs
The AD9516 features a flexible PLL reference input circuit that
allows either a fully differential input or two separate singleended inputs. The input frequency range for the reference
inputs is specified in Ta b le 2 . Both the differential and the
single-ended inputs are self-biased, allowing for easy ac
coupling of input signals.
The differential input and the single-ended inputs share the two
pins, REFIN/
reference input type is selected and controlled by Register 0x01C
(see and ). Tabl e 52Tab l e 5 4
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (~100 mV, see Ta b le 2 ) to
prevent chattering of the input buffer when the reference is slow
or missing. This increases the voltage swing that is required of the
driver and overcomes the offset. The differential reference input
can be driven by either ac-coupled LVDS or ac-coupled LVPECL
signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down, or when the differential reference input
is not selected. The single-ended buffers power down when the
PLL is powered down, and when their individual power down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
AD9516-3
VCO
31pF
CHARGE
PUMP
AD9516-3
CHARGE
PUMP
REFIN
LF
CP
BYPASS
C
CLK/CLK
CP
= 220nF
BP
R2
R1
C1C2C3
EXTERNAL
VCO/VCXO
R2
R1
C1C2C3
(REF1 and REF2, respectively). The desired
06422-065
06422-265
Page 34
AD9516-3 Data Sheet
V
In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by
a single-ended signal, the unused side (
decoupled via a suitable capacitor to a quiet ground.
REFIN
) should be
Figure 49
shows the equivalent circuit of REFIN.
S
85kΩ
REF1
V
S
REFIN
REFIN
REF2
10kΩ 12kΩ
150Ω
150Ω
10kΩ 10kΩ
V
S
85kΩ
Figure 49. REFIN Equivalent Circuit
06422-066
Reference Switchover
The AD9516 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9516 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin
REFIN
). This feature supports networking
and other applications that require smooth switching of redundant
references. When used in conjunction with the automatic
holdover function, the AD9516 can achieve a worst-case
reference input switchover with an output frequency disturbance as
low as 10 ppm.
When using reference switchover, the single-ended reference
inputs should be dc-coupled CMOS levels and never be allowed
to go to high impedance. If these inputs are allowed to go to high
impedance, noise may cause the buffer to chatter, causing a
false detection of the presence of a reference.
Reference switchover can be performed manually or automatically. Manual switchover is performed either through
Register 0x01C or by using the REF_SEL pin. Manual switchover
requires the presence of a clock on the reference input that is
being switched to, or that the deglitching feature be disabled
(Register 0x01C[7]). The reference switching logic fails if this
condition isn’t met, and the PLL does not reacquire.
Automatic revertive switchover relies on the REFMON pin to
indicate when REF1 disappears. By programming Register 0x01B =
0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed
to be high when REF1 is invalid, which commands the switch to
REF2. When REF1 is valid again, the REFMON pin goes low, and
the part again locks to REF1. It is also possible to use the STATUS
pin for this function, and REF2 can be used as the preferred
reference.
A switchover deglitch feature ensures that the PLL does not
receive rising edges that are far out of alignment with the newly
selected reference.
Automatic nonrevertive switching is not supported.
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16383 by
writing to Register 0x011 and Register 0x012. (Both R = 0 and
R = 1 give divide-by-1.) The output of the R divider goes to one
of the PFD inputs to be compared to the VCO frequency
divided by the N divider. The frequency applied to the PFD
must not exceed the maximum allowable frequency, which
depends on the antibacklash pulse setting (see Tabl e 2).
The R counter has its own reset. R counter can be reset using
the shared reset bit of the R, A, and B counters. It can also be
reset by a
SYNC
operation.
VCXO/VCO Feedback Divider N—P, A, B, R
The N divider is a combination of a prescaler (P) and two
counters, A and B. The total divider value is
N = (P × B) + A
where the value of P can be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9516 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3, 4
and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of
operation are given in Tabl e 54 , Register 0x016[2:0]. Not all
modes are available at all frequencies (see Tabl e 2 ).
When operating the AD9516 in dual modulus mode (P//P + 1),
the equation used to relate input reference frequency to VCO
output frequency is
f
= (f
VCO
/R) × (P × B + A) = f
REF
× N/R
REF
However, when operating the prescaler in FD mode, 1, 2, or 3,
the A counter is not used (A = 0) and the equation simplifies to
f
= (f
VCO
/R) × (P × B) = f
REF
× N/R
REF
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
in which case the previous equation also applies.
Rev. B | Page 34 of 80
Page 35
Data Sheet AD9516-3
By using combinations of DM and FD modes, the AD9516 can
achieve values of N all the way down to N = 1 and up to N =
26,2175. Table 28 shows how a 10 MHz reference input can be
locked to any integer multiple of N.
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode of P = 2 with B = 6; use the dual modulus mode of
2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with
A = 0, B = 3.
The maximum frequency into the prescaler in 2/3 dual-modulus
mode is limited to 200 MHz. There are only two cases where
this frequency limitation limits the flexibility of that N divider:
N = 7 and N = 11. In these two cases, the maximum frequency
into the prescaler is 300 MHz and is achieved by using the P = 1
FD mode. In all other cases, the user can achieve the desired N
divider value by using the other prescaler modes.
A and B Counters
The B counter must be ≥3 or bypassed, and, unlike the R counter,
A = 0 is actually zero.
When the prescaler is in dual modulus mode, the A counter
must be less than the B counter.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) that is
specified in Ta b le 2 . This is the prescaler input frequency (VCO or
CLK) divided by P. For example, a dual modulus mode of P = 8/9
is not allowed if the VCO frequency is greater than 2400 MHz
because the frequency going to the A/B counter is too high.
When the AD9516 B counter is bypassed (B = 1), the A counter
should be set to 0, and the overall resulting divide is equal to the
prescaler setting, P. The possible divide ratios in this mode are
1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an
external VCO/VCXO is used because the frequency range of the
internal VCO requires an overall feedback divider greater than 32.
Although manual reset is not normally required, the A/B counters
have their own reset bit. Alternatively, the A and B counters can be
reset using the shared reset bit of the R, A, and B counters. Note
that these reset bits are not self-clearing.
R, A, and B Counters—
SYNC
Pin Reset
The R, A, and B counters can also be reset simultaneously through
SYNC
the
(see ). The Tabl e 54
pin. This function is controlled by Register 0x019[7:6]
SYNC
pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Tabl e 54 .
Table 28. Using a 10 MHz Reference Input to Generate Different VCO Frequencies
f
REF
(MHz) R P A B N
10 1 1 X 1 1 10 FD P = 1, B = 1 (A and B counters are bypassed).
10 1 2 X 1 2 20 FD P = 2, B = 1 (A and B counters are bypassed).
10 1 1 X 3 3 30 FD A counter is bypassed.
10 1 1 X 4 4 40 FD A counter is bypassed.
10 1 1 X 5 5 50 FD A counter is bypassed.
10 1 2 X 3 6 60 FD A counter is bypassed.
10 1 2 0 3 6 60 DM
10 1 2 1 3 7 70 DM
Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.
If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz
to 300 MHz, use P = 1, and N = 7 or 11, respectively.
P = 32 is not allowed (A > B not allowed).
P = 16 is also permitted.
Rev. B | Page 35 of 80
Page 36
AD9516-3 Data Sheet
V
V
CLKC
DIGITAL LOCK DETECT (DLD)
By selecting the proper output through the mux on each pin,
the DLD function can be made available at the LD, STATUS,
and REFMON pins. The DLD circuit indicates a lock when the
time difference of the rising edges at the PFD inputs is less than
a specified value (the lock threshold). The loss of a lock is
indicated when the time difference exceeds a specified value
(the unlock threshold). Note that the unlock threshold is wider
than the lock threshold, which allows some phase error in
excess of the lock window to occur without chattering on the
lock indicator.
The lock detect window timing depends on three settings: the
digital lock detect window bit (Register 0x018[4]), the antibacklash pulse width setting (Register 0x017[1:0], see Table 2 ),
and the lock detect counter (Register 0x018[6:5]). A lock is not
indicated until there is a programmable number of consecutive
PFD cycles with a time difference that is less than the lock
detect threshold. The lock detect circuit continues to indicate
a lock until a time difference greater than the unlock threshold
occurs on a single subsequent cycle. For the lock detect to work
properly, the period of the PFD frequency must be greater than
the unlock threshold. The number of consecutive PFD cycles
required for lock is programmable (Register 0x018[6:5]).
Analog Lock Detect (ALD)
The AD9516 provides an ALD function that can be selected for
use at the LD pin. There are two versions of ALD, as follows:
•N-channel open-drain lock detect. This signal requires
a pull-up resistor to positive supply, VS. The output is
normally high with short, low going pulses. Lock is indicated
by the minimum duty cycle of the low-going pulses.
•P-channel open-drain lock detect. This signal requires
a pull-down resistor to GND. The output is normally
low with short, high going pulses. Lock is indicated by
the minimum duty cycle of the high-going pulses.
The analog lock detect function requires an R-C filter to
provide a logic level indicating lock/unlock.
= 3.3
S
AD9516-3
LD
ALD
Figure 50. Example of Analog Lock Detect Filter, Using
N-Channel Open-Drain Driver
Current Source Digital Lock Detect (DLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is made possible by using
the current source lock detect function. This function is set
R2
V
R1
OUT
C
06422-067
when it is selected as the output from the LD pin control
(Register 0x01A[5:0]).
The current source lock detect provides a current of 110 μA
when DLD is true, and it shorts to ground when DLD is false.
If a capacitor is connected to the LD pin, it charges at a rate that
is determined by the current source during the DLD true time
but is discharged nearly instantly when DLD is false. By
monitoring the voltage at the LD pin (top of the capacitor), it is
possible to get a logic high level only after the DLD has been
true for a sufficiently long time. Any momentary DLD false
resets the charging. By selecting a properly sized capacitor, it is
possible to delay a lock detect indication until the PLL is stably
locked, and the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (Register 0x01B[4:0]) or the STATUS pin control
(Register 0x017[7:2]) as an active high signal. It is also available
as an active low signal (REFMON, Register 0x01B[4:0] and
STATUS, Register 0x017[7:2]). The internal LD pin comparator
trip point and hysteresis are listed in Tab le 1 6.
AD9516-3
110µA
C
V
OUT
CLK
06422-068
)
DLD
LD PIN
COMPARAT OR
Figure 51. Current Source Lock Detect
LD
REFMON
OR
STATUS
External VCXO/VCO Clock Input (CLK/
CLK is a differential input that can be used as an input to drive
the AD9516 clock distribution section. This input can receive
up to 2.4 GHz. The pins are internally self-biased and the input
signal should be ac-coupled via capacitors.
CLOCK INPUT
STAGE
06422-032
The CLK/
VS
LK
2.5kΩ2.5kΩ
5kΩ
5kΩ
Figure 52. CLK Equivalent Input Circuit
CLK
input can be used either as a distribution only
input (with the PLL off ), or as a feedback input for an external
VCO/VCXO using the internal PLL, when the internal VCO is
not used. The CLK/
CLK
input can be used for frequencies up
to 2.4 GHz.
Rev. B | Page 36 of 80
Page 37
Data Sheet AD9516-3
Holdover
The AD9516 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a state of high
impedance. This is useful when the PLL reference clock is lost.
Holdover mode allows the VCO to maintain a relatively constant
frequency even though there is no reference clock. Without this
function, the charge pump is placed into a constant pump-up or
pump-down state resulting in a massive VCO frequency shift.
Because the charge pump is placed in a high impedance state,
any leakage that occurs at the charge pump output or the VCO
tuning node causes a drift of the VCO frequency. This can be
mitigated by using a loop filter that contains a large capacitive
component because this drift is limited by the current leakageinduced slew rate (I
/C) of the VCO control voltage. For most
LEAK
applications, the frequency accuracy is sufficient for 3 sec to 5 sec.
SYNC
Both a manual holdover, using the
pin, and an automatic
holdover mode are provided. To use either function, the
holdover function must be enabled (Register 0x01D[0] and
Register 0x01D[2]).
Note that the VCO cannot be calibrated with the holdover enabled
because the holdover resets the N divider during calibration,
which prevents proper calibration. Disable holdover before
issuing a VCO calibration.
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user
to place the charge pump into a high impedance state when the
SYNC
pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state take the
SYNC
pin high. The charge pump then leaves
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between
SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state as long as there
is no reference clock present.
The B counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, set the channel dividers to ignore the
SYNC
pin (at least after an initial
not set to ignore the
SYNC
each time
is taken low to put the part into holdover.
SYNC
SYNC
event). If the dividers are
pin, the distribution outputs turn off
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappears.
See Figure 53 for a flowchart of the internal/automatic holdover
function operation.
PLL ENABLED
LOOP OUT OF LOCK. DIGITAL LOCK
NO
DETECT SIGNAL G OES L OW WHEN THE
LOOP L EAVES L OCK AS DET ERMINED
DLD == LOW
YES
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
YES
HIGH IMPEDANCE
CHARGE PUMP
YES
REFERENCE
EDGE AT PFD?
YES
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
YES
DLD == HIG H
Figure 53. Flowchart of Automatic/Internal Holdover Mode
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
NO
ANALOG L OCK DETE CT PIN I NDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
REGISTER 0x1D[3] = 1: USE LD PIN
VOLTAGE WITH HOLDOVER.
REGIST ER 0x1D[3] = 0: IGNORE LD PIN
VOLTAGE,TREAT LD PIN AS ALWAYS HIGH.
CHARGE PUMP I S MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTI NUE
OPERATI NG NORMALLY.
NO
CHARGE PUMP REMAINS HI GH
IMPEDANCE UNTIL T HE REFERENCE
HAS RETURNED.
YES
TAKE CHARGE P UMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
NO
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCL ES (PROGRAMMING OF
THE DLD DEL AY COUNTER) WIT H THE
REFERENCE AND FEEDBACK CL OCKS
INSIDE T HE LOCK W INDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEF ORE THE HOLDOVER
FUNCTIO N CAN BE RETRI GGERED.
6422-069
Rev. B | Page 37 of 80
Page 38
AD9516-3 Data Sheet
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (Register 0x01D[3]), which causes the holdover
function to always sense LD as high. If DLD is used, it is possible
for the DLD signal to chatter some while the PLL is reacquiring
lock. The holdover function may retrigger, thereby preventing
the holdover mode from ever terminating. Use of the current
source lock detect mode is recommended to avoid this situation
(see the Current Source Digital Lock Detect section).
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N
divider) is reset synchronously with the charge pump leaving the
high impedance state on the reference path PFD event. This
helps align the edges out of the R and N dividers for faster settling
of the PLL and to reduce frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close because this results in a smaller phase
difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if Register 0x01D[3] = 1) before it can
re-enter holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (Register 0x01C). If the loop loses
lock during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the internal/automatic holdover
function:
•Register 0x018[6:5], lock detect counter. These bits change
the number of consecutive PFD cycles with edges inside the
lock detect window that are required for the DLD indicator
to indicate lock. This impacts the time required before the
LD pin can begin to charge as well as the delay from the end
of a holdover event until the holdover function can be
reengaged.
•Register 0x018[3], disable digital lock detect. This bit must
be set to a 0 to enable the DLD circuit. Internal/automatic
holdover does not operate correctly without the DLD function
enabled.
•Register 0x01A[5:0], lock detect pin output select. Set these
bits to 000100b for the current source lock detect mode if
using the LD pin comparator. Load the LD pin with a
capacitor of an appropriate value.
• Register 0x01D[2]=1b; enable the holdover function.
• Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
•Register 0x01D[0] = 1b; enable the holdover function.
(VCO calibration must be complete before this bit is
enabled.)
•Connect REFMON pin to REFSEL pin.
Frequency Status Monitors
The AD9516 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 54.
The PLL reference frequency monitors have two threshold
frequencies: normal and extended (see Tabl e 16 ). The reference
frequency monitor thresholds are selected in Register 0x01B[7:5].
Frequency monitor status can be found in Register 0x01F[3:1].
Page 39
Data Sheet AD9516-3
V
REF1
REF2
REFIN (REF1)
REFIN (REF2)
BYPASS
REGULATOR (LDO)
LF
CLK
CLK
REF_SELCPRSETVCP
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPOUT
VCO
SGNDRSET
DISTRIBUTION
REFERENCE
R
DIVIDER
N DIVIDER
P, P + 1
PRESCALER
DIVIDE BY
2, 3, 4, 5, OR 6
01
A/B
COUNTERS
Figure 54. Reference and VCO Status Monitors
VCO Calibration
The AD9516 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off of a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be present.
During the first initialization after a power-up or a reset of the
AD9516, a VCO calibration sequence is initiated by setting
Register 0x018[0] = 1b. This can be done as part of the initial
setup, before executing update registers (Register 0x232[0] = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting Register 0x018[0] = 0b, executing an update
registers operation, setting Register 0x018[0] = 1b, and executing
another update registers operation. A readback bit, Bit 6 in
Register 0x01F, indicates when a VCO calibration is finished
by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is as follows:
•Program the PLL registers to the proper values for the
PLL loop. Note that that automatic holdover mode
must be disabled, and the VCO divider must not be
set to “Static.”
• Ensure that the input reference signal is present.
• For the initial setting of the registers after a power-up or
reset, initiate VCO calibration by setting Register
0x018[0] = 1b. Subsequently, whenever a calibration is
desired, set Register 0x018[0] = 0b, update registers;
and then set Register 0x018[0] = 1b, update registers.
•A SYNC operation is initiated internally, causing the
outputs to go to a static state determined by normal
SYNC function operation.
•VCO calibrates to the desired setting for the requested
VCO frequency.
•Internally, the SYNC signal is released, allowing
outputs to continue clocking.
• PLL loop is closed.
• PLL locks.
Rev. B | Page 39 of 80
PROGRAMMABLE
PROGRAMMABLE
VCO STATUS
0
1
REFMON
LD
CP
STATUS
06422-070
R DELAY
N DELAY
LOCK
DETECT
PHASE
FREQUENC Y
DETECTOR
PLL
REFERENCE
CHARGE
PUMP
HOLD
A sync is executed during the VCO calibration; therefore, the
outputs of the AD9516 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Tabl e 54
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
f
CAL_CLOCK
= f
REFIN
/(R × cal_div)
where:
f
is the frequency of the REFIN signal.
REFIN
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
Table 29. Example Time to Complete a VCO Calibration
with Different f
f
(MHz) R Divider PFD Time to Calibrate VCO
REFIN
Frequencies
REFIN
100 1 100 MHz 88 μs
10 10 1 MHz 8.8 ms
10 100 100 kHz 88 ms
Page 40
AD9516-3 Data Sheet
VCO calibration must be manually initiated. This allows for
flexibility in deciding what order to program registers and when
to initiate a calibration, instead of having it happen every time
certain PLL registers have their values change. For example, this
allows for the VCO frequency to be changed by small amounts
without having an automatic calibration occur each time; this
should be done with caution and only when the user knows that
the VCO control voltage is not going to exceed the nominal best
performance limits. For example, a few 100 kHz steps are fine,
but a few MHz might not be). In addition, because the calibration
procedure results in rapid changes in the VCO frequency, the
distribution section is automatically placed in SYNC until the
calibration is finished. Therefore, this temporary loss of outputs
must be expected.
A VCO calibration should be initiated under the following
conditions:
•After changing any of the PLL R, P, B, and A divider
settings, or after a change in the PLL reference clock
frequency. This, in effect, means any time a PLL register
or reference clock is changed such that a different VCO
frequency results.
•Whenever system calibration is desired. The VCO is designed
to operate properly over extremes of temperatures even when
first calibrated at the opposite extreme. However, a VCO
calibration can be initiated at any time, if desired.
CLOCK DISTRIBUTION
A clock channel consists of a pair (or double pair, in the case of
CMOS) of outputs that share a common divider. A clock output
consists of the drivers that connect to the output pins. The clock
outputs have either LVPECL or LVDS/CMOS signal levels at
the pins.
The AD9516 has five clock channels: three channels are LVPECL
(six outputs); two channels are LVDS/CMOS (up to four LVDS
outputs, or up to eight CMOS outputs).
Each channel has its own programmable divider that divides
the clock frequency that is applied to its input. The LVPECL
channel dividers can divide by any integer from 2 to 32, or
the divider can be bypassed to achieve a divide by one. Each
LVDS/CMOS channel divider contains two of these divider
blocks in a cascaded configuration. The total division of the
channel is the product of the divide value of the cascaded dividers.
This allows divide values of (1 to 32) × (1 to 32), or up to 1024
(note that this is not all values from 1 to 1024 but only the set
of numbers that are the product of the two dividers).
Because the internal VCO frequency is above the maximum
channel divider input frequency (1600 MHz), the VCO divider
must be used after the on-chip VCO. The VCO divider can be
set to divide by 2, 3, 4, 5, or 6. External clock signals connected
to the CLK input also require the VCO divider if the frequency
of the signal is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function,
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or start low.
Internal VCO or External CLK as Clock Source
The clock distribution of the AD9516 has two clock input sources:
an internal VCO or an external clock connected to the CLK/
CLK
pins. Either the internal VCO or CLK must be chosen as
the source of the clock signal to distribute. When the internal
VCO is selected as the source, the VCO divider must be used.
When CLK is selected as the source, it is not necessary to use
the VCO divider if the CLK frequency is less than the
maximum channel divider input frequency (1600 MHz);
otherwise, the VCO divider must be used to reduce the
frequency to one acceptable by the channel dividers.
shows how the VCO, CLK, and VCO divider are selected.
Register 0x1E1[1:0] selects the channel divider source and
determines whether the VCO divider is used. It is not possible
to select the VCO without using the VCO divider.
Table 30. Selecting VCO or CLK as Source for Channel
Divider, and Whether VCO Divider Is Used
Register 0x1E1
Bit 1 Bit 0
0 0 CLK Used
0 1 CLK Not used
1 0 VCO Used
1 1 Not allowed Not allowed
Channel Divider SourceVCO Divider
Tabl e 30
CLK or VCO Direct to LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs, OUT0 to OUT5. This configuration
can pass frequencies up to the maximum frequency of the VCO
directly to the LVPECL outputs. The LVPECL outputs may not
be able to provide full voltage swing at the highest frequencies.
Rev. B | Page 40 of 80
Page 41
Data Sheet AD9516-3
To connect the LVPECL outputs directly to the internal VCO or
CLK, the VCO divider must be selected as the source to the
distribution section, even if no channel uses it.
Either the internal VCO or the CLK can be selected as the
source for the direct to output routing.
Table 31. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting Selection
0x1E1[1:0] = 00b CLK is the source; VCO divider selected
0x1E1[1:0] = 10b VCO is the source; VCO divider selected
0x192[1] = 1b Direct to output OUT0, OUT1
0x195[1] = 1b Direct to output OUT2, OUT3
0x198[1] = 1b Direct to output OUT4, OUT5
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, 6) and the
division of the channel divider. Tabl e 3 2 and Tabl e 33 indicate
how the frequency division for a channel is set. For the LVPECL
outputs, there is only one divider per channel. For the LVDS/
CMOS outputs, there are two dividers (X.1, X.2) cascaded
per channel.
Table 32. Frequency Division for Divider 0 to Divider 2
CLK
or VCO
Selected
CLK/VCO 2 to 6 1 (bypassed) Yes 1
CLK/VCO 2 to 6 1 (bypassed) No (2 to 6) × (1)
CLK/VCO 2 to 6 2 to 32 No
CLK Not used 1 (bypassed) No 1
CLK Not used 2 to 32 No 2 to 32
VCO
Divider
Channel
Divider
Direct to
Output
Frequency
Division
(2 to 6) ×
(2 to 32)
Table 33. Frequency Division for Divider 3 and Divider 4
CLK
or VCO
Selected
CLK/VCO 2 to 6
CLK/VCO 2 to 6 2 to 32
CLK/VCO 2 to 6 2 to 32 2 to 32
CLK Not used 1 1 1
CLK Not used 2 to 32 1 (2 to 32) × (1)
CLK Not used 2 to 32 2 to 32
VCO
Divider
Channel Divider
X.1 X.2
1
(bypassed) 1 (bypassed)
1
(bypassed)
Frequency
Division
(2 to 6) ×
(1) × (1)
(2 to 6) ×
(2 to 32) × (1)
(2 to 6) ×
(2 to 32) ×
(2 to 32)
2 to 32 ×
(2 to 32)
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 2 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Tab l e 5 2 through Tabl e 62 ).
VCO Divider
The VCO divider provides frequency division between
the internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Tab le 6 0 , Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving a total of
six LVPECL outputs (OUT0 to OUT5). Tabl e 34 lists the register
locations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting
of the DCCOFF bits.
Table 34. Setting D
Low Cycles M High Cycles
Divider
0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0]
1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0]
2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0]
1
Note that the value stored in the register = # of cycles minus 1.
for Divider 0, Divider 1, and Divider 21
X
N Bypass DCCOFF
Channel Frequency Division (0, 1, and 2)
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, D
, is set by the values of M and N
X
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, D
Otherwise, D
= (N + 1) + (M + 1) = N + M + 2. This allows
X
= 1.
X
each channel divider to divide by any integer from 2 to 32.
Rev. B | Page 41 of 80
Page 42
AD9516-3 Data Sheet
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
The duty cycle of the clock signal at the output of a channel is
a result of some or all of the following conditions:
• What are the M and N values for the channel?
• Is the DCC enabled?
• Is the VCO divider used?
• What is the CLK input duty cycle? (The internal VCO has
a 50% duty cycle.)
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
• An even division must be set as M = N
• An odd division must be set as M = N + 1
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as a percentage (%).
The duty cycle at the output of the channel divider for various
configurations is shown in Tabl e 3 5 to Ta ble 37 .
Table 35. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
DX Output Duty Cycle VCO
Divider
Even
Odd = 3
Odd = 5
Even, Odd Even
Even, Odd Odd
N + M + 2 DCCOFF = 1 DCCOFF = 0
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
50% 50%
33.3% 50%
40% 50%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%; requires M = N
50%; requires M = N + 1
Table 36. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
DX Output Duty Cycle VCO
Divider
Even
Odd = 3
Odd = 5
Even Even
Odd
Odd = 3 Even
Odd = 3 Odd
Odd = 5 Even
Odd = 5 Odd
N + M + 2 DCCOFF = 1 DCCOFF = 0
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
50% 50%
33.3% (1 + X%)/3
40% (2 + X%)/5
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%,
requires M = N
50%,
requires M = N + 1
50%,
requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%,
requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
DX Output Duty Cycle Input
Clock
Duty
Cycl e
Any 1
Any Even
50% Odd
X% Odd
N + M + 2 DCCOFF = 1 DCCOFF = 0
1 (divider
bypassed)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Same as input
duty cycle
50%, requires M = N
50%, requires
M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Rev. B | Page 42 of 80
Page 43
Data Sheet AD9516-3
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Tabl e 38 ).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset or delay the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register, plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M) that
are programmed for the divider.
The SYNC function must be used to make phase offsets effective
(see the Synchronizing the Outputs—SYNC Function section).
Table 38. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 2
The channel divide-by is set as N = high cycles, and M = low cycles.
Case 1
For Φ ≤ 15:
Δt = Φ × T
Δc = Δt/T
X
= Φ
X
Case 2
For Φ ≥ 16:
Δt = (Φ − 16 + M + 1) × T
X
Δc = Δt/TX
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 55 shows the results of setting such a coarse
offset between outputs.
CHANNEL
DIVIDER I NPUT
DIVIDER 0
DIVIDER 1
DIVIDER 2
0123456789101112131415
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
Tx
C
A
H
1 × Tx
2 × Tx
E
L
D
N
N
I
D
V
T
P
T
U
S
U
E
D
R
O
I
V
I
=
5
0
4
,
=
%
T
U
D
Y
Figure 55. Effect of Coarse Phase Offset (or Delay)
06419-071
Rev. B | Page 43 of 80
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 3 and Channel Divider 4 each drive a pair of
LVDS outputs, giving a total of four LVDS outputs (OUT6 to
OUT9). Alternatively, each of these LVDS differential outputs
can be configured individually as a pair (A and B) of CMOS
single-ended outputs, providing for up to eight CMOS outputs.
By default, the B output of each pair is off but can be turned on
as desired.
Channel Divider 3 and Channel Divider 4 each consist of two
cascaded, 2 to 32, frequency dividers. The channel frequency
division is D
X.1
× D
or up to 1024. Divide-by-1 is achieved by
X.2
bypassing one or both of these dividers. Both of the dividers
also have DCC enabled by default, but this function can be
disabled, if desired, by setting the DCCOFF bit of the channel.
A coarse phase offset or delay is also programmable (see the
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
section). The channel dividers operate up to 1600 MHz. The
features and settings of the dividers are selected by programming
the appropriate setup and control registers (see Tabl e 52 and
Tabl e 53 through Tabl e 62 ).
Note that the value stored in the register = # of cycles minus 1.
Channel Frequency Division (Divider 3 and Divider 4)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2)
Number of Low Cycles = M
Number of High Cycles = N
When both X.1 and X.2 are bypassed, D
When only X.2 is bypassed, D
When both X.1 and X.2 are not bypassed, D
(N
+ M
X.2
+ 2).
X.2
X.Y
X.Y
= (N
X
+ 1
+ 1
X.1
= 1 × 1 = 1.
X
+ M
+ 2) × 1.
X.1
= (N
X
X.1
+ M
+ 2) ×
X.1
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (D
X.1
× D
) can be realized.
X.2
If only one divider is needed when using Divider 3 and Divider 4,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
Page 44
AD9516-3 Data Sheet
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the
Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section);
however, with these channel dividers, the number of possible
configurations is even more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
•An even D
must be set as M
X.Y
X.Y
= N
(low cycles = high
X.Y
cycles).
•An odd D
must be set as M
X.Y
X.Y
= N
+ 1 (the number of
X.Y
low cycles must be one greater than the number of high
cycles).
•If only one divider is bypassed, it must be the second
divider, X.2.
•If only one divider has an even divide by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Divider 3 and Divider 4 are shown in Tab le 4 0 through Tabl e 44 .
Table 44. Divider 3, Divider 4 Duty Cycle; VCO Divider Not
Used; Duty Cycle Correction On (DCCOFF = 0)
Input
Clock
Duty
Cycle N
D
D
X.1
+ M
X.1
+ 2 N
X.1
X.2
+ M
X.2
Output
Duty Cycle
+ 2
X.2
50% 1 1 50%
50%
Even
(N
X.1
= M
X.1
1 50%
)
X% 1 1 X% (High)
X%
50%
X%
50%
X%
50%
X%
50%
X%
Even
(N
X.1
Odd
(M
X.1
Odd
(M
X.1
Odd
(M
X.1
Even
(N
X.1
Even
(N
X.1
Odd
(M
X.1
Odd
(M
X.1
Odd
(M
X.1
Odd
(M
X.1
= M
= N
= N
= N
= M
= M
= N
= N
= N
= N
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
1 50%
)
1 50%
+ 1)
+ 1)
+ 1)
)
)
+ 1)
+ 1)
+ 1)
+ 1)
1
1
Even
(N
X.2
Even
(N
X.2
Even
(N
X.2
Even
(N
X.2
Odd
(M
X.2
Odd
(M
X.2
= M
= M
= M
= M
= N
= N
X.2
X.2
X.2
X.2
X.2
X.2
)
)
)
)
+ 1)
+ 1)
(N
X.1
(2N
(N
X.1
(2N
50%
50%
50%
50%
50%
(2N
3N
X.2
((2N
+ 1 + X%)/
+ 3)
X.1
+ 1 + X%)/
+ 3)
X.1
+ 3N
X.1NX.2
+ 4 + X%)/
+ 3)(2N
X.1
X.2
+
X.1
+ 3))
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
Divider 3 and Divider 4 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Tab l e 4 5 ).
Table 45. Setting Phase Offset and Division for Divider 3 and
Divider 4
Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes
an analog delay element that can be programmed to give
variable time delays (Δt) in the clock signal at that output.
CLK
VCO
DIVIDER
DIVIDER
DIVIDER
X.1
X.2
Figure 56. Fine Delay (OUT6 to OUT9)
BYPASS
∆t
FINE DEL AY
ADJUST
BYPASS
∆t
FINE DEL AY
ADJUST
CMOS
LVDS
CMOS
CMOS
LVDS
CMOS
OUTM
OUTM
OUTPUT
DRIVERS
OUTN
OUTN
The amount of delay applied to the clock signal is determined
by programming four registers per output (see Tabl e 46 ).
Fine Delay (ns) =
Delay Range × Delay Fraction × (1/63) + Offset
Note that only delay fraction values up to 47 decimal (101111b;
0x2F) are supported.
In no case can the fine delay exceed one-half of the output clock
period. If a delay longer than half of the clock period is attempted,
the output stops clocking.
The delay function adds some jitter that is greater than that
specified for the nondelayed output. This means that the delay
function should be used primarily for clocking digital chips,
such as FPGA, ASIC, DUC, and DDC. An output with this
delay enabled may not be suitable for clocking data converters.
The jitter is higher for long full scales because the delay block
uses a ramp and trip points to create the variable delay. A slower
ramp time produces more time jitter.
Synchronizing the Outputs—SYNC Function
The AD9516 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and, subsequently, releasing
these outputs to continue clocking at the same instant with the
preset conditions applied. This allows for the alignment of the
edges of two or more outputs or for the spacing of edges,
according to the coarse phase offset settings for two or more
outputs.
⎞
⎟
×
⎟
⎠
Synchronization of the outputs is executed in several ways,
as follows:
By forcing the
•
SYNC
pin low and then releasing it (manual
sync).
•
By setting and then resetting any one of the following three
bits: the soft sync bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), and the power-down
distribution reference bit (Register 0x230[1]).
By executing synchronization of the outputs as part of the
•
chip power-up sequence.
By forcing the
•
6
reset).
By forcing the
•
RESET
pin low and then releasing it (chip
PD
pin low and then releasing it (chip power-
down).
Following completion of a VCO calibration. An internal
•
SYNC signal is automatically asserted at the beginning and
released upon the completion of a VCO calibration.
The most common way to execute the SYNC function is to use
SYNC
the
This requires a low-going signal on the
pin to do a manual synchronization of the outputs.
SYNC
pin, which is held
low and then released when synchronization is desired. The
timing of the SYNC operation is shown in (using
VCO divider) and (VCO divider not used). There is
Figure 58
Figure 57
an uncertainty of up to one cycle of the clock at the input to the
channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the AD9516. The
SYNC
delay from the
rising edge to the beginning of synchronized
output clocking is between 14 and 15 cycles of clock at the
channel divider input, plus either one cycle of the VCO divider
input (see ) or one cycle of the channel divider input
(see ), depending on whether the VCO divider is used.
Figure 57
Figure 58
Cycles are counted from the rising edge of the signal.
Another common way to execute the SYNC function is by
setting and resetting the soft sync bit at Register 0x230[0] (see
Tabl e 5 3 through Tabl e 62 for details). Both setting and
resetting of the soft sync bit require an update all registers
operation (Register 0x232[0] = 1) to take effect.
Rev. B | Page 46 of 80
Page 47
Data Sheet AD9516-3
S
R
R
R
R
R
CHANNEL DIVIDE
OUTPUT CLOCKING
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
YNC PIN
OUTPUT OF
CHANNEL DIVIDER
CHANNEL DIVIDE
OUTPUT CLOCKING
INPUT TO CLK
CHANNEL DIVIDER O UTPUT STAT IC
123 456 78910
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER I NPUT
Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER O UTPUT STAT IC
CHANNEL DIVIDE
OUTPUT CLOCKING
1
11
1314
12
06422-073
CHANNEL DIVIDE
OUTPUT CLO CKING
1
INPUT TO CHANNEL DIVIDE
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
12345678910
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
A sync operation brings all outputs that have not been excluded
(by the nosync bit) to a preset condition before allowing the
outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static
state of each output when the SYNC operation is happening and
the state and relative phase of the outputs when they begin
clocking again upon completion of the SYNC operation.
Between outputs and after synchronization, this allows for the
setting of phase offsets.
The AD9516 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
11
13 14
12
Each channel (a divider and its outputs) can be excluded from
any sync operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a sync operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
Clock Outputs
The AD9516 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0 to OUT5 are LVPECL
differential outputs; and OUT6 to OUT9 are LVDS/CMOS
outputs. These outputs can be configured as either LVDS
differential or as pairs of single-ended CMOS outputs.
6422-074
Rev. B | Page 47 of 80
Page 48
AD9516-3 Data Sheet
V
3
A
3
A
V
LVPECL Outputs—OUT0 to OUT5
The LVPECL differential voltage (VOD) is selectable from ~400 mV
to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]).
The LVPECL outputs have dedicated pins for power supply
(VS_LVPECL), allowing a separate power supply to be used.
V
can be from 2.5 V to 3.3 V.
S_LVPECL
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up, as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are not connected (unused),
it is acceptable to use the total power-down mode.
3.3
Figure 60. LVDS Output Simplified Equivalent Circuit with
Each LVDS/CMOS output can be powered down as needed to
save power. The CMOS output power-down is controlled by the
same bit that controls the LVDS power-down for that output.
This power-down control affects both CMOS Output A and
CMOS Output B. However, when CMOS Output A is powered up,
CMOS Output B can be powered on or off separately.
OUT6 to OUT9 can be configured as either an LVDS
differential output or as a pair of CMOS single-ended outputs.
The LVDS outputs allow for selectable output current from
~1.75 mA to ~7 mA.
The LVDS output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVDS output can be powered down
if not needed to save power.
OUT6 to OUT9 can also be CMOS outputs. Each LVDS output
can be configured to be two CMOS outputs. This provides for
up to eight CMOS outputs: OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, and OUT9B. When an output is
configured as CMOS, CMOS Output A is automatically turned on.
CMOS Output B can be turned on or off independently. The
relative polarity of the CMOS outputs can also be selected for any
combination of inverting and noninverting (see Tab l e 5 7 for
Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5],
and Register 0x143[7:5]).
Rev. B | Page 48 of 80
06422-035
Figure 61. CMOS Equivalent Output Circuit
RESET MODES
The AD9516 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is
Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Tab le 5 2. At
power-on, the AD9516 also executes a SYNC operation, which
brings the outputs into phase alignment according to the default
settings.
Asynchronous Reset via the
An asynchronous hard reset is executed by momentarily pulling
RESET
low. A reset restores the chip registers to the default settings.
Soft Reset via Register 0x000[2]
A soft reset is executed by writing Register 0x000[2] and
Register 0x000[5] = 1b. This bit is not self-clearing; it must be
cleared by writing Register 0x000[2] and Register 0x000[5] = 0b to
reset it and complete the soft reset operation. A soft reset restores
the default values to the internal registers. The soft reset bit does
not require an update registers command (Register 0x232) to be
issued.
RESET
Pin
Page 49
Data Sheet AD9516-3
POWER-DOWN MODES
Chip Power-Down via PD
The AD9516 can be put into a power-down condition by
pulling the
functions and currents inside the AD9516. The chip remains in
this power-down state until
When the AD9516 wakes up, it returns to the settings programmed
into its registers prior to the power-down, unless the registers
are changed by new programming while the
The
the bias current that is necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9516 is in a
following state:
The PLL is off (asynchronous power-down).
•
•
The VCO is off.
•
The CLK input buffer is off.
•
All dividers are off.
•
All LVDS/CMOS outputs are off.
•
All LVPECL outputs are in safe off mode.
•
The serial control port is active, and the chip responds
If the AD9516 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section). A VCO
calibration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9516 can be selectively powered
down. There are three PLL operating modes that are set by
Register 0x010[1:0], as shown in Tab l e 5 4 .
PD
pin low. Power-down turns off most of the
PD
is brought back to logic high.
PD
pin is held low.
PD
power-down shuts down the currents on the chip, except
PD
power-down, the chip is in the
to commands.
In asynchronous power-down mode, the device powers down
as soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency
jumps. The device goes into power-down on the occurrence
of the next charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[1] = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down.
If the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and may be damaged
under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output
(see Tabl e 52 ). The LVDS/CMOS outputs can be powered
down, regardless of their output load configuration.
The LVPECL outputs have multiple power-down modes
(see Tabl e 56 ), which give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
Register 0x230[1] = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Other AD9516 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
Rev. B | Page 49 of 80
Page 50
AD9516-3 Data Sheet
SERIAL CONTROL PORT
The AD9516 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9516 serial control port is compatible with most synchronous
transfer formats, including both the Motorola SPI® and Intel®
SSR® protocols. The serial control port allows read/write access
to all registers that configure the AD9516. Single or multiple
byte transfers are supported, as well as MSB first or LSB first
transfer formats. The AD9516 serial control port can be
configured for a single bidirectional I/O pin (SDIO only) or
for two unidirectional I/O pins (SDIO/SDO). By default, the
AD9516 is in bidirectional mode, long instruction (long
instruction is only instruction mode supported).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin that acts
as either an input only (unidirectional mode) or as both an
input/output (bidirectional mode). The AD9516 defaults to the
bidirectional I/O mode (Register 0x000[0] = 0b).
(serial data out) is used only in the unidirectional I/O
SDO
mode (Register 0x000[0] = 1b) as a separate output pin for
reading back data.
CS
(chip select bar) is an active low control that gates the read
and write cycles. When
CS
is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to VS.
16
SCLK
CS
SDO
SDIO
Figure 62. Serial Control Port
AD9516-3
17
SERIAL
21
CONTRO L
22
PORT
06422-036
GENERAL OPERATION OF SERIAL CONTROL PORT
A write or a read operation to the AD9516 is initiated by pulling
CS
low.
CS
stall high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (see ).
In these modes,
CS
can temporarily return high on any byte
boundary, allowing time for the system controller to process the
next byte.
CS
can go high on byte boundaries only and can go
high during either part (instruction or data) of the transfer.
Table 4 7
Rev. B | Page 50 of 80
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset, either by completing the remaining transfers or
CS
by returning the
(but less than eight SCLK cycles). Raising the
low for at least one complete SCLK cycle
CS
on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In the streaming mode (see Ta b l e 47 ), any number of data bytes
can be transferred in a continuous stream. The register address
is automatically incremented or decremented (see the MSB/LSB
First Transfers section).
CS
must be raised at the end of the last
byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9516.
The first part writes a 16-bit instruction word into the AD9516,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9516 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9516. Data bits are registered on the rising edge of SCLK.
The length of the transfer (1, 2, 3 bytes or streaming mode) is
indicated by two bits ([W1:W0]) in the instruction byte. When
the transfer is 1, 2, or 3 bytes, but not streaming,
CS
can be
raised after each sequence of eight bits to stall the bus (except
after the last byte, where it ends the cycle). When the bus is
CS
stalled, the serial transfer resumes when
is lowered. Raising CS
on a nonbyte boundary resets the serial control port. During a
write, streaming mode does not skip over reserved or blank
registers; therefore, the user must know the bit pattern to write
to the reserved registers to preserve proper operation of the part.
Refer to the register map (see ) to determine if the default
Tabl e 5 2
value for reserved registers is nonzero. It does not matter what data
is written to blank registers.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9516, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9516,
thereby causing them to become active. The update registers
operation consists of setting Register 0x232[0] = 1b (this bit is
self-clearing). Any number of bytes of data can be changed before
executing an update registers. The update registers operation
simultaneously actuates all register changes that have been
written to the buffer since any previous update.
Page 51
Data Sheet AD9516-3
Read
If the instruction word is for a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by [W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until
is raised. Streaming mode does not skip over reserved
CS
or blank registers. The readback data is valid on the falling
edge of SCLK.
The default mode of the AD9516 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible
to set the AD9516 to unidirectional mode via the SDO active bit
(Register 0x000[0] = 1b). In unidirectional mode, the readback
data appears on the SDO pin.
A readback request reads the data that is in the serial control
port buffer area, or the data that is in the active registers (see
Figure 63). Readback of the buffer or active registers is controlled
by Register 0x004[0].
The AD9516 supports only the long instruction mode, therefore
Register 0x000[4:3] must be set to 11b. (This register uses mirrored
bits). Long instruction mode is the default at power-up or reset.
The AD9516 uses Register Address 0x000 to Register
Address 0x232.
SCLK
SDIO
SDO
CS
SERIAL
CONTROL
PORT
WRITE RE GISTE R 0x232 = 0x01
TO UDATE REG ISTERS
Figure 63. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9516
UPDATE
REGISTERS
BUFFER REGIS TERS
ACTIVE REGISTERS
06422-037
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits,
[W1:W0], indicate the length of the transfer in bytes. The final
13 bits are the address ([A12:A0]) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0] (see Ta b le 4 7).
Table 47. Byte Transfer Count
W1 W0 Bytes to Transfer
0 0 1
0 1 2
1 0 3
1 1 Streaming mode
The 13 bits found in [A12:A0] select the address within the
register map that is written to or read from during the data
transfer portion of the communications cycle. Only Bits[A9:A0]
are needed to cover the range of the 0x232 registers used by the
AD9516. Bits[A12:A10] must always be 0b. For multibyte
transfers, this address is the starting byte address. In MSB first
mode, subsequent bytes decrement the address.
MSB/LSB FIRST TRANSFERS
The AD9516 instruction word and byte data can be MSB first
or LSB first. Any data written to Register 0x000 must be mirrored;
the upper four bits (Bits[7:4]) with the lower four bits (Bits[3:0]).
This makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, see the default setting
for this register: 0x18, which mirrors Bit 4 and Bit 3. This sets
the long instruction mode (which is the default and the only
mode that is supported).
The default for the AD9516 is MSB first.
When LSB first is set by Register 0x000[1] and Register 0x000[6],
it takes effect immediately because it affects only the operation
of the serial control port and does not require that an update
be executed.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow, in order, from the high address to the
low address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the
multibyte transfer cycle.
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. The internal byte address generator of the serial
control port increments for each byte of the multibyte
transfer cycle.
The AD9516 serial control port register address decrements from
the register address just written toward 0x000 for multibyte I/O
operations if the MSB first mode is active (default). If the LSB
first mode is active, the register address of the serial control port
increments from the address just written toward Address 0x232
for multibyte I/O operations.
Streaming mode always terminates when it hits Address 0x232.
Note that unused addresses are not skipped during multibyte
I/O operations.
Table 48. Streaming Mode (No Addresses Are Skipped)
Write Mode Address Direction Stop Sequence
LSB first Increment 0x230, 0x231, 0x232, stop
MSB first Decrement 0x001, 0x000, 0x232, stop
Rev. B | Page 51 of 80
Page 52
AD9516-3 Data Sheet
K
Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First
Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Blank
(PECL)
bypass
(PECL)
bypass
(PECL)
bypass
(LVDS/CMOS)
(LVDS/CMOS)
Divider 0 low cycles Divider 0 high cycles 0x00
Divider 0
no sync
Divider 1 low cycles Divider 1 high cycles 0xBB
Divider 1
no sync
Divider 2 low cycles Divider 2 high cycles 0x00
Divider 2
no sync
Low Cycles Divider 3.1 High Cycles Divider 3.1 0x22
Low Cycles Divider 4.1 High Cycles Divider 4.1 0x22
Divider 0
force high
Divider 1
force high
Divider 2
force high
Divider 3.2
Divider 4.2
Divider 0
start high
Divider 1
start high
Divider 2
start high
Bypass
Divider 3.1
Bypass
Divider 4.1
down
clock input
section
Divider 3
no sync
Divider 4
no sync
Blank
Power-down
VCO clock
interface
Blank
Divider 0 phase offset 0x80
direct to
output
Divider 1 phase offset 0x00
direct to
output
Divider 2 phase offset 0x00
direct to
output
Divider 3
force high
Divider 4
force high
Powerdown VCO
and CLK
Start High
Divider 3.2
Start High
Divider 4.2
Select
VCO or CLK
Divider 0
DCCOFF
Divider 1
DCCOFF
Divider 2
DCCOFF
Start High
Divider 3.1
DCCOFF
Start High
Divider 4.1
DCCOFF
Bypass VCO
divider
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Rev. B | Page 57 of 80
Page 58
AD9516-3 Data Sheet
Reg.
Addr.
(Hex)
System
0x230 Power-down
0x231 Blank Reserved 0x00
Update All Registers
0x232 Update all
Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
and sync
registers
Reserved Power-
down sync
Blank Update all
Powerdown
distribution
reference
Soft sync 0x00
registers (selfclearing bit)
Default
Value
(Hex)
0x00
Rev. B | Page 58 of 80
Page 59
Data Sheet AD9516-3
REGISTER MAP DESCRIPTIONS
Tabl e 5 3 through Tabl e 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2].
Table 53. Serial Port Configuration
Reg.
Addr
(Hex)
0x000 [7:4] Mirrored, Bits[3:0]
Bit 7 = Bit 0.
Bit 6 = Bit 1.
Bit 5 = Bit 2.
Bit 4 = Bit 3.
3 Long instruction
1 LSB first MSB or LSB data orientation.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
0 SDO active Selects unidirectional or bidirectional data transfer mode.
0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default).
1: SDO used for read, SDIO used for write; unidirectional mode.
0x003 [7:0] Part ID (read only) Uniquely identifies the dash version (-0 through -4) of the AD9516.
AD9516-0: 0x01.
AD9516-1: 0x41.
AD9516-2: 0x81.
AD9516-3: 0x43.
AD9516-4: 0xC3.
0x004 0 Read back active registers Selects register bank used for a readback.
0: reads back buffer registers (default).
1: reads back active registers.
Bits Name Description
Bits[7:4] should always mirror Bits[3:0] so that it does not matter whether the part
is in MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows:
Short/long instruction mode. This part uses long instruction mode only, so this bit should
always be set to 1.
1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to
0 to complete reset operation.
Rev. B | Page 59 of 80
Page 60
AD9516-3 Data Sheet
Table 54. PLL
Reg.
Addr.
(Hex)
0x010 7 PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
0x013 [5:0] 6-bit A counter A counter (part of N divider) (default = 0x00).
0x014 [7:0] 13-bit B counter,
0x015 [4:0] 13-bit B counter,
0x016 7 Set CP pin to VCP/2 Sets the CP pin to one-half of the VCP supply voltage.
6 Reset R counter Resets R counter (R divider).
5 Reset A, B counters Resets A and B counters (part of N divider).
4 Reset all counters Resets R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
3 B counter B counter bypass. This is valid only when operating the prescaler in FD mode.
bypass 0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
Bits Name Description
positive polarity; Bit 7 = 0.
3 2 Charge Pump Mode
0 0 High impedance state.
0 1 Force source current (pump up).
1 0 Force sink current (pump down).
1 1 Normal operation (default).
Bits[7:0] (LSB)
Bits[13:8] (MSB)
Bits[7:0] (LSB)
Bits[12:8] (MSB)
0: CP normal operation (default).
0: normal (default).
0: normal (default).
1 0 Mode
0 0 Normal operation.
0 1 Asynchronous power-down (default).
1 0 Normal operation.
1 1 Synchronous power-down.
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
1: CP pin set to V
1: holds the R counter in reset.
1: holds the A and B counters in reset.
/2.
CP
Rev. B | Page 60 of 80
Page 61
Data Sheet AD9516-3
Reg.
Addr.
(Hex)
0x016 [2:0] Prescaler P Prescaler: DM = dual modulus, and FD = fixed divide.
2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1.
0 0 1 FD Divide-by-2.
0 1 0 DM Divide-by-2 (2/3 mode).
0 1 1 DM Divide-by-4 (4/5 mode).
1 0 0 DM Divide-by-8 (8/9 mode).
1 0 1 DM Divide-by-16 (16/17 mode).
1 1 0 DM Divide-by-32 (32/33 mode) (default).
1 1 1 FD Divide-by-3.
0x017 [7:2] STATUS pin Selects the signal that is connected to the STATUS pin.
control
0 0 0 0 0 0 LVL Ground (dc) (default).
0 0 0 0 0 1 DYN N divider output (after the delay).
0 0 0 0 1 0 DYN R divider output (after the delay).
0 0 0 0 1 1 DYN A divider output.
0 0 0 1 0 0 DYN Prescaler output.
0 0 0 1 0 1 DYN PFD up pulse.
0 0 0 1 1 0 DYN PFD down pulse.
0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1 0 0 0 0 0 LVL Ground (dc).
1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
1 0 0 0 1 0 DYN REF2 clock (not available in differential mode).
1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active
1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode);
1 0 0 1 1 1 LVL Status REF1 frequency (active high).
1 0 1 0 0 0 LVL Status REF2 frequency (active high).
1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency).
1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
1 0 1 0 1 1 LVL Status of VCO frequency (active high).
1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
1 0 1 1 0 1 LVL Digital lock detect (DLD); active high.
1 0 1 1 1 0 LVL Holdover active (active high).
1 0 1 1 1 1 LVL LD pin comparator output (active high).
1 1 0 0 0 0 LVL VS (PLL supply).
1 1 0 0 0 1 DYN REF1 clock
1 1 0 0 1 0 DYN REF2 clock
1 1 0 0 1 1 DYN Selected reference to PLL
1 1 0 1 0 0 DYN Unselected reference to PLL
1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low.
1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low.
1 1 0 1 1 1 LVL Status of REF1 frequency (active low).
1 1 1 0 0 0 LVL Status of REF2 frequency (active low).
1 1 1 0 0 1 LVL
0: high range (default).
1: low range.
3 Disable digital Digital lock detect operation.
lock detect 0: normal lock detect operation (default).
1: disables lock detect.
[2:1] VCO cal VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
divider
0 0 2.
0 1 4.
1 0 8.
1 1 16 (default).
[0] VCO cal now Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. To initiate
[5:3] R path delay R path delay (default = 0x00) (see Table 2).
[2:0] N path delay N path delay (default = 0x00) (see Table 2).
0x01A [6] Reference
threshold 0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
Bits Name Description
counter
window
pin reset
frequency monitor
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
2 1 VCO Calibration Clock Divider
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not
zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1, followed by another update bit
(Register 0x232, Bit 0).
7 6 Action
0 0
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 16: REF1, REF2, and VCO Frequency Status Monitor parameter).
Does nothing on
Does nothing on
SYNC
SYNC
(default).
.
Rev. B | Page 62 of 80
Page 63
Data Sheet AD9516-3
Reg.
Addr.
(Hex)
0x01A [5:0] LD pin control Selects the signal that is connected to the LD pin.
0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock) (default).
0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect).
0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect).
0 0 0 0 1 1 HIZ High-Z LD pin.
0 0 0 1 0 0 CUR Current source lock detect (110 μA when DLD is true).
0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1 0 0 0 0 0 LVL Ground (dc).
1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
1 0 0 0 1 0 DYN REF2 clock (not available in differential mode).
1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when indifferential mode).
1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high.
1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active
1 0 0 1 1 1 LVL Status REF1 frequency (active high).
1 0 1 0 0 0 LVL Status REF2 frequency (active high).
1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency).
1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
1 0 1 0 1 1 LVL Status of VCO frequency (active high).
1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
1 0 1 1 0 1 LVL Digital lock detect (DLD); active high.
1 0 1 1 1 0 LVL Holdover active (active high).
1 0 1 1 1 1 LVL Not available. Do not use.
1 1 0 0 0 0 LVL VS (PLL supply).
1 1 0 0 0 1 DYN REF1 clock
1 1 0 0 1 0 DYN REF2 clock
1 1 0 0 1 1 DYN Selected reference to PLL
1 1 0 1 0 0 DYN Unselected reference to PLL
1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low.
1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active
1 1 0 1 1 1 LVL Status of REF1 frequency (active low).
1 1 1 0 0 0 LVL Status of REF2 frequency (active low).
1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency)
1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO)
1 1 1 0 1 1 LVL Status of VCO frequency (active low).
1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1).
1 1 1 1 0 1 LVL Digital lock detect (DLD); active low.
1 1 1 1 1 0 LVL Holdover active (active low).
1 1 1 1 1 1 LVL Not available. Do not use.
0x01B 7 VCO frequency Enables or disables VCO frequency monitor.
monitor 0: disables VCO frequency monitor (default).
1: enables VCO frequency monitor.
6
frequency monitor 0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
5 REF1 (REFIN)
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
Bits Name Description
5 4 3 2 1 0
REFIN
REF2 (
frequency monitor
)
Enables or disables REF2 frequency monitor.
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
Level or
Dynamic
Signal
Signal at LD Pin
high.
(differential reference when in differential mode).
(not available in differential mode).
(differential reference when in differential mode).
(not available when in differential mode).
low.
.
.
Rev. B | Page 63 of 80
Page 64
AD9516-3 Data Sheet
Reg.
Addr.
(Hex)
0x01B [4:0] REFMON Selects the signal that is connected to the REFMON pin.
pin control
0 0 0 0 0 LVL Ground (dc) (default).
0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
0 0 0 1 0 DYN REF2 clock (not available in differential mode).
0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high.
0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high.
0 0 1 1 1 LVL Status REF1 frequency (active high).
0 1 0 0 0 LVL Status REF2 frequency (active high).
0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency).
0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
0 1 0 1 1 LVL Status of VCO frequency (active high).
0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
0 1 1 0 1 LVL Digital lock detect (DLD); active low.
0 1 1 1 0 LVL Holdover active (active high).
0 1 1 1 1 LVL LD pin comparator output (active high).
1 0 0 0 0 LVL VS (PLL supply).
1 0 0 0 1 DYN REF1 clock
1 0 0 1 0 DYN REF2 clock
1 0 0 1 1 DYN Selected reference to PLL
1 0 1 0 0 DYN Unselected reference to PLL
1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low.
1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low.
1 0 1 1 1 LVL Status of REF1 frequency (active low).
1 1 0 0 0 LVL Status of REF2 frequency (active low).
1 1 0 0 1 LVL (Status of REF1 frequency) AND (Status of REF2 frequency)
1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (Status of VCO)
1 1 0 1 1 LVL Status of VCO frequency (active low).
1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1).
1 1 1 0 1 LVL Digital lock detect (DLD); active low.
1 1 1 1 0 LVL Holdover active (active low).
1 1 1 1 1 LVL LD pin comparator output (active low).
0x01C 7 Disable Disables or enables the switchover deglitch circuit.
switchover 0: enables switchover deglitch circuit (default).
deglitch 1: disables switchover deglitch circuit.
6 Select REF2 If Register 0x01C, Bit 5 = 0, select reference for PLL.
0: selects REF1 (default).
1: selects REF2.
5 Use REF_SEL pin Sets method of PLL reference selection.
0: uses Register 0x01C, Bit 6 (default).
1: uses REF_SEL pin.
4 Reserved 0: (default).
3 Reserved 0: (default).
2 REF2 power-on This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
1 REF1 power-on This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
0 Differential
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic
switchover or REF1 and REF2 to work.
Level or
Dynamic
Signal
Rev. B | Page 64 of 80
Signal at REFMON Pin
(differential reference when in differential mode).
(not available in differential mode).
(differential reference when in differential mode).
(not available when in differential mode).
.
.
Page 65
Data Sheet AD9516-3
Reg.
Addr.
(Hex)
0x01D 4 PLL status Disables the PLL status register readback.
registerdisable0: PLL status register enable (default).
1: PLL status register disable.
3 LD pin comparator
0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).
1: enables LD pin comparator.
2 Holdover enable Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
1 External
holdover control 0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default)
0 Holdover enable Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
0x01F 6 VCO cal finished Read-only register. Indicates status of the VCO calibration.
0: VCO calibration not finished.
1: VCO calibration finished.
5 Holdover active Read-only register. Indicates if the part is in the holdover state (see Figure 53). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
4 REF2 selected Read-only register. Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
3 VCO frequency >
0: VCO frequency is less than the threshold.
1: VCO frequency is greater than the threshold.
2 REF2 frequency >
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
1 REF1 frequency >
0: REF1 frequency is less than threshold frequency.
1: REF1 frequency is greater than threshold frequency.
0 Digital lock detect Read-only register. Digital lock detect.
0: PLL is not locked.
1: PLL is locked.
Bits Name Description
enable
threshold
threshold
threshold
Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When
in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if
the PLL was previously in a locked state (see Figure 53). Otherwise, this function can be used with the REFMON and
STATUS pins to monitor the voltage on this pin.
Enables the external hold control through the
1: external holdover mode—holdover controlled by
Read-only register. Indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and VCO
frequency status monitor).
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x01A, Bit 6.
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A, Bit 6.
SYNC
pin. (This disables the internal holdover mode.)
SYNC
pin.
Rev. B | Page 65 of 80
Page 66
AD9516-3 Data Sheet
Table 55. Fine Delay Adjust—OUT6 to OUT9
Reg.
Addr.
(Hex)
0x0A0 0 OUT6 delay bypass Bypasses or uses the delay function.
0: uses delay function.
1: bypasses delay function (default).
0x0A1 [5:3] OUT6 ramp capacitors
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
5 4 3 Number of Capacitors
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2 1 0 Current (μA)
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2 1 0 Current (μA)
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of capacitors and the ramp current sets the delay full scale.
5 4 3 Number of Capacitors
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2 1 0 Current (μA)
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Rev. B | Page 67 of 80
Page 68
AD9516-3 Data Sheet
Reg.
Addr.
(Hex) Bits Name Description
0x0A9 0 OUT9 delay bypass Bypasses or uses the delay function.
0: uses delay function.
1: bypasses delay function (default).
0x0AA [5:3] OUT9 ramp capacitors
Selects the number of ramp capacitors used by the delay function. The combination of the
number of capacitors and the ramp current sets the delay full scale.
5 4 3 Number of Capacitors
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2 1 0 Current Value (μA)
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7 6 5 OUT7A (CMOS) OUT7B (CMOS) OUT7 (LVDS)
Rev. B | Page 72 of 80
Page 73
Data Sheet AD9516-3
Reg.
Addr.
(Hex) Bits Name Description
0x143 [2:1] OUT9 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.
0 0 1.75 100
0 1 3.5 100 (default)
1 0 5.25 50
1 1 7 50
0 OUT9 power-down Power-down output (LVDS/CMOS).
0: power on (default).
1: power off.
Table 58. LVPECL Channel Dividers
Reg.
Addr.
(Hex) Bits Name Description
0x190 [7:4] Divider 0 low cycles
[3:0] Divider 0 high cycles
0x191 7 Divider 0 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
6 Divider 0 nosync Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Divider 0 force high Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
4 Divider 0 start high Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0] Divider 0 phase offset Phase offset (default = 0x0).
0x192 1 Divider 0 direct to output Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
0x194 7 Divider 1 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6 Divider 1 nosync Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Divider 1 force high Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
2 1 Current (mA) Recommended Termination (Ω)
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
Number of clock cycles of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Rev. B | Page 73 of 80
Page 74
AD9516-3 Data Sheet
Reg.
Addr.
(Hex) Bits Name Description
0x194 4 Divider 1 start high Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0] Divider 1 phase offset Phase offset (default = 0x0).
0x195 1 Divider 1 direct to output Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
0x197 7 Divider 2 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
6 Divider 2 nosync Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Divider 2 force high Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
4 Divider 2 start high Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0] Divider 2 phase offset Phase offset (default = 0x0).
0x198 1 Divider 2 direct to output Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
Table 59. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex) Bits Name Description
0x199 [7:4] Low Cycles Divider 3.1
[3:0] High Cycles Divider 3.1
0x19A [7:4] Phase Offset Divider 3.2 Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high. A value of
0x0 means that the divider is high for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1)of 3.2 divider input during which 3.2 output stays high. A value
of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Rev. B | Page 74 of 80
Page 75
Data Sheet AD9516-3
Reg.
Addr.
(Hex) Bits Name Description
0x19C 5 Bypass Divider 3.2 Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
4 Bypass Divider 3.1 Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass 3.1 divider logic (default).
1: bypasses 3.1 divider logic.
3 Divider 3 nosync Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2 Divider 3 force high Force Divider 3 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
1 Start High Divider 3.2 Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
0 Start High Divider 3.1 Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
0x19D 0 Divider 3 DCCOFF Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x19E [7:4] Low Cycles Divider 4.1
[3:0] High Cycles Divider 4.1
0x19F [7:4] Phase Offset Divider 4.2 Refer to LVDS/CMOS channel divider function description (default = 0x0).
[3:0] Phase Offset Divider 4.1 Refer to LVDS/CMOS channel divider function description (default = 0x0).
0x1A0 [7:4] Low Cycles Divider 4.2
[3:0] High Cycles Divider 4.2
0x1A1
0x1A2 0 Divider 4 DCCOFF
5 Bypass Divider 4.2 Bypasses (and powers down) 4.2 divider logic; route clock to 4.2 output.
0: does not bypass 4.2 divider logic (default).
1: bypasses 4.2 divider logic.
4 Bypass Divider 4.1 Bypasses (and powers down) 4.1 divider logic; route clock to 4.1 output.
0: does not bypass 4.1 divider logic (default).
1: bypasses 4.1 divider logic.
3 Divider 4 nosync Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2 Divider 4 force high Forces Divider 4 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
1 Start High Divider 4.2 Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
0 Start High Divider 4.1
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x1E1 4 Power down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
3 Power down VCO clock interface Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
2 Power down VCO and CLK Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
0x1E1 1 Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
0 Bypass VCO divider Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
2 1 0 Divide
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Table 61. System
Reg.
Addr.
(Hex) Bits Name Description
0x230 2 Power down SYNC Powers down the SYNC function.
0: normal operation of the SYNC function (default).
1: powers down SYNC circuitry.
1 Power down distribution reference Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
0 Soft SYNC
The soft SYNC bit works the same as the SYNC
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
0: same as SYNC
1: same as SYNC
high (default).
low.
pin, except that the polarity of the bit
Table 62. Update All Registers
Reg.
Addr
(Hex) Bits Name Description
0x232 0 Update all registers
1 (self-clearing): updates all active registers to the contents of the buffer registers.
This bit must be set to 1 to transfer the contents of the buffer registers into the active
registers. This bit is self-clearing; that is, it does not have to be set back to 0.
Rev. B | Page 76 of 80
Page 77
Data Sheet AD9516-3
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9516
The AD9516 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9516, keep in mind the following
guidelines.
The AD9516 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
Within the AD9516 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9516 family. If the desired
frequency plan can be achieved with a version of the AD9516
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter. However,
choosing a higher VCO frequency may result in more flexibility
in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9516 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.
Considering an ideal ADC of infinite resolution, where the step
size and quantization error can be ignored, the available SNR
can be expressed approximately by
SNR
⎛
⎜
×=
log20(dB)
⎜
⎝
⎞
1
⎟
⎟
π
tf
2
J
A
⎠
where:
is the highest analog frequency being digitized.
f
A
is the rms jitter on the sampling clock.
t
J
Figure 70 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
110
f
A
(MHz)
SNR = 20log
t
J
=
1
0
2
0
0
f
S
4
0
0
f
S
1
p
s
2
p
s
1
0
p
s
0
100
90
80
70
SNR (dB)
60
50
40
30
101k100
Figure 70. SNR and ENOB vs. Analog Input Frequency
1
2πf
f
S
AtJ
18
16
14
12
ENOB
10
8
6
See the AN-756 Application Note, Sampled Systems and the Effects
of Clock Phase Noise and Jitter; and the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance, at
www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9516 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
06422-044
Rev. B | Page 77 of 80
Page 78
AD9516-3 Data Sheet
V
V
V
V
V
V
V
V
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9516 provide the lowest jitter
clock signals that are available from the AD9516. The LVPECL
outputs (because they are open emitter) require a dc termination
to bias the output transistors. The simplified equivalent circuit
in Figure 59 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 71) or Y-termination (see Figure 72) is recommended.
In each case, the V
VS_LVPECL. If it does not, ac coupling is recommended (see
Figure 73).
The resistor network is designed to match the transmission line
impedance (50 Ω) and the switching threshold (V
S_LVPECL
LVPECL
Figure 71. DC-Coupled 3.3 V LVPECL, Far-End Thevenin Termination
S_LVPECL
LVPECL
Figure 72. DC-Coupled 3.3 V LVPECL, Y-Termination
S_LVPECL
LVPECL
200Ω200Ω
Figure 73. AC-Coupled LVPECL with Parallel Transmission Line
of the receiving buffer should match the
S
− 1.3 V).
S
S_DRV
V
S
50Ω
127Ω127Ω
83Ω83Ω
50Ω
50Ω
100Ω
LVPECL
= 3.3V
S
LVPECL
S
LVPECL
50Ω
SINGLE-ENDED
(NOT CO UPLED)
50Ω
Z0 = 50Ω
Z0 = 50Ω
0.1nF
100Ω DIFFERENTIAL
0.1nF
(COUPLED)
TRANSMISSION LINE
06422-145
06422-147
06422-146
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 72, where VS_LVPECL = 2.5 V, the 50 Ω
termination resistor that is connected to ground should be
changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below V
of the LVPECL
OL
driver. In this case, VS_LVPECL on the AD9516 should equal V
of the receiving buffer. Although the resistor combination shown
in Figure 72 results in a dc bias point of VS_LVPECL − 2 V, the
actual common-mode voltage is VS_LVPECL − 1.3 V because
additional current flows from the AD9516 LVPECL driver through
the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that
the pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.
LVDS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields 350 mV output swing
across a 100 Ω resistor. An output current of 7 mA is also available
in cases where a larger output swing is required. The LVDS
output meets or exceeds all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 74.
S
LVDS
DIFFERENTIAL (COUPLED)
100Ω
100Ω
Figure 74. LVDS Output Termination
See the AN-586 Application Note, LVDS Data Outputs for HighSpeed Analog-to-Digital Converters for more information on LVDS.
S
LVDS
06422-047
S
Rev. B | Page 78 of 80
Page 79
Data Sheet AD9516-3
V
Ω
CMOS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9)
that are selectable as either CMOS or LVDS level outputs.
When selected as CMOS, each output becomes a pair of CMOS
outputs, each of which can be individually turned on or off and
set as noninverting or inverting. These outputs are 3.3 V CMOS
compatible.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver.
The value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
60.4
(1.0 INCH)
10Ω
CMOSCMOS
Figure 75. Series Termination of CMOS Output
MICROSTRIP
06422-076
Termination at the far-end of the PCB trace is a second option.
The CMOS outputs of the AD9516 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 76. The farend termination network should match the PCB trace impedance
and provide the desired switching point. The reduced signal
swing may still meet receiver input requirements in some
applications. This can be useful when driving long trace
lengths on less critical nets.
S
10Ω
CMOSCMOS
Figure 76. CMOS Output with Far-End Termination
50Ω
100Ω
100Ω
6422-077
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9516 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
Rev. B | Page 79 of 80
Page 80
AD9516-3 Data Sheet
OUTLINE DIMENSIONS
49
48
33
32
0.60 MAX
EXPOSED PAD
(BOTTOM VIEW)
64
1
16
17
7.50
REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATI ON AND
FUNCTION DE SCRIPTI ONS
SECTION O F THIS DATA SHEET.
PIN 1
INDICATOR
6.35
6.20 SQ
6.05
0.25 MIN
091707-C
9.00
PIN 1
INDICATOR
1.00
0.85
0.80
SEATING
PLANE
12° MAX
BSC SQ
TOP VIE W
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIAN T TO JEDEC S TANDARDS MO-220- VMMD-4
8.75
BSC SQ
0.20 REF
MAX
0.50
BSC
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.60
Figure 77. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
CP-64-4
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9516-3BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4
AD9516-3BCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4
AD9516-3/PCBZ Evaluation Board