Page 1
Triple 8-Bit, 140 MSPS
8
T/H
QUANTIZER
AD9483
TIMING
R AIN
R AIN
G AIN
G AIN
B AIN
B AIN
ENCODE
ENCODE
DS
DS
VREF
OUT
RVREFINGVREFINBVREFINV
CC
V
DD
GND
PD
I/P
OMS
CLKOUT
CLKOUT
D
B
B
7-0
DBA
7-0
DGB
7-0
DGA
7-0
DRB
7-0
DRA
7-0
8
T/H
QUANTIZER
8
T/H
QUANTIZER
CONTROL
+2.5V
a
FEATURES
140 MSPS Guaranteed Conversion Rate
100 MSPS Low Cost Version Available
330 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal +2.5 V Reference
Differential or Single-Ended Clock Input
3.3 V/5.0 V Three-State CMOS Outputs
Single or Demultiplexed Output Ports
Data Clock Output Provided
Low Power: 1.0 W Typical
+5 V Converter Power Supply
APPLICATIONS
RGB Graphics Processing
High Resolution Video
LCD Monitors and Projectors
Micromirror Projectors
Plasma Display Panels
Scan Converters
A/D Converter
AD9483
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD9483 is a triple 8-bit monolithic analog-to-digital
converter optimized for digitizing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 330 MHz
supports display resolutions of up to 1280 × 1024 at 75 Hz with
sufficient input bandwidth to accurately acquire and digitize
each pixel.
To minimize system cost and power dissipation, the AD9483
includes an internal +2.5 V reference and track-and-hold circuit. The user provides only a +5 V power supply and an encode clock. No external reference or driver components are
required for many applications. The digital outputs are threestate CMOS outputs. Separate output power supply pins support interfacing with 3.3 V or 5 V logic.
The AD9483’s encode input interfaces directly to TTL, CMOS,
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual channel or single
channel digital outputs. The Dual Channel (demultiplexed)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
mode interleaves ADC data through two 8-bit channels at onehalf the clock rate. Operation in Dual Channel mode reduces
the speed and cost of external digital interfaces while allowing
the ADCs to be clocked to the full 140 MSPS conversion rate.
In the Single Channel mode, all data is piped at the full clock
rate to the Channel A outputs and the ADCs conversion rate is
limited to 100 MSPS. A data clock output is provided at the
Channel A output data rate for both Dual-Channel or SingleChannel output modes.
Fabricated in an advanced BiCMOS process, the AD9483 is
provided in a space-saving 100-lead MQFP surface mount plas-
tic package (S-100) and is specified over the 0°C to +85°C
temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
Page 2
(VCC = +5 V, VDD = +3.3 V, external reference, ENCODE = maximum conversion rate
AD9483–SPECIFICATIONS
differential PECL)
Test AD9483KS-140 AD9483KS-100
Parameter Temperature Level Min Typ Max Min Typ Max Units
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity +25°C I 0.8 1.25/–1.0 0.8 1.25/–1.0 LSB
Full VI 1.50/–1.0 1.50/–1.0 LSB
Integral Nonlinearity +25°C I 0.9 1.50/–1.50 0.9 1.50/–1.50 LSB
Full VI 1.75/–1.75 1.75/–1.75 LSB
No Missing Codes Full VI Guaranteed Guaranteed
Gain Error
Gain Tempco
1
1
+25°CI ±1 ±2 ±1 ±2% FS
Full V 160 160 ppm/°C
ANALOG INPUT
Input Voltage Range
(With Respect to AIN) Full V ±512 ±512 mV p–p
Compliance Range AIN or AIN Full V 1.8 3.2 1.8 3.2 V
Input Offset Voltage +25°CI ±4 ±16 ±4 ±16 mV
Full VI ±20 ±20 mV
Input Resistance +25°C I 35 83 35 83 kΩ
Full VI 25 25 kΩ
Input Capacitance +25°CV 4 4 pF
Input Bias Current +25°C I 17 36 17 36 µA
Full VI 50 50 µA
Analog Bandwidth, Full Power +25°C V 330 330 MHz
REFERENCE OUTPUT
Output Voltage Full VI +2.4 +2.5 +2.6 +2.4 +2.5 +2.6 V
Temperature Coefficient Full V 110 110 ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 140 100 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t
) +25°C V 1.5 1.5 ns
A
) +25°C IV 2.8 50 4.0 50 ns
EH
) +25°C IV 2.8 50 4.0 50 ns
EL
Aperture Delay Matching +25°C V 100 100 ps
Aperture Uncertainty (Jitter) +25°C V 2.3 2.3 ps rms
Data Sync Setup Time (t
Data Sync Hold Time (t
Data Sync Pulsewidth (t
Output Valid Time (t
Output Propagation Delay (t
Clock Valid Time (t
CV
Clock Propagation Delay (t
Data to Clock Skew (t
Data to Clock Skew (tPD–t
) +25°CIV0 0 ns
SDS
) +25°C IV 0.5 0.5 ns
HDS
) +25°C IV 2.0 2.0 ns
PWDS
2
)
V
PD
3
)
CPD
) Full VI –1.0 0 1.0 –1.0 0 1.0 ns
V–tCV
) Full VI –2.0 0 2.0 –2.0 0 2.0 ns
CPD
Full VI 4.0 6.3 4.0 6.3 ns
2
)
Full VI 8.0 10 8.0 10 ns
Full VI 3.8 6.2 3.8 6.2 ns
3
)
Full VI 8.0 10 8.0 10 ns
DIGITAL INPUTS
Input Capacitance +25°CV 3 3 pF
DIFFERENTIAL INPUTS
Differential Signal Amplitude (VID) Full IV 400 400 mV
HIGH Input Voltage (V
LOW Input Voltage (V
Common-Mode Input (V
HIGH Level Current (I
) Full IV 0.4 V
IHD
) Full IV 0 0 V
ILD
) Full IV 1.5 1.5 V
ICM
) Full VI 1.2 1.2 mA
IH
CC
0.4 V
CC
V
LOW Level Current (IIL) Full VI 1.2 1.2 mA
VREF IN
Input Resistance +25°C V 2.5 2.5 kΩ
–2–
REV. A
Page 3
AD9483
Test AD9483KS-140 AD9483KS-100
Parameter Temperature Level Min Typ Max Min Typ Max Units
SINGLE-ENDED INPUTS
HIGH Input Voltage (VIH) Full IV 2.0 V
LOW Input Voltage (V
HIGH Level Current (I
) Full IV 0 0.8 0 0.8 V
IL
) Full VI 1 1 mA
IH
CC
LOW Level Current (IIL) Full VI 1 1 mA
DIGITAL OUTPUTS
Logic “1” Voltage Full VI V
– 0.05 V
DD
Logic “0” Voltage Full VI 0.05 0.05 V
Output Coding Binary Binary
POWER SUPPLY
VCC Supply Current Full VI 215 215 mA
V
Supply Current Full VI 60 60 mA
DD
Total Power Dissipation
4
Full VI 1.0 1.3 1.0 1.3 W
Power-Down Supply Current +25°CV 420 420mA
Power-Down Dissipation +25°C V 20 100 20 100 mW
DYNAMIC PERFORMANCE
5
Transient Response +25°C V 1.5 1.5 ns
Overvoltage Recovery Time +25°C V 1.5 1.5 ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
= 19.7 MHz +25°C V 45 45 dB
f
IN
f
= 49.7 MHz +25°C I 41 44 41 44 dB
IN
f
= 69.7 MHz +25°C V 44 44 dB
IN
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
= 19.7 MHz +25°C V 44 44 dB
f
IN
= 49.7 MHz +25°C I 40 43 40 43 dB
f
IN
f
= 69.7 MHz +25°C V 42 42 dB
IN
Effective Number of Bits
= 19.7 MHz +25°C V 7.0 7.0 Bits
f
IN
f
= 49.7 MHz +25°C I 6.4 6.8 6.4 6.8 Bits
IN
f
= 69.7 MHz +25°C V 6.8 6.8 Bits
IN
2nd Harmonic Distortion
= 19.7 MHz +25°C V 63 63 dBc
f
IN
f
= 49.7 MHz +25°C I 50 58 50 58 dBc
IN
= 69.7 MHz +25°C V 51 51 dBc
f
IN
3rd Harmonic Distortion
f
= 19.7 MHz +25°C V 56 56 dBc
IN
= 49.7 MHz +25°C I 46 54 46 54 dBc
f
IN
f
= 69.7 MHz +25°C V 51 51 dBc
IN
Crosstalk Full V 55 55 dB
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2
tV and t
3
tCV and t
4
Measured under the following conditions: analog input is –1 dBFS at 19.7 MHz.
5
SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range.
Typical thermal impedance for the S-100 (MQFP) 100-lead package: θJC = 10°C/W, θCA = 17°C/W, θJA = 27°C/W.
Specifications subject to change without notice.
are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 5 pF.
PDF
are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 20 pF.
CPD
2.0 V
– 0.05 V
DD
CC
V
–3–REV. A
Page 4
AD9483
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
V
DD
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
to 0.0 V
CC
to 0.0 V
CC
to 0.0 V
CC
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . .+150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C and sample tested at
specified temperatures.
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – 100% production tested at +25°C; guaranteed by design
and characterization testing.
Table I. Output Coding
Step AIN–AIN Code Binary
255 ≥0.512 V 255 1111 1111
254 0.508 V 254 1111 1110
253 0.504 V 253 1111 1101
•• • •
•• • •
•• • •
129 0.006 V 129 1000 0001
128 0.002 V 128 1000 0000
127 –0.002 V 127 0111 1111
126 –0.006 V 126 0111 1110
•• • •
•• • •
•• • •
2 –0.504 V 2 0000 0010
1 –0.508 V 1 0000 0001
0 ≤–0.512 V 0 0000 0000
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9483KS-100 0°C to +85°C Plastic Thin Quad Flatpack S-100B
AD9483KS-140 0°C to +85°C Plastic Thin Quad Flatpack S-100B
AD9483/PCB +25°C Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9483 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Page 5
AD9483
PIN FUNCTION DESCRIPTIONS
Pin Number Name Function
1, 6, 7, 10, 20, 30, 40, 50,
60, 70, 73, 77, 78, 80, 81,
95, 96, 100 GND Ground
2 ENCODE Encode clock for ADC (ADC samples on rising edge of ENCODE).
3 ENCODE Encode clock complement (ADC samples on falling edge of ENCODE).
4 DS Data Sync Aligns output channels in Dual-Channel mode.
5 DS Data Sync complement.
8 DCO Data Clock Output. Clock output at Channel A data rate.
9 DCO Data Clock Output complement.
11, 21, 31, 41, 51, 61, 71 V
79, 82, 83, 93, 94, 98, 99 V
12–19 D
22–29 D
32–39 D
42–49 D
52–59 D
62–69 D
DD
CC
BB7–DBB0
BA7–DBA0
GB7–DGB0
GA7–DGA0
RB7–DRB0
RA7–DRA0
72 NC No Connect.
74 OMS Selects Single Channel or Dual Channel output mode, (HIGH = single,
75 I/P Selects interleaved or parallel output mode, (HIGH = interleaved, LOW = parallel).
76 PD Power-Down and Three-State Select (HIGH = power-down).
84 R AIN Analog Input Complement for Converter “R.”
85 R AIN Analog Input True for Converter “R.”
86 R REF IN Reference Input for Converter “R” (+2.5 V Typical, ±10%).
87 G AIN Analog Input Complement for Converter “G.”
88 G AIN Analog Input True for Converter “G.”
89 G REF IN Reference Input for Converter “G” (+2.5 V Typical, ±10%).
90 B AIN Analog Input Complement for Converter “B.”
91 B AIN Analog Input True for Converter “B.”
92 B REF IN Reference Input for Converter “B” (+2.5 V Typical, ±10%).
97 REF OUT Internal Reference Output (+2.5 V Typical); Bypass with 0.01 µF to Ground.
Output Power Supply. Nominally 3.3 V.
Converter Power Supply. Nominally 5.0 V.
Digital Outputs of Converter “B,” Channel B. DBB7 is the MSB.
Digital Outputs of Converter “B,” Channel A. DBA7 is the MSB.
Digital Outputs of Converter “G,” Channel B. DGB7 is the MSB.
Digital Outputs of Converter “G,” Channel A. DGA7 is the MSB.
Digital Outputs of Converter “R,” Channel B. DRB7 is the MSB.
Digital Outputs of Converter “R,” Channel A. DRA7 is the MSB.
LOW = demuxed).
–5–REV. A
Page 6
AD9483
GND
1
GND
GND
DCO
DCO
GND
V
DBB
DBB
DBB
DBB
DBB
DBB
DBB
DBB
GND
V
DBA
DBA
DBA
DBA
DBA
DBA
DBA
DBA
GND
DS
DS
2
3
4
5
6
7
8
9
10
11
DD
12
7
13
6
14
5
15
4
16
3
17
2
18
1
19
0
20
21
DD
22
7
23
6
24
5
25
4
26
3
27
2
28
1
29
0
30
ENCODE
ENCODE
NC = NO CONNECT
PIN CONFIGURATION
Plastic Thin Quad Flatpack (S-100B)
CC
CC
V
V
GND
100
PIN 1
IDENTIFIER
GND
REF OUT
99989796959493
GND
CC
CC
B AIN
V
V
B REF IN
929190
B AIN
G REF IN
G AIN
89
88
G AIN
R REF IN
8786858483
AD9483
TOP VIEW
(PINS DOWN)
31
33
32
7
6
B
B
DD
G
G
V
D
D
37
35
34
5
4
B
B
G
G
D
D
39
40
38
36
3
2
B
B
G
G
D
D
41
1
0
B
B
DD
G
G
V
GND
D
D
45
43
44
42
7
6
5
A
D
4
A
A
A
G
G
G
G
D
D
D
R AIN
46
3
A
G
D
R AIN
47
2
A
G
D
CC
CC
GND
V
V
81
82
80
GND
79
V
CC
78
GND
77
GND
76
PD
75
I/P
74
OMS
73
GND
72
NC
71
V
DD
70
GND
69
DRA
0
68
DRA
1
67
DRA
2
66
DRA
3
65
DRA
4
64
DRA
5
63
DRA
6
62
DRA
7
61
V
DD
60
GND
59
DRB
0
58
DRB
1
57
DRB
2
56
DRB
3
55
DRB
4
54
DRB
5
DRB
53
6
52
DRB
7
51
V
DD
50
49
48
1
0
A
A
G
G
GND
D
D
–6–
REV. A
Page 7
TIMING
AD9483
AIN
ENCODE
ENCODE
DS
AIN
ENCODE
ENCODE
D7–D0
CLOCK OUT
CLOCK OUT
SAMPLE N–2
SAMPLE N–1
SAMPLE N
t
EH
SAMPLE N+3
A
SAMPLE N+1
t
EL
1/f
t
SAMPLE N+2
S
SAMPLE N+4
t
DATA N–5 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N
t
CPD
Figure 1. Timing—Single Channel Mode
SAMPLE N–1
t
EH
t
HDS
t
EL
t
SDS
SAMPLE N
t
A
1/f
SAMPLE N+1
S
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
SAMPLE N+5
PD
t
V
t
CV
SAMPLE N+6
DS
PORT A
D7–D0
PORT B
D7–D0
PORT A
D7–D0
PORT B
D7–D0
CLKOUT
CLKOUT
DATA N–7
OR N–8
DATA N–8
OR N–7
DATA N–9
OR N–8
DATA N–8
OR N–7
DATA N–7
DATA N–6
OR N–7
DATA N–7
OR N–8
DATA N–6
OR N–7
INTERLEAVED DATA OUT
OR N–6
INVALID IF OUT OF SYNC
DATA N–5 IF IN SYNC
INVALID IF OUT OF SYNC
DATA N–5 IF IN SYNC
INVALID IF OUT OF SYNC
DATA N–4 IF IN SYNC
PARALLEL DATA OUT
DATA N–7
OR N–6
DATA N–3
INVALID IF OUT OF SYNC
DATA N–4 IF IN SYNC
DATA N–3
Figure 2. Timing—Dual Channel Mode
t
PD
DATA N–2
t
V
DATA N
DATA N–1
DATA N–2
DATA N–1
t
t
CV
CPD
DATA N+1
DATA N
DATA N+1
–7–REV. A
Page 8
AD9483
V
DD
DIGITAL
OUTPUTS
AD9483
V
CC
AD9483
DIGITAL
INPUTS
EQUIVALENT CIRCUITS
V
CC
AIN
AIN
AD9483
Figure 3. Equivalent Analog Input Circuit
V
CC
VREF IN
500V
2kV
AD9483
Figure 4. Equivalent Reference Input Circuit
17.5kV
ENCODE
300V
DS
AD9483
300V
7.5kV
V
CC
ENCODE
DS
Figure 7. Equivalent Digital Output Circuit
V
CC
VREF
OUT
AD9483
Figure 8. Equivalent Reference Output Circuit
Figure 5. Equivalent Encode and Data Select Input Circuit
V
AD9483
DEMUX
Input Circuit
DEMUX
Figure 6. Equivalent
Figure 9. Equivalent Digital Input Circuit
CC
–8–
REV. A
Page 9
Typical Performance Characteristics–
1412 130
2.6
2.5
2.4
12345678910
VOLTS
2.3
2.2
2.1
2
1.9
1.8
1.7
1.6
11 15
I
REF
– mA
AD9483
0
–0.5
–1
–3dB
(333MHz)
dB
–1.5
–2
–2.5
–3
–3.5
–4
–4.5
–5
NYQUIST FREQUENCY
(70MHz)
050
150 250 300 400 450
100 200 350
f
IN
– MHz
Figure 10. Frequency Response: fS = 140 MSPS
–70
–60
–50
–40
dB
–30
–20
2.5
2.48
2.46
VOLTS
2.44
2.42
2.4
–40 0
–20 20 40 60 80 100
TEMPERATURE – 8C
Figure 13. Reference Voltage vs. Temperature
2.6
2.5
2.4
2.3
REF
V
2.2
–10
0
Figure 11. Crosstalk vs. fIN: fS = 140 MSPS
–80
–75
–70
–65
dB
–60
–55
–50
0
Figure 12. Crosstalk vs. Temperature: fIN = 70 MHz
05
10 20 30 40 50 60 70 80 90
10 50 100 200 2502.5 7.5 25 75 150
fIN – MHz
TEMPERATURE – 8C
100
2.1
2
3
3.2 3.4 3.6 3.8 4 4.2
4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4
VCC – V
Figure 14. Reference Voltage vs. Power Supply Voltage
Figure 15. Reference Voltage vs. Reference Load
–9–REV. A
Page 10
AD9483
–Typical Performance Characteristics
9
8.5
8
7.5
7
6.5
ns
6
5.5
5
4.5
4
5101520
T
3.3V
PD
TV 5V
LOAD CAPACITANCE – pF
T
5V
PD
TV 3.3V
25 30
Figure 16. Clock Output Delay vs. Capacitance
9
8
VDD – V
T
PD
T
V
DD
7
6
5
ns
4
3
2
1
0
3 3.3
3.6 3.9 4.2 4.5 4.75 5 5.25 5.5
Figure 17. Output Delay vs. V
5
4.5
4
3.5
3
2.5
VOLTS
2
1.5
1
0.5
0
V
= +3.3V
DD
0 2 10 16 20
468 1214 18
IOH – mA
V
= +5V
DD
Figure 19. Output Voltage HIGH vs. Output Current
2
1.8
1.6
1.4
1.2
1
VOLTS
0.8
0.6
0.4
0.2
0
0 5 10 15 20
V
DD
= +3.3V
V
= +5V
DD
I
OL
Figure 20. Output Voltage LOW vs. Output Current
9
T
3.3V
8.5
7.5
6.5
ns
5.5
4.5
PD
8
7
6
5
4
–40 0 50 100
T
PD
TEMPERATURE – 8C
TV 5V
5V
TV 3.3V
Figure 18. Output Delay vs Temperature
–10–
600
500
400
300
mW
200
100
0
3 3.5 4 4.5 5 5.5
Figure 21. Output Power vs. VDD, C
VDD – V
LOAD
= 10 pF
REV. A
Page 11
AD9483
MHz
0
dB
–90
10 20 30 40 50 60 70 80 90 100
–80
–70
–60
–50
–40
–30
–20
–10
0
FUNDAMENTAL = –0.5dBFS
SNR = 44.6dB
SINAD = 37.6dB
2ND HARMONIC = 63.1dB
3RD HARMONIC = 39.1dB
50
48
46
44
42
40
dB
38
36
34
32
30
0
30 60 140 180
100
fS – MSPS
SNR
SINAD
Figure 22. SNR vs. fS: fIN = 19.7 MHz
–75
–70
3RD HARMONIC
–65
dB
–60
2ND HARMONIC
–55
–50
0
25 50 130 170
f
– MSPS
S
90
Figure 23. Harmonic Distortion vs. fS: fIN = 19.7 MHz
50
48
46
44
42
40
dB
38
36
34
32
30
0
20 140 180
40 60 80 100 120 160 200
f
– MSPS
S
SINAD
SNR
Figure 25. SNR vs fS: fIN = 71.7 MHz
–56
dB
–54
–52
–50
–48
–46
–44
–42
–40
–38
–36
3RD HARMONIC
0
40 80 155 175120
fS – MSPS
2ND HARMONIC
Figure 26. Harmonic Distortion vs fS: fIN = 71.7 MHz
0
–10
–20
–30
–40
dB
–50
–60
–70
–80
–90
10 20 30 40 50 60 70 80 90 100
0
Figure 24. Spectrum: fS = 140 MSPS, fIN = 19.57 MHz
FUNDAMENTAL = –0.5dBFS
SNR = 45.8dB
SINAD = 45.2dB
2ND HARMONIC = 69.8dB
3RD HARMONIC = 61.6dB
MHz
Figure 27. Spectrum: fS = 140 MSPS, fIN = 70.3 MHz
–11–REV. A
Page 12
AD9483
dB
46
44
42
40
38
36
34
32
30
fS = 140 MSPS
f
= 19.3MHz
IN
28%231%
25%
1.8
38%
2.2
ENCODE DUTY CYCLE – %
ENCODE PULSEWIDTH – ns
2.7
45%
3.2
SNR
52%
3.7
59%
4.2
Figure 28. SNR vs. Clock Pulsewidth (t
55
50
45
dB
40
35
NYQUIST FREQUENCY
(70.0MHz)
SINAD
66%
73%
4.7
PWH
SINAD
76%
5.2
5.4
): fS = 140 MSPS
SNR
46
SNR
45
44
43
dB
42
41
40
–25
0 406080100
SINAD
TEMPERATURE – 8C
Figure 31. SNR vs. Temperature, fS = 140 MSPS
–70
–65
–60
–55
dB
–50
–45
30
050
100 150 200 250
fIN – MHz
Figure 29. SNR vs. fIN: fS = 140 MSPS
–60
–56
–52
dB
–48
–44
–40
–25
0 40 60 80 100
TEMPERATURE – 8C
Figure 30. 3rd Harmonic vs. Temperature, fS = 140 MSPS
–40
–25
0 40 60 80 100
TEMPERATURE – 8C
Figure 32. 2nd Harmonic vs. Temperature, fS = 140 MSPS
0
–10
–20
–30
–40
–50
dB
–60
–70
–80
–90
–100
10 20 30 40 50 60 70 80 90 100
0
MHz
F1 = 55.0MHz
F2 = 56.0MHz
F1 = F2 = –7.0dBFS
Figure 33. Two Tone Intermodulation Distortion
–12–
REV. A
Page 13
AD9483
V
ID
V
ID
V
IH D
V
IC M
V
IL D
V
IN D
V
IC M
V
IL D
ENC
ENC
CLOCK
CLOCK
ENC
ENC
CLOCK
0.1mF
DRIVING DIFFERENTIAL INPUTS DIFFERENTIALLY
DRIVING DIFFERENTIAL INPUTS SINGLE-ENDEDLY
APPLICATION NOTES
Theory of Operation
The AD9483 combines Analog Devices’ patented MagAmp bitper-stage architecture with flash converter technology to create a
high performance, low power ADC. For ease of use the part
includes an on board reference and input logic that accepts
TTL, CMOS or PECL levels.
Each of the three analog input signals is buffered by a high speed
differential amplifier and applied to a track-and-hold (T/H)
circuit. This T/H captures the value of the input at the sampling
instant and maintains it for the duration of the conversion. The
sampling and conversion process is initiated by a rising edge on
the ENCODE input. Once the signal is captured by the T/H,
the four Most Significant Bits (MSBs) are sequentially encoded
by the MagAmp string. The residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). The comparator outputs are decoded and combined into the 8-bit result.
If the user has selected Single Channel mode (OMS = HIGH)
the 8-bit data word is directed to an A output bank. Data are
strobed to the output on the rising edge of the ENCODE input
with four pipeline delays. If the user has selected Dual Channel
mode (OMS = LOW) the data are alternately directed between
the A and B output banks and the data has five pipeline delays.
At power-up, the N sample data can appear at either the A or B
Port. To align the data in a known state, the user must strobe
DATA SYNC (DS, DS) per the conditions described in the
Timing section.
Graphics Applications
The high bandwidth and low power of the AD9483 makes it
very attractive for applications that require the digitization of
presampled waveforms, wherein the input signal rapidly slews
from one level to another, then is relatively stable for a period of
time. Examples of these include digitizing the output of computer graphic display systems, and very high speed solid state
imagers.
These applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. The architecture of the AD9483 is vastly superior to older flash architectures, which not only exhibit excessive input capacitance (which
is very hard to drive), but can make major errors when fed a
very rapidly slewing signal. The AD9483’s extremely wide
bandwidth Track/Hold circuit processes these signals without
difficulty.
Using the AD9483
Good high speed design practices must be followed when using
the AD9483. Decoupling capacitors should be physically as
close as possible to the chip to obtain maximum benefit. We
recommend placing a 0.1 µF capacitor at each power ground
pin pair (14 total) for high frequency decoupling and including
one 10 µF capacitor for local low frequency decoupling. Each of
the three VREF IN pins should also be decoupled by a 0.1 µF
capacitor.
The part should be located on a solid ground plane and output
trace lengths should be short (<1 inch) to minimize transmission line effects. This will avoid the need for termination resistors on the output bus and reduces the load capacitance that
needs to be driven, which in turn minimizes on-chip noise due
to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all V
CC
to a quiet analog power supply system and tying all GND pins
to a quiet analog system ground.
Minimum Encode Rate
The minimum sampling rate for the AD9483 is 10 MHz for the
140 MSPS and 100 MSPS versions. To achieve this sampling
rate, the Track/Hold circuit employs a very small hold capacitor.
When operated below the minimum guaranteed sampling rate,
the T/H droop becomes excessive. This is first observed as an
increase in offset voltage, followed by degraded linearity at even
lower frequencies.
Lower effective sampling rates may be easily supported by operating the converter in Dual Port output mode and using only
one output channel. A majority of the power dissipated by the
AD9483 is static (not related to conversion rate), so the penalty
for clocking at twice the desired rate is not high.
Digital Inputs
SNR performance is directly related to the sampling clock stability in A/D converters, particularly for high input frequencies
and wide bandwidths.
ENCODE and Data Select (DS) can be driven differentially or
single-ended. For single-ended operation, the complement
inputs (ENCODE, DS) are internally biased to V
/3 (~1.5 V)
DD
by a high impedance on-chip resistor divider (Figure 5), but
they may be externally driven to establish an alternate threshold
if desired. A 0.1 µF decoupling capacitor to ground is sufficient
to maintain a threshold appropriate for TTL or CMOS logic.
When driven differentially, ENCODE and DS will accommodate differential signals centered between 1.5 V and 4.5 V with a
total differential swing ≥800 mV (V
≥400 mV).
ID
Note the 6-diode clock input protection circuitry in Figure 5.
This limits the differential input voltage to ±2.1 V. When the
diodes turn on, current is limited by the 300 Ω series resistor.
Exceeding 2.1 V across the differential inputs will have no impact on the performance of the converter, but be aware of the
clock signal distortion that may be produced by the nonlinear
impedance at the converter.
Figure 34. Input Signal Level Definitions
–13–REV. A
pins
Page 14
AD9483
ADC Gain Control
Each of the three ADC channels has independent limited gain
control. The full-scale signal amplitude for a given ADC is set by
the dc voltage on its VREF In pin. The equation relating the full
scale amplitude to VREF In is as follows: FS = (0.4) × (VREF
IN). The three ADCs are optimized for a full-scale signal ampli-
tude of 1 V, but will accommodate up to ±10% variation.
ADC Offset Control
The offset for each of the three ADCs can be independently
controlled. For a single-ended analog input where the analog
input is connected to a reference, offset can be adjusted simply
by adjusting the dc voltage of the reference. For differential
analog inputs, the user must provide the offset in their signal.
Offset can be adjusted up or down as far as the common-mode
input range will allow.
Power Dissipation
Power dissipation for the AD9483 has two components, V
CC
and VDD. Power dissipation from VCC is relatively constant for a
given supply voltage, whereas power dissipation from V
vary greatly. V
supplies power to the analog circuity. V
CC
DD
can
DD
supplies power to the digital outputs and can be approximated
by the following equation:
P (V
) = 1/2 C × V2 × F × N
DD
C = Output Load Capacitance
V =V
Supply Voltage
DD
F = Encode Frequency
N = Number of Outputs Switching
Nominally, C = 10 pF, V = 3.3 V, F = 140 MSPS, and N = 26.
N comes from the 24 output bits plus two clock outputs, P(V
DD
) =
197 mW.
Power-Down
The power-down function allows users to reduce power dissipation when output data is not required. A TTL/CMOS HIGH
signal on pin 76, (PD), shuts down most of the chip and brings
the total power dissipation to less than 100 mW. The internal
bandgap voltage reference remains active during power-down
mode to minimize reactivation time. If the power-down function
is not desired, the PD pin should be tied to ground or held to a
TTL/CMOS LOW level.
Bandgap Voltage Reference
The AD9483 internal reference, VREF OUT (Pin 97), provides
a simple, cost effective reference for many applications. It exhibits reasonable accuracy and excellent stability over power supply
and temperature variations. The reference output can be used to
set the three ADCs’ gain and offset. The reference is capable of
providing up to 1 mA of additional current beyond the requirements of the AD9483.
As the ADC gain and offset are set by the reference inputs,
some applications may require a reference with greater accuracy
or temperature performance. In these cases, an external reference may be connected directly to the VREF IN pins. VREF
OUT, if unused, should be left floating. Note, each of the three
VREF IN pins will require up to 1 mA of current.
Modes of Operation
The AD9483 has three modes of operation, Single Channel
output mode, and a Dual Channel output mode with two possible data formats, interleaved or parallel. Two pins control which
mode of operation the chip is in, Pin 74 Output Mode Select
(OMS) and Pin 75 Interleaved/Parallel Select (I/P). Table II
shows the configuration required for each mode.
Table II. Output Mode Selection
MODE OMS I/P
Dual Channel—Parallel LOW LOW
Dual Channel—Interleaved LOW HIGH
Single Channel HIGH DON’T CARE
Demuxed Output Mode
In demuxed mode, (Pin 74 OMS = LOW), the ADC output
data are alternated between the two output ports (Port A and
Port B). This limits the data output rate to 1/2 the rate of
ENCODE, and facilitates conversion rates up to 140 MSPS.
Demuxed output mode is recommended for guaranteed operation above 100 MSPS, but may be enabled at any specified
conversion rate.
Two data formats are possible in Dual Channel output mode,
parallel data out and interleaved data out. Pin 75 I/P should be
LOW for parallel format and HIGH for interleaved format.
Figures 1 and 2 show the timing requirements for each format.
Note that the Data Sync input, (DS), is required in Dual Channel output mode for both formats. The section on Data Sync
describes the requirements of the Data Sync input.
As shown in Figures 1 and 2, when using the interleaved data
format, a sample is taken on an ENCODE rising edge N. The
resulting data is produced on an output port following the fifth
rising edge of ENCODE after the sample was taken, (five pipeline delays). The following sample, (N+1), will be produced on
the opposite port, also five pipeline delays after it was taken.
The state of CLKOUT when the sample was taken will determine out of which port the data will come. If CLKOUT was
LOW, the data will come out Port A. If CLKOUT was HIGH,
the data will come out Port B.
In order to achieve parallel data format on the two output data
ports, the data is internally aligned. This is accomplished by
adding an extra pipeline delay to just the A Data Port. Thus,
data coming out Port A will have six pipeline delays and data
coming out Port B will have five pipeline delays. As with the
interleaved format, the state of Data Sync when a sample is
taken will determine out of which port the data will come. If
CLKOUT was LOW, the data will come out Port A. If CLKOUT was HIGH, the data will come out Port B.
–14–
REV. A
Page 15
AD9483
Data Sync
The Data Sync input, DS, is required to be driven for most
applications to guarantee at which output port a given sample
will appear. When DS is held high, the ADC data outputs and clock
outputs do not switch—they are held static. Synchronization is
accomplished by the assertion (falling edge) of DS, within the
timing constraints T
SDS
and T
edge. (On initial synchronization T
falls T
before a given encode rising edge N, the analog value
SDS
relative to an encode rising
HDS
is not relevant.) If DS
HDS
at that point in time will be digitized and available at Port A five
cycles later (interleaved mode). The very next sample, N+l, will
be sampled by the next rising encode edge and available at Port
B five cycles after that encode edge (interleaved mode). In dual
parallel mode the A port has a six cycle latency, the B port has a
five cycle latency as described in Demuxed Outputs Mode section.
DS can be asserted once per video line if desired by using the
horizontal sync signal (HSYNC). The start of HSYNC should
occur after the end of active video by at least the chip latency.
The HSYNC front porch is usually much greater than this in a
typical SXGA system. If this is true in a given system then DS
can be reset high by the HSYNC leading edge (the samples at
that point should not be required in a typical system). DS can
then be reasserted (brought low), by triggering from HSYNC
trailing edge—observing T
of the next rising encode edge.
SDS
The first pixel data (on A Port) would be available five cycles
after the first rising encode after HSYNC goes high.
It is possible to use the phase of the data clock outputs and
software programming to accommodate situations where DS is
not driven. The data clock outputs (CLKOUT and CLKOUT)
can be used to determine when data is valid on the output ports.
In these cases DS should be grounded and DS left floating or
connected to V
. If CLKOUT was low when a given sample
CC
was taken, the digitized value will be available on Port A, five
cycles later. Data Sync has no effect when Single Channel
Mode is selected, it should be grounded
Figure 2 shows how to use DS properly. The DS rising edge
does not have any special timing requirements except that no
data will come out of either port while it is held HIGH. The
falling edge of DS must, however, meet a minimum setup-andhold time with respect to the rising edge of ENCODE.
Single Channel Outputs Mode
In Single Channel mode, (Pin 74 OMS = HIGH), the timing of
the AD9483 is similar to any high speed ADC (Figure 1). A
sample is taken on every rising edge of ENCODE, and the resulting data is produced on the output pins following the fourth
rising edge of ENCODE after the sample was taken, (four pipeline delays). The output data are valid t
of ENCODE, and remain valid until at least t
after the rising edge
PD
after the next
V
rising edge of ENCODE.
The maximum conversion rate in the mode should be limited to
100 MSPS. This is recommended because the guaranteed output data valid time minus the propagation delay is only 4 ns at
100 MSPS. This is about as fast as standard logic is able to capture
the data with reasonable design margins. The AD9483 will
operate faster in this mode if the user is able to capture the data.
When operating in single channel mode, all data comes out the
A Ports while the B Ports are held static in a random state.
Data Clock Outputs
The data clock outputs will switch at two potential frequencies.
In Single Channel mode, where all data comes out of Port A
at the full ENCODE rate, the data clock outputs switch at the
same frequency as the ENCODE. In Dual Channel mode,
where the data alternates between the two ports, each of which
operate at 1/2 the full ENCODE rate, the data clock outputs
also switch at 1/2 the full ENCODE rate.
The data clock outputs have two potential purposes. The first is
to act as a latch signal for capturing output data. In order to do
this, simply drive the data latches with the appropriate data
clock output. The second use is in Dual Channel data mode to
help determine out of which data port data will come out. Refer
to Figure 2 for a complete timing diagram, but in this mode, a
rising edge on data clock will correspond to data switching on
data Port B.
LAYOUT AND BYPASSING CONSIDERATIONS
Proper high speed layout and bypassing techniques should be
used with the AD9483. Each V
and VDD power pin should be
CC
bypassed as close to the pin as possible with a 0.01 µF to 0.1 µF
capacitor Also, one 10 µF capacitor to ground should be used
per supply per board. The VREF OUT pin and each of the
three VREF IN pins should also be bypassed with a 0.01 µF to
0.1 µF capacitor to ground.
A single, substantial, low impedance ground plane should be
place under and around the AD9483. Try to maximize the
distance between the sensitive analog signals, (AIN, VREF),
and the digital signals. Capacitive loading on the digital outputs
should be kept to a minimum. This can be facilitated by keeping
the traces short and in the case of the clock outputs by driving
as few other devices as possible. Socketing the AD9483 should
also be avoided. Try to match trace lengths of similar signals to
avoid mismatches in propagation delays, (the encode inputs,
analog inputs, digital outputs).
POWER SUPPLIES
At power up, VCC must come up before VDD. VCC is considered
the converter supply, nominally 5.0 V (±5.0%) V
is consider
DD
output power supply, nominally 3.3 V (±10%) or 5.0 V (±5%).
At power off, V
must turn off first. Failure to observe the
DD
correct power supply sequencing many damage this device.
–15–REV. A
Page 16
AD9483
EVALUATION BOARD
The AD9483 evaluation board offers an easy way to test the
AD9483. It provides ac or dc biasing for the analog input, it
generates the output latch clocks for Single Mode, Dual
Parallel Mode and Dual Interleaved Mode. Each of the three
channels has a reconstruction DAC (A Port only). The board
has several different modes of operation, and is shipped in
the following configuration:
• Single-ended ac coupled analog input (1 V p-p centered
at ground)
• Differential clock inputs (PECL) (See ENCODE section
for TTL drive)
• Internal voltage references connected to externally buff-
ered on-chip reference (VREF OUT)
• Preset for Dual Mode Interleaved
Analog Input
The evaluation board accepts a 1 V p-p input signal centered
at ground for ac coupled input mode (Set Jumpers W4, W5,
W12, W13, W18, W17 to jump Pin 1 to Pin 2). This signal
biased up to 2.5 V by the on-chip reference. Note: input
signal should be bandlimited (filtered) prior to sampling to
avoid aliasing. The analog inputs are terminated to ground
by a 75 Ω resistor on the board. The analog inputs are ac
coupled through 0.1 µF caps C2, C4, C6 on top of the
board. These can be increased to accommodate lower frequency inputs if desired using test points PR1–PR6 on bottom of board. In dc coupled input mode (Set Jumpers W4,
W5, W12, W13, W18, W17 to jump Pin 3 to Pin 2 ) the
board accepts typical video level signal levels (0 mV to 700 mV)
the signal is level shifted and amplified to 1 V p-p by the
AD8055 preamp. Trimpots R98–R100 are used to adjust dc
black level to 2 V at ADC inputs.
Encode
The AD9483 ENCODE input can be driven two ways.
1. Differential PECL (V
= 3, VHI = 4 nominal). It is
LO
shipped in this mode.
2. Single ended TTL or CMOS. (At Encode Bar–Remove
50 Ω termination resistor R10, add 0.1 µF capacitor C7)
Voltage Reference
The AD9483 has an internal 2.5 V voltage reference (VREF
OUT). This is buffered externally on board to support additional level shifting circuitry (the AD9483 VREF OUT pin can
drive the three VREF IN pins in applications where level shifting
is not required with no additional buffering). An external reference may be employed instead to drive each VREF IN pin independently (requires moving Jumpers W14, W15 and W16).
Single Channel Mode
Single Channel mode sets the AD9483 to produce data on
every clock cycle on output port A only. The maximum speed
in Single Channel mode is 100 MSPS.
Dual Channel Modes (Outputs Clocked at 1/2 Encode Clock)
Dual Channel Interleaved
Sets the ADC to produce data alternately on Port A and Port B.
the maximum speed in this mode is 140 MSPS.
Dual Channel Parallel
Sets the ADC to produce data concurrently on Port A and Port
B. Maximum speed in this mode is 140 MSPS.
DAC Out
The DAC output is a representation of the data on output Port
A only. The DAC is terminated on the board into 75 Ω. Full-
scale voltage swing at DAC output is nominally 0 mV to 800 mV
when terminated into external 75 Ω (doubly terminated).
Output Port B is not reconstructed. The DAC outputs are NOT
filtered and will exhibit sampling noise. The DACs can be powered down at W1, W2, and W3 (jumper not installed).
Data Ready
An output clock for latching the ADC outputs is available at
Pin 1 at the 25-pin connector. Its complement is located at
Pin 14. The clocks are terminated on the board by a 75 Ω
Thevenin termination to V
/2. The timing on these clock out-
D
puts can be inverted at W9, W10 (jumper not installed).
Schematics
The schematics for the evaluation board follow. (Note bypass
capacitors for ADC are shown in Figure 39.)
Table III. Evaluation Board Jumper Settings
MODE W7 (OMS) W6 (I/P) W11 (A_LAT) W11 (B_LAT)
Dual Channel/PARALLEL LOW LOW DATA_CLK_OUT (4–5) DATA_CLK_OUT (2–3)
Dual Channel/INTERLEAVED LOW HIGH DATA_CLK_OUT (5–6) DATA_CLK_OUT (2–3)
SINGLE HIGH DON’T CARE DATA_CLK_OUT (5–6) NC
DESIGN NOTES
Maximum frequency for PARALLEL is 140 MHz.
Maximum frequency for INTERLEAVED is 140 MHz.
Maximum frequency for SINGLE is 100 MHz.
DS is tied to ground through a 50 Ω resistor.
DS is left floating.
–16–
REV. A
Page 17
AD9483
A[0-7]
B[0-7]
OUTB
OUTB
A6
A5
A4
A3
A2
A1
A0
A2
A1
A0
A6
A5
A4
A3
VDD
OUTA_A[0-7]
OUTA_B[0-7]
W7
1
3
W6
1
3
49 OUTB
A7
A6
A5
A4
A3
A2
A1
52OUTA
B7
OUTA
53OUTA
B6
OUTA
54OUTA
B5
OUTA
B4
55OUTA
OUTA
56OUTA
B3
OUTA
57OUTA
B2
OUTA
58OUTA
B1
OUTA
59OUTA B0
OUTA B0
62OUTA
A7
OUTA
63OUTA
A6
OUTA
64OUTA
A5
OUTA
65OUTA
A4
OUTA
66OUTA
A3
OUTA
67OUTA
A2
OUTA
68OUTA
A1
OUTA
69OUTA A0
OUTA
R101
74
100V
2
2
R102
100V
OMS
75
I/P
76
PWR
84
A0
B7
B6
B5
B4
B3
B2
B1
A7
A6
A5
A4
A3
A2
A1
A0
DN
AIN A
85
REF
A
A
AIN
OUTB
87
OUTB
OUTB
B
AIN
88
B
REF
OUTB
B
AIN
OUTB
90
OUTB
OUTB
AD9483
C
AIN
91
C
OUTB
C
AIN
REF
38 OUTB
39 OUTB
OUTB_B1
OUTB_B0
REF IN
A
86
REF
A
36 OUTB
37 OUTB
OUTB_B3
OUTB_B2
89
B
42 OUTB A7
43 OUTB
44 OUTB
45 OUTB
46 OUTB
47 OUTB
48 OUTB
33 OUTB
34 OUTB
35 OUTB
OUTB_B5
OUTB_B4
DATA CLK OUT
DATA
REF IN
B
92
C
REF
32 OUTB A7
OUTC
OUTC
OUTB_B7
OUTB_B6
OUTC
OUTC
OUTC
OUTC
OUTC
OUTC_A7
OUTC
OUTC
OUTC
OUTC
OUTC
OUTC
OUTC
OUTC
CLK OUT
ENCODE
ENCODE
REF IN
C
REF
A0
A1
A2
A3
A4
A5
A6
B0
B1
B2
B3
B4
B5
B6
B7
DS
DS
OUT
REF
97
REF OUT
29 OUTC
A0
28 OUTC
A1
27 OUTC
A2
A3
26 OUTC
25 OUTC
A4
24 OUTC
A5
23 OUTC
A6
22 OUTC A7
19 OUTC
B0
18 OUTC
B1
17 OUTC
B2
16 OUTC
B3
15 OUTC
B4
14 OUTC
B5
13 OUTC
B6
12 OUTC B7
9
8
5
4
3
2
R9
50V
ENCODE
SMB
ENC
OUTC_A[0-7]
OUTC_B[0-7]
DATA
CLK OUT
DATA_CLK_OUT
DS
DS
C7
0.1mF
NOT
INSTALLED
J1
SMB
R10
50V
ENCODE
J2
ENC
PR2
PR1
1kV
–VA
PR5
PR6
1kV
C
REF
C5
0.1mF
R6
R90
360V
C6
0.1mF
TP3
W18
BNC
W17
VA
R91
274V
1
1
7
2
2
2
3
6
U16
AD8055
TRIM
3
R3
75V
J5
R105
200V
4
3
–VA
C
PR4
PR3
1kV
B
REF
C3
0.1mF
R5
R89
360V
C4
0.1mF
TP1
W12
BNC
VA
274V
1
W13
R88
2
2
1
7
U15
AD8055
2
3
R2
75V
J6
3
R104
200V
6
3
TRIM
4
B
A
REF
C1
0.1mF
R4
R86
360V
C2
0.1mF
TP2
VA
W4
BNC
W5
R87
274V
1
1
2
2
2
7
U14
AD8055
3
R1
75V
J7
3
R103
200V
6
3
TRIM
4
–VA
A
Figure 35. ADC and Preamp Section
–17–REV. A
Page 18
AD9483
VD
U8
R7
301VR8301V
GND: 10
EN
11
1
GND
VD: 20
C1
VD
R76
301V
R77
301V
GND: 10
VD: 20
74LCX574
1D
OUTC A0 2 19 BLUE A0
OUTC A1 3 18 BLUE A1
OUTC A2 4 17 BLUE A2
OUTC A3 5 16 BLUE A3
OUTC A4 6 15 BLUE A4
OUTC A5 7 14 BLUE A5
OUTC A6 8 13 BLUE A6
OUTC A7 9 12 BLUE A7
U11
1
EN
GND
C1
1D
11
OUTC B0 2 19 BLUE B0
OUTC B1 3 18 BLUE B1
OUTC B2 4 17 BLUE B2
OUTC B3 5 16 BLUE B3
OUTC B4 6 15 BLUE B4
OUTC B5 7 14 BLUE B5
74LCX574
OUTC B6 8 13 BLUE B6
OUTC B7 9 12 BLUE B7
U10
U6
EN
1
GND
EN
1
GND
GND: 10
VD: 20
C1
11
GND: 10
VD: 20
C1
11
GND: 10
VD: 20
74LCX574
1D
OUTB A0 2 19 GREEN A0
OUTB A1 3 18 GREEN A1
OUTB A2 4 17 GREEN A2
OUTB A3 5 16 GREEN A3
OUTB A4 6 15 GREEN A4
OUTB A5 7 14 GREEN A5
OUTB A6 8 13 GREEN A6
OUTB A7 9 12 GREEN A7
74LCX574
1D
OUTA A0 2 19 RED A0
OUTA A1 3 18 RED A1
OUTA A2 4 17 RED A2
OUTA A3 5 16 RED A3
OUTA A4 6 15 RED A4
OUTA A5 7 14 RED A5
OUTA A6 8 13 RED A6
OUTA A7 9 12 RED A7
C1
VD: 20
C1
1D
OUTB B0 2 19 GREEN B0
OUTB B1 3 18 GREEN B1
OUTB B2 4 17 GREEN B2
OUTB B3 5 16 GREEN B3
OUTB B4 6 15 GREEN B4
OUTB B5 7 14 GREEN B5
1D
OUTA B0 2 19 RED B0
OUTA B1 3 18 RED B1
OUTA B2 4 17 RED B2
OUTA B3 5 16 RED B3
OUTA B4 6 15 RED B4
OUTA B5 7 14 RED B5
U7
EN
11
1
GND
GND: 10
U9
EN
11
1
GND
74LCX574
OUTB B6 8 13 GREEN B6
OUTB B7 9 12 GREEN B7
74LCX574
OUTA B6 8 13 RED B6
OUTA B7 9 12 RED B7
A_LAT
A [0-7]
A [0-7]
OUTA A [0-7]
OUTB
OUTC
B_LAT
Figure 36. Output Latches Section
–18–
OUTA B [0-7]
B [0-7]
OUTB
B [0-7]
OUTC
REV. A
Page 19
U1
74LCX86
R79
U1
74LCX86
DAC_CLK
8
9
10
A LAT
DR
0V
6
5
4
B LAT
VD : 14
GND : 7
W8
VD : 14
GND : 7
W10
VD
VD
R73
R22
AD9483
J10
SMB
R15
R16
75V
22
U3
C15
VD
VD
C17
C12
C14
0.1mF
19 24 27
23
0.1mF
U4
0.1mF
23 19 24 27
0.1mF
2kV
2kV
DA
12
10
DA
12
10
COMP
COMP
DB1
DB0
COMP
COMP
DB0
DB1
OUT A
I
DB2
DB3
DB4
A0
BLUEA1BLUEA2BLUEA3BLUE
BLUE
J5
SMB
R18
75V
22
OUT A
I
DB2
DB3
DB4
A0
GREENA1GREENA2GREENA3GREEN
GREEN
AD9760
DB5
DB6
A4
AD9760
DB5
DB6
A4
21
OUT B
I
DB7
DB8
123456789
A5
BLUE
BLUEA6BLUE
21
OUT B
I
DB7
DB8
123456789
A5
GREENA6GREEN
GREEN
75V
FSADJ
IO
LO
REF
GND: 20,26
SLEEP
CLK
DB9
A7
R17
75V
FSADJ
IO
LO
REF
GND: 20,26
SLEEP
CLK
DB9
A7
R13
1kV
C16
0.1mF
28 15 16 17 18
R20
1kV
W2
CLK
VD
DAC
R23
1kV
C13
0.1mF
28 15 16 17 18
R11
1kV
W3
CLK
VD
DAC
R78
U1
74LCX86
1
0V
3
A LAT
DR
2
VD : 14
GND : 7
W9
VD
R21
J10
SMB
R24
75V
R14
75V
AD9760
DB4
DB5
DB6
A4
21
DB7
A5
RED
OUT B
I
DB8
REDA6RED
REF
GND: 20,26
CLK
DB9
123456789
A7
FSADJ
IO
LO
SLEEP
28 15 16 17 18
CLK
DAC
C9
VD
W1
R12
1kV
VD VD
0.1mF
R19
1kV
CLOCK LINE TERMINATIONS
VD
22
U2
C10
VD
C11
0.1mF
23 19 24 27
0.1mF
2kV
DA
12
10
COMP
COMP
DB1
DB0
OUT A
I
DB2
DB3
A0
REDA1REDA2REDA3RED
RED
R83
R80
R85
DR
R62
DR
CLK
DAC
R61
R64
150V
150V
150V
150V
150V
150V
Figure 37. DACs and Clock Buffer Section
–19–REV. A
Page 20
AD9483
123456789
DR
GND
BL_A0
BL_A1
BL_A2
BL_A3
BL_A4
BL_A5
123456789
DR
GND
GR_A0
GR_A1
GR_A2
GR_A3
GR_A4
GR_A5
123456789
DR
GND
R_A0
R_A1
R_A2
R_A3
R_A4
R_A5
J4
SMB
R74
DS
SMB
50V
101112131415161718192021222324
DR
GND
BL_A6
BL_A7
101112131415161718192021222324
GND
GR_A6
GR_A7
101112131415161718192021222324
GND
R_A6
R_A7
J3
R75
50V
C8
0.1mF
DS
DR
DR
GND
GND
GND
BL_B0
BL_B1
GR_B0
GR_B1
R_B0
R_B1
U1
74LCX86
BL_B2
GR_B2
R_B2
11
12
BL_B3
BL_B4
GR_B3
GR_B4
R_B3
R_B4
VD: 14
13
BL_B5
BL_B6
GR_B5
GR_B6
R_B5
R_B6
GND: 7
25
GND
BL_B7
25
GND
GR_B7
25
GND
R_B7
EXTRA GATES
P3
CON-DB25HF
P2
CON-DB25HF
P1
CON-DB25HF
P1P2P3P4P5P6P7P8P9
123456789
201918171615141312
P20
P19
P18
P17
P1P2P3P4P5P6P7P8P9
123456789
123456789
P1P2P3P4P5P6P7P8P9
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10
P16
P15
TEST POINT GROUNDS
P10
10
11
P14
P13
P12
P11
P10
10
10
P10
ST1
ST4
U13
P1P2P3P4P5
12345
12345
P1P2P3P4P5
VD
ST6
ST5
R45
R26
100V
GREEN_A0 GR_A0
100V
RED_A0 R_A0
R44
R25
100V
GREEN_A1 GR_A1
100V
RED_A1 R_A1
R46
R27
100V
GREEN_A2 GR_A2
100V
RED_A2 R_A2
R47
R28
100V
GREEN_A3 GR_A3
100V
RED_A3 R_A3
R48
R29
100V
GREEN_A4 GR_A4
100V
RED_A4 R_A4
R43
R30
P1P2P3P4P5P6P7P8P9
123456789
CUSTOMER WORKSPACE
201918171615141312
P20
P19
P18
P17
P1P2P3P4P5P6P7P8P9
123456789
123456789
P1P2P3P4P5P6P7P8P9
R37
BLUE_A0 BL_A0
100V
BLUE_A1 BL_A1
R35
100V
BLUE_A2 BL_A2
R34
100V
BLUE_A3 BL_A3
R33
100V
P16
R38
BLUE_A4 BL_A4
100V
GREEN_A5 GR_A5
100V
RED_A5 R_A5
R42
R31
100V
GREEN_A6 GR_A6
100V
RED_A6 R_A6
R41
R32
NOT INSTALLED
R52
100V
100V
GREEN_A7 GR_A7
GREEN_B0 GR_B0
R68
100V
100V
RED_A7 R_A7
RED_B0 R_B0
R53
R69
100V
GREEN_B1 GR_B1
100V
RED_B1 R_B1
R51
R67
100V
GREEN_B2 GR_B2
100V
RED_B2 R_B2
R50
R66
100V
GREEN_B3 GR_B3
100V
RED_B3 R_B3
R49
R65
100V
GREEN_B4 GR_B4
100V
RED_B4 R_B4
R54
R70
100V
GREEN_B5 GR_B5
100V
RED_B5 R_B5
R55
R71
100V
GREEN_B6 GR_B6
100V
RED_B6 R_B6
R56
R72
100V
GREEN_B7 GR_B7
100V
RED_B7 R_B7
R36
100V
Figure 38. Digital Outputs Connectors and Terminations Section
–20–
P15
100V
BLUE_A5 BL_A5
P14
R39
P13
100V
BLUE_A6 BL_A6
P12
R40
P10
10
11
P11
P10
10
10
P10
100V
BLUE_A7 BL_A7
ST1
ST4
R61
100V
BLUE_B0 BL_B0
U13
P1P2P3P4P5
12345
12345
P1P2P3P4P5
R60
R62
100V
BLUE_B1 BL_B1
100V
BLUE_B2 BL_B2
R63
100V
BLUE_B3 BL_B3
R64
100V
BLUE_B4 BL_B4
R59
ST7
ST8
100V
GND
R58
100V
BLUE_B5 BL_B5
BLUE_B6 BL_B6
REV. A
R57
100V
BLUE_B7 BL_B7
Page 21
VA
C55
C26
C25
C24
C22
C21
C23
C57
C19
C50
C20
10mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
–VA
C65
0.1mF
C62
0.1mF
C61
0.1mF
C60
0.1mF
C63
10mF
VD
C34
0.1mF
C33
0.1mF
C32
0.1mF
C31
0.1mF
C30
0.1mF
BYPASS CAPS
C29
0.1mF
C28
0.1mF
VD
C56
C45
C44
C43
C42
C40
C39
C38
AD9483
16
REF
B
R96
1.3kV
R100
A_LAT
5
2
B
TRIM
500V
R97
4
3
1.5kV
REF
C
DATA_LOCK_OUT
W11
LATCH CLK SOURCE SELECT
10mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
REF
A
R92
A
TRIM
1.3kV
R93
1.5kV
R98
500V
B_LAT
DATA_LOCK_OUT
C
TRIM
C37
C18
0.1mF
R95
1.3kV
R94
1.5kV
C36
0.1mF
C35
0.1mF
C49
10mF
VA
2
REF SOURCE SELECT
0.1mF
6
4
7
AD9483
3
OUT
REF
C41
–VA
0.1mF
W14
C46
0.1mF
3
1
2
C51
10mF
EXT REF A
W15
C47
0.1mF
3
1
2
C53
EXT REF B
R99
500V
C48
0.1mF
3
1
2
W16
10mF
C54
10mF
EXT REF C
C27
C52
AD9483 EXTERNAL
REFERENCES
REF A
REF B
REF C
POWER/DC INPUTS
–VA AD9483 SUPPORT LOGIC – SUPPLY
VA AD9483 ANALOG SUPPLY
–VA AD9483 DIGITAL SUPPLY
–VA AD9483 SUPPORT LOGIC + SUPPLY
EXT
EXT
EXT
1234567
TB1
8
0.1mF
10mF
GND
Figure 39. Power Connector, Decoupling Capacitors, DC Adjust Trimpot Section
–21–REV. A
Page 22
AD9483
PCB LAYOUT
The PCB is designed on a four layer (1 oz. Cu) board. Components and routing are on the top layer with a ground flood for
additional isolation. Test and ground points were judiciously
placed to facilitate high speed probing. Each channel has a
separate 25-pin connector for it’s digital outputs. A common
ground plane exists on the second layer.
The third layer has the 3 split power planes:
1. 5 V analog for the ADC and preamps,
2. 3.3 V (or 5 V) ADC output supply, and
3. A separate 3.3 V supply for support logic. The fourth layer
contains the –5 V plane for the preamps and additional components and routing. There is additional space for two extra components on top of the board to allow for modification.
Table IV. 25-Pin Connector Pinout
Pin No. Pin Name
1 DR (Data Ready)
2 GND
3A0
4A1
5A2
6A3
7A4
8A5
9A6
10 A7
11 GND
12 NC (No Connect)
13 NC (No Connect)
14 DRB (Data Ready Bar)
15 GND
16 B0
17 B1
18 B2
19 B3
20 B4
21 B5
22 B6
23 B7
24 GND
25 NC (No Connect)
–22–
REV. A
Page 23
AD9483
Figure 40. Layer 1. Routing and Top Layer Ground
Figure 41. Layer 2 Ground Plane
–23–REV. A
Page 24
AD9483
Figure 42. Layer 3 Split Power Planes
Figure 43. Layer 4 Routing and Negative 5 V
–24–
REV. A
Page 25
AD9483
EVALUATION BOARD PARTS LIST
# QTY REFDES DEVICE PACKAGE PART NUMBER VALUE SUPPLIER
1 54 C1-17, C19-50, CAPACITOR 0805 C0805C104K5RAC7025 0.1 µF KEMIT
C57, C60-62, C65
2 8 C18, C51-56, C63 CAPACITOR TAJD T491C106K016AS 10 µF KEMIT
3 16 GND1-10, PR1, PART OF PCB OMIT
PR2, PR3, PR4,
PR5, PR6
4 7 J1-4, J8-10 CONNECTOR SMB B51-351-000-220 ITT CANNON
5 3 J5-7 CONNECTOR BNC 227699-2 AMP
6 3 P1-3 CONNECTOR “D” 25 PINS 745783-2 AMP
7 9 R1-3, R14-18, R24 RESISTOR 1206 CRCW120675R0FT 75 Ω DALE
8 9 R4-6, R11-13, RESISTOR 1206 CRCW12061001FT 1K DALE
R19-20, R23
9 4 R7-8, R76-77 RESISTOR 1206 CRCW12063010FT 301 Ω DALE
10 4 R9-10, R74-75 RESISTOR 1206 CRCW120649R9FT 49.9 Ω DALE
11 3 R21-22, R73 RESISTOR 1206 CRCW12062001FT 2K DALE
12 50 R25-72, R101-102 RESISTOR 1206 CRCW12061000FT 100 Ω DALE
13 2 R78-79 RESISTOR 1206 CRCW1206000ZT 0 Ω DALE
14 6 R80-85 RESISTOR 1206 CRCW12061500FT 150 Ω DALE
15 3 R86, R89-90 RESISTOR 1206 CRCW12063600FT 360 Ω DALE
16 3 R87-88, R91 RESISTOR 1206 CRCW12062740FT 274 Ω DALE
17 3 R92, R95-96 RESISTOR 1206 CRCW12061301FT 1.3K DALE
18 3 R93-94, R97 RESISTOR 1206 CRCW12061501FT 1.5K DALE
19 3 R98-100 TRIMMER VRES 3296W001501 500 Ω BOURNES
20 2 R103-105 RESISTOR 1206 CRCW12062000F 200 Ω DALE
21 4 ST1-4 PART OF PCB STRIP10 NOT INSTALLED
22 4 ST5-8 PART OF PCB STRIP5 NOT INSTALLED
23 1 TB1 POWER
CONNECTOR TB8A 95F6002 WIELAND
(2 PIECE) 50F3583
24 3 TP1-3 PART OF PCB TSTPT NOT INSTALLED
25 1 U1 MC74LCX86D SO14NB MC74LCX86D MOTOROLA
26 3 U2-4 AD9760AR SO28WB AD9760AR ADI
27 1 U5 AD9483KS-140/100 MQFP-100 AD9483KS-140/100 ADI
28 6 U6-11 MC74LCX574DW SO20WB MC74LCX574DW MOTOROLA
29 4 U12, U14-16 AD8055AN SO8NB AD8055AN ADI
30 2 U13, U17 DIP20 DIP20 NOT INSTALLED
31 6 W1-3, W8-10 2 PIN JUMPER JMP-2P SEE NOTE
32 11 W4-7, W12-18 3 PIN JUMPER JMP-3P SEE NOTE
33 1 W11 6 PIN JUMPER JMP_6 SEE NOTE
34 5 FEET SJ-5518 3M
NOTES
All resistors are surface mount (size 1206) and have a 1% tolerance.
Jumpers are Samtec parts TSW-110-08-G-D and TSW-110-08-G-S.
Jumpers W1, W2, W3, W9, W8, W10 are omitted.
–25–REV. A
Page 26
AD9483
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead Plastic Quad Flatpack
(S-100B)
0.921 (23.4)
0.906 (23.0)
0.791 (20.10)
0.783 (19.90)
0.742 (18.85) TYP
80
81
51
50
51
50
CONDUCTIVE HEAT SINK
ON BOTTOM OF PACKAGE
80
81
C3268a–1–12/98
30
0.004
(0.10)
MAX
31
0.555 (14.10)
0.547 (13.90)
0.685 (17.4)
0.669 (17.0)
0.110 (2.80)
0.102 (2.60)
0.010
(0.25)
MIN
BOTTOM
VIEW
(PINS UP)
31
30
0.433 (11.0)
0.787 (20.0)
0.362
(9.2)
100
1
0.486
(12.35)
TYP
PIN 1
100
1
0.134
(3.40)
MAX
0.041 (1.03)
0.031 (0.78)
NOTE: THE AD9483KS PACKAGE USES A COPPER INSERT TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION
OVER THE FULL 08C TO +858C TEMPERATURE RANGE. THIS COPPER INSERT IS EXPOSED ON THE UNDERSIDE OF THE
DEVICE. IT IS RECOMMENDED THAT DURING THE DESIGN OF THE PC BOARD NO THROUGHHOLES OR SIGNAL TRACES BE
PLACED UNDER THE AD9483 THAT COULD COME IN CONTACT WITH THE COPPER INSERT. COMMONLY ACCEPTED BOARD
LAYOUT PRACTICES FOR HIGH SPEED CONVERTERS SPECIFY THAT ONLY GROUND PLANES SHALL BE LOCATED UNDER
THESE DEVICES TO MINIMIZE NOISE OR DISTORTION OF VIDEO SIGNALS.
0.029 (0.73)
0.023 (0.57)
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.015 (0.35)
0.009 (0.25)
0.551
(14.0)
PIN 1
–26–
PRINTED IN U.S.A.
REV. A
Loading...