Datasheet AD9446 Datasheet (ANALOG DEVICES)

www.BDTIC.com/ADI

16-Bit, 80/100 MSPS ADC

FEATURES

100 MSPS guaranteed sampling rate (AD9446-100)

83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS)

82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS)
89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS)
95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS)
60 fsec rms jitter
Excellent linearity

DNL = ±0.4 LSB typical
INL = ±3.0 LSB typical

2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available

3.3 V and 5 V supply operation

APPLICATIONS

MRI receivers
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation

GENERAL DESCRIPTION

The AD9446 is a 16-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit. It is
optimized for performance, small size, and ease of use. The
product operates up to a 100 MSPS, providing superior SNR for
instrumentation, medical imaging, and radar receivers
employing baseband (<100 MHz) IF frequencies.

The ADC requires 3.3 V and 5.0 V power supplies and a low
v

oltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.

AD9446

FUNCTIONAL BLOCK DIAGRAM

AGND DRGND DRVDD

AVDD1 AVDD2

2

32

2

DFS
DCS MODE
OUTPUT MODE
OR

D15 TO D0

DCO

AD9446

VIN+
VIN–

CLK+
CLK–

BUFFER

CLOCK

AND TIMING

MANAGEMENT

T/H

PIPELINE

VREF

ADC

REF

Figure 1.

16

CMOS

OR

LVDS

OUTPUT

STAGING

REFBSENSE REFT

Optional features allow users to implement various selectable
op

erating conditions, including input range, data format select,

and output data mode.

The AD9446 is available in a Pb-free, 100-lead, surface-mount,

lastic package (100-lead TQFP/EP) specified over the

p
industrial temperature range −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. True 16-bit linearity.

2. H

igh performance: outstanding SNR performance for
baseband IFs in data acquisition, instrumentation,
magnetic resonance imaging, and radar receivers.

ase of use: on-chip reference and high input impedance

3. E

track-and-hold with adjustable analog input range and an
output clock simplifies data capture.

ackaged in a Pb-free, 100-lead TQFP/EP package.

4. P

5. C

lock duty cycle stabilizer (DCS) maintains overall ADC

performance over a wide range of clock pulse widths.

6. O

R (out-of-range) outputs indicate when the signal is

beyond the selected input range.

05490-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD9446

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Te r mi n ol o g y .......................................................................................9

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ......................... 10

Equivalent Circuits......................................................................... 15

Typical Perf or m an c e Chara c t e ristic s ........................................... 16

Theory of Operation ...................................................................... 24

Analog Input and Reference Overview ................................... 24

Clock Input Considerations...................................................... 26

Power Considerations ................................................................ 27

Digital Outputs........................................................................... 27

Timing ......................................................................................... 27

Operational Mode Selection ..................................................... 28

Evaluation Board ............................................................................ 29

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9446

www.BDTIC.com/ADI

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), A

Table 1.

AD9446BSVZ-80 AD9446BSVZ-100
Parameter Te mp Min Typ Max Min Typ Max Unit

RESOLUTION Full 16 16 Bits
ACCURACY

No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −5 ±0.1 +5 −5 ±0.1 +5 mV
Gain Error Full −3 ±0.6 +3 −3 ±0.5 +3 % FSR
25°C −2 ±0.3 +2 −2 ±0.3 +2 % FSR
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)1 25°C −5 ±3.0 +5 −6 ±3.0 +6 LSB

VOLTAGE REFERENCE

Output Voltage

1

VREF = 1.6 V (3.2 V p-p Analog Input Range) Full 1.6 1.6 V
Load Regulation @ 1.0 mA Full ±2 ±2 mV
Reference Input Current (External 1.6 V Reference) Full µA

INPUT REFERRED NOISE 25°C 1.5 1.9 LSB rms
ANALOG INPUT

Input Span

VREF = 1.6 V Full 3.2 3.2 V p-p

VREF = 1.0 V (External) Full 2.0 2.0 V p-p
Internal Input Common-Mode Voltage Full 3.5 3.5 V
External Input Common-Mode Voltage Full 3.2 3.8 3.2 3.8 V
Input Resistance
Input Capacitance

2

2

POWER SUPPLIES

Supply Voltage

AVDD1 Full 3.14 3.3 3.46 3.14 3.3 3.46 V

AVDD2 Full 4.75 5.0 5.25 4.75 5.0 5.25 V

DRVDD—LVDS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V

DRVDD—CMOS Outputs Full 3.0 3.3 3.6 3.0 3.3 3.6 V
Supply Current

1

I

AVDD

1

I

AVDD2

1

I

—LVDS Outputs Full 68 75 69 75 mA

DRVDD

1

I

—CMOS Outputs Full 14 14 mA

DRVDD

PSRR

Offset Full 1 1 mV/V

Gain Full 0.2 0.2 %/V

POWER CONSUMPTION

LVDS Outputs Full 2.4 2.6 2.6 2.8 W
CMOS Outputs (DC Input) Full 2.2 2.3 W

1

Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and

approximately 5 pF loading on each output bit for CMOS output mode.

2

Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.

= −1.0 dBFS, DCS on, unless otherwise noted.

IN

1

Full −0.75 ±0.4 +0.75 −0.85 ±0.4 +0.85 LSB

Full 1 1 kΩ
Full 6 6 pF

Full 335 365 368 401 mA
Full 204 234 223 255 mA

Rev. 0 | Page 3 of 36

AD9446

www.BDTIC.com/ADI

AC SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), A

Table 2.

AD9446BSVZ-80 AD9446BSVZ-100
Parameter Te m p Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 10 MHz 25°C 79.6 81.8 78.4 79.7 dB
fIN = 30 MHz 25°C 80.5 81.6 78.3 79.5 dB
Full 79.2 77.9 dB
fIN = 70 MHz 25°C 79.0 80.6 77.7 79.0 dB
Full 78.2 77.6 dB
fIN = 92 MHz 25°C 80.1 78.9 dB
fIN = 125 MHz 25°C 78.8 78.2 dB
fIN = 170 MHz 25°C 77.1 77.0 dB

fIN = 10 MHz (2 V p-p Input) 25°C 78.3 76.6 dB
fIN = 30 MHz (2 V p-p Input) 25°C 78.3 76.6 dB
fIN = 70 MHz (2 V p-p Input) 25°C 77.6 76.2 dB
fIN = 92 MHz (2 V p-p Input) 25°C 77.5 76 dB
fIN = 125 MHz (2 V p-p Input) 25°C 76.7 75.6 dB
fIN = 170 MHz (2 V p-p Input) 25°C 75.5 75.1 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 10 MHz 25°C 77.1 80.5 76.9 78.9 dB
fIN = 30 MHz 25°C 75.9 80.4 75.5 78.6 dB
Full 74.9 71.7 dB
fIN = 70 MHz 25°C 75.5 78.6 73.8 77.7 dB
Full 74.4 69.1 dB
fIN = 92 MHz 25°C 79.2 77.1 dB
fIN = 125 MHz 25°C 74.9 76.9 dB
fIN = 170 MHz 25°C 66.0 70.5 dB

fIN = 10 MHz (2 V p-p Input) 25°C 77.9 76.2 dB
fIN = 30 MHz (2 V p-p Input) 25°C 77.8 76.1 dB
fIN = 70 MHz (2 V p-p Input) 25°C 77.1 75.9 dB
fIN = 92 MHz (2 V p-p Input) 25°C 77.1 75.7 dB
fIN = 125 MHz (2 V p-p Input) 25°C 75.7 75.3 dB
fIN = 170 MHz (2 V p-p Input) 25°C 72.5 73.6 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 10 MHz 25°C 13.2 13.0 Bits
fIN = 30 MHz 25°C 13.2 12.9 Bits
fIN = 70 MHz 25°C 12.9 12.8 Bits
fIN = 92 MHz 25°C 13.0 12.7 Bits
fIN = 125 MHz 25°C 12.3 12.6 Bits
fIN = 170 MHz 25°C 10.8 11.6 Bits

= −1 dBFS, DCS on, unless otherwise noted.

IN

Rev. 0 | Page 4 of 36

AD9446

www.BDTIC.com/ADI

AD9446BSVZ-80 AD9446BSVZ-100
Parameter Te m p Min Typ Max Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE

(SFDR, Second or Third Harmonic)
fIN = 10 MHz 25°C 82 90 82 92 dBc
fIN = 30 MHz 25°C 82 89 82 89 dBc
Full 80 79 dBc
fIN = 70 MHz 25°C 80 87 81 89 dBc
Full 79 77 dBc
fIN = 92 MHz 25°C 84 84 dBc
fIN = 125 MHz 25°C 80 83 dBc
fIN = 170 MHz 25°C 66 74 dBc

fIN = 10 MHz (2 V p-p Input) 25°C 92 94 dBc
fIN = 30 MHz (2 V p-p Input) 25°C 93 92 dBc
fIN = 70 MHz (2 V p-p Input) 25°C 92 92 dBc
fIN = 92 MHz (2 V p-p Input) 25°C 90 89 dBc
fIN = 125 MHz (2 V p-p Input) 25°C 85 87 dBc
fIN = 170 MHz (2 V p-p Input) 25°C 77 82 dBc

WORST SPUR EXCLUDING SECOND OR

THIRD HARMONICS
fIN = 10 MHz 25°C −98 −89 −96 −91 dBc
fIN = 30 MHz 25°C −97 −89 −97 −89 dBc
Full −89 −87 dBc
fIN = 70 MHz 25°C −98 −90 −96 −90 dBc
Full −89 −88 dBc
fIN = 92 MHz 25°C −98 −95 dBc
fIN = 125 MHz 25°C −96 −96 dBc
fIN = 170 MHz 25°C −95 −92 dBc

fIN = 10 MHz (2 V p-p Input) 25°C −97 −93 dBc
fIN = 30 MHz (2 V p-p Input) 25°C −97 −96 dBc
fIN = 70 MHz (2 V p-p Input) 25°C −94 −94 dBc
fIN = 92 MHz (2 V p-p Input) 25°C −97 −99 dBc
fIN = 125 MHz (2 V p-p Input) 25°C −97 −95 dBc
fIN = 170 MHz (2 V p-p Input) 25°C −93 −95 dBc

TWO-TONE SFDR

fIN = 10.8 MHz @ −7 dBFS,

9.8 MHz @ −7 dBFS

fIN = 70.3 MHz @ −7 dBFS,

69.3 MHz @ −7 dBFS

ANALOG BANDWIDTH Full 325 540 MHz

25°C 96 95 dBFS

25°C 92 92 dBFS

Rev. 0 | Page 5 of 36

AD9446

www.BDTIC.com/ADI

DIGITAL SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R

Table 3.

AD9446BSVZ-80 AD9446BSVZ-100
Parameter Te mp Min Typ Max Min Typ Max Unit

CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)

High Level Input Voltage Full 2.0 2.0 V
Low Level Input Voltage Full 0.8 0.8 V
High Level Input Current Full 200 200 µA
Low Level Input Current Full −10
Input Capacitance Full

DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)

DRVDD = 3.3 V

High Level Output Voltage Full 3.25
Low Level Output Voltage Full

DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR)

VOD Differential Output Voltage

2

VOS Output Offset Voltage Full 1.125

CLOCK INPUTS (CLK+, CLK−)

Differential Input Voltage Full 0.2
Common-Mode Voltage Full 1.3 1.5 1.6 1.3 1.5 1.6 V
Input Resistance Full 1.1 1.4 1.7 1.1 1.4 1.7 kΩ
Input Capacitance Full

1

Output voltage levels measured with 5 pF load on each output.

2

LVDS R

TERM

= 100 Ω.

= 3.74 kΩ, unless otherwise noted.

LVD S_ BI AS

1

Full 247

2

+10 −10 +10 µA

0.2 0.2 V

2

545 247 545 mV

1.375 1.125 1.375 V

2 pF

3.25 V

0.2 V

2 pF

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9446BSVZ-80 AD9446BSVZ-100
Parameter Te mp Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full 80 100 MSPS
Minimum Conversion Rate Full 1 1 MSPS
CLK Period Full 12.5 10 ns
CLK Pulse Width High1 (t
CLK Pulse Width Low1 (t

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns
Output Propagation Delay—LVDS (tPD)3 (Dx+), (t
Pipeline Delay (Latency) Full 13 13 Cycles
Aperture Delay (tA) Full ns
Aperture Uncertainty (Jitter, tJ) Full 60 60

1

With duty cycle stabilizer (DCS) enabled.

2

Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.

3

LVDS R

= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

TERM

) Full 5.0 4.0 ns

CLKH

) Full 5.0 4.0 ns

CLKL

)3 (DCO+) Full 2.1 3.6 4.8 2.3 3.6 4.8 ns

CPD

fsec

s

rm

Rev. 0 | Page 6 of 36

AD9446

www.BDTIC.com/ADI

TIMING DIAGRAMS

A

CLK+

CLK–

N–1

IN

t

CLKH

t

CLKL

N

N + 1

1/

f

S

t

PD

DATA OUT

DCO+

DCO–

VIN

CLK–

CLK+

DX

DCO+

DCO–

N–1

t

CLKH

N + 1

05490-002

t

CPD

N – 13

13 CLOCK CYCLES

N–12

N

Figure 2. LVDS Mode Timing Diagram

N

N + 1

t

CLKL

t

PD

N – 13 N – 12 N – 1 N

N + 2

13 CLOCK CYCLES

05490-003

Figure 3. CMOS T

iming Diagram

Rev. 0 | Page 7 of 36

AD9446

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ABSOLUTE MAXIMUM RATINGS

Table 5.

With

t

Respec

Parameter

ELECTRICAL

AVDD1 AGND −0.3 V to +4 V
AVDD2 AGND −0.3 V to +6 V
DRVDD DGND −0.3 V to +4 V
AGND DGND −0.3 V to +0.3 V
AVDD1 DRVDD −4 V to +4 V
AVDD2 DRVDD −4 V to +6 V
AVDD2 AVDD1 −4 V to +6 V
D0± to D15± DGND –0.3 V to DRVDD + 0.3 V
CLK+/CLK− AGND –0.3 V to AVDD1 + 0.3 V
OUTPUT MODE,

DCS MODE, DFS
VIN+, VIN− AGND –0.3 V to AVDD2 + 0.3 V
VREF AGND –0.3 V to AVDD1 + 0.3 V
SENSE AGND –0.3 V to AVDD1 + 0.3 V
REFT, REFB AGND –0.3 V to AVDD1 + 0.3 V

ENVIRONMENTAL

Storage Temperature

Range
Operating Temperature

Range
Lead Temperature

(Soldering 10 sec)
Junction Temperature 150°C

to

AGND –0.3 V to AVDD1 + 0.3 V

–65°C to +125°C

–40°C to +85°C

300°C

Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The heat sink of the AD9446 package must be soldered to
ground.

Table 6.

Package Type θ

100-lead TQFP/EP 19.8 8.3 2 °C/W

JA

Typical θJA = 19.8°C/W (heat sink soldered) for multilayer
board in still air.

Typical θ

= 8.3°C/W (heat sink soldered) for multilayer board

JB

in still air.

Typical θ

= 2°C/W (junction to exposed heat sink) represents

JC

the thermal resistance through heat sink path.

Airflow increases heat dissipation, effectively reducing θ
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θ

. It is required that the exposed heat sink be soldered to

JA

the ground plane.

θ

JB

θ

JC

Unit

. Also,

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 36

AD9446

www.BDTIC.com/ADI

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the

undamental frequency (as determined by the FFT analysis) is

f
reduced by 3 dB.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.

Aperture Delay (t

The delay between the 50% point of the rising edge of the clock

nd the instant at which the analog input is sampled.

a

Aperture Uncertainty (Jitter, t

The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the

lock pulse should be left in the Logic 1 state to achieve rated

c
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

part. DNL is the deviation from this ideal value. Guaranteed

a
no missing codes to 16-bit resolution indicates that all 65,536
codes must be present over all operating ranges.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given

put frequency can be calculated directly from its measured

in
SINAD using the following formula:

ENOB

Gain Error

The first code transition should occur at an analog value of
½ LSB above negative full scale. The last transition should occur
at an analog value of 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

)

A

)

J

()

SINAD

=

1.76−

6.02

Offset Error

The major carry transition should occur for an analog value of
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the clock rising edge and the time when all
bits are within valid logic levels.

Power-Supply Rejection Ratio

The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.

Signal-to-Noise and Distortion (SINAD)

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may be a harmonic. SFDR can be reported in dBc (that is, degrades
as signal level is lowered) or dBFS (always related back to converter
full scale).

Tem p er at u re Dr i ft

The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T

or T

MIN

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.

Two -Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.

MAX

.

Rev. 0 | Page 9 of 36

AD9446

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AGND99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89OR–88DRVDD87DRGND86D15+ (MSB)85D15–84D14+83D14–82D13+81D13–80D12+79D12–78D11+77D11–76DRVDD

100

DNC

DFS

AVDD1
SENSE

VREF

AGND

REFT

REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1

AGND

VIN+
VIN–

AGND

AVDD2

1
2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DCS MODE

OUTPUT MODE

LVDS_BIAS

DNC = DO NOT CONNECT

PIN 1

AD9446

LVDS MODE

TOP VIEW

(Not to Scale)

26

AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1

39

40

AGND

41

CLK+

42

CLK–

AGND

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

43

AVDD144AVDD145AVDD1

46

47

AGND

48

DRVDD

DRGND

75

DRGND

74

D10+

73

D10–

72

D9+

71

D9–

70

D8+

69

D8–

68

DCO+

67

DCO–

66

D7+

65

D7–

64

DRVDD

63

DRGND

62

D6+

61

D6–

60

D5+

59

D5–

58

D4+

57

D4–

56

D3+

55

D3–

54

D2+

53

D2–

52

D1+

51

D1–

49

50

D0+

D0– (LSB)

05490-004

Rev. 0 | Page 10 of 36

AD9446

www.BDTIC.com/ADI

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode

Pin No. Mnemonic Description

1 DCS MODE

2 DNC Do Not Connect. These pins should float.
3

4 DFS

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36, 38,

43 to 45, 92 to 97
7 SENSE

8 VREF

9, 21, 24, 39, 42, 46, 91, 98,
99, 100, Exposed Heat Sink

10 REFT

11 REFB

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).
22 VIN+ Analog Input—True.
23 VIN− Analog Input—Complement.
40 CLK+ Clock Input—True.
41 CLK− Clock Input—Complement.
47, 63, 75, 87, DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
49 D0− (LSB) D0 Complement Output Bit (LVDS Levels).
50 D0+ D0 True Output Bit.
51 D1− D1 Complement Output Bit.
52 D1+ D1 True Output Bit.
53 D2− D2 Complement Output Bit.
54 D2+ D2 True Output Bit.
55 D3− D3 Complement Output Bit.
56 D3+ D3 True Output Bit.
57 D4− D4 Complement Output Bit.
58 D4+ D4 True Output Bit.
59 D5− D5 Complement Output Bit.
60 D5+ D5 True Output Bit.
61 D6− D6 Complement Output Bit.
62 D6+ D6 True Output Bit.
65 D7− D7 Complement Output Bit.
66 D7+ D7 True Output Bit.
67 DCO− Data Clock Output—Complement.
68 DCO+ Data Clock Output—True.
69 D8− D8 Complement Output Bit.
70 D8+ D8 True Output Bit.
71 D9− D9 Complement Output Bit.
72 D9+ D9 True Output Bit.
73 D10− D10 Complement Output Bit.
74 D10+ D10 True Output Bit.
77 D11− D11 Complement Output Bit.
78 D11+ D11 True Output Bit.

OUTPUT
MODE

AVDD1 3.3 V (±5%) Analog Supply.

AGND

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable

ecommended); DCS = high (AVDD1) to disable DCS.

DCS (r

CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE

Data Format Select Pin. CMOS control pin that det
high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

Reference Mode Selection. Connect to AGND for internal 1.6 V reference (3.2 V p-p analog

ange); connect to AVDD1 for external reference.

input r

1.6 V Reference I/O. Function dependent on SENSE and ex
Decouple to ground with 0.1 µF and 10 µF capacitors.

Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AG

ND.

Differential Reference Output. Decoupled to ground with 0.1 µF
with 0.1 µF and 10 µF capacitors.

Differential Reference Output. Decoupled to ground with a 0.1 µ
(Pin 10) with 0.1 µF and 10 µF capacitors.

= 1 (AVDD1) for LVDS outputs.

ermines the format of the output data. DFS =

ternal programming resistors.

capacitor and to REFB (Pin 11)

F capacitor and to REFT

Rev. 0 | Page 11 of 36

AD9446

www.BDTIC.com/ADI

Pin No. Mnemonic Description

79 D12− D12 Complement Output Bit.
80 D12+ D12 True Output Bit.
81 D13− D13 Complement Output Bit
82 D13+ D13 True Output Bit.
83 D14− D14 Complement Output Bit
84 D14+ D14 True Output Bit.
85 D15− D15 Complement Output Bit.
86 D15+ (MSB) D15 True Output Bit.
89 OR− Out-of-Range Complement Output Bit.
90 OR+ Out-of-Range True Output Bit.

Rev. 0 | Page 12 of 36

AD9446

www.BDTIC.com/ADI

AGND99AGND98AGND97AVDD196AVDD195AVDD194AVDD193AVDD192AVDD191AGND90OR+89D15+ (MSB)88DRVDD87DRGND86D14+85D13+84D12+83D11+82D10+81D9+80D8+79D7+78D6+77D5+76DRVDD

100

DNC

DFS

AVDD1
SENSE

VREF

AGND

REFT

REFB
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1

AGND

VIN+
VIN–

AGND

AVDD2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DCS MODE

OUTPUT MODE

LVDS_BIAS

DNC = DO NOT CONNECT

PIN 1

AD9446

CMOS MODE

TOP VIEW

(Not to Scale)

26

AVDD227AVDD228AVDD229AVDD230AVDD231AVDD232AVDD133AVDD134AVDD135AVDD236AVDD137AVDD238AVDD1

Figure 5. 100-Lead TQFP/EP Pin C

onfiguration in CMOS Mode

39

40

AGND

41

CLK+

42

CLK–

43

AGND

AVDD144AVDD145AVDD1

46

47

AGND

48

DRVDD

DRGND

49

DNC50DNC

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DRGND
D4+
D3+
D2+
D1+
D0+ (LSB)
DNC
DCO+
DCO–
DNC
DNC
DRVDD
DRGND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC

05490-005

Rev. 0 | Page 13 of 36

AD9446

www.BDTIC.com/ADI

Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode

Pin No. Mnemonic Description

1 DCS MODE

2, 49 to 62, 65 to 66, 69, DNC Do Not Connect. These pins should float.
3 OUTPUT MODE

4 DFS

5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
6, 18 to 20, 32 to 34, 36,

38, 43 to 45, 92 to 97
7 SENSE

8 VREF

9, 21, 24, 39, 42, 46, 91, 98,
99, 100, Exposed Heat
Sink

10 REFT

11 REFB

12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%).
22 VIN+ Analog Input—True.
23 VIN− Analog Input—Complement.
40 CLK+ Clock Input—True.
41 CLK− Clock Input—Complement.
47, 63, 75, 87, DRGND Digital Output Ground.
48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
67 DCO− Data Clock Output—Complement.
68 DCO+ Data Clock Output—True.
70 D0+ (LSB) D0 True Output Bit (CMOS levels).
71 D1+ D1 True Output Bit.
72 D2+ D2 True Output Bit.
73 D3+ D3 True Output Bit.
74 D4+ D4 True Output Bit.
77 D5+ D5 True Output Bit.
78 D6+ D6 True Output Bit.
79 D7+ D7 True Output Bit.
80 D8+ D8 True Output Bit.
81 D9+ D9 True Output Bit.
82 D10+ D10 True Output Bit.
83 D11+ D11 True Output Bit.
84 D12+ D12 True Output Bit.
85 D13+ D13 True Output Bit.
86 D14+ D14 True Output Bit.
89 D15+ (MSB) D15 True Output Bit.
90 OR+ Out-of-Range True Output Bit.

AVDD1 3.3 V (±5%) Analog Supply.

AGND

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to
enable DCS (r

CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE

Data Format Select Pin. CMOS control pin tha
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.

Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1

r external reference.

fo

1.6 V Reference I/O. Function dependent on SENSE and external programming resistors.
couple to ground with 0.1 µF and 10 µF capacitors.

De
Analog Ground. The exposed heat sink on the bottom of the package must be connected to

AGND.

Differential Reference Output. Decoupled to ground with
with 0.1 µF and 10 µF capacitors.

Differential Reference Output. Decoupled to ground with a 0.1 µF capacitor and to REFT (Pin 10)
with 0.1 µF and 10 µF capacitor

ecommended); DCS = high (AVDD1) to disable DCS.

= 1 (AVDD1) for LVDS outputs.

t determines the format of the output data.

0.1 µF capacitor and to REFB (Pin 11)

s.

Rev. 0 | Page 14 of 36

AD9446

www.BDTIC.com/ADI

EQUIVALENT CIRCUITS

AVDD2

VIN+

VIN–

3.5V

6pF

6pF

X1

AVDD2

1k

Ω

1k

Ω

Figure 6. Equivalent Analog Input Circuit

DRVDD DRVDD

1.2V

LVDSBIAS

3.74k

Ω

I

LVDSOUT

Figure 7. Equivalent LVDS_BIAS Circuit

T/H

DRVDD

DX

05490-006

05490-009

Figure 9. Equivalent CMOS Digital Output Circuit

VDD

K

05490-007

DCS MODE,

OUTPUT MODE,

DFS

30kΩ

05490-010

Figure 10. Equivalent Digital Input Circuit,

DFS, DCS MO

DE, OUTPUT MODE

DRVDD

V

DX– DX+

V

Figure 8. Equivalent LVDS Dig

V

V

05490-008

ital Output Circuit

Rev. 0 | Page 15 of 36

CLK+

AVDD2

3k

2.5k

Ω

Ω

3k

Ω

Figure 11. Equivalent Sample Clock Input Circuit

2.5k

CLK–

Ω

05490-011

AD9446

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 3.2 V p-p differential
input, AIN = −1dBFS, internal trimmed reference (nominal VREF = 1.6 V), unless otherwise noted.

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 50.0

12.5 25.0 37.5
FREQUENCY (MHz)

100MSPS

10.3MHz @ –1.0dBFS
SNR = 79.7dB
ENOB = 13.1BITS
SFDR = 90dBc

Figure 12. AD9446-100 64k Point Single-Tone FFT/100 MSPS/10.3 MHz

05490-012

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100

–110
–120
–130

0 50.0

12.5 25.0 37.5
FREQUENCY (MHz)

100MSPS

92.16MHz @ –1.0dBFS
SNR = 78.9dB
ENOB = 12.7BITS
SFDR = 84dBc

Figure 15. AD9446-100 64k Point Single-Tone FFT/100 MSPS/92.16 MHz

05490-015

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 50.0

12.5 25.0 37.5
FREQUENCY (MHz)

100MSPS

30.3MHz @ –1.0dBFS
SNR = 79.5dB
ENOB = 12.9BITS
SFDR = 90dBc

Figure 13. AD9446-100 64k Point Single-Tone FFT/100 MSPS/30.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90

–100
–110
–120
–130

0 50.0

12.5 25.0 37.5
FREQUENCY (MHz)

100MSPS

70.3MHz @ –1.0dBFS
SNR = 79.0dB
ENOB = 12.9BITS
SFDR = 86dBc

Figure 14. AD9446-100 64k Point Single-Tone FFT/100 MSPS/70.3 MHz

05490-013

05490-014

0.6

0.4

0.2

0

–0.2

DNL ERROR (MSB)

–0.4

–0.6

0

0 655368192 16384 24576 32768 40960 49152 57344

Figure 16. AD9446-100 DNL Error vs. O

4

3

2

1

0

–1

INL ERROR (MSB)

–2

–3

–4

0 655368192 16384 24576 32768 40960 49152 57344

0

Figure 17. AD9446-100 INL Error vs. O

OUTPUT CODE

utput Code, 100 MSPS, 10.3 MHz

OUTPUT CODE

utput Code, 100 MSPS, 10.3 MHz

05490-016

05490-017

Rev. 0 | Page 16 of 36

AD9446

www.BDTIC.com/ADI

AMPLITUDE (dBFS)

–10
–20
–30
–40
–50
–60
–70
–80

–90
–100
–110
–120
–130

0

0

12.5 25.0 37.5
FREQUENCY (MHz)

80MSPS

10.3MHz @ –1.0dBFS
SNR = 81.8dB
ENOB = 13.2BITS
SFDR = 90dBc

Figure 18. AD9446-80 64k Point Single-Tone FFT/80 MSPS/10.3 MHz

05490-018

AMPLITUDE (dBFS)

–10
–20
–30
–40
–50
–60
–70
–80

–90
–100
–110
–120
–130

0

0

12.5 25.0 37.5
FREQUENCY (MHz)

80MSPS

100.3MHz @ –1.0dBFS
SNR = 79.5dB
ENOB = 12.7BITS
SFDR = 92dBc

Figure 21. AD9446-80 64k Point Single-Tone FFT/80 MSPS/100.3 MHz

05490-021

0

80MSPS

–10

30.3MHz @ –1.0dBFS
SNR = 81.6dB

–20

ENOB = 13.2BITS
SFDR = 89dBc

–30
–40
–50
–60
–70
–80

AMPLITUDE (dBFS)

–90
–100
–110
–120
–130

0

12.5 25.0 37.5
FREQUENCY (MHz)

Figure 19. AD9446-80 64k Point Single-Tone FFT/80 MSPS/30.3 MHz

AMPLITUDE (dBFS)

–10
–20
–30
–40
–50
–60
–70
–80

–90
–100
–110
–120
–130

0

0

12.5 25.0 37.5
FREQUENCY (MHz)

80MSPS

70.3MHz @ –1.0dBFS
SNR = 80.6dB
ENOB = 12.9BITS
SFDR = 85dBc

Figure 20. AD9446-80 64k Point Single-Tone FFT/80 MSPS/70.3 MHz

05490-019

05490-020

0.6

0.4

0.2

0

–0.2

DNL ERROR (MSB)

–0.4

–0.6

0 655368192 16384 24576 32768 40960 49152 57344

0

Figure 22. AD9446-80 DNL Error vs. Ou

4

3

2

1

0

–1

INL ERROR (MSB)

–2

–3

–4

0 655368192 16384 24576 32768 40960 49152 57344

0

OUTPUT CODE

tput Code, 80 MSPS, 10.3 MHz

OUTPUT CODE

Figure 23. AD9446-80 INL Error vs. Output Code, 80 MSPS, 10.3 MHz

05490-022

05490-023

Rev. 0 | Page 17 of 36

AD9446

www.BDTIC.com/ADI

95

90

85

SFDR (dBc) –40°C

SFDR (dBc) +85°C

SFDR (dBc) +25°C

95

90

85

SFDR (dBc) +85°C

SFDR (dBc) +25°C

SFDR (dBc) –40°C

(dB)

Figure 24. AD9446-100 SNR/SFDR vs. Analog Input

(dB)

SNR (dB) +25°C

80

75

70

0 180

20 40 60 80 100 120 140 160

ANALOG INPUT FREQUENCY (MHz)

SNR (dB) –40°C

SNR (dB) +85°C

Frequency, 100 MSPS, 3.2 V p-p

95

SFDR (dBc) +85°C

90

85

80

75

70

0 180

SFDR (dBc) +25°C

SFDR (dBc) –40°C

SNR (dB) +25°C

20 40 60 80 100 120 140 160

ANALOG INPUT FREQUENCY (MHz)

SNR (dB) –40°C

SNR (dB) +85°C

Figure 25. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS,

3.2 V p-p, CMOS

Output Mode

05490-024

05490-025

(dB)

80

SNR (dB) +25°C

75

70

0 180

20 40 60 80 100 120 140 160

Figure 27. AD9446-100 SNR/SFDR vs. Analog Input

86

85

84

83

82

(dB)

81

80

79

78

77

1.8 4.2

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

SNR (dB) –40°C

SNR (dB) +85°C

ANALOG INPUT FREQUENCY (MHz)

Frequency, 100 MSPS, 2.0 V p-p

80M SNR dBFS

100M SNR dBFS

ANALOG INPUT RANGE (V p-p)

Figure 28. AD9446-100 SNR vs. Input Range, 30.3 MHz, −30 dBFS

05490-027

05490-039

120

100

80

60

(dB)

40

20

0

–100 0

SFDR dBFS

SNR dBFS

SFDR dBc

SNR dB

–90 –80 –70 –60 –50 –40 –30 –20 –10

ANALOG INPUT AMPLITUDE (dB)

05490-026

Figure 26. AD9446-100 SNR/SFDR vs. Analog Input Level, 100 MSPS

Rev. 0 | Page 18 of 36

130

110

90

70

(dB)

50

30

10

0
–100 0

SFDR dBFS

SNR dBFS

SFDR dBc

SNR dB

–90 –80 –70 –60 –50 –40 –30 –20 –10

ANALOG INPUT AMPLITUDE (dB)

Figure 29. AD9446-100 SNR/SFDR vs. Analog Input Level, 100 MSPS,

CMOS Output Mod

e

05490-029

AD9446

www.BDTIC.com/ADI

(dB)

95

90

85

80

75

70

SFDR (dBc) +85°C

SFDR (dBc) –40°C

SFDR (dBc) +25°C

SNR (dB) –40°C

SNR (dB) +85°C

SNR (dB) +25°C

(dB)

95

90

SFDR (dBc) +25°C

85

SNR (dB) –40°C

80

75

SNR (dB) +25°C

70

SFDR (dBc) –40°C

SFDR (dBc) +85°C

SNR (dB) +85°C

65

60

0 180

20 40 60 80 100 120 140 160

ANALOG INPUT FREQUENCY (MHz)

05490-030

Figure 30. AD9446-80 SNR/SFDR vs. Analog Input Frequency, 80 MSPS, 3.2 V p-p

95

SFDR (dBc) +25°C

90

85

80

SNR (dB) +25°C

(dB)

75

70

65

60

0 180

SFDR (dBc) –40°C

SFDR (dBc) +85°C

SNR (dB) –40°C

SNR (dB) +85°C

20 40 60 80 100 120 140 160

ANALOG INPUT FREQUENCY (MHz)

05490-031

Figure 31. AD9446-80 SNR/SFDR vs. Analog Input Frequency, 80 MSPS, 3.2 V p-p,

CMOS Mode

65

60

0 180

20 40 60 80 100 120 140 160

ANALOG INPUT FREQUENCY (MHz)

05490-033

Figure 33. AD9446-80 SNR/SFDR vs. Analog Input Frequency, 80 MSPS, 2.0 V p-p

90

88

86

84

82

80

(dB)

78

76

74

72
70

2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
ANALOG INPUT COMMON-MODE VOLTAGE

SFDR dBc

SNR dB

05490-034

Figure 34. AD9446-80 SNR/SFDR vs. Analog Input Common Mode, 80 MSPS

120

100

80

60

(dB)

40

20

0

–100 0

SFDR dBFS

SNR dBFS

SFDR dBc

SNR dB

–90 –80 –70 –60 –50 –40 –30 –20 –10

ANALOG INPUT AMPLITUDE (dB)

05490-032

Figure 32. AD9446-80 SNR/SFDR vs. Analog Input Level, 80 MSPS

Rev. 0 | Page 19 of 36

120

100

80

60

(dB)

40

20

0

–100 0

SFDR dBFS

SNR dBFS

SFDR dBc

SNR dB

–90 –80 –70 –60 –50 –40 –30 –20 –10

ANALOG INPUT AMPLITUDE (dB)

Figure 35. AD9446-80 SNR/SFDR vs. Analog Input Level, 80 MSPS,

CMOS Output Mod

e

05490-035

AD9446

www.BDTIC.com/ADI

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120
–130
–140

0 50.0

12.5 25.0 37.5
FREQUENCY (MHz)

Figure 36. AD9446-100 64k Point Two-Tone FFT/100 MSPS/9.8 MHz, 10.8 MHz

100MSPS

9.8MHz @ –7.0dBFS

10.8MHz @ –7.0dBFS
SFDR = 95dBc

05490-037

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

SPUR AND IMD3 (dB)

–100
–110
–120
–130

–100 0

WORST IMD3 dBc

SFDR dBFS

WORST IMD3 dBFS

–90 –80 –70 –60 –50 –40 –30 –20 –10

FUNDAMENTAL LEVEL (dB)

SFDR dBc

05490-041

Figure 39. AD9446-100 Two-Tone SFDR vs. Analog Input Level 100 MSPS/

3 MHz, 70.3 MHz

69.

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

SPUR AND IMD3 (dB)

–100
–110
–120
–130

–100 0

WORST IMD3 dBc

–90 –80 –70 –60 –50 –40 –30 –20 –10

SFDR dBc

SFDR dBFS

WORST IMD3 dBFS

FUNDAMENTAL LEVEL (dB)

05490-038

Figure 37. AD9446-100 Two-Tone SFDR vs. Analog Input Level 100 MSPS/

.8 MHz, 10.8 MHz

9

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120
–130
–140

0 50.0

12.5 25.0 37.5
FREQUENCY (MHz)

100MSPS

69.3MHz @ –7.0dBFS

70.3MHz @ –7.0dBFS
SFDR = 92dBc

05490-040

Figure 38. AD9446-100 64k Point Two-Tone FFT/100 MSPS/69.3 MHz, 70.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100

–110
–120
–130
–140

04

10 20 30

FREQUENCY (MHz)

80MSPS

9.8MHz @ –7.0dBFS

10.8MHz @ –7.0dBFS
SFDR = 96dBc

05490-042

0

Figure 40. AD9446-80 64k Point Two-Tone FFT/80 MSPS/9.8 MHz, 10.8 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

SPUR AND IMD3 (dB)

–100
–110
–120
–130

–100 0

–90 –80 –70 –60 –50 –40 –30 –20 –10

WORST IMD3 dBc

FUNDAMENTAL LEVEL (dB)

SFDR dBc

SFDR dBFS

WORST IMD3 dBFS

05490-043

Figure 41. AD9446-80 Two-Tone SFDR vs. Analog Input Level 80 MSPS/

9

.8 MHz, 10.8 MHz

Rev. 0 | Page 20 of 36

AD9446

www.BDTIC.com/ADI

16000

11927

7277

N– 2

N– 3

OUTPUT CODE

14296

N– 1

12619

8376

N

N + 1

14000

12000

10000

8000

FREQUENCY

6000

4000

2000

0

11 40

N– 7

3424

1192

315

N– 4

N– 5

N– 6

Figure 42. AD9446-100 Grounded Input Histogram

SAMPLE SIZE = 65538

4073

1458

426

80

N + 6

N + 5

N + 4

N + 3

N + 2

22

05490-044

N + 7

18000

SAMPLE SIZE = 65538

16000

14000

12000

10000

8000

FREQUENCY

6000

4000

2000

310

0

3916

947

146

N– 3

N– 4

N– 5

N– 6

17090

16450

10145

N

N– 1

N– 2

OUTPUT CODE

Figure 45. AD9446-80 Grounded Input Histogram

11027

N + 1

4393

N + 2

1181

N + 3

N + 4

198

N + 5

30

05490-047

N + 6

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

AMPLITUDE (dBFS)

–100
–110
–120
–130
–140

040

10 20 30

FREQUENCY (MHz)

80MSPS

69.3MHz @ –7.0dBFS

70.3MHz @ –7.0dBFS
SFDR = 92dBc

05490-045

Figure 43. AD9446-80 64k Point Two-Tone FFT/80 MSPS/69.3 MHz, 70.3 MHz

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

SPUR AND IMD3 (dB)

–100
–110
–120
–130

–100 0

–90 –80 –70 –60 –50 –40 –30 –20 –10

WORST IMD3 dBc

WORST IMD3 dBFS

FUNDAMENTAL LEVEL (dB)

SFDR dBc

SFDR dBFS

05490-046

Figure 44. AD9446-80 Two-Tone SFDR vs. Analog Input Level 80 MSPS/

69.

3 MHz, 70.3 MHz

0

–0.1

–0.2

–0.3

–0.4

–0.5

GAIN ERROR (%FSR)

–0.6

–0.7

–0.8

–40

–20 0 20 40 60 80

TEMPERATURE (°C)

Figure 46. AD9446-100 Gain vs. Temperature

400

350

(mA)

SUPPLY

I

300

250

200

150

100

AVDD1

AVDD2

DRVDD

50

0

20 40 60 80 100 120

0

SAMPLE RATE (MSPS)

Figure 47. AD9446-80 Power Supply Current vs. Sample Rate

10.

3 MHz @ −1 dBFS

140

05490-048

05490-049

Rev. 0 | Page 21 of 36

AD9446

www.BDTIC.com/ADI

95

82

93

10.3MHz SFDR dBc

70.3MHz SFDR dBc

(dB)

91

89

87

85

83

81

79

1.8

30.3MHz SFDR dBc

ANALOG INPUT RANGE (V p-p)

Figure 48. AD9446-100/SFDR vs. Analog Input Range,

0 MSPS

10

1.625

1.620

1.615

VREF

1.610

1.605
–40

–20 0 20 40 60 80

TEMPERATURE (°C)

Figure 49. AD9446-100 VREF vs. Temperature

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

05490-050

05490-051

81

80

70.3MHz SFDR dBc

(dB)

79

78

77

76

1.8

10.3MHz SFDR dBc

30.3MHz SFDR dBc

ANALOG INPUT RANGE (V p-p)

Figure 51. AD9446-100 SNR vs. Analog Input Range,

0 MSPS

10

95

(dB)

93

91

89

87

85

83

81

79

1.8

30.3MHz SFDR dBc

ANALOG INPUT RANGE (V p-p)

10.3MHz SFDR dBc

70.3MHz SFDR dBc

Figure 52. AD9446-80 SFDR vs. Analog Input Range,

10

0 MSPS

05490-064

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

05490-065

4.22.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

450

400

350

AVDD1

AVDD2

DRVDD

50

0

0

20 40 60 80 100 120

SAMPLE RATE (MSPS)

140

05490-063

(mA)

SUPPLY

I

300

250

200

150

100

Figure 50. AD9446-100 Power Supply Current vs. Sample Rate

3 MHz @ −1 dBFS

10.

Rev. 0 | Page 22 of 36

84

10.3MHz SNR dB

70.3MHz SNR dB

(dB)

83

82

81

80

79

78

77

1.8

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
ANALOG INPUT RANGE (V p-p)

Figure 53. AD9446-80/SNR vs. Analog Input Range,

80 MSPS

30.3MHz SNR dB

4.2

05490-066

AD9446

www.BDTIC.com/ADI

100

0

100M SFDR dBc

80M SFDR dBc

80M SNR dB

100M SNR dB

2010 30 40 50 60 70 80 90 100 110

SAMPLE RATE (MSPS)

95

90

(dB)

85

80

75

Figure 54. AD9446 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz

05490-036

Rev. 0 | Page 23 of 36

AD9446

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD9446 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 16-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.

ANALOG INPUT AND REFERENCE OVERVIEW

A stable and accurate 0.5 V band gap voltage reference is built
into the AD9446. The input range can be adjusted by varying
the reference voltage applied to the AD9446, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.

Internal Reference Connection

A comparator within the AD9446 detects the potential at the
SENSE pin and configures the reference into three possible states,
which are summarized in Ta bl e 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 55), setting VREF to ~1.6 V. If a resistor

er is connected as shown in Figure 56, the switch again sets

divid

o the SENSE pin. This puts the reference amplifier in a

t
noninverting mode with the VREF output defined as

R2

⎛

VVREF 15.0

⎜
⎝

In all reference configurations, REFT and REFB drive the

nalog-to-digital conversion core and establish its input span.

a
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.

Internal Reference Trim

The internal reference voltage is trimmed during the production
test; therefore, there is little advantage to the user supplying an
external voltage reference to the AD9446. The gain trim is per­formed with the AD9446 input range set to 3.2 V p-p nominal
(SENSE connected to AGND). Because of this trim and the
maximum ac performance provided by the 3.2 V p-p analog
input range, there is little benefit to using analog input ranges

⎞

+×=

⎟

R1

⎠

<2 V p-p. However, reducing the range can improve SFDR
performance in some applications. Likewise, increasing the
range up to 3.8 V p-p can improve SNR. Users are cautioned
that the differential nonlinearity of the ADC varies with the
reference voltage. Configurations that use <2.0 V p-p may
exhibit missing codes and therefore degraded noise and
distortion performance.

VIN+

10μF+0.1μF

10μF+0.1μF

VIN–

ADC

CORE

VREF

SELECT

LOGIC

SENSE

0.5V

AD9446

Figure 55. Internal Reference Configuration

VIN+

VIN–

VREF

R2

SENSE

R1

Figure 56. Programmable Reference Configuration

SELECT

LOGIC

0.5V

AD9446

ADC

CORE

REFT

0.1μF

0.1μF 10μF

REFB

0.1μF

REFT

0.1μF

0.1μF 10μF

REFB

0.1μF

+

05490-052

+

05490-053

Rev. 0 | Page 24 of 36

AD9446

www.BDTIC.com/ADI

Table 9. Reference Configuration Summary

Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A 2 × external reference
Programmable Reference 0.2 V to VREF

Programmable Reference

(Set for 2 V p-p)

Programmable Reference

(Set for 2 V p-p)

Internal Fixed Reference AGND to 0.2 V 1.6 3.2

0.2 V to VREF

0.2 V to VREF

R2

⎛
⎜
⎝

⎛
⎜
⎝

⎛
⎜
⎝

⎞

(See Figure 56)

+×

10.5

⎟

R1

⎠

R2

⎞

, R1 = R2 = 1 kΩ

+×

10.5

⎟

R1

⎠

R2

⎞

, R1 = 1 kΩ , R2 = 2.8 kΩ

+×

10.5

⎟

R1

⎠

External Reference Operation

When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent

VIN+

7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC

1.6V p-p

core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a

VIN–

maximum of 2.0 V. See Figure 46 for gain variation vs.
temperature.

DIGITAL OUT = ALL 1s DIGITAL OUT = ALL 0s

2 × VREF

2.0

3.8

3.5V

Analog Inputs

As with most new high speed, high dynamic range ADCs, the
analog input to the AD9446 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9446 cannot be realized with a single-ended analog input, so
such configurations are discouraged. Contact sales for
recommendations of other 16-bit ADCs that support single­ended analog input configurations.

With the 1.6 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of

e AD9446 analog input is nominally 3.2 V p-p or 1.6 V p-p on

th
each input (VIN+ or VIN−).

Figure 57. Differential Analog Input Range for VREF = 1.6 V

The AD9446 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer. The
internal bias network on the input properly biases the buffer for
maximum linearity and range (see the
s

ection). Therefore, the analog source driving the AD9446

Equivalent Circuits

should be ac-coupled to the input pins. The recommended
method for driving the analog input of the AD9446 is to use an
RF transformer to convert single-ended signals to differential

Figure 58). Series resistors between the output of the

(see

nsformer and the AD9446 analog inputs help isolate the

tra
analog input source from switching transients caused by the
internal sample-and-hold circuit. The series resistors, along
with the 1 kΩ resisters connected to the internal 3.5 V bias,
must be considered in impedance matching the transformer
input. For example, if R

is set to 51 Ω, RS is set to 33 Ω and

T

there is a 1:1 impedance ratio transformer, the input will match a
50 Ω source with a full-scale drive of 16.0 dBm. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board
schematic (see Figure 61).

05490-054

Rev. 0 | Page 25 of 36

AD9446

www.BDTIC.com/ADI

0.1

R

S

VIN+

AD9446

R

S

μF

VIN–

05490-055

R

ADT1–1WT

T

ANALOG

INPUT

SIGNAL

Figure 58. Transformer-Coupled Analog Input Circuit

CLOCK INPUT CONSIDERATIONS

Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-to­digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9446, and the user is
advised to give careful thought to the clock source.

Typical high speed ADCs use both clock edges to generate a

riety of internal timing signals and, as a result, may be sensitive

va
to the clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance charac­teristics. The AD9446 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal ~50% duty cycle. Noise and distortion per­formance are nearly flat for a 30% to 70% duty cycle with the DCS
enabled. The DCS circuit locks to the rising edge of CLK+ and
optimizes timing internally. This allows for a wide range of input
duty cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and is
not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 30 MHz
nominally. The loop is associated with a time constant that
should be considered in applications where the clock rate can
change dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.

The DCS circuit is controlled by the DCS MODE pin; a CMOS

gic low (AGND) on DCS MODE enables the duty cycle stabilizer,

lo
and logic high (AVDD1 = 3.3 V) disables the controller.

The AD9446 input sample clock signal must be a high quality,

remely low phase noise source to prevent degradation of per-

ext
formance. Maintaining 16-bit accuracy places a premium on the
encode clock phase noise. SNR performance can easily degrade
by 3 dB to 4 dB with 70 MHz analog input signals when using a
high jitter clock source. (See the AN-501 Application Note,

Aperture Uncertainty and ADC System Performance.”) For

“
optimum performance, the AD9446 must be clocked differentially.
The sample clock inputs are internally biased to ~1.5 V, and the
input signal is usually ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors.
m

ethod for clocking the AD9446. The clock source (low jitter)

Figure 59 shows one preferred

is converted from single-ended to differential using an RF trans­former. The back-to-back Schottky diodes across the secondary
of the transformer limit clock excursions into the AD9446 to
approximately 0.8 V p-p differential. This helps prevent the large
voltage swings of the clock from feeding through to other portions
of the AD9446 and limits the noise presented to the sample
clock inputs.

If a low jitter clock is available, it may help to band-pass filter

he clock reference before driving the ADC clock inputs. Another

t
option is to ac couple a differential ECL/PECL signal to the encode
input pins, as shown in Figure 60.

CRYSTAL

SINE

SOURCE

Figure 59. Crystal Clock Oscillator, Differential Encode

PECL

ADT1–1WT

0.1

μF

HSMS2812

DIODES

VT

0.1

μF

ECL/

Figure 60. Differential ECL for Encode

0.1μF

VT

CLK+

AD9446

CLK–

ENCODE

AD9446

ENCODE

05490-057

05490-056

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input

f

frequency (

t

) can be calculated using the following equation:

(

J

SNR = 20 log[2πf

) and rms amplitude due only to aperture jitter

INPUT

× tJ]

INPUT

In the equation, the rms aperture jitter represents the root-mean-

uare of all jitter sources, which includes the clock input, analog

sq
input signal, and ADC aperture jitter specification. IF under­sampling applications are particularly sensitive to jitter

The clock input should be treated as an analog signal in cases
w

here aperture jitter may affect the dynamic range of the AD9446.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
synchronized by the original clock during the last step.

Rev. 0 | Page 26 of 36

AD9446

www.BDTIC.com/ADI

POWER CONSIDERATIONS

Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9446. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 μF chip capacitors.

The AD9446 has separate digital and analog power supply pins.
The a

nalog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best per­formance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.

The DRVDD supply of the AD9446 is a dedicated supply for the

igital outputs in either LVDS or CMOS output mode. When in

d
LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode,
the DRVDD supply can be connected from 2.5 V to 3.6 V for
compatibility with the receiving logic.

DIGITAL OUTPUTS

LVDS Mode

The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ R
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, is maximized
when the AD9446 is used in LVDS mode; designers are
encouraged to take advantage of this mode. The AD9446
outputs include complimentary LVDS outputs for each data bit
(Dx+/Dx−), the overrange output (OR+/OR−), and the output

SET

data clock output (DCO+/DCO−). The R
multiplied on-chip, setting the output current at each output
equal to a nominal 3.5 mA (11 × I

termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended, with a 100 Ω termination resistor
located as close to the receiver as possible. It is recommended to
keep the trace length less than 2 inches and to keep differential
output trace lengths as equal as possible.

R

SET

CMOS Mode

In applications that can tolerate a slight degradation in dynamic
performance, the AD9446 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR+. The output clock is provided as a differential CMOS
signal, DCO+/DCO−. Lower supply voltages are recommended
to avoid coupling switching transients back to the sensitive
analog sections of the ADC. The capacitive load to the CMOS
outputs should be minimized, and each output should be
connected to a single gate through a series resistor (220 Ω) to
minimize switching transients caused by the capacitive loading.

TIMING

The AD9446 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (t
Figure 3 for detailed timing diagrams.

) after the rising edge of CLK+. Refer to Figure 2 and

PD

resistor current is

SET

). A 100 Ω differential

Rev. 0 | Page 27 of 36

AD9446

www.BDTIC.com/ADI

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9446 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Tabl e 10 summarizes the output coding.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS-

Table 10. Digital Output Coding

VIN+ − VIN−

Code

65,536 +1.600 +1.000 1111 1111 1111 1111 0111 1111 1111 1111
32,768 0 0 1000 0000 0000 0000 0000 0000 0000 0000
32,767 −0.0000488 −0.000122 0111 1111 1111 1111 1111 1111 1111 1111
0 −1.60 −1.00 0000 0000 0000 0000 1000 0000 0000 0000

Input Span = 3.

2 V p-p (V)

VIN+ − VIN−
Input Span = 2 V p-p (V)

compatible input. With OUTPUT MODE = 0 (AGND), the
AD9446 outputs are CMOS compatible, and the pin assignment
for the device is as defined in Tabl e 8. With OUTPUT MODE = 1

VDD1, 3.3 V), the AD9446 outputs are LVDS compatible, and

(A
the pin assignment for the device is as defined in

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.

Digital Output
Offset Binary (D15••••••D0)

Digital Output
Twos Complement (D15••••••D0)

Tabl e 7 .

Rev. 0 | Page 28 of 36

AD9446

www.BDTIC.com/ADI

EVALUATION BOARD

Evaluation boards are offered to configure the AD9446 in either
CMOS or LVDS mode only. This design represents a recom­mended configuration for using the device over a wide range of
sampling rates and analog input frequencies. These evaluation
boards provide all the support circuitry required to operate
the ADC in its various modes and configurations. Complete
schematics are shown in

iles are available from engineering applications demonstrating

f
the proper routing and grounding techniques that should be
applied at the system level.

Figure 61 through Figure 64. Gerber

The LVDS mode evaluation boards include an LVDS-to-CMOS

ranslator, making them compatible with the high speed ADC

t
FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a
high speed data capture board that provides a hardware solution
for capturing up to 32 kB samples of high speed ADC output
data in a FIFO memory chip (user upgradeable to 256 kB
samples). Software is provided to enable the user to download
the captured data to a PC via the USB port. This software also
includes a behavioral model of the AD9446 and many other
high speed ADCs.

It is critical that signal sources with very low phase noise
(

<60 fsec rms jitter) be used to realize the ultimate performance
of the converter. Proper filtering of the input signal to remove
harmonics and lower the integrated noise at the input is also
necessary to achieve the specified noise performance.

The evaluation boards are shipped with a 115 V ac to 6 V dc
p

ower supply. The evaluation boards include low dropout
regulators to generate the various dc supplies required by the
AD9446 and its support circuitry. Separate power supplies are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see Figure 61).

Behavioral modeling of the AD9446 is also available at
www.analog.com/ADIsimADC. The ADIsimADC™ software
supp

orts virtual ADC evaluation using ADI proprietary behavioral
modeling technology. This allows rapid comparison between the
AD9446 and other high speed ADCs with or without hardware
evaluation boards.

The user can choose to remove the translator and terminations

o access the LVDS outputs directly.

t

Rev. 0 | Page 29 of 36

AD9446

www.BDTIC.com/ADI

P21

P22

GND

DRGND

1

P1

2

P2

3

P3

4

P4

PTMICRO4

1

P1

2

P2

3

P3

4

P4

PTMICRO4

DRGND

GND

GND

H4
MTHOLE6

H3
MTHOLE6

H1
MTHOLE6

H2
MTHOLE6

XTALPWR
EXTREF

DRVDD

VCC

5V

(MSB) D15_T/D15_Y

DRVDD
D11_C/D6_Y
D11_T/D7_Y
D12_C/D8_Y
D12_T/D9_Y

D13_C/D10_Y

D13_T/D11_Y

D14_C/D12_Y

D14_T/D13_Y

D15_C/D14_Y

DRGND

DRVDD

DOR_C

DOR_T/DOR_Y

GND

VCC
VCC
VCC

VCC
VCC
VCC
GND

100

101

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

DRVDD
D11_C
D11_T
D12_C
D12_T
D13_C
D13_T
D14_C
D14_T
D15_C
D15_T
DRGND
DRVDD
OR_C
OR_T
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND

EPAD

DRGND

D10_T/D5_Y

74

75

D10_T

DRGND

D9_C/D2_Y

D9_T/D3_Y

D10_C/D4_Y

72

73

71

D9_T

D9_C

D10_C

D8_C/D0_Y

D8_T/D1_Y

68

69

70

D8_T

D8_C

DR

67

DCO

DRB

66

DCOB

D7_T

65

D7_T

D7_C

64

D7_C

U1

AD9445/AD9446

DRGND

DRVDD

63

DRVDD

DRGND

62

D6_T

61

D6_T

D6_C

60

D6_C

D5_T

59

D5_T

D5_C

58

D5_C

D4_T

57

D4_T

D4_C

56

D4_C

D3_T

55

D3_T

D3_C

54

D3_C

D2_T

53

D2_T

D2_C

52

D1_T

D2_C

DRVDD
DRGND

AGND
AVDD1
AVDD1
AVDD1

AGND

ENCB

AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2

D1_T

51

D0_T

D0_C

ENC

D1_C

D1_C

50

D0_T

49

D0_C (LSB)

48

DRVDD

47

DRGND

46

GND

45

VCC

44

VCC

43

VCC

42

GND

41

ENCB

40

ENC

39

GND

38

VCC

37

5V

36

VCC

35

5V

34

VCC

33

VCC

32

VCC

31
30
29
28
27
26

5V

E19

VCC

E66

E18

GND

E4

VCC

DCS MODE

DNC

OUTPUT MODE

DFS

LVDSBIAS

AVDD1

SENSE

VREF

AGND

REFT

REFB

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD2

AVDD1

AVDD1

AVDD1

AGND

VIN+

VIN–

AGND

6

VCC

GND

GND

7

C86

E26

VCC

8

0.1μF

E25

9

E27

E41

GND

R1

11

10

C3

GND

E24

EXTREF

DNP

R3

3.74kΩ

12

0.1μF

+

GND

5V

13

C2

C51

C40

GND

R2

5V

GND

0.1μF

10μF

0.1μF

C39

14

C9

DNP

15

16

5V

5V

0.1μF

GND

10μF

20

21

19

18

17

5V

5V

C98

GND

DNP

VCC

VCC

GND

GND

VCC

T1

ETC1-1-13

R5

234

E14

GND

R11

E2

GND

5

1kΩ

VCC

1

GND

E10

E5

E6

GND

VCC

E1

GND

SCLK

E3

E9

VCC

23

22

24

GND

R28

33Ω

C7

0.1μF

GND

GND

TOUT

C12

CT

2

15

GND

L1

10nH

DNP

J4

SMBMST

AVDD2

25

5V

C13

OPTIONAL

R9

R4

36Ω

ETC1-1-13

125

T2

3

PRI SEC

TOUTB

0.1μF

34

PRI SEC

TINB

C5

0.1μF

ANALOG

DNP

DNP

4

C91

0.1μF

R6

E15

36Ω

T5

ADT1-1WT

GND

GND

TOUT

624

153

GND

R35

33Ω

C8

0.1μF

CT

PRI SEC

NC

TINB TOUTB

05490-059

Figure 61. AD9446 Evaluation Board Schematic

Rev. 0 | Page 30 of 36

AD9446

X

www.BDTIC.com/ADI

VIN

U6

GND

5

NC

ECLOSC

C42

4

XTALINPUT

8

OUTVCC

14

VXTAL

ENCB

3

1
2

GND

0.1μF

SEC

PRI

C41

0.1μF

C1

10μF

+

5V

E31

0Ω

ENC

VXTAL

E30

XTALPWR

E20

2

1

3

GND

C44

+

T3

10μF

ADT1-1WT

C36

CR1

CR2

DNP

6

123

DNP

VXTAL

OPTIONAL ENCODE CIRCUITS

LOADING SYMMETRICAL

CR2 TO MAKE LAYOUT AND PARASITIC

ENCODE

GND

R39

1

7

VEE ~OUT

GND

L5

FERRITE

DRVDDXDRVDD

VCCXVCC

L4

FERRITE

L2

DNP

L3

FERRITE

DRGNDGND

5VX5V

U3

3.3V

ADP3338

U7

3.3V

ADP3338

5V

U14

ADP3338

DRGND

1

GND

GND

1

GND

GND

1

GND

DRVDD

OUT1

OUT

DRVDDX

VCCX

OUT1

OUT

VCCX

5VX

OUT1

OUT

C4

10μF

+

342

IN

VIN

C6

10μF

+

342

IN

VIN

C34

10μF

+

342

IN

DRGND

C88

10μF

+

C87

10μF

+

C89

10μF

+

DRGND

GND

GND

GND

GND

GND

R7

DNP

J5

SMBMST

C26

0.1μF

GND

R8

50Ω

J1

SMBMST

XTALINPUT

Figure 62. AD9446 Evaluation Board Schematic (Continued)

Rev. 0 | Page 31 of 36

POWER OPTIONS

5VX

VIN

C33

GND

1

3

2

P4

PJ-102A

1

3

2

10μF

+

GND

05490-060

AD9446

www.BDTIC.com/ADI

BYPASS CAPACITORS

VCC

+

C64
10μF

GND

C43

0.1μF

C35

0.1μF

C32

0.1μF

C30

0.01μF

C28

0.1μF

C27

0.1μF

C90

0.1μF

C50

0.1μF

C60

0.1μF

C10

0.1μF

C61

0.1μF

C75

0.1μF

VCC

GND

DRVDD

DRGND

GND

GND

GND

C11XXC14

+

C65

C47

0.1μF

C85

0.1μF

C23

0.1μF

10μF

5V

+

C56
10μF

5V

5V

C17XXC16XXC15

XX

C53

C52

0.1μF

0.1μF

C72XXC73

XX

C94

C95

0.1μF

0.1μF

C21

0.1μF

C58

0.01μF

C22

0.1μF

C20

0.1μF

C31
XX

XX

C108XXC109

XX

C59

C93

0.1μF

0.1μF

DRVDD

DRGND

C38XXC29XXC19

C69XXC70

C37

0.1μF

C110
XX

C96

C97

0.1μF

0.1μF

XX

C48

0.1μF

C84

0.1μF

XX

C45XXC49

EXTREF

C18

0.1μF
GND

C46

0.1μF

XX

+

C55
10μF

05490-061

Figure 63. AD9446 Evaluation Board Schematic (Continued)

Rev. 0 | Page 32 of 36

AD9446

www.BDTIC.com/ADI

DRVDD

DRO

R190ΩR20

DRVDD

0Ω

DRGND

ORO

DRVDD

DRO

GND??

DRGND

33

35

37

39

P35

P37

P39

P36

P38

P40

34

36

38

40

ORO

DRGND

D14O

D15O

16151413121110

220

R3R1R2

RSO16ISO

RZ5

DRVDD

DRGND

DRVDD

DRGND

DRVDD

312

D15O

P33

P34

D13O

7

8

D2O

6

DRVDD

D2O

P7

P8

R7

DRGND

D0O

D1O

DRGND

1

3

5

P1

P3

P5

P7

C40MS

P2

P4

P6

2

4

6

DRGND

D1O

D0O

9

R8

RZ4

8

7

DRVDD

DRVDD

DRGND

D13O

D11O

D9O

D8O

D10O

D12O

D14O

23

25

27

29

31

P23

P25

P27

P29

P31

P24

P26

P28

P30

P32

24

26

28

30

32

D8O

D9O

D10O

D11O

D12O

9

R8

R7

R6

R5

R4

8

7

6

5

4

DRVDD

DRGND

DRVDD

D7O

17

19

21

P17

P19

P21

P18

P20

P22

18

20

22

D7O

16151413121110

220

RSO16ISO

DRVDD

DRGND

15

16

D6O

P15

D6O

P16

D4O

D3O

D5O

9

11

13

P9

P11

P13

P10

P12

P14

10

12

14

D4O

D5O

D3O

R6

R5

R4

R3R1R2

5

4

312

DRVDD

91011

12

13

14

15

16

4Y

3Y

2Y

1Y

VCC

GND

3A

2B

EN_3_4

4B

4A

3B

8765432

DOR_C

DRO_T/DOR_Y

EN_1_2

U15

2A

1B

1A

SN75LVDT390

1

DR

DRB

64

D4Y

D3Y

D2Y

D1Y

C4Y

C3Y

C2Y

23

24

16

D9_C/D2_Y

P23

P24

D9_T/D3_Y

VCC3

B4B

17

D8_C/D0_Y

C1Y

VCC4

GND3

C2A

C1B

C1A

20

19

18

D7_T

D6_T

D7_C

D8_C/DO_Y

DRB

19

21

P19

P21

P20

P22

20

22

DR

D8_T/D1_Y

C2B

D6_C

D7_C

17

P17

18

D7_T

21

P18

C3A

D5_T

22

15

16

C3B

D5_C

D6_C

P15

P16

D6_T

ENC

C4B

C4A

24

23

D4_T

D4_C

D5_C

13

P13

P14

14

D5_T

END

VCC6

VCC5

GND5

GND4

D4B

D4A

D3B

D3A

D2B

D2A

D1B

D1A

32

31

30

29

28

27

26

25

D3_T

D2_T

D1_T

D2_C

7

8

D2_C

P7

P8

D2_T

D0_T

D1_C

D0_C

D0_C

D1_C

DRGND

1

3

5

P1

P3

P5

P2

P4

P6

2

4

6

D0_T

D1_T

DRGND

11

12

D4_C

P11

P12

D4_T

D3_C

D3_C

9

P9

P10

10

D3_T

C78

0.1μF

C77

0.1μF

C82

0.1μF

C76

0.1μF

GND

GND

P6

C40MS

05490-062

A1Y

VCC1

A1B

D15_C/D14_Y

39

40

VCC2

GND1

A2B

A2A

D14_T/D13_Y

D14_C/D12_Y

DOR_C

DRGND

37

P37

P39

P38

P40

38

DRGND

DOR_T/DOR_Y

ENA

A3A

D13_T/D11_Y

35

36

A3B

D13_C/D10_Y

GND

U8

A1A

SN75LVDS386

D15_T/D14_Y

D15_C/D14_Y

P35

P36

D15_T/D15_Y

A4A

D12_T/D9_Y

33

34

A4B

987654321

D12_C/D8_Y

D14_C/D12_Y

P33

P34

D14_T/D13_Y

B1A

D11_T/D7_Y

D13_C/D10_Y

31

P31

P32

32

D13_T/D11_Y

ENB

B2A

B1B

11

10

D10_T/D5_Y

D11_C/D6_Y

D12_C/D8_Y

29

P29

P30

30

D12_T/D9_Y

GND2

B4A

B3B

B3A

B2B

15

14

13

12

D9_T/D3_Y

D8_T/D1_Y

D9_C/D2_Y

D10_C/D4_Y

D10_C/D4_Y

D11_C/D6_Y

25

27

P25

P27

P26

P28

26

28

D10_T/D5_Y

D11_T/D7_Y

B4Y

B3Y

B2Y

B1Y

A4Y

A3Y

A2Y

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Figure 64. AD9446 Evaluation Board Schematic (Continued)

Rev. 0 | Page 33 of 36

AD9446

www.BDTIC.com/ADI

Table 11. AD9446 Customer Evaluation Board Bill of Material

Reference

Item Qty.

1 7

2 44

3 2 C30, C58 Capacitor 201 0.01 F Digi-Key Corporation 445-1796-1-ND
4 4 C39, C56, C64, C65 Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2
5 1 C51 Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND
6 1 CR1 Diode SOT23M5 Digi-Key Corporation

7 1 CR2 Diode SOT23M5 Digi-Key Corporation

8 20

9 2 J1, J4 SMA SMA Digi-Key Corporation ARFX1231-ND
10 1 L1 Inductor 0603A 10 nH Coilcraft, Inc. 0603CS-10NXGBU
11 3 L3, L4, L5

12 1 P4 PJ-002A PJ-002A Digi-Key Corporation CP-002A-ND
13 1 P7 Header C40MS Samtec, Inc.

14 1 R3 Resistor 402 3.74 kΩ Digi-Key Corporation P3.74KLCT-ND
15 1 R8 Resistor 402 50 Ω Digi-Key Corporation P49.9LCT-ND
16 4 R10, R19, R39, L2 Resistor 402 0 Ω Digi-Key Corporation P0.0JCT-ND
17 1 R11 BRES402 402 1 kΩ Digi-Key Corporation P1.0KLCT-ND
18 2 R28, R35 Resistor 402 33 Ω Digi-Key Corporation P33JCT-ND
19 2 RZ4, RZ5 Resistor array 16PIN 22 Ω Digi-Key Corporation

20 2 T3, T5 Transformer ADT1-1WT Mini-Circuits ADT1-1WT
21 1 U1 AD9445BSVZ-125 SV-100-3 Analog Devices, Inc. AD9445BSVZ-100
22 1 U14 ADP3338-5

23 2 U3, U7 ADP3338-3.3

24 1 U8 SN75LVDT386 TSSOP64 Arrow Electronics, Inc. SN75LVDT386
25 1 U15 SN75LVDT390 SOIC16PW Arrow Electronics, Inc. SN75LVDT390
26 2 R4, R6 Resistor 402 36 Ω Digi-Key Corporation P36JCT-ND
27 2 C1, C44, C55
28 23

29 1 C98

Designa

C4, C6, C33, C34, C87,
C88, C89

C2, C3, C5, C7, C8,
C9, C10, C11, C1
C15, C20, C21, C22,
C23, C26, C27, C28,
C32, C35, C38, C40,
C42, C43, C46, C47,
C48, C50, C52, C53,
C59, C60, C76, C77,
C78, C82, C84, C85,
C86, C90, C91, C94,
C95, C96, C97

E1, E2, E3, E4, E5, E6,
E9, E10, E14,
E20, E24, E25, E26, E27,
E30, E31, E36, E41

C13, C14, C16, C17,
C18, C19, C29, C
C36, C37, C41, C45,
C49, C61, C69, C70,
C72, C73, C75, C93,
C108, C109, C110

tor Description Package Value Manufacturer Mfg. P

2,

E18, E19,

1

31,

1

1

art No.

Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2

Capacitor 402 0.1 F Digi-Key Corporation PCC2146CT-ND

MA3X71600LCT­ND

MA3X71600LCT­ND

Header EHOLE Mouser Elec

EMIFIL®
BLM31PG500SN1L

Capacitor TAJD 10 F Digi-Key Corporation 478-1699-2
CAP402 402 XX

Capacitor 805 10 F Digi-Key Corporation 490-1717-1-ND

1206MIL Mouser Electronics 81-BLM31P500S

SOT­223HS

SOT­223HS

Analog Devices, Inc. ADP3338-5

Analog Devices, Inc. ADP3338-33

tronics 517-6111TG

TSW-120-08-L-D­RA

742C163220JCT­ND

Rev. 0 | Page 34 of 36

AD9446

www.BDTIC.com/ADI

Reference

Item Qty.

30 E15
31 J5
32 P6

33 2 R1, R2
34 3 R5, R7, R9
35 1 U2
36 4 H1, H2, H3, H4
37 2 T1, T2
38 2 P21, P22

1

Parts not populated.

Designator Description Package Value Manufacturer Mfg. Part No.

1

1

1

1

1

1

1

1

1

Header EHOLE Mouser Electronics 517-6111TG
SMA SMA Digi-Key Corporation ARFX1231-ND
Header C40MS Samtec, Inc.

TSW-120-08-L-D-

RA
BRES402 402 XX
BRES402 402 XX
ECLOSC DIP4(14)
MTHOLE6 MTHOLE6
Balun transformer SM-22 M/A-COM ETC1-1-13
Term strip PTMICRO4 Newark Electronics

Rev. 0 | Page 35 of 36

AD9446

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.20

MAX

16.00 BSC SQ

1

PIN 1

14.00 BSC SQ

76100

76 100

75

75

1

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

TOP VIEW

(PINS DOWN)

0° MIN

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARITY

NOTES

1. CENTER FIGURES ARE TY P ICAL UNLESS O THERWISE NOTED.

2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPER ATIO N OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EX P OSED ON THE BO TTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECO M M E NDED THAT NO PCB SIGNAL
TRACES OR VI AS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHI CH MAY BE BENEFICIAL IN HIGH TEMPE RATURE ENVIRONM E NTS.

25

26 49

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

50

51

EXPOSED

BOTTO M V IEW

0.50 BSC

LEAD PITCH

PAD

(PINS UP)

0.27

0.22

0.17

9.50 SQ

25

2650

Figure 65. 100-Lead Thin Quad Flat Packag

e, Exposed Pad [TQFP_EP]

(SV-100-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9446BSVZ-80
AD9446BSVZ-100
AD9446-100LVDS/PCB AD9446-100 LVDS Mode Evaluation Board
AD9446-80LVDS/PCB AD9446-80 LVDS Mode Evaluation Board

1

Z = Pb-free part.

1

1

–40°C to +85°C 100-Lead TQFP_EP SV-100-3
–40°C to +85°C 100-Lead TQFP_EP SV-100-3

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05490–0–10/05(0)

Rev. 0 | Page 36 of 36