SNR = 65 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at f
SFDR = 78 dBc at f
Integrated input buffer
Excellent linearity
DNL = ±0.5 LSB typical
INL = ±0.6 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation
690 mW at 500 MSPS—LVDS SDR mode
660 mW at 500 MSPS—LVDS DDR mode
Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9434 is a 12-bit monolithic sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a sample-and-hold and voltage
reference, are included on the chip to provide a complete signal
conversion solution. The VREF pin can be used to monitor the
internal reference or provide an external voltage reference
(external reference mode must be enabled through the SPI
port).
The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is
available for proper output data timing.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
up to 250 MHz at 500 MSPS (−1.0 dBFS)
IN
up to 250 MHz at 500 MSPS (−1.0 dBFS)
IN
1.8 V Analog-to-Digital Converter
AD9434
FUNCTIONAL BLOCK DIAGRAM
REF
REFERENCE
CML
VIN+
VIN–
CLK+
CLK–
TRACK-AND-HOLD
CLOCK
MANAGEME NT
SCLK/DFS
Fabricated on an advanced BiCMOS process, the AD9434 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C). This part is protected
under a U.S. patent.
PRODUCT HIGHLIGHTS
1. High Performance.
Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input.
2. Low Power.
Consumes only 660 mW at 500 MSPS.
3. Ease of Use.
LVDS output data and output clock signal allow interface
to FPGA technology. The on-chip reference and sampleand-hold provide flexibility in system design. Use of a
single 1.8 V supply simplifies system power supply design.
4. Serial Port Control.
Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.
5. The AD9434 is pin compatible with the AD9230, and can
be substituted in many applications with minimal design
changes.
Changes to General Description .................................................... 1
Changes to Table 4, Aperture Time Values ................................... 6
Changes to Figure 32 ...................................................................... 17
Changes to Figure 42 ...................................................................... 19
Changes to Table 13, Register 10, Bits[7:0] Value, Register 14
Default Value, Register 15 Default Value, Register 17, Bit 7 Value
and Register 18, Bit[4:0] Values .................................................... 26
3/11—Revision 0: Initial Version
Rev. A | Page 2 of 28
Page 3
AD9434
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
Table 1.
Parameter1 Temp Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error 25°C ±0.25 ±0.25 mV
Full −3.0 +1.0 −3.0 +1.0 mV
Gain Error 25°C 1.0 1.0 % FS
Full −5.0 +7.0 −5.0 +7.0 % FS
Differential Nonlinearity (DNL) 25°C ±0.4 ±0.5 LSB
Full −0.9 +0.9 −0.95 +1.0 LSB
Integral Nonlinearity (INL) 25°C ±0.4 ±0.6 LSB
Full −0.92 +0.92 −1.3 +1.3 LSB
INTERNAL REFERENCE
VREF Full 0.71 0.75 0.78 0.71 0.75 0.78 V
TEMPERATURE DRIFT
Offset Error Full 18 18 μV/°C
Gain Error Full 0.07 0.07 %/°C
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range2 Full 1.18 1.5 1.6 1.18 1.5 1.6 V p-p
Input Common-Mode Voltage Full 1.7 1.7 V
Input Resistance (Differential) Full 1 1 kΩ
Input Capacitance (Differential) 25°C 1.3 1.3 pF
POWER SUPPLY
AVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V
DRVDD Full 1.75 1.8 1.9 1.75 1.8 1.9 V
Supply Currents
3
I
Full 260 280 283 301 mA
AVDD
3
I
/SDR Mode4 Full 88 100 100 114 mA
DRVDD
3
I
/DDR Mode5 Full 70 80 82 96 mA
DRVDD
Power Dissipation
SDR Mode4 Full 625 685 690 747 mW
DDR Mode5 Full 595 648 657 715 mW
Standby Mode Full 40 50 40 50 mW
Power-Down Mode Full 2.5 7 2.5 7 mW
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
3
I
and I
AVDD
4
Single data rate mode; this is the default mode of the AD9434.
5
Double data rate mode; user-programmable feature. See the Memory Map section.
are measured with a −1 dBFS, 30.3 MHz sine input at rated sample rate.
DRVDD
= −40°C, T
MIN
= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
MAX
AD9434-370AD9434-500
Rev. A | Page 3 of 28
Page 4
AD9434
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
Table 2.
Parameter
SNR
SINAD
EFFECTIVE NUMBER OF BITS (ENOB)
WORST HARMONIC (SECOND or THIRD)
SFDR
WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD)
TWO-TONE IMD
ANALOG INPUT BANDWIDTH
1
All ac specifications tested by driving CLK+ and CLK− differentially.
2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
1, 2
Temp Min Typ Max Min Typ Max Unit
fIN = 30.3 MHz 25°C 66.3 65.9 dBFS
fIN = 70.3 MHz 25°C 66.2 65.9 dBFS
fIN = 100.3 MHz 25°C 66.1 65.8 dBFS
Full 65.3 64.5 dBFS
fIN = 250.3 MHz 25°C 65.5 65.2 dBFS
fIN = 450.3 MHz 25°C 64.0 63.5 dBFS
fIN = 30.3 MHz 25°C 66.1 65.9 dBFS
fIN = 70.3 MHz 25°C 66.1 65.8 dBFS
fIN = 100.3 MHz 25°C 66.0 65.8 dBFS
Full 65.2 64.4 dBFS
fIN = 250.3 MHz 25°C 65.3 64.8 dBFS
fIN = 450.3 MHz 25°C 63.7 62.9 dBFS
fIN = 30.3 MHz 25°C 10.7 10.7 Bits
fIN = 70.3 MHz 25°C 10.7 10.6 Bits
fIN = 100.3 MHz 25°C 10.7 10.6 Bits
fIN = 250.3 MHz 25°C 10.6 10.5 Bits
fIN = 450.3 MHz 25°C 10.3 10.2 Bits
fIN = 30.3 MHz 25°C −93 −93 dBc
fIN = 70.3 MHz 25°C −89 −91 dBc
fIN = 100.3 MHz 25°C −83 −87 dBc
Full −75 −74 dBc
fIN = 250.3 MHz 25°C −80 −78 dBc
fIN = 450.3 MHz 25°C −78 −69 dBc
fIN = 30.3 MHz 25°C 89 84 dBc
fIN = 70.3 MHz 25°C 88 82 dBc
fIN = 100.3 MHz 25°C 83 83 dBc
Full 75 74 dBc
fIN = 250.3 MHz 25°C 79 78 dBc
fIN = 450.3 MHz 25°C 78 68 dBc
fIN = 30.3 MHz 25°C −90 −85 dBc
fIN = 70.3 MHz 25°C −90 −82 dBc
fIN = 100.3 MHz 25°C −91 −84 dBc
Full −75 −74 dBc
fIN = 250.3 MHz 25°C −83 −85 dBc
fIN = 450.3 MHz 25°C −82 −78 dBc
f
= 119.5 MHz, f
IN1
= 122.5 MHz 25°C −85 −85 dBc
IN2
Full Power 25°C 1 1 GHz
= −40°C, T
MIN
= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
MAX
AD9434-370AD9434-500
Rev. A | Page 4 of 28
Page 5
AD9434
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
Table 3.
AD9434-370 AD9434-500
Parameter1 Temp Min Typ Max Min Typ Max Unit
CLOCK INPUTS
Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 0.9 V
Differential Input Voltage
High Level Input (VIH) Full 0.2 1.8 0.2 1.8 V p-p
Low Level Input (VIL) Full −1.8 −0.2 −1.8 −0.2 V p-p
High Level Input Current (IIH) Full −10 +10 −10 +10 μA
Low Level Input Current (IIL) Full −10 +10 −10 +10 μA
Input Resistance (Differential) Full 8 10 12 8 10 12 kΩ
Input Capacitance Full 4 4 pF
LOGIC INPUTS
Logic 1 Voltage Full 0.8 × DRVDD 0.8 × DRVDD V
Logic 0 Voltage Full 0.2 × DRVDD 0.2 × DRVDD V
Logic 1 Input Current (SDIO, CSB) Full 0 0 μA
Logic 0 Input Current (SDIO, CSB) Full −60 −60 μA
Logic 1 Input Current (SCLK, PDWN) Full 50 50 μA
Logic 0 Input Current (SCLK, PDWN) Full 0 0 μA
Input Capacitance 25°C 4 4 pF
LOGIC OUTPUTS2
VOD Differential Output Voltage Full 247 454 247 454 mV
VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V
Output Coding Twos complement, Gray code, or offset binary (default)
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
LVDS R
TERMINATION
= 100 Ω.
= −40°C, T
MIN
= +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
MAX
Rev. A | Page 5 of 28
Page 6
AD9434
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
Table 4.
AD9434-370 AD9434-500
Parameter Temp Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 370
Minimum Conversion RateFull
1, 2
CLK+ Pulse Width High (tCH)
CLK+ Pulse Width Low (tCL) Full 1.1 11 0.9 11 ns
Output (LVDS—SDR Mode)1
Data Propagation Delay (tPD) Full 0.85 0.85 ns
Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns
Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns
DCO Propagation Delay (t
Data to DCO Skew (t
CPD
) Full 0.15 0.38 0.15 0.38 ns
SKEW
Latency Full 15 15 Cycles
Output (LVDS—DDR Mode)2
Data Propagation Delay (tPD) Full 0.6 0.6 ns
Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns
Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns
DCO Propagation Delay (t
Data to DCO Skew (t
to DRGND
DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V
OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V
CLK+ to AGND −0.3 V to AVDD + 0.2 V
CLK− to AGND −0.3 V to AVDD + 0.2 V
VIN+ to AGND −0.3 V to AVDD + 0.2 V
VIN− to AGND −0.3 V to AVDD + 0.2 V
CML to AGND −0.3 V to AVDD + 0.2 V
VREF to AGND −0.3 V to AVDD + 0.2 V
SDIO to DRGND −0.3 V to DRVDD + 0.2 V
PDWN to AGND −0.3 V to DRVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.2 V
SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V
Environmental
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature
(Soldering, 10 sec)
Junction Temperature 150°C
−0.3 V to DRVDD + 0.2 V
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the
thermal capability of the package.
Table 6.
Package Type θJA θ
56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W
Unit
JC
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, metal in direct contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θ
1. DNC = DO NOT CONNECT. DO NOT CO NNECT TO THIS PIN.
2. AGND AND DRGND SHOULD BE T IED TO A COMMON
QUIET G ROUND PLANE.
3. THE EXPOSED PADDLE MUST BE SOLDERED T O
A GROUND PLANE .
21
17
18
19
20
23
22
OR–
D10–
OR+
D11–
D10+
D11+
DRGND
28
27
26
25
24
CSB
DNC
SDIO
DRVDD
SCLK/DFS
09383-004
Figure 4. Pin Configuration—Single Data Rate Mode
Table 7. Pin Function Descriptions—Single Data Rate Mode
Pin No. Mnemonic Description
0 AGND1 Analog Ground. The exposed paddle must be soldered to a ground plane.
30, 32 to 34, 37 to 39,
AVDD 1.8 V Analog Supply.
41 to 43, 46
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
8, 23, 48 DRGND1 Digital Output Ground.
35 VIN+ Analog Input—True.
36 VIN− Analog Input—Complement.
40 CML
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input—True.
45 CLK− Clock Input—Complement.
31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V.
28 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating.
25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output—Complement.
50 DCO+ Data Clock Output—True.
51 D0− D0 Complement Output (LSB).
52 D0+ D0 True Output (LSB).
53 D1− D1 Complement Output.
54 D1+ D1 True Output.
55 D2− D2 Complement Output.
56 D2+ D2 True Output.
1 D3− D3 Complement Output.
2 D3+ D3 True Output.
3 D4− D4 Complement Output.
Table 8. Pin Function Descriptions—Double Data Rate Mode
Pin No. Mnemonic Description
0 AGND1 Analog Ground. The exposed paddle must be soldered to a ground plane.
30, 32 to 34, 37 to 39, 41
AVDD 1.8 V Analog Supply.
to 43, 46
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
8, 23, 48 DRGND1 Digital Output Ground.
35 VIN+ Analog Input—True.
36 VIN− Analog Input—Complement.
40 CML
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized
internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input—True.
45 CLK− Clock Input—Complement.
31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V.
25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output—Complement.
50 DCO+ Data Clock Output—True.
51 D0/D6− D0/D6 Complement Output (LSB).
52 D0/D6+ D0/D6 True Output (LSB).
53 D1/D7− D1/D7 Complement Output.
54 D1/D7+ D1/D7 True Output.
55 D2/D8− D2/D8 Complement Output.
56 D2/D8+ D2/D8 True Output.
1 D3/D9− D3/D9 Complement Output.
2 D3/D9+ D3/D9 True Output.
3 D4/D10− D4/D10 Complement Output.
4 D4/D10+ D4/D10 True Output.
5 D5/D11− D5/D11 Complement Output (MSB).
Rev. A | Page 11 of 28
Page 12
AD9434
Pin No. Mnemonic Description
6 D5/D11+ D5/D11 True Output (MSB).
9 OR−
10 OR+ Overrange True Output. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.)
11 to 20, 28 DNC Do Not Connect. Do not connect to these pins. These pins should be left floating.
21 DNC/(OR−)
22 DNC/(OR+)
1
Tie AGND and DRGND to a common quiet ground plane.
Overrange Complement Output. (This pin is disabled if Pin 21 is reconfigured through the SPI to
be OR−.)
Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange
complement output through the serial port register.)
Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange true
output through the serial port register.)
Rev. A | Page 12 of 28
Page 13
AD9434
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, TA = 25°C, 1.5 V p-p differential input, AIN = −1 dBFS, unless otherwise noted.
The AD9434 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, whereas the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
enter a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9434 is a differential buffer. For best
dynamic performance, match the source impedances driving
VIN+ and VIN− such that common-mode settling errors are
symmetrical. The analog input is optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance degrades
significantly if the analog input is driven with a single-ended
signal.
A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip reference to a nominal 1.7 V.
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.5 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of an SPI control. See the AD9434 Configuration
Using the SPI section for more details.
Differential Input Configurations
Optimum performance is achieved while driving the AD9434
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
49.9Ω1V p-p
499Ω
523Ω
0.1µF
Figure 41. Differential Input Configuration Using the AD8138
499Ω
AD8138
499Ω
33Ω
33Ω
20pF
AVDD
VIN+
AD9434
VIN–
CML
9383-013
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9434. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few megahertz (MHz), and excessive signal
power can cause core saturation, which leads to distortion.
In any configuration, the value of the shunt capacitor, C (see
Figure 43), is dependent on the input frequency and may need
to be reduced or removed.
As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver
can be used (see Figure 43).
Rev. A | Page 19 of 28
Page 20
AD9434
V
A
A
A
A
CC
0.1µF
0Ω
NALOG INP UT
NALOG INP UT
C
DRDRG
0.1µF
16
0Ω
8, 13
1
2
AD8352
3
4
5
14
0.1µF
Figure 43. Differential Input Configuration Using the AD8352
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9434 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased at ~0.9 V
internally and require no additional bias. If the clock signal is
dc-coupled, then the common-mode voltage should remain
within a range of 0.9 V.
Figure 44 shows one preferred method for clocking the AD9434.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9434 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9434 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
MINI-CIRCUITS
ADT1–1WT, 1:1Z
CLOCK
INPUT
50Ω
100Ω
Figure 44. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 45. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
XFMR
0.1µF
0.1µF0.1µF
0.1µF
SCHOTTKY
DIODES:
HSM2812
CLK+
ADC
AD9434
CLK–
09383-016
0.1µF
11
10
0.1µF
0.1µF
CLOCK
INPUT
CLOCK
INPUT
1
50Ω RESISTORS ARE OPTIONAL.
200Ω
200Ω
50Ω
1
R
C
R
0.1µF
0.1µF
0.1µF
50Ω
AD9434
1
VIN+
CML
VIN–
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK
PECL DRIVER
CLK
09383-015
0.1µF
CLK+
100Ω
0.1µF
240Ω240Ω
ADC
AD9434
CLK–
Figure 45. Differential PECL Sample Clock
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK
INPUT
CLOCK
INPUT
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
0.1µF
CLK
0.1µF
50Ω
CLK
1
1
LVDS DRIVER
0.1µF
100Ω
0.1µF
CLK+
ADC
AD9434
CLK–
Figure 46. Differential LVDS Sample Clock
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate,
and bypass the CLK− pin to ground with a 0.1 F capacitor in
parallel with a 39 k resistor (see Figure 47).
V
CC
0.1µF
CLOCK
INPUT
1
50Ω RESISTOR IS OPTIONAL.
50Ω
1kΩ
1
1kΩ
AD951x
CMOS DRIVER
0.1µF
OPTIONAL
100Ω
39kΩ
0.1µF
CLK+
ADC
AD9434
CLK–
Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
09383-017
09383-018
09383-024
Rev. A | Page 20 of 28
Page 21
AD9434
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. A 5% tolerance is commonly
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9434 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9434.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 5 µs to allow the
DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
) due only to aperture jitter (tJ) can be calculated by
(f
A
SNR Degradation = 20 × log
(1/2 × π × fA × tJ)
10
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 48).
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9434. Separate power
supplies for clock drivers from the ADC output driver supplies
to avoid modulating the clock signal with digital noise. Low
jitter, crystal-controlled oscillators make the best clock sources.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock at the last step.
Refer to the AN-501 Application Noteand the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
130
RMS CLOCK JITTER REQUIREMENT
120
110
100
90
80
SNR (dB)
70
10 BITS
60
8 BITS
50
40
30
1101001000
Figure 48. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPUT FREQ UENCY (MHz)
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
16 BITS
14 BITS
12 BITS
09383-019
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 31, the power dissipated by the AD9434 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
By asserting PDWN (Pin 29) high, the AD9434 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9434 to its normal operational mode.
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 50 MHz, the
AD9434 assumes a standby state. In this case, the biasing network
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9434 resumes normal
operation after allowing for the pipeline latency.
DIGITAL OUTPUTS
Digital Outputs and Timing
The AD9434 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. See the Memory Map section for more information. The LVDS driver current is derived on chip and sets
the output current at each output equal to a nominal 3.5 mA.
A 100 Ω differential termination resistor placed at the LVDS
receiver inputs results in a nominal 350 mV swing at the receiver.
The AD9434 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far end receiver termination or poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths.
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 49. Figure 50 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
Rev. A | Page 21 of 28
Page 22
AD9434
O
500
400
300
200
100
0
–100
–200
–300
EYE DIAGRAM: VOLTAGE (mV)
–400
–500
–3 –2 –1 012 3
TIME (ns)
14
12
10
8
6
4
TIE JITTER HISTOGRAM (Hits)
2
0
–40–2002040
TIME (ps)
Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
than 24 Inches on Standard FR-4, AD9434-500
600
400
200
0
12
10
8
6
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR+ and OR− (OR±)
are digital outputs that are updated along with the data output
corresponding to the particular sampled input voltage. Thus,
OR± has the same pipeline latency as the digital data. OR± is
low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 51. OR± remains high until the analog
input returns to within the input range and another conversion
is completed. By logically AND’ing OR± with the MSB and its
complement, overrange high or underrange low conditions can
be detected.
09383-020
R± DATA OUTPUT S
1
1111
1111
1111
1111
0000
0000
0000
1111
1111
1110
0001
0000
0000
0
1111
0
1111
0
0000
0
0000
1
0000
OR±
–FS + 1/2 LSB
–FS – 1/2 L SB
Figure 51. OR± Relation to Input Voltage and Output Data
+FS – 1 LSB
+FS–FS
+FS – 1/2 L SB
09383-022
EYE DIAGRAM: VOLTAGE (mV)
–200
–400
–600
–3 –2 –1
0123
TIME (ns)
4
TIE JITTER HISTOGRAM (Hits)
2
0
–100
010
TIME (ps)
0
Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9434-500
The format of the output data is offset binary by default. An
example of the output coding format can be found in Tab l e 1 2 .
If it is desired to change the output data format to twos complement, see the AD9434 Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9434. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data
rate mode (SDR), data is clocked out of the AD9434 and must
be captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9434 and must be
captured on the rising and falling edges of the DCO. See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
Output Data Rate and Pinout Configuration
The output data of the AD9434 can be configured to drive 12
pairs of LVDS outputs at the same rate as the input clock signal
(SDR mode), or six pairs of LVDS outputs at 2× the rate of the
input clock signal (DDR mode). SDR is the default mode; the
device can be reconfigured for DDR by setting Bit 3 in Register 14
(see Tabl e 13 ).
TIMING
The AD9434 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation delay (t
) after the rising edge of the clock signal.
PD
Minimize the length of the output data lines and loads placed
09383-021
on them to reduce transients within the AD9434. These transients can degrade the dynamic performance of the converter.
The AD9434 also provides a data clock output (DCO) intended
for capturing the data in an external register. The data outputs are
valid on the rising edge of DCO.
The lowest conversion rate of the AD9434 is 50 MSPS. At clock
rates below 1 MSPS, the AD9434 assumes the standby mode.
VREF
The AD9434 VREF pin (Pin 31) allows the user to monitor the
on-board voltage reference, or provide an external reference
(requires configuration through the SPI). The three optional
settings are internal V
export V
, and import V
REF
(pin is connected to 20 kΩ to ground),
REF
. Do not attach a bypass capacitor
REF
to this pin. VREF is internally compensated and additional
loading may impact performance.
AD9434 CONFIGURATION USING THE SPI
The AD9434 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
1-byte words. Each byte can be further divided into fields,
which are documented in the Memory Map section.
Rev. A | Page 22 of 28
Page 23
AD9434
There are three pins that define the serial port interface (SPI) to
this particular ADC. They are the SCLK/DFS, SDIO, and CSB
pins. The SCLK/DFS (serial clock) is used to synchronize the
read and write data presented to the ADC. The SDIO (serial
data input/output) is a dual-purpose pin that allows data to be
sent to and read from the internal ADC memory map registers.
The CSB is an active low control that enables or disables the
read and write cycles (see Tab l e 9).
USING THE AD9434 TO REPLACE THE AD9230
The AD9434 can be used to replace the AD9230 in many
applications. In these designs, the user should consider these
important differences:
•Pin 28 is a DNC (do not connect) on the AD9434, and
should be left floating. The reset functionality of the
AD9230 is not available through an external pin, but is
available through the SPI interface.
•Pin 31 is the interface to the AD9434 reference circuit. It
can be used to monitor the internal reference or provide an
external reference voltage (nominally 0.5 V). If the internal
reference is used, then this pin can float. The RBIAS function of the AD9230is not necessary with the AD9434.
•The input voltage range of the AD9434 is nominally
1.5 V p-p, whereas the AD9230 input range is 1.25 V p-p.
Table 9. Serial Port Pins
Mnemonic Function
SCLK
SDIO
CSB
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 52
and Tabl e 11 .
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
SCLK (serial clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select) is an active low control that
gates the read and write cycles.
the W0 and W1 bits, which is one or more bytes of data. All
data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether this is a read or write command. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI at www.analog.com.
HARDWARE INTERFACE
The pins described in Ta b l e 9 comprise the physical interface
between the programming device of the user and the serial port
of the AD9434. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during the write phase and as an
output during readback.
This interface is flexible enough to be controlled by either
PROMs or PIC® mirocontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device poweron. The Configuration Without the SPI section describes the
strappable functions supported on the AD9434.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SCLK/DFS pin can alternately serve as a standalone CMOScompatible control pin. In this mode, connect the CSB pin to
AVDD, which disables the serial port interface.
Each row in the memory map table (see Ta b le 1 3 ) has eight
address locations. The memory map is roughly divided into
three sections: chip configuration register map (Address 0x00 to
Address 0x02), transfer register map (Address 0xFF), and ADC
functions register map (Address 0x08 to Address 0x2A).
The Addr. (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x2A, OVR_CONFIG, has a hexadecimal default value
of 0x01. This means that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0,
Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in
binary. The default value enables the OR± output. Overwriting
this default so that Bit 0 = 0 disables the OR± output. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High-Speed ADCs via SPI® at
www.analog.com.
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than with the default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Exiting out of reset, critical registers are preloaded with default
values. These values are indicated in Tab le 1 3. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”