10-Bit, 210 MSPS
a
FEATURES
SNR = 54 dB with 99 MHz Analog Input
500 MHz Analog Bandwidth
On-Chip Reference and Track/Hold
1.5 V p-p Differential Analog Input Range
5.0 V and 3.3 V Supply Operation
3.3 V CMOS/TTL Outputs
Power: 2.1 W Typical at 210 MSPS
Demultiplexed Outputs Each at 105 MSPS
Output Data Format Option
Data Sync Input and Data Clock Output Provided
Interleaved or Parallel Data Output Option
APPLICATIONS
Communications and Radar
Local Multipoint Distribution Service (LMDS)
High-End Imaging Systems and Projectors
Cable Reverse Path
Point-to-Point Radio Link
A
A
DS
DS
ENCODE
ENCODE
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
IN
IN
REFINREF
REFERENCE
T/H
TIMING AND
SYNCHRONIZATION
DFS I/P
OUT
ADC
10-BIT
CORE
AGND
10
AD9410
V
DGND
D
AD9410
PORT
A
PORT
B
V
V
DD
CC
OR
A
10
D9A–D0
A
OR
B
10
D9B–D0
B
DCO
DCO
GENERAL DESCRIPTION
The AD9410 is a 10-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is optimized for high-speed conversion and ease of use. The product
operates at a 210 MSPS conversion rate, with outstanding
dynamic performance over its full operating range.
The ADC requires a 5.0 V and 3.3 V power supply and up to a
210 MHz differential clock input for full performance operation.
No external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS-compatible,
and separate output power supply pins also support interfacing
with 3.3 V logic.
The clock input is differential and TTL/CMOS-compatible. The
10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V)
supplies. Two output buses support demultiplexed data up to
105 MSPS rates, and binary or two’s complement output coding
format is available. A data sync function is provided for timingdependent applications. An output clock simplifies interfacing to
external logic. The output data bus timing is selectable for parallel
or interleaved mode, allowing for flexibility in latching output data.
Fabricated on an advanced BiCMOS process, the AD9410
is available in an 80-lead surface-mount plastic package
(PowerQuad
®
2) specified over the industrial temperature range
(–40°C to +85°C).
PRODUCT HIGHLIGHTS
High Resolution at High Speed—The architecture is specifically
designed to support conversion up to 210 MSPS with outstanding dynamic performance.
Demultiplexed Output—Output data is decimated by two and
provided on two data ports for ease of data transport.
Output Data Clock—The AD9410 provides an output data
clock synchronous with the output data, simplifying the timing
between data and other logic.
Data Synchronization—A DS input is provided to allow for
synchronization of two or more AD9410s in a system, or
to synchronize data to a specific output port in a single
AD9410 system.
PowerQuad is a registered trademark of Amkor Electronics, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD9410–SPECIFICATIONS
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
DC SPECIFICATIONS
Parameter Temp Level Min Typ Max Unit
RESOLUTION 10 Bits
DC ACCURACY
No Missing Codes
Differential Nonlinearity 25°C I –1.0 ±0.5 +1.25 LSB
Integral Nonlinearity 25°C I –2.5 ±1.65 +2.5 LSB
Gain Error 25°C I –6.0 0 +6.0 % FS
Gain Tempco Full V 130 ppm/°C
ANALOG INPUT
Input Voltage Range (With Respect to AIN) Full V ±768 mV p-p
Common-Mode Voltage Full V 3.0 V
Input Offset Voltage 25°C I –15 +3 +15 mV
Reference Voltage Full VI 2.4 2.5 2.6 V
Reference Tempco Full V 50 ppm/°C
Input Resistance Full VI 610 875 1250 Ω
Input Capacitance 25°CV 3 pF
Analog Bandwidth, Full Power 25°C V 500 MHz
POWER SUPPLY
Power Dissipation AC
Power Dissipation DC
3
I
VCC
3
I
VD
Power Supply Rejection Ratio PSRR 25°C I –7.5 +0.5 +7.5 mV/V
NOTES
1
Package heat slug should be attached when operating at greater than 70°C ambient temperature.
2
Encode = 210 MSPS, AIN = –0.5 dBFS 10 MHz sine wave, I
3
Encode = 210 MSPS, AIN = dc, outputs not switching.
Specifications subject to change without notice.
1
TA = 25C; unless otherwise noted.)
2
3
Test
Full IV Guaranteed
Full VI –1.0 +1.5 LSB
Full VI –3.0 +3.0 LSB
Full VI –20 +20 mV
25°C V 2.1 W
Full VI 2.0 2.4 W
Full VI 128 145 mA
Full VI 401 480 mA
= 31 mA typical at C
VDD
LOAD
= 5 pF.
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock
SWITCHING SPECIFICATIONS
input = 210 MSPS; TA = 25C; unless otherwise noted.)
Test
Parameter Temp Level Min Typ Max Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 210 MSPS
Minimum Conversion Rate Full IV 100 MSPS
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t
)25°C V 1.0 ns
A
)25°C IV 1.2 2.4 ns
EH
)25°C IV 1.2 2.4 ns
EL
Aperture Uncertainty (Jitter) 25°C V 0.65 ps rms
Output Valid Time (t
Output Propagation Delay (t
Output Rise Time (t
Output Fall Time (t
CLKOUT Propagation Delay
Data to DCO Skew (t
DS Setup Time (t
DS Hold Time (t
) Full VI 3.0 ns
V
)25°C V 1.8 ns
R
)25°C V 1.4 ns
F
PD–tCPD
SDS
) Full IV 0 ns
HDS
) Full VI 7.4 ns
PD
1
(t
) Full VI 2.6 4.8 6.4 ns
CPD
) Full IV 0 1 2 ns
) Full IV 0.5 ns
Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles
Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles
NOTES
1
C
= 5 pF.
LOAD
Specifications subject to change without notice.
–2–
REV. 0
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS;
AD9410
DIGITAL SPECIFICATIONS
Parameter Temp Level Min Typ Max Unit
DIGITAL INPUTS
DFS, Input Logic “1” Voltage Full IV 4 V
DFS, Input Logic “0” Voltage Full IV 1 V
DFS, Input Logic “1” Current Full V 50 µA
DFS, Input Logic “0” Current Full V 50 µA
I/P Input Logic “1” Current
I/P Input Logic “0” Current
ENCODE, ENCODE Differential Input Voltage Full IV 0.4 V
ENCODE, ENCODE Differential Input Resistance Full V 1.6 kΩ
ENCODE, ENCODE Common-Mode Input Voltage
DS, DS Differential Input Voltage Full IV 0.4 V
DS, DS Common-Mode Input Voltage Full V 1.5 V
Digital Input Pin Capacitance 25°CV 3 pF
DIGITAL OUTPUTS
Logic “1” Voltage (V
Logic “0” Voltage (V
Output Coding Binary or Two’s Complement
NOTES
1
I/P pin Logic “1” = 5 V, Logic “0” = GND. It is recommended to place a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic “1” to limit input current.
2
See Encode Input section in Applications section.
Specifications subject to change without notice.
AC SPECIFICATIONS
1
1
= 3.3 V) Full VI V
DD
= 3.3 V) Full VI 0.05 V
DD
(V
TA = 25C; unless otherwise noted.)
Clock input = 210 MSPS; TA = 25C; unless otherwise noted.)
Test
Full V 400 µA
Full V 1 µA
2
Full V 1.5 V
– 0.05 V
DD
= 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
DD
Test
Parameter Temp Level Min Typ Max Unit
DYNAMIC PERFORMANCE
Transient Response 25°CV 2 ns
Overvoltage Recovery Time 25°CV 2 ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
= 10.3 MHz 25°C I 52.5 55 dB
IN
= 82 MHz 25°C I 52 54 dB
f
IN
f
= 160 MHz 25°CV 53 dB
IN
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
f
= 10.3 MHz 25°C I 51 54 dB
IN
f
= 82 MHz 25°C I 50 53 dB
IN
= 160 MHz 25°CV 52 dB
f
IN
Effective Number of Bits
f
= 10.3 MHz 25°C I 8.3 8.8 Bits
IN
f
= 82 MHz 25°C I 8.1 8.6 Bits
IN
= 160 MHz 25°C V 8.4 Bits
f
IN
Second Harmonic Distortion
f
= 10.3 MHz 25°C I –56 –65 dBc
IN
f
= 82 MHz 25°C I –55 –63 dBc
IN
= 160 MHz 25°C V –65 dBc
f
IN
Third Harmonic Distortion
f
= 10.3 MHz 25°C I –58 –69 dBc
IN
f
= 82 MHz 25°C I –57 –67 dBc
IN
= 160 MHz 25°C V –62 dBc
f
IN
Spurious Free Dynamic Range (SFDR)
f
= 10.3 MHz 25°C I 56 61 dBc
IN
f
= 82 MHz 25°C I 54 60 dBc
IN
= 160 MHz 25°C V 58 dBc
f
IN
Two-Tone Intermod Distortion IMD
f
= 80.3 MHz, f
IN1
NOTES
1
IN1, IN2 level = –7 dBFS.
Specifications subject to change without notice.
= 81.3 MHz 25°C V 58 dBFS
IN2
REV. 0
1
–3–
AD9410
DATA N+3DATA N+1
V
t
DATA N+1
SAMPLE N+5
SAMPLE N+4
SAMPLE N+3
SAMPLE N+6
SAMPLE N+2
SAMPLE N+1
S
1/f
DATA N DATA N+2
PD
t
INVALID
INVALID
INVALID
INVALID
SDS
t
INTERLEAVED DATA OUT
INVALID INVALID INVALID INVALID
PARALLEL DATA OUT
DATA N DATA N+2
t
INVALIDINVALIDINVALID
CPD
SAMPLE N
SAMPLE N–1
AIN
EL
t
A
t
EH
t
HDS
t
SAMPLE N–2
DS
DS
ENCODE
ENCODE
STATIC INVALID INVALID
D7D0
PORT A
STATIC
D7D0
PORT B
STATIC
D7D0
PORT A
STATIC
D7D0
PORT B
DCO
STATIC
DCO
Figure 1. Timing Diagram
–4–
REV. 0
AD9410
ABSOLUTE MAXIMUM RATINGS
VD, V
CC, VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
1
+ 0.5 V
CC
+ 0.5 V
DD
+ 0.5 V
D
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability. Stresses
above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied.
2
Typical θJA = 22°C/W (heat slug not soldered), typical θJA = 16°C/W (heat slug
soldered), for multilayer board in still air with solid ground plane.
2
. . . . . . . . . . . . . . . . 150°C
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9410BSQ –40°C to +85°C PowerQuad 2 SQ-80
AD9410/PCB 25°C Evaluation Board
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9410 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD9410
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24, AGND Analog Ground.
27, 28, 29, 30, 71, 72, 73, 74, 77, 78
3, 7, 14, 15 V
4 REF
5 REF
CC
OUT
IN
6 DNC Do Not Connect.
10 A
IN
11 AIN Analog Input—Complement.
18 ENCODE Clock Input—True.
19 ENCODE Clock Input—Complement.
22 DS Data Sync (Input)—True. Tie LOW if not used.
23 DS Data Sync (Input)—Complement. Float and decouple with 0.1 µF
25, 26, 31, 32, 69, 70, 75, 76 V
D
33, 40, 49, 52, 59, 68 DGND Digital Ground.
34, 41, 48, 53, 60, 67 V
35–39 D
42–46 D
47 OR
DD
B0–DB4
B5–DB9
B
50 DCO Clock Output—Complement.
51 DCO Clock Output—True.
54–58 D
61–65 D
66 OR
A0–DA4
A5–DA9
A
79 DFS Data Format Select. HIGH = Two’s Complement, LOW = Binary.
80 I/P Interleaved or Parallel Output Mode. Low = Parallel Mode, High =
5 V Supply. (Regulate to within ±5%.)
Internal Reference Output.
Internal Reference Input.
Analog Input—True.
capacitor if not used.
3.3 V Analog Supply. (Regulate to within ±5%.)
3.3 V Digital Output Supply. (2.5 V to 3.6 V)
Digital Data Output for Channel B. (LSB = DB0.)
Digital Data Output for Channel B. (MSB = DB9.)
Data Overrange for Channel B.
Digital Data Output for Channel A. (LSB = DA0.)
Digital Data Output for Channel A. (MSB = DA9.)
Data Overrange for Channel A.
Interleaved Mode. If tying high, use a current limiting series resistor
(2.5 kΩ) to the 5 V supply.
–6–
REV. 0
1
AGND
AGND
2
V
3
CC
4
REF
OUT
5
REF
IN
6
DNC
V
7
CC
AGND
8
AGND
9
10
A
IN
A
11
IN
AGND
12
AGND
13
14
V
CC
15
V
CC
AGND
16
17
AGND
ENCODE
18
19
ENCODE
20
AGND
DNC DO NOT CONNECT
PIN CONFIGURATION
(MSB)
A
A9
VDDDGND
AGND
VDV
VDVDAGND
D
DGND
DD
V
OR
B0
DB1DB2DB3D
B4
(LSB) D
AGND
AGND
AGND
AGND
VDV
VDVDAGND
80-Lead PowerQuad2
D
AGND
AGND
AD9410
TOP VIEW
(Not to Scale)
AGND
AGND
DFS
I/P
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PIN 1
IDENTIFIER
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DS
DS
AGND
DA5DA6DA7DA8D
DGND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
DD
DGND
D
A4
D
A3
D
A2
D
A1
D
A0
V
DD
DGND
DCO
DCO
DGND
V
DD
OR
B
D
B9
D
B8
D
B7
D
B6
D
B5
V
DD
AD9410
(LSB)
(MSB)
REV. 0
–7–
AD9410
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage
is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of
phase. Peak-to-peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement
again. The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SINAD based on the equation.
ENOB
SINAD dB
MEASURED
=
– . log
176 20
+
.
602
Full Scale Amplitude
Input Amplitude
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implications of changing t
in text. At a given clock rate, these specs
ENCH
define an acceptable ENCODE duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
2
POWER
FULL SCALE
V
FULL SCALE
Z
INPUT
10
log
.
0 001
=
rms
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least-square curve fit.
–8–
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Noise (For Any Range Within the ADC)
VZ
=××
NOISE
|| .0 001 10
−
FS SIGNAL
dBm dBFS
10
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and SIGNAL is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Transient Response Time
Transient response time is defined as the time it takes for the
ADC to reacquire the analog input after a transient from 10%
above negative full scale to 10% below positive full scale.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
REV. 0
AD9410
Table I. Output Coding (V
= 2.5 V)
REF
Digital Outputs Digital Outputs
Step AIN–AIN Offset Binary Two’s Complement ORA, OR
B
> 0.768 11 1111 1111 01 1111 1111 1
1023 0.768 11 1111 1111 01 1111 1111 0
•• • • •
•• • • •
513 0.0015 10 0000 0001 00 0000 0001 0
512 0.0 10 0000 0000 00 0000 0000 0
511 –0.0015 01 1111 1111 11 1111 1111 0
•• • • •
•• • • •
0 –0.768 00 0000 0000 10 0000 0000 0
< –0.768 00 0000 0000 10 0000 0000 1
V
CC
1.5k
A
IN
2.25k
1.5k
2.25k
A
IN
V
CC
VREFOUT
Figure 6. Equivalent Reference Output Circuit
Figure 2. Equivalent Analog Input Circuit
V
CC
VREFIN
Figure 3. Equivalent Reference Input Circuit
V
CC
ENCODE
450 450
17k
100 100
8k 8k
17k
Figure 4 Equivalent Encode Input Circuit
V
DD
ENCODE
DFS
100k
Figure 7. Equivalent DFS Input Circuit
17.5k
300
7.5k
DS
300
Figure 8. Equivalent DS Input Circuit
I/P
300
17.5k
V
CC
V
CC
DS
V
CC
REV. 0
DIGITAL
OUTPUT
Figure 5. Equivalent Digital Output Circuit
7.5k
Figure 9. Equivalent I/P Input Circuit
–9–
AD9410
–Typical Performance Characteristics
–20
–40
–60
dB
–80
–100
–120
0
0
ENCODE = 210MSPS
A
= 40MHz @ –0.5dBFS
IN
SNR = 54.5dB
SINAD = 53.5dB
MHz
105
TPC 1. Single Tone at 40 MHz, Encode = 210 MSPS
0
ENCODE = 210MSPS
A
= 100MHz @ –0.5dBFS
IN
–20
SNR = 53.5dB
SINAD = 52.5dB
–40
–60
dB
–80
–100
–120
0
MHz
105
TPC 2. Single Tone at 100 MHz, Encode = 210 MSPS
55
54
dB
53
52
51
50
49
48
47
46
45
0
50 100 150 200 250
AIN – MHz
SNR
SINAD
TPC 4. SNR/SINAD vs. AIN Encode = 210 MSPS
55.0
dB
54.5
54.0
53.5
53.0
52.5
52.0
51.5
51.0
50.5
50.0
120 140 160 200 240
100
SNR
SINAD
180 220
MHz
TPC 5. SNR/SINAD vs. FS AIN = 70 MHz
–20
–40
–60
dB
–80
–100
–120
0
0
ENCODE = 210MSPS
A
= 160MHz @ –0.5dBFS
IN
SNR = 53dB
SINAD = 52dB
MHz
105
TPC 3. Single Tone at 160 MHz, Encode = 210 MSPS
–10–
60
dB
55
50
45
40
35
30
0.5 1.0 1.5 2.5 4.0
0
SNR
SINAD
2.0 3.5
ns
3.0
TPC 6. SNR/SINAD vs. Encode Positive Pulsewidth
(F
= 210 MSPS, AIN = 70 MHz)
S
REV. 0
0
ANALOG SUPPLY
2.48
4.0
VOLTS
2.47
2.46
4.2 4.4 4.6 5.0 5.6
2.51
2.52
2.50
4.8 5.4
2.49
5.2
ENCODE = 210MSPS
1, AIN2 = –7dBFS
A
IN
SFDR = 62dBFS
–20
–40
–60
dB
–80
–100
AD9410
–120
0
MHz
105
TPC 7. Two Tone Test AIN 1 = 80.3 MHz, AIN 2 = 81.3 MHz
55.5
55.0
54.5
dB
54.0
53.5
53.0
52.5
52.0
51.5
–20 0 20 40 60 80 100 120
–40
TEMPERATURE – C
SNR
SINAD
TPC 8. SNR/SINAD vs. Temperature,
Encode = 210 MSPS, A
74
= 70 MHz
IN
TPC 10. VREF
460
410
360
310
260
mA
210
160
110
60
10
100
120 140 160 200
vs. Analog 5 V Supply
OUT
IAhi3
IAhi5
Ivdd
MSPS
180
TPC 11. Power Supply Currents vs. Encode
2.55
220
72
H2
H3
–20 0 20 40 60 80 100 120
TEMPERATURE – C
dB
70
68
66
64
62
60
58
–40
TPC 9. Second and Third Harmonics vs. Temperature;
A
= 70 MHz, Encode = 210 MSPS
IN
REV. 0
–11–
2.50
2.45
2.40
VOLTS
2.35
2.30
2.25
0
0.5 1.0 2.01.5
TPC 12. VREF
mA
OUT
vs. I
2.5
LOAD
AD9410
2.503
2.502
2.501
2.500
VOLTS
2.499
2.498
2.497
2.496
–40
–20 0 4020 60
TPC 13. VREF
TEMPERATURE – C
vs. Temperature
OUT
5.1
T
4.9
4.7
4.5
ns
4.3
4.1
3.9
–40
80
–20 0 4020 60
TPC 14. TPD, TV, T
TEMPERATURE – C
vs. Temperature
CPD
PD
T
V
T
CPD
80
–12–
REV. 0
AD9410
APPLICATION NOTES
THEORY OF OPERATION
The AD9410 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantization by the flash 10-bit core. For ease of use the part includes
an onboard reference and input logic that accepts TTL, CMOS,
or PECL levels.
USING THE AD9410
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/Hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9410, and the
user is advised to give commensurate thought to the clock source.
To limit SNR degradation to less than 1 dB, a clock source with
less than 1.25 ps rms jitter is required for sampling at Nyquist.
(Valpey Fisher VF561 is an example.) Note that required jitter
accuracy is a function of input frequency and amplitude. Consult
Analog Devices’ application note AN-501, “Aperture Uncertainty and ADC System Performance,” for more information.
The ENCODE input is fully TTL/CMOS-compatible. The
clock input can be driven differentially or with a single-ended
signal. Best performance will be obtained when driving the clock
differentially. Both ENCODE inputs are self-biased to 1/3 × V
by a high impedance resistor divider. (See Equivalent Circuits
section.) Single-ended clocking, which may be appropriate for
lower frequency or nondemanding applications, is accomplished
by driving the ENCODE input directly and placing a 0.1 µF
capacitor at ENCODE.
TTL/CMOS
GATE
0.1F
ENCODE
ENCODE
AD9410
Figure 10. Driving Single-Ended Encode Input at
TTL/CMOS Levels
An example where the clock is obtained from a PECL driver is
shown in Figure 11. Note that the PECL driver is ac-coupled to
the ENCODE inputs to minimize input current loading. The
AD9410 can be dc-coupled to PECL logic levels resulting in the
ENCODE input currents increasing to approximately 8 mA
typically. This is due to the difference in dc bias between the
ENCODE inputs and a PECL driver. (See Equivalent Circuits section.)
PECL
GATE
GND
0.1F
F
0.1
510510
ENCODE
ENCODE
AD9410
Figure 11. Driving the Encode Inputs Differentially
CC
Analog Input
The analog input to the AD9410 is a differential buffer. For
best dynamic performance, impedances at A
and AIN should
IN
match. The analog input has been optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance will degrade
significantly if the analog input is driven with a single-ended
signal. A wideband transformer such as Minicircuits ADT1-1WT
can be used to provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both
analog inputs are self-biased by an on-chip resistor divider to a
nominal 3 V. (See Equivalent Circuits section.)
Special care was taken in the design of the Analog Input section
of the AD9410 to prevent damage and corruption of data when the
input is overdriven. The nominal input range is 1.5 V diff p-p.
The nominal differential input range is 768 mV p-p × 2.
A
3.384
3.000
VOLTS
2.616
IN
A
IN
Figure 12. Typical Analog Input Levels
Digital Outputs
The digital outputs are TTL/CMOS-compatible for lower power
consumption. The outputs are biased from a separate supply
(V
), allowing easy interface to external logic. The outputs are
DD
CMOS devices which will swing from ground to V
(with no
DD
dc load). It is recommended to minimize the capacitive load the
ADC drives by keeping the output traces short (<1 inch, for a
total C
< 5 pF). It is also recommended to place low value
LOAD
(20 Ω) series damping resistors on the data lines to reduce switching transient effects on performance.
Clock Outputs (DCO, DCO)
The input ENCODE is divided by two and available off-chip at
DCO and DCO. These clocks can facilitate latching off-chip,
providing a low skew clocking solution (see timing diagram).
These clocks can also be used in multiple AD9410 systems to
synchronize the ADCs. Depending on application, DCO or
DCO can be buffered and used to drive the DS inputs on a
second AD9410, ensuring synchronization. The on-chip clock
buffers should not drive more than 5 pF–7 pF of capacitance to
limit switching transient effects on performance.
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9410 (VREF OUT). The input range can be adjusted by
varying the reference voltage. No appreciable degradation in
performance occurs when the reference is adjusted ±5%. The fullscale range of the ADC tracks reference voltage changes linearly
within the ±5% tolerance.
REV. 0
–13–
AD9410
Timing
The AD9410 provides latched data outputs, with six pipeline
delays in interleaved mode (see Figure 1). In parallel mode, the
A Port has one additional cycle of latency added on-chip to line
up transitions at the data ports—resulting in a latency of seven
cycles for the A Port. The length of the output data lines and
loads placed on them should be minimized to reduce transients
within the AD9410; these transients can detract from the
converter’s dynamic performance.
The minimum guaranteed conversion rate of the AD9410 is
100 MSPS. At internal clock rates below 100 MSPS, dynamic
performance may degrade. Note that lower effective sampling
rates can be obtained simply by sampling just one output port—
decimating the output by two. Lower sampling frequencies can
also be accommodated by restricting the duty cycle of the clock
such that the clock high pulsewidth is a maximum of 5 ns.
EVALUATION BOARD
The AD9410 evaluation board offers an easy way to test the
AD9410. The board requires an analog input, clock, and 3 V,
5 V power supplies. The digital outputs and output clocks are
available at a standard 80-lead header P2, P3. The board has
several different modes of operation, and is shipped in the following configuration:
•
Output Timing = Parallel Mode
•
Output Format = Offset Binary
•
Internal Voltage Reference
Power Connector
Power is supplied to the board via detachable 4-pin power strips
P1, P4, P5.
VDAC – Optional DAC Supply Input (3.3 V)
EXT REF – Optional External VREF Input (2.5 V)
V
– Logic Supply (3.3 V)
DD
3.3 VA – Analog Supply (3.3 V)
5 V – Analog Supply (5 V)
Analog Inputs
The evaluation board accepts a 1.5 V p-p analog input signal
centered at ground at SMB J8. This input is terminated to 50 Ω
on the board at the transformer secondary, but can be terminated at the SMB if an alternative termination is desired. The
input is ac-coupled prior to the transformer. The transformer is
band limited to frequencies between approximately 1 MHz and
400 MHz.
Encode
The encode input to the board is at SMB connector J1. The
input is terminated on the board with 50 Ω to ground. The
(>0.5 V p-p) input is ac-coupled and drives a high-speed
differential line receiver (MC10EL16). This receiver provides
sub- nanosecond rise times at its outputs—a requirement for
the ADC clock inputs for optimum performance. The EL16
outputs are PECL levels and are ac-coupled to meet the commonmode dc levels at the AD9410 encode inputs.
Data Sync (DS)
The Data Sync input, DS, can be used in applications requiring that a given sample will appear at a specific output Port A or
B. When DS is held high, the ADC data outputs and clock do not
switch and are held static. Synchronization is accomplished by the
assertion (falling edge) of DS, within the timing constraints
and T
T
SDS
synchronization T
required setup time (T
relative to an encode rising edge. (On initial
HDS
is not relevant.) If DS falls within the
HDS
) before a given encode rising edge N,
SDS
the analog value at that point in time will be digitized and available at Port B six cycles later (interleaved mode). The very next
sample, N+1, will be sampled by the next rising encode edge and
available at Port A six cycles after that encode edge (interleaved
mode). In dual parallel mode the A Port has a seven cycle latency,
the B Port has a six cycle latency, but data is available at the
same time.
REFERENCE
The AD9410 has an on-chip reference of 2.5 V available at
REF
to the REF
(Pin 4). Most applications will simply tie this output
OUT
input (Pin 5). This is accomplished by placing a
IN
jumper at E1, E6. An external reference can be used placing a
jumper at E1, E3.
Output Timing
The chip has two timing modes (see timing diagram). Interleaved mode is selected by Jumper E11, E7. Parallel mode is
selected by Jumper E11, E14.
Data Format Select
Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 79) low at E12, E10 sets the output
format to be offset binary; setting DFS high at E12, E16 sets the
output to be two’s complement.
DS Pin
The DS, DS inputs are available at SMB connectors J9X and
J10X. The board is shipped with DS pulled to ground by R26.
DS is floating (R25X is not placed).
DAC Outputs
Each channel is reconstructed by an on-board dual channel
DAC, an AD9751 to assist in debug. The performance of the
DAC has not been optimized and will not give an accurate
measure of the full performance of the ADC. It is a current
output DAC with on-board 50 Ω termination resistors. The
outputs are available at J3 and J4.
–14–
REV. 0
AD9410
EXT
REF
J8
GND
AIN
GND
0.1F
P4
P1
P5
C7
E3
R23
50
E6
GND
GND
5V
1
2
3
4
1
2
3
4
1
2
3
4
E1
C1
10F
3.3VA
VDAC
GND
EXT REF
GND
GND
GND
VDD/3.3V
GND
3.3VA
GND
5V
GND
GND
C28
0.1F
T1
1
2
3
1 : 1
C25
0.1F
GND
C2
10F
5V
6
5
4
GND
R27
50
GND
VDD
5V
0.1F
5V
GND
C27
GND
C3
10F
100
100
GND
C26
0.1F
R24
EXT REF
R3
C24
0.1F
C5
10F
VDAC
100
E7
E11
E14
1
GND
2
GND
3
4
5
6
7
8
GND
9
10
11
12
13
14
15
5V
16
17
18
19
20
GND
GND
GND
ENCT
ENCC
C4
10F
GND
R6
E10
AGND
AGND
V
CC
REF
REF
DNC
V
CC
AGND
AGND
A
IN
A
IN
AGND
AGND
V
CC
V
CC
AGND
AGND
ENCODE
ENCODE
AGND
5V
E16
E12
80
I/P
OUT
IN
21
J1
GND
50
R4
2.5k
GND
78 77
79
DFS
AGND
AGND
DSDSAGND
23
22
5V
5V
R19
8.2k
C6
R8
0.1F
R18
24k
R14
8.2k
R9
24k
MC10EL16
1
NC
2
D
3
D
4
VBB
VCC
Q
U1
Q
VEE
GND
GND GND
VDD
V
GND
DVD
DGND
C14
0.1F
DAOR
DD
V
OR
A
GND
DA9
DA8
A9
3.3VA
C10
0.1F
3.3VA
GND
C11
R7
100
3.3VA
GND
0.1F
GND
3.3VA
GND
767574 73727170696867666564636261
DVD
V
AGND
AGND
AGND
AGND
AGND
AD9410
U3
DVD
AGND
AGND
AGND
AGND
V
27
25
24
28
26
29
VDVDDGND
31
30
VDDDB0DB1DB2DB3DB4DGND
36
3433
32
35
GND
8
7
6
5
C40
0.1F
GND
GND
R11
330
C7
0.1F
5V
ENCT
ENCC
C8
R15
0.1F
330
GND
NOTE:
R3, R6, R7, R24 OPTIONAL
DA7
(CAN BE ZERO )
DA6
DA5
GND
DA5DA6DA7DA8D
V
DGND
D
D
D
D
D
V
DGND
DCO
DCO
DGND
V
OR
D
D
D
D
D
V
393837
40
C12
0.1F
60
DD
A4
A3
A2
A1
A0
DD
DD
B9
B8
B7
B6
B5
DD
VDD
59
GND
58
DA4
57
DA3
56
DA2
55
DA1
54
DA0
53
52
GND
51
DCOT
50
DCOC
49
GND
48
47
DBOR
B
46
DB9
45
DB8
44
DB7
43
DB6
42
DB5
41
C18
0.1F
VDD
GND
GND
VDD
C21
0.1F
C22
0.1F
VDD
GND
REV. 0
J9X
GND
R26
50
GND
J10X
GND
R25X
50
3.3VA
GND
3.3VA
Figure 13a. PCB Schematic
–15–
GND
C15
0.1F
C16
0.1F
GND
GND
3.3VA
3.3VA
GND
VDD
DB0
C19
0.1F
DB1
DB2
DB3
DB4
GND
AD9410
GND
DRA
39
37
GND
35
DM9
33
DM8
31
DM7
29
DM6
27
DM5
25
DM4
23
DM3
21
DM2
19
DM1
17
DM0
15
GND
13
GND
11
GND
9
GND
7
GND
5
GND
3
GND
1
GND
39
DRB
37
GND
35
DN9
33
DN8
31
DN7
29
DN6
27
DN5
25
DN4
23
DN3
21
DN2
19
DN1
17
DN0
15
GND
13
GND
11
GND
9
GND
7
GND
5
GND
3
GND
1
40
38
32
34
36
DM9
DM8
15
14
16
1B2B3B4B5B6B7B
RPACK
1A2A3A4A5A6A7A
3
2
1
D9A
D8A
GND
P2
30
DM7
13
28
DM6
12
26
DM5
11
24
DM4
10
22
DM3
9
8B
18
20
R34
8A
4
5
D7A
D6A
C37
0.1F
74LCXB21
8
6
7
D5A
D4A
D3A
VDD
D9A
D8A
D7A
D6A
20
21
23
24
22
Y0Y1Y2Y3Y4Y5Y6Y7Y8
VCC
DEX0X1X2X3X4X5X6X7
1
GND
2
DX9
3
DX8
4
DX7
5
DX6
12
14
16
DM2
16
DM1
15
10
DM0
14
1B2B3B4B5B6B7B
RPACK
1A2A3A4A5A6A7A
3
2
1
D2A
D1A
D0A
D5A
D4A
D3A
D2A
D1A
15
16
17
19
18
U4
X8
9
8
7
6
DX5
DX4
DX3
DX2
10
DX1
8
NC
13
4
NC
R36
D0A
14
Y9
X9
11
DX0
6
NC
12
5
NC
CLKA
13
CLK
GND
12
GND
11
6
NC
NC
4
2
NC
10
7
NC
HEADER 40
GND
NC
9
8B
8A
8
NC
40
38
32
34
36
NCNCNCNCNC
16
14
15
1B2B3B4B5B6B7B
RPACK
1A2A3A4A5A6A7A
1
3
2
NCNCNCNCNC
P3
28
30
12
13
22
24
26
DN9
DN8
9
10
11
8B
R28
8A
7
6
4
GND
5
C39
74LCXB21
8
D9B
D8B
VDD
0.1F
D9B
D8B
21
23
24
22
Y0Y1Y2
VCC
DEX0X1X2X3X4X5X6X7
1
GND
2
DY9
3
DY8
4
16
18
20
DN7
16
1B2B3B4B5B6B7B
RPACK
1A2A3A4A5A6A7A
1
D7B
D7B
D6B
D5B
20
19
Y3Y4Y5Y6Y7
U5
7
6
5
DY7
DY6
DY5
14
D4B
18
DY4
12
DN6
15
2
D6B
D3B
17
8
DY3
DN5
14
3
D5B
D2B
16
9
DY2
HEADER 40
6
8
10
2
4
GND
DN4
DN3
DN2
DN1
DN0
9
13
10
12
11
8B
R38
8A
6
D2B
CLKB
13
CLK
GND
12
GND
7
D1B
8
D0B
4
D4B
D1B
15
Y8
X8
10
DY1
5
D3B
D0B
14
Y9
X9
11
DY0
DXOR
DX9
DX8
DX7
13
14
15
16
1B2B3B4B5B6B7B
2
DA9
3
DA8
R32
4
DA7
RPACK
1A2A3A4A5A6A7A
1
DAOR
DX6
12
5
DA6
11
6
DA5 DX5
DX4
10
7
DA4
DX3
9
8B
8A
8
DA3
VDD
C32
DX2
DX1
15
16
1B
2B3B4B5B6B7B8B
RPACK
1A2A3A4A5A6A7A
2
1
DA2
DA1
0.1F
GND
DX0
14
3
DA0
R16
DCOT DCOTA
13
4
00
12
R40
5
11
6
R17
00
DCOC DCOCA
DY9
DYOR
DY8
9
10
16
1B
RPACK
8A
8
7
1A2A3A4A5A6A7A
1
13
15
12
14
2B3B4B5B6B7B8B
R29
4
3
2
5
11
6
DBOR
10
7
DB9
9
8A
8
DB8
DRA
R44
00
3
U9
74AC86
2
R2
VDD
1
DCOTA
100
E24
E17
XORA
XORA
E18
GND
4
R37
E26
VDD
DCOTA
100
6
U9
CLKA
5
XORB
E27
DY7
DY6
15
16
2B3B4B5B6B7B8B
1B
RPACK
2A3A4A5A6A7A8A
1A
2
1
DB7
DB6
R45
00
11
U9
74AC86
12
13
DCOCA
XORB
R42
100
E20
E28
GND
E19
VDD
DY5
14
3
DB5
DRB
74AC86
XORC
XORC
E21
DY4
13
4
DB4
GND
DY3
12
R39
5
DB3
9
R43
E23
VDD
DY2
DY1
10
11
7
6
DB2
DB1
8
CLKB
U9
10
XORD
DCOTA
XORD
100
E25
DY0
9
8
DB0
74AC86
E22
GND
Figure 13b. PCB Schematic (Continued)
–16–
REV. 0
AD9410
VDAC
GND
VDAC
E34
GND
E32
E33
C13
0.1F
VDAC
VDAC
DCOCA
DCOTA
GND
E35
DM9
DM8
DM7
DM6
DM5
DM4
GND
1
2
3
4
5
6
7
8
9
10
11
12
R5
392
C20
0.1F
J3
GND
J4
GND
47
48
46
GND
C33
1F
R13
392
GND
45
R12
50
GND
GND
44
R1
50
42
43
AD9751
U2
GND
41
C3
0.1F
40
VDAC
R10
2k
C23
0.1F
37
38
39
GND
GND
E2
E4
E5
E31 VDAC
E29
E30
36
35
34
33
32
31
30
29
28
27
26
25
VDAC
GND
GND
DN0
DN1
DN2
DN3
DN4
DN5
DN6
DN7
14
13
DM3
DM2
15
DM1
16
DM0
17
Figure 13c. PCB Schematic (Continued)
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
•
Verify power at IC pins.
•
Check that all jumpers are in the correct position for the
desired mode of operation.
•
Verify VREF is at 2.5 V.
24
23
22
21
20
19
18
DN8
GND
DN9
C17
0.1F
GND
VDAC
• Try running encode clock and analog input at low speeds
(10 MSPS/1 MHz) and monitor latch outputs, DAC outputs,
and ADC outputs for toggling.
The AD9410 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
REV. 0
–17–
AD9410
EVALUATION BOARD LAYOUT
Figure 14. Top Silkscreen
Figure 15. Split Power Plane
Figure 17. Bottom Components and Routing
Figure 18. Bottom Silkscreen
Figure 16. Ground Plane
–18–
Figure 19. Top Components and Routing
REV. 0
AD9410
AD9410 Evaluation Board Bill of Material
Quantity Reference Description Device Package Value
5C1–C5 Capacitor TAJD 10 µF
29 C6–C30, C32, C37, C39, C40 Capacitor 603 0.1 µF
1 C33 Capacitor 1206 1 µF
31 E1–E7, E10–E12, E14, E16–E35 Ehole
6 J1, J3, J4, J8, J9X, J10X SMB
3 P1, P4, P5 4-Pin Power 25.531.3425.0 Wieland
Connector 25.602.5453.0
2 P2, P3 40-Pin Header
7 R1, R8, R12, R23*, R25X, R26, R27 Resistor 1206 50 Ω
8 R2, R3, R4, R6, R24, R37, R42, R43 Resistor 1206 100 Ω
1 R13 Resistor 1206 392 Ω
1 R7 Resistor 1206 100 Ω
2 R9, R18 Resistor 1206 24 kΩ
1 R10 Resistor 1206 2 kΩ
2 R11, R15 Resistor 1206 330 Ω
2 R14, R19 Resistor 1206 8.2 kΩ
5 R5, R16, R17, R44, R45 Resistor 1206 0 Ω
8 R28, R29, R32, R34, R36, R38–R40 RPACK 766163220G CTS
22 Ω
1 T1 Transformer (1:1) ADT1-1WT Minicircuits
1 U1 MC10EL16 SOIC8
1 U2 AD9751 LQFP48
1 U3 AD9410 LQFP80
2 U4, U5 74LCX821 SOIC24
1 U9 74AC86 SOIC14
*Optional R23 not placed on board (50 Ω termination resistor).
REV. 0
–19–
AD9410
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead PowerQuad 2 (LQFP_ED)
(SQ-80)
0.630 (16.00) SQ
PIN 1
0.0256 (0.65)
BSC
0.551 (14.00) SQ
TOP VIEW
(PINS DOWN)
0.015 (0.38)
0.013 (0.32)
0.009 (0.22)
61
60
41
40
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
SEATING
PLANE
COPLANARITY
0.004 (0.10)
MAX
0.006 (0.15)
0.002 (0.05)
0.063 (1.60)
MAX
0.008 (0.20)
0.004 (0.09)
80
1
20
21
NOTE
The AD9410 has a conductive heat slug to help dissipate heat
and ensure reliable operation of the device over the full industrial temperature range. The slug is exposed on the bottom of
the package. It is recommended that no PCB traces or vias be
located under the package that could come in contact with the
conductive slug. Attaching the slug to a ground plane while not
required in most applications will reduce the junction temperature of the device which may be beneficial in high temperature
environments.
61
60
0.120 (3.04) 45C CHAMFER
4 PLACES
BOTTOM
VIEW
NICKEL PLATED
XX
41
40
0.413 (10.50)
0.394 (10.00) REF
0.374 (9.50)
7
0
CONTROLLING DIMENSION IN MILLIMETERS.
CENTER FIGURES ARE TYPICAL UNLESS
OTHERWISE NOTED.
80
1
0.413 (10.50)
0.394 (10.00) REF
0.374 (9.50)
20
21
C01679–4.5–10/00 (rev. 0)
–20–
PRINTED IN U.S.A.
REV. 0
Loading...