Datasheet AD9389B Datasheet (ANALOG DEVICES)

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A

T

High Performance

Preliminary Technical Data

FEATURES

General

Digital video

Digital audio

Special features for easy system design

APPLICATIONS

DVD players and recorders
Digital set-top boxes
A/V receivers
Digital cameras and camcorders
HDMI repeater/splitter

GENERAL DESCRIPTION

The AD9389B is a 165 MHz, high definition multimedia inter­face (HDMI) v. 1.3 transmitter. It supports HDTV formats up to
1080p, and computer graphic resolutions up to UXGA (1600 ×
1200 @ 60 Hz). With the inclusion of HDCP, the AD9389B allows
the secure transmission of protected content as specified by the
HDCP v. 1.2 protocol.

™

HDMI

/DVI transmitter compatible with HDMI v. 1.3,
DVI v. 1.0, and HDCP v. 1.2
Internal key storage for HDCP
Single 1.8 V power supply
Video/audio inputs accept logic levels from 1.8 V to 3.3 V
80-lead LQFP, Pb-free package
64-lead LFCSP, Pb-free package

165 MHz operation supports all resolutions from 480i to

1080p and UXGA at 60 Hz
Programmable two-way color space converter
Supports RGB, YCbCr, and DDR
Supports ITU656-based embedded syncs
Automatic input video format timing detection (CEA-861B)

Supports standard S/PDIF for stereo LPCM or compressed

audio up to 192 kHz
8-channel, uncompressed, LPCM I

On-chip MPU with I

2

C® master to perform HDCP

2

S audio up to 192 kHz

operations and EDID reading operations
5 V tolerant I

2

C and HPD I/Os, no extra device needed

No audio master clock needed for supporting

S/PDIF and I

2

S

On-chip MPU reports HDMI events through interrupts and

registers

HDMI/DVI Transmitter

AD9389B

FUNCTIONAL BLOCK DIAGRAM

INTERRUPT

HANDLER

HDCP-EDID

MICRO-

CONTROLLER

MASTER

XOR

MASK

AD9389B

IN

I2C

HDMI

Tx

CORE

HPD

DDCSDA
DDCSCL

Tx0–/Tx0+

Tx1–/Tx1+

Tx2–/Tx2+

TxC–/TxC+

2

S audio.

SD

CLK
VSYNC
HSYNC

DE

D[23:0]

S/PDIF

MCLK
I2S[3:0]
LRCLK

SCLK

SCL

I2C

SLAVE

REGISTER

CONFIGURATION

LOGIC

VIDEO

DATA

CAPTURE

AUDIO

DATA

CAPTURE

COLOR
SPACE

CONVER-

SION

4:2:2 TO

4:4:4

CONVER-

SION

MDAMCL

HDCP
CORE

Figure 1.

The AD9389B supports both S/PDIF and 8-channel I

2

Its high fidelity, 8-channel I

S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo LPCM
audio or compressed audio, including DTS®, THX®, and Dolby®
Digital.

The AD9389B helps reduce system design complexity and cost
by incorporating such features as an internal MPU for HDCP
operations, an I
supply, and 5 V tolerance on the I

2

C master for EDID reading, a single 1.8 V power

2

C and hot plug detect pins.

Fabricated in an advanced CMOS process, the AD9389B is
available in a space-saving, 64-lead LFCSP surface-mount
package, and an 80-lead LQFP surface-mount package. All
packages are available as Pb-free and are specified from −25°C
to +85°C.

06555-001

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD9389B Preliminary Technical Data

TABLE OF CONTENTS

Features .............................................................................................. 1

Design Resources ..........................................................................9

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Explanation of Test Levels........................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Applications....................................................................................... 9

Document Conventions ...............................................................9

PCB Layout Recommendations.................................................... 10

Power Supply Bypassing ............................................................ 10

Digital Inputs .............................................................................. 10

External Swing Resistor............................................................. 10

Output Signals ............................................................................ 10

Outline Dimensions ....................................................................... 11

Ordering Guide .......................................................................... 12

Rev. PrA | Page 2 of 12

Preliminary Technical Data AD9389B

SPECIFICATIONS

Table 1.

Te st

Parameter Conditions Temp

DIGITAL INPUTS

Input Voltage, High (VIH) Full VI 1.4 3.5 V
Input Voltage, Low (VIL) Full VI 0.7 V
Input Capacitance 25°C V 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VDD − 0.1 V
Output Voltage, Low (VOL) Full VI 0.4 V

THERMAL CHARACTERISTICS

Thermal Resistance

θJC Junction-to-Case V 15.2 °C/W
θJA Junction-to-Ambient V 59 °C/W

Ambient Temperature Full V −25 +25 +85 °C

DC SPECIFICATIONS

Input Leakage Current, I

IL

25°C VI −10 +10 μA
Input Clamp Voltage −16 mA 25°C V −0.8 V
+16 mA 25°C V +0.8 V
Differential High Level Output

V AV
Voltage

Differential Output Short-Circuit

IV 10 μA
Current

POWER SUPPLY

VDD (All) Supply Voltage Full IV 1.71 1.8 1.89 V
VDD Supply Voltage Noise Full V 50 mV p-p
Power-Down Current

With active video applied, 165 MHz, typical

25°C IV 9 mA

random pattern
I

AVDD

2

With active video applied, 165 MHz, typical

25°C IV TBD

random pattern

2

I

PVDD

With active video applied, 165 MHz, typical

25°C IV TBD

random pattern

2

I

DVDD

With active video applied, 165 MHz, typical

25°C IV TBD

random pattern
Transmitter Supply Current

2

With active video applied, 165 MHz, typical

25°C IV TBD mA

random pattern
Transmitter Total Power Full VI TBD mW

AC SPECIFICATIONS

CLK Frequency 25°C IV 13.5 80 MHz
TMDS Output CLK Duty Cycle 25°C IV 48 52 %
Worst Case CLK Input Jitter Full IV 2 ns
Input Data Setup Time Full IV 1 ns
Input Data Hold Time Full IV 1 ns
TMDS Differential Swing VI 800 1000 1200 mV
V

SYNC

and H

Delay from DE

SYNC

VI 1 UI
Falling Edge

V

SYNC

and H

Delay to DE

SYNC

VI 1 UI
Rising Edge

DE High Time 25°C VI 8191 UI
DE Low Time 25°C VI 138 UI
Differential Output Swing

Low-to-High Transition Time 25°C VII 75 490 ps
High-to-Low Transition Time 25°C VII 75 490 ps

Level

1

Min Typ Max Unit

V

CC

3

Rev. PrA | Page 3 of 12

AD9389B Preliminary Technical Data

Te st

Parameter Conditions Temp

AUDIO AC TIMING

Sample Rate I2S and S/PDIF Full IV 32 192 kHz
I2S Cycle Time 25°C IV 1 UI
I2S Setup Time 25°C IV 15 ns
I2S Hold Time 25°C IV 0 ns
Audio Pipeline Delay 25°C IV 75 μs

1

See Explanation of Test Levels section.

2

Using low output drive strength.

3

UI = unit interval.

Level

1

Min Typ Max Unit

Rev. PrA | Page 4 of 12

Preliminary Technical Data AD9389B

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Digital Inputs 5 V to 0.0 V
Digital Output Current 20 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at

specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design

and characterization testing.

VII. Limits defined by HDMI specification; guaranteed by

design and characterization testing.

ESD CAUTION

Rev. PrA | Page 5 of 12

AD9389B Preliminary Technical Data

V

C

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND79GND78D177D276D375D474D573D672D771D870D969D1068D1167D1266D1365D1464DVDD63DVDD62DVDD61DVDD

80

DVDD

HSYNC

VSYNC

CLK

S/PDIF

MCLK

I2S0
I2S1
I2S2
I2S3

SCLK

LRCLK

GND

PVDD

GND

GND
PVDD
PVDD

DE

1

PIN 1
INDICATOR

2

D0

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21

22

24

25

23

GND

PVDD

HPD

AVDD

26

27

GND

AD9389B

(Not to S cale)

28

29

TxC–

TxC+

TOP VIEW

30

31

Tx0–

AVDD

33

34

35

36

32

GND

Tx0+

Tx1–

PD/A0

38

37

Tx2–

Tx1+

Tx2+

AVDD

EXT_SWG

60

GND

59

GND

58

D15

57

D16

56

D17

55

D18

54

D19

53

D20

52

D21

51

D22

50

D23

49

MCL

48

MDA

47

SDA

46

SCL

45

DDCSDA

44

DDCSCL

43

GND

42

GND

41

AVDD

40

39

INT

GND

06555-002

Figure 2. 80-Lead LQFP Pin Configuration (Top View)

DVDD

DE

HSYNC

SYN

CLK

S/PDIF

MCLK

2

I

2

I

2

I

2

I

SCLK

LRCLK

PVDD
PVDD

DGNDD1D2D3D4D5D6D7D8D9D10

D11

D12

D13

D14

646362616059585756555453525150

PIN 1

1

D0

S0

10

S1

11

S2

12

S3

13
14
15
16

INDICATOR

2
3
4
5
6
7
8
9

+

AD9389B

TOP VIEW

(Not to S cale)

171819202122232425262728293031

HPD

Tx0–

Tx1–

AVDD

TxC+

AVDD

PVDD

Tx0+

TxC–

Tx2–

Tx1+

Tx2+

AVDD

PD/A0

EXT_SWG

NOTES

1. GND PADDLE ON BOTTO M OF PACKAGE.

Figure 3. 64-Lead LFCSP Pin Configuration (Top View)

DVDD
49

32
INT

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

DVDD
D15
D16
D17
D18
D19
D20
D21
D22
D23
MCL
MDA
SDA
SCL
DDCSDA
DDCSCL

06555-003

Rev. PrA | Page 6 of 12

Preliminary Technical Data AD9389B

Table 3. Pin Function Descriptions

Pin No.

LFCSP LQFP

2, 39 to 47,
50 to 63

2, 50 to 58,
65 to 78

Mnemonic Type

D[23:0] I

6 6 CLK I Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
3 3 DE I

4 4 HSYNC I Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
5 5 VSYNC I Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
18 23 EXT_SWG I

20 25 HPD I

7 7 S/PDIF I

8 8 MCLK I

9 to 12 9 to 12 I2S[3:0] I

13 13 SCLK I I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
14 14 LRCLK I Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
26

2

33

2

PD/A0 I

21, 22 27, 28 TxC−/TxC+ O

30, 31 37, 38 Tx2−/Tx2+ O

27, 28 34, 35 Tx1−/Tx1+ O

24, 25 30, 31 Tx0−/Tx0+ O

32 40 INT O

19, 23, 29 24, 29, 36, 41
1, 48, 49 1, 61 to 64

15 to 17 16, 19 to 21

64, paddle
on bottom
side

15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79, 80

AVDD P 1.8 V Power Supply for TMDS Outputs.
DVDD P

PVDD P

GND P

36 47 SDA C

35 46 SCL C

37 48 MDA C

38 49 MCL C

1

Description

Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic
levels from 1.8 V to 3.3 V.

Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to

3.3 V.

Sets internal reference currents. Place an 887 Ω resistor (1% tolerance)
between this pin and ground.

Hot Plug Detect Signal. This indicates to the interface whether the receiver is
connected. 1.8 V to 5.0 V CMOS logic level.

S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input
from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V
to 3.3 V.

Audio Reference Clock. 128 × N × f
sampling frequency (f

), 256 × fS, 384 × fS, or 512 × fS. Supports 1.8 V to 3.3 V

S

with N = 1, 2, 3, or 4. Set to 128 ×

S

CMOS logic level.

2

S Audio Data Inputs. These represent the eight channels of audio (two per

I
input) available through I

Power-Down Control and I

2

S. Supports CMOS logic levels from 1.8 V to 3.3 V.

2

C Address Selection. The I2C address and the PD
polarity are set by the PD/A0 pin state when the supplies are applied to the
AD9389B. Supports 1.8 V to 3.3 V CMOS logic level.

Differential Clock Output. Differential clock output at pixel clock rate; TMDS
logic level.

Differential Output Channel 2. Differential output of the red data at 10× the
pixel clock rate; TMDS logic level.

Differential Output Channel 1. Differential output of the green data at 10× the
pixel clock rate; TMDS logic level.

Differential Output Channel 0. Differential output of the blue data at 10× the
pixel clock rate; TMDS logic level.

Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply
is recommended.

1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power
to the digital logic and I/Os. They should be filtered and as quiet as possible.

1.8 V PLL Power Supply. The most sensitive portion of the AD9389B is the
clock generation circuitry. These pins provide power to the clock PLL. The
designer should provide quiet, noise-free power to these pins.

Ground. The ground return for all circuitry on-chip. It is recommended that
the AD9389B be assembled on a single, solid ground plane with careful
attention given to ground current paths.

2

Serial Port Data I/O. This pin serves as the serial port data I/O slave for register
access. Supports CMOS logic levels from 1.8 V to 3.3 V.

2

Serial Port Data Clock. This pin serves as the serial port data clock slave for
register access. Supports CMOS logic levels from 1.8 V to 3.3 V.

2

Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.

2

Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic
levels from 1.8 V to 3.3 V.

Rev. PrA | Page 7 of 12

AD9389B Preliminary Technical Data

Pin No.

LFCSP LQFP

Mnemonic Type

34 45 DDCSDA C

33 44 DDCSCL C

1

I = input, O = output, P = power supply, C = control.

2

For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from [e-mail].

1

Description

2

Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus.
Supports a 5 V CMOS logic level.

2

Serial Port Data Clock to Receiver. This pin serves as the master clock for the
DDC bus. Supports a 5 V CMOS logic level.

Rev. PrA | Page 8 of 12

Preliminary Technical Data AD9389B

APPLICATIONS

DESIGN RESOURCES

Analog Devices, Inc. evaluation kits, reference design
schematics, and other support documentation are available
under the nondisclosure agreement (NDA) from
[e-mail].

Other resources include:

EIA/CEA-861B which describes audio and video infoframes as
well as the E-EDID structure for HDMI. It is available from
Consumer Electronics Association (CEA).

The HDMI v. 1.3, a defining document for HDMI Version 1.3,
and the HDMI Compliance Test Specification Version 1.3 are
available from HDMI Licensing, LLC.

The HDCP v. 1.2 is the defining document for HDCP
Version 1.2 available from Digital Content Protection, LLC.

DOCUMENT CONVENTIONS

In this data sheet, data is represented using the conventions
described in

Table 4. Document Conventions

Data
Type

0xNN

0bNN

NN

Bit

Tabl e 4.

Format

Hexadecimal (Base-16) numbers are represented using
the C language notation, preceded by 0x.

Binary (Base-2) numbers are represented using the C
language notation, preceded by 0b.

Decimal (Base-10) numbers are represented using no
additional prefixes or suffixes.

Bits are numbered in little endian format, that is, the
least significant bit of a byte or word is referred to as Bit 0.

Rev. PrA | Page 9 of 12

AD9389B Preliminary Technical Data

PCB LAYOUT RECOMMENDATIONS

The AD9389B is a high precision, high speed analog device. As
such, to obtain the maximum performance from the part, it is
important to have a well laid out board.

Other Input Signals

The HPD must be connected to the HDMI connector. A 10 kΩ
pull-down resistor to ground is also recommended.

POWER SUPPLY BYPASSING

It is recommended to bypass each power supply pin with a

0.1 µF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is necessary to have only one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9389B, as that interposes resistive vias in the path.

The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make a
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.

It is particularly important to maintain low noise and good
stability of PVDD (the PLL supply). Abrupt changes in PVDD
can result in similarly abrupt changes in sampling clock phase
and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is best practice to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD and PVDD).

It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and long ground loops can result.

DIGITAL INPUTS

Video and Audio Data Input Signals

The digital inputs on the AD9389B are designed to work with
signals ranging from 1.8 V to 3.3 V logic level. Therefore, no
extra components need to be added when using 3.3 V logic.
Any noise that gets onto the clock input (labeled CLK) trace
adds jitter to the system. Therefore, minimize the video clock
input (Pin 6: CLK) trace length and do not run any digital or
other high frequency traces near it. Make sure to match the
length of the input data signals to optimize data capture,
especially for high frequency modes such as 1080p, UXGA, and
double data rate input formats.

The PD/A0 input pin can be connected to GND or supply
(through a resistor or a control signal). The device address and
power-down polarity are set by the state of the PD/A0 pin when
the AD9389B supplies are applied/enabled. For example, if the
PD/A0 pin is low (when the supplies are turned on), then the
device address is 0x72 and the power-down is active high. If the
PD/A0 pin is high (when the supplies are turned on), the device
address is 0x7A and the power-down is active low.

2

The SCL and SDA pins should be connected to the I
A pull-up resistor of 2 k to 1.8 V or 3.3 V is recommended.

C master.

EXTERNAL SWING RESISTOR

The external swing resistor must be connected directly to the
EXT_SWG pin and ground. The external swing resistor must
have a value of 887 Ω (±1% tolerance). Avoid running any high
speed ac or noisy signals next to, or close to, the EXT_SWG pin.

OUTPUT SIGNALS

TMDS Output Signals

The AD9389B has three TMDS data channels (0, 1, and 2) that
output signals up to 800 MHz as well as the TMDS output data
clock. To minimize the channel-to-channel skew, make the
trace length of these signals the same. Additionally, these traces
need to have a 50  characteristic impedance and need to be
routed as 100  differential pairs. Best practice recommends
routing these lines on the top PCB layer to avoid the use of vias.

Other Output Signals (non TMDS)

DDCSCL and DDCSDA

The DDCSCL and DDCSDA outputs need to have a minimum
amount of capacitance loading to ensure the best signal integrity.
The DDCSCL and DDCSDA capacitance loading must be less
than 50 pF to meet the HDMI compliance specification. The
DDCSCL and DDCSDA must be connected to the HDMI
connector and a pull-up resistor to 5 V is required. The pull-up
resistor must have a value between 1.5 kΩ and 2 kΩ.

INT Pin

The INT pin is an output that should be connected to the micro­controller of the system. A pull-up resistor to 1.8 V or 3.3 V is
required for proper operation—the recommended value is 2 kΩ.

MCL and MDA

The MCL and MDA outputs should be connected to the
EEPROM containing the HDCP key (if HDCP is implemented).
Pull-up resistors of 2 kΩ are recommended.

Rev. PrA | Page 10 of 12

Preliminary Technical Data AD9389B

OUTLINE DIMENSIONS

16.20

0.75

0.60

0.45

1.60
MAX

80

1

16.00 SQ

15.80

61

60

PIN 1

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09

7°

3.5°
0°

0.10 MAX
COPLANARITY

20

21

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-BEC

Figure 4. 80-Lead Low Profile Quad Flat Package [LQFP]

(ST-80-2)

Dimensions shown in millimeters

9.00

BSC SQ

PIN 1
INDICATOR

VIEW

TOP

8.75

BSC SQ

0.60 MAX

TOP VIEW

(PINS DOWN)

0.65

BSC

LEAD PITCH

0.60 MAX

49

48

EXPOSED PAD**

(BOTTOM VIEW)

0.38

0.32

0.22

0.30

0.25

0.18

14.20

14.00 SQ

13.80

41

40

PIN 1

64

INDICATOR

1

+

4.85

4.70 SQ*

4.55

1.00

0.85

0.80

12° MAX

SEATING
PLANE

0.45

0.40

0.35

0.80 MAX

0.65 TYP

0.50 BSC

64 LFCSP (LEAD FRAME CHIP SCALE PACKAGE)

*

COMPLIANT T O JEDEC STANDARDS M O -220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION

**Note: PAD is CONNECTED to GND

DIMENSIO N S in Millim e ters

0.20 REF

0.05 MAX

0.02 NOM

33

32

7.50
REF

16

17

Figure 5. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

Rev. PrA | Page 11 of 12

AD9389B Preliminary Technical Data

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9389BBCPZ-801 −25°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD9389BBCPZ-1651 −25°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-1
AD9389BBSTZ-801 −25°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9389BBSTZ-1651 −25°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9389B/PCB Evaluation Board

1

Z = RoHS Compliant Part.

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06555-0-3/07(PrA)

Rev. PrA | Page 12 of 12