/DVI transmitter compatible with HDMI v1.2a,
DVI v1.0, and HDCP 1.1
Internal key storage for HDCP
Single 1.8 V power supply
Video/audio inputs accept logic levels from 1.8 V to 3.3 V
64-lead LFCSP, Pb-free package
80 MHz operation supports all resolutions from 480i to
720p/1080i and XGA-75 Hz
Programmable two-way color space converter
Supports RGB, YCbCr, DDR
Supports ITU656 based embedded syncs
Auto input video format timing detection (CEA-861B)
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
Supports 8-channel uncompressed LPCM I
2
S audio up to
192 kHz
On-chip MPU with I
2
C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I
2
C and HPD I/Os, no extra device needed
No audio master clock needed for supporting
S/PDIF and I
2
S
On-chip MPU reports HDMI events through interrupts and
registers
CLK
VSYNC
HSYNC
D[23:0]
S/PDIF
MCLK
I2S[3:0]
LRCLK
SCLK
DE
HDMI/DVI Transmitter
AD9389A
FUNCTIONAL BLOCK DIAGRAM
INTERRUPT
HANDLER
HDCP-EDID
MICRO-
CONTROLLER
MASTER
XOR
MASK
AD9389A
INT
I2C
HDMI
Tx
CORE
SD
SCL
I2C
SLAVE
REGISTER
CONFIGURATION
LOGIC
VIDEO
DATA
CAPTURE
AUDIO
DATA
CAPTURE
COLOR
SPACE
CONVER-
SION
4:2:2 TO
4:4:4
CONVER-
SION
Figure 1.
HDCP
CORE
HPD
DDCSDA
DDCSCL
Tx0[1:0]
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
06187-001
APPLICATIONS
DVD players and recorders
Digital set-top boxes
A/V receivers
Digital cameras and camcorders
HDMI repeater/splitter
GENERAL DESCRIPTION
The AD9389A-BBCZ is an 80 MHz, high definition multimedia
interface (HDMI) v.1.2a transmitter. It supports HDTV formats
up to 720p/1080i, and computer graphic resolutions up to XGA
(1024 × 768 @ 75 Hz). With the inclusion of HDCP, the AD9389A
allows the secure transmission of protected content as specified
by the HDCP v1.1 protocol.
2
The AD9389A supports both S/PDIF and 8-channel I
2
Its high fidelity 8-channel I
S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo LPCM
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
S audio.
audio or compressed audio including Dolby® Digital, DTS®,
and THX®.
The AD9389A helps to reduce system design complexity and
cost by incorporating such features as an internal MPU for
2
HDCP operations, an I
1.8 V power supply and 5 V tolerance on I
C master for EDID reading, a single
2
C and hot plug
detect pins.
Fabricated in an advanced CMOS process, the AD9389A is
available in a space saving, 64-lead LFCSP surface-mount
package. The LFCSP package is specified from 0°C to 70°C.
Input Voltage, High (VIH) Full VI 1.4 V
Input Voltage, Low (VIL) Full VI 0.7 V
Input Capacitance 25°C V 3 pF
DIGITAL OUTPUTS
Output Voltage, High (VOH) Full VI VDD − 0.1 V
Output Voltage, Low (VOL) Full VI 0.4 V
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case V 15.2 °C/W
θJA Junction-to-Ambient V 59 °C/W
Ambient Temperature Full V −25 +25 +90 °C
DC SPECIFICATIONS
Input Leakage Current, I
IL
25°C VI −10 +10 μA
Input Clamp Voltage −16 mA 25°C V −0.8 V
+16 mA 25°C V +0.8 V
Differential High Level Output Voltage V AVCC V
Differential Output Short-Circuit Current IV 10 μA
POWER SUPPLY
VDD (All) Supply Voltage Full IV 1.71 1.8 1.89 V
VDD Supply Voltage Noise Full V 50 mV p-p
Power-Down Current With active video applied 25°C IV 9 mA
Transmitter Supply Current
2
80 MHz, typical random
25°C IV 143 155 mA
pattern
Transmitter Total Power Full VI 257 280 mW
AC SPECIFICATIONS
CLK Frequency 25°C IV 13.5 80 MHz
TMDS Output CLK Duty Cycle 25°C IV 48 52 %
Worst Case CLK Input Jitter Full IV 2 ns
Input Data Setup Time Full IV 1 ns
Input Data Hold Time Full IV 1 ns
TMDS Differential Swing VI 800 1000 1200 mV
V
SYNC
and H
Delay from DE Falling
SYNC
VI 1 UI
Edge
V
SYNC
and H
Delay to DE Rising Edge VI 1 UI
SYNC
DE High Time 25°C VI 8191 UI
DE Low Time 25°C VI 138 UI
Differential Output Swing
Low-to-High Transition Time 25°C VII 75 490 ps
High-to-Low Transition Time 25°C VII 75 490 ps
AUDIO AC TIMING
Sample Rate I2S and S/PDIF Full IV 32 192 kHz
I2S Cycle Time 25°C IV 1 UI
I2S Setup Time 25°C IV 15 ns
I2S Hold Time 25°C IV 0 ns
Audio Pipeline Delay 25°C IV 75 μs
1
See the Explanation of Test Levels section.
2
Using low output drive strength.
3
UI = unit interval.
Rev. 0 | Page 3 of 12
Level
1
Min Typ Max Unit
3
Page 4
AD9389A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Digital Inputs 5 V to 0.0 V
Digital Output Current 20 mA
Operating Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design
VII. Limits defined by HDMI specification; guaranteed by
D[23:0] I Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.
50 to 63
6 CLK I Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
3 DE I Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
4
5
18
20
HSYNC I Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
VSYNC I Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
EXT_SW I Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground.
HPD I
Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to
5.0 V CMOS logic level.
7
S/PDIF I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips
digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
8
9 to 12
13
14
26
MCLK I
2
S[3:0] I
I
SCLK I I
Audio Reference Clock. 128 × N × f
256 × f
, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level.
S
2
S Audio Data Inputs. These represent the eight channels of audio (two per input) available
I
through I
2
2
S. Supports CMOS logic levels from 1.8 V to 3.3 V.
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS),
S
LRCLK I Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
PD/A0 I
Power-Down Control and I
2
C Address Selection. The I2C address and the PD polarity are set by the
PD/A0 pin state when the supplies are applied to the AD9389A. 1.8 V to 3.3 V CMOS logic level.
Differential Output Channel 2. Differential output of the red data at 10 × the pixel clock rate;
TMDS logic level.
27, 28
Tx1−/Tx1+ O
Differential Output Channel 1. Differential output of the green data at 10 × the pixel clock rate;
TMDS logic level.
24, 25
Tx0−/Tx0+ O
Differential Output Channel 0. Differential output of the blue data at 10 × the pixel clock rate;
TMDS logic level.
32
INT O
Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is
recommended.
19, 23, 29
AVDD P 1.8 V Power Supply for TMDS Outputs.
Rev. 0 | Page 5 of 12
Page 6
AD9389A
Pin No. Mnemonic Type1Description
1, 48, 49
15, 16, 17
64, Paddle on
Bottom Side
36 SDA C
35 SCL C
34 DDCSDA C
33 DDCSCL C
1
I = input, O = output, P = power supply, C = control.
2
For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from flatpanel_apps@analog.com.
DVDD P
PVDD P
GND P
2
2
2
2
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic
and I/Os. They should be filtered and as quiet as possible.
1.8 V PLL Power Supply. The most sensitive portion of the AD9389A is the clock generation
circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free
power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that the AD9389A be
assembled on a single, solid ground plane with careful attention given to ground current paths.
Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports
CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data Clock. This pin serves as the serial port data clock slave for register access.
Supports CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. 5 V CMOS logic level.
Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. 5 V CMOS
logic level.
Rev. 0 | Page 6 of 12
Page 7
AD9389A
APPLICATIONS
DESIGN RESOURCES
Analog Devices, Inc. evaluation kits, reference design
schematics, and other support documentation are available
under NDA from
Other resources include:
EIA/CEA-861B that describes audio and video infoframes as
well as the E-EDID structure for HDMI. It is available from
Consumer Electronics Association (CEA).
The HDMI v1.2a, a defining document for HDMI Version 1.2a,
and the HDMI Compliance Test Specification Version 1.2a are
available from HDMI Licensing, LLC.
The HDCP v1.1 is the defining document for HDCP
Version 1.1, available from Digital Content Protection, LLC.
flatpanel_apps@analog.com.
DOCUMENT CONVENTIONS
In this data sheet, data is represented using the conventions
described in
Table 4. Document Conventions
Data
Type
0xNN
0bNN
NN
Bit
Tabl e 4.
Format
Hexadecimal (Base-16) numbers are represented using
the C language notation, preceded by 0x.
Binary (Base-2) numbers are represented using the C
language notation, preceded by 0b.
Decimal (Base-10) numbers are represented using no
additional prefixes or suffixes.
Bits are numbered in little endian format, that is, the
least significant bit of a byte or word is referred to as Bit 0.
Rev. 0 | Page 7 of 12
Page 8
AD9389A
PCB LAYOUT RECOMMENDATIONS
The AD9389A is a high precision, high speed analog device. As
such, to get the maximum performance out of the part, it is
important to have a well laid out board.
Other Input Signals
The HPD must be connected to the HDMI connector. A 10 kΩ
pull-down resistor to ground is also recommended.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply pin with a
0.1 µF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is necessary to have only one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9389A, as that interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make a
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
It is particularly important to maintain low noise and good
stability of PVDD (the PLL supply). Abrupt changes in PVDD
can result in similarly abrupt changes in sampling clock phase
and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is best practice to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD and PVDD).
It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground
plane. Using multiple ground planes can be detrimental
because each separate ground plane is smaller, and long
ground loops can result.
DIGITAL INPUTS
Video and Audio Data Input Signals
The digital inputs on the AD9389A are designed to work with
signals ranging from 1.8 V to 3.3 V logic level. Therefore, no
extra components need to be added when using 3.3 V logic.
Any noise that gets onto the clock input (labeled CLK) trace
adds jitter to the system. Therefore, minimize the video clock
input (Pin 6: CLK) trace length and do not run any digital or
other high frequency traces near it. Make sure to match the
length of the input data signals to optimize data capture,
especially for high frequency modes (such as 720p or XGA
75 MHz) and double data rate input formats.
The PD/A0 input pin can be connected to GND or supply
(through a resistor or a control signal). The device address and
power-down polarity are set by the state of the PD/A0 pin when
the AD9389A supplies are applied/enabled. For example, if the
PD/A0 pin is low (when the supplies are turned on), then the
device address is 0x72 and the power down is active high. If the
PD/A0 pin is high (when the supplies are turned on), the device
address is 0x7A and the power down is active low.
2
The SCL and SDA pins should be connected to the I
A pull-up resistor of 2 k to 1.8 V or 3.3 V is recommended.
C master.
EXTERNAL SWING RESISTOR
The external swing resistor must be connected directly to the
EXT_SWG pin and ground. The external swing resistor must
have a value of 887 Ω (±1% tolerance). Avoid running any high
speed ac or noisy signals next to, or close to, the EXT_SWG pin.
OUTPUT SIGNALS
TMDS Output Signals
The AD9389A has three TMDS data channels (0, 1, and 2) that
output signals up to 800 MHz as well as the TMDS output data
clock. To minimize the channel-to-channel skew, make the
trace length of these signals the same. Also, these traces need to
have a 50 characteristic impedance and routed as 100
differential pairs. It is also recommended to route these lines on
the top PCB layer avoiding the use of vias.
Other Output Signals (non TMDS)
DDCSCL and DDCSDA
The DDCSCL and DDCSDA outputs need to have a minimum
amount of capacitance loading to ensure the best signal integrity.
The DDCSCL and DDCSDA capacitance loading must be less
than 50 pF to meet the HDMI compliance specification. The
DDCSCL and DDCSDA must be connected to the HDMI
connector and a pull-up resistor to 5 V is required. The pull-up
resistor must have a value between 1.5 kΩ and 2 kΩ.
INT Pin
The INT pin is an output that should be connected to the microcontroller of the system. A pull-up resistor to 1.8 V or 3.3 V is
required for proper operation: the recommended value is 2 kΩ.
Rev. 0 | Page 8 of 12
Page 9
AD9389A
OUTLINE DIMENSIONS
9.00
BSC SQ
PIN 1
INDICATOR
VIEW
TOP
8.75
BSC SQ
0.60 MAX
0.60 MAX
49
48
0.30
0.25
0.18
1
PIN 1
INDICATOR
*
4.85
4.70 SQ
4.55
64
1.00
0.85
0.80
SEATING
PLANE
12° MAX
0.45
0.40
0.35
0.80 MAX
0.65 TYP
0.50 BSC
*
COMPLIANT TO JEDEC S T ANDARDS MO-220-VMMD- 4
EXCEPT FOR EXPOSED PAD DIMENSION
0.20 REF
0.05 MAX
0.02 NOM
33
32
7.50
REF
16
17
112805-0
Figure 3. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9389AKCPZ-80
1
Z = Pb-free part.
1
0°C to 70°C 64-Lead LFCSP_VQ CP-64-1
Rev. 0 | Page 9 of 12
Page 10
AD9389A
NOTES
Rev. 0 | Page 10 of 12
Page 11
AD9389A
NOTES
Rev. 0 | Page 11 of 12
Page 12
AD9389A
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.