Page 1
8-Bit, 40/80/100 MSPS
T/H
ADC
REF
T/H
ADC
OUTPUT REGISTER
8
8
8
8
OUTPUT REGISTER
TIMING
TIMING
AD9288
V
DD
D7A–D0
A
SELECT #1
SELECT #2
DATA FORMAT
SELECT
D7B–D0
B
ENC
A
AINA
A
IN
A
REFINA
REF
OUT
REFINB
A
IN
B
AINB
ENC
B
VDGND V
DD
a
FEATURES
Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low Power: 90 mW at 100 MSPS per Channel
On-Chip Reference and Track/Holds
475 MHz Analog Bandwidth Each Channel
SNR = 47 dB @ 41 MHz
1 V p-p Analog Input Range Each Channel
Single +3.0 V Supply Operation (2.7 V–3.6 V)
Standby Mode for Single Channel Operation
Twos Complement or Offset Binary Output Mode
Output Data Alignment Mode
APPLICATIONS
Battery Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications
GENERAL DESCRIPTION
The AD9288 is a dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
Dual A/D Converter
AD9288
FUNCTIONAL BLOCK DIAGRAM
The encode input is TTL/CMOS compatible and the 8-bit
digital outputs can be operated from +3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combination of standby modes, digital data formats and digital data
timing schemes. In standby mode, the digital outputs are driven
to a high impedance state.
Fabricated on an advanced CMOS process, the AD9288 is avail-
able in a 48-lead surface mount plastic package (7 × 7 mm,
1.4 mm LQFP) specified over the industrial temperature range
(–40°C to +85°C).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Page 2
AD9288–SPECIFICATIONS
(VDD = 3.0 V; VD = 3.0 V, Differential Input; External reference unless otherwise noted.)
Test AD9288BST-100 AD9288BST-80 AD9288BST-40
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Units
RESOLUTION 8 8 8 Bits
DC ACCURACY
Differential Nonlinearity +25°CI ±0.5 +1.25 ±0.5 +1.25 ±0.5 +1.25 LSB
Full VI +1.50 +1.50 +1.50 LSB
Integral Nonlinearity +25°CI ±0.50 +1.25 ±0.50 +1.25 ±0.50 +1.25 LSB
Full VI +1.50 +1.50 +1.50 LSB
No Missing Codes Full VI Guaranteed Guaranteed Guaranteed
Gain Error
Gain Tempco
1
1
+25°CI –6 ±2.5 +6 –6 ±2.5 +6 –6 ±2.5 +6 % FS
Full VI –8 +8 –8 +8 –8 +8 % FS
Full VI 80 80 80 ppm/°C
Gain Matching +25°CV ±1.5 ±1.5 ±1.5 % FS
Voltage Matching +25°CV ±15 ±15 ±15 mV
ANALOG INPUT
Input Voltage Range
(With Respect to AIN) Full V ±512 ±512 ±512 mV p-p
Common-Mode Voltage Full V ±200 ±200 ±200 mV
Input Offset Voltage +25°C I –35 ±10 +35 –35 ±10 +35 –35 ±10 +35 mV
Full VI ±40 ±40 ±40 mV
Reference Voltage Full VI 1.2 1.25 1.3 1.2 1.25 1.3 1.2 1.25 1.3 V
Reference Tempco Full VI ±130 ±130 ±130 ppm/°C
Input Resistance +25°C I 7 10 13 7 10 13 7 10 13 kΩ
Full VI 5 16 5 16 5 16 kΩ
Input Capacitance +25°CV 2 2 2 pF
Analog Bandwidth, Full Power +25°C V 475 475 475 MHz
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 100 80 40 MSPS
Minimum Conversion Rate +25°CIV111MSPS
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t
) +25°CV 0 0 0 ns
A
Aperture Uncertainty (Jitter) +25°C V 5 5 5 ps rms
Output Valid Time (t
) +25°C IV 4.3 1000 5.0 1000 8.0 1000 ns
EH
) +25°C IV 4.3 1000 5.0 1000 8.0 1000 ns
EL
2
)
V
Full VI 3.0 3.0 3.0 ns
Output Propagation Delay (tPD)2Full VI 4.5 4.5 4.5 ns
DIGITAL INPUTS
Logic “1” Voltage Full VI 2.0 2.0 2.0 V
Logic “0” Voltage Full VI 0.8 0.8 0.8 V
Logic “1” Current Full VI ±1 ±1 ±1 µA
Logic “0” Current Full VI ±1 ±1 ±1 µA
Input Capacitance +25°C V 2.0 2.0 2.0 pF
DIGITAL OUTPUTS
3
Logic “1” Voltage Full VI 2.45 2.45 2.45 V
Logic “0” Voltage Full VI 0.05 0.05 0.05 V
POWER SUPPLY
Power Dissipation
Standby Dissipation
4
4, 5
Full VI 180 218 171 207 156 189 mW
Full VI 6 11 6 11 6 11 mW
Power Supply Rejection Ratio
(PSRR) +25°C I 8 20 8 20 8 20 mV/V
DYNAMIC PERFORMANCE
6
Transient Response +25°CV 2 2 2 ns
Overvoltage Recovery Time +25°CV 2 2 2 ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
= 10.3 MHz +25°C I 47.5 47.5 44 47.5 dB
IN
= 26 MHz +25°C I 47.5 44 47 dB
f
IN
f
= 41 MHz +25°C I 44 47.0 dB
IN
–2–
REV. 0
Page 3
AD9288
Test AD9288BST-100 AD9288BST-80 AD9288BST-40
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Units
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SINAD) (With Harmonics)
f
= 10.3 MHz +25°C I 47 47 44 47 dB
IN
f
= 26 MHz +25°C I 47 44 47 dB
IN
f
= 41 MHz +25°C I 44 47 47 dB
IN
Effective Number of Bits
f
= 10.3 MHz +25°C I 7.5 7.5 7.0 7.5 Bits
IN
f
= 26 MHz +25°C I 7.5 7.0 7.5 Bits
IN
= 41 MHz +25°C I 7.0 7.5 7.5 Bits
f
IN
2nd Harmonic Distortion
= 10.3 MHz +25°C I 70 70 55 70 dBc
f
IN
f
= 26 MHz +25°C I 70 55 70 dBc
IN
= 41 MHz +25°C I 55 70 70 dBc
f
IN
3rd Harmonic Distortion
= 10.3 MHz +25°C I 60 60 55 60 dBc
f
IN
f
= 26 MHz +25°C I 60 55 60 dBc
IN
= 41 MHz +25°C I 52 60 60 dBc
f
IN
Two-Tone Intermod Distortion (IMD)
f
= 10.3 MHz +25°C V 60 60 60 dBc
IN
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2
tV and tPD are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 10 pF or a dc current of ±40 µA.
3
Digital supply current based on VDD = +3.0 V output drive with <10 pF loading under dynamic test conditions.
4
Power dissipation measured under the following conditions: fS = 100 MSPS, analog input is –0.7 dBFS, both channels in operation.
5
Standby dissipation calculated with encode clock in operation.
6
SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Model Ranges Options
AD9288BST
-40, -80, -100 –40°C to +85°C ST-48*
AD9288/PCB +25°C Evaluation Board
*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7 × 7 mm: LQFP).
6
(Continued)
ORDERING GUIDE
Temperature Package
+ 0.5 V
D
+ 0.5 V
DD
+ 0.5 V
D
EXPLANATION OF TEST LEVELS
Test Level
I 100% production tested.
II 100% production tested at +25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes for
military devices.
Table I. User Select Options
S1 S2 User Select Options
0 0 Standby Both Channels A and B.
0 1 Standby Channel B Only.
1 0 Normal Operation (Data Align Disabled).
1 1 Data align enabled (data from both channels avail-
able on rising edge of Clock A. Channel B data is
delayed a 1/2 clock cycle).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9288 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0 –3–
WARNING!
ESD SENSITIVE DEVICE
Page 4
AD9288
PIN CONFIGURATION
A
GND
A
A
IN
A
A
IN
DFS
REF
A
IN
REF
OUT
REFINB
S1
S2
10
A
B
IN
11
A
B
IN
GND
12
NC = NO CONNECT
(MSB)
A
ENC
B
ENC
DD
V
DD
V
A
GND
D6
D7
AD9288
TOP VIEW
(Not to Scale)
B
B
D6
GND
(MSB) D7
D
V
48 47 46 45 44 39 38 3743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22 23 24
D
V
A
A
A
A
A
D4
D5
B
B
D4
D5
A
D2
D1
D3
D0
36
NC
35
NC
34
GND
V
33
DD
32
GND
31
V
D
30
V
D
29
GND
V
28
DD
27
GND
26
NC
25
NC
B
B
B
B
D1
D2
D0
D3
PIN FUNCTION DESCRIPTIONS
Pin No. Name Description
1, 12, 16, 27, 29,
32, 34, 45 GND Ground.
2A
A Analog Input for Channel A.
IN
3 AINA Analog Input for Channel A
(Complementary).
4 DFS Data Format Select: (Offset
binary output available if set
low. Twos complement output
available if set high).
5 REF
A Reference Voltage Input for
IN
Channel A.
6 REF
7 REF
OUT
IN
Internal Reference Voltage.
B Reference Voltage Input for
Channel B.
8 S1 User Select #1 (Refer to Table
I), Tied with Respect to V
.
D
9 S2 User Select #2 (Refer to Table
I), Tied with Respect to V
.
D
10 AINB Analog Input for Channel B
(Complementary).
11 A
13, 30, 31, 48 V
14 ENC
15, 28, 33, 46 V
17–24 D7
B Analog Input for Channel B.
IN
D
B
DD
–D0BDigital Output for Channel B.
B
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (3 V).
25, 26, 35, 36 NC Do Not Connect.
37–44 D0
47 ENC
–D7ADigital Output for Channel A.
A
A
Clock Input for Channel A.
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
–4–
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
REV. 0
Page 5
AD9288
AINA, AINB
ENCODE A, B
D7
–D0
A
D7
–D0
B
AINA, AINB
SAMPLE N SAMPLE N+1
t
A
t
EH
A
B
DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N
DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N+1
t
EL
SAMPLE N+2 SAMPLE N+3 SAMPLE N+4
1/
f
S
t
PD
SAMPLE N+5
t
V
Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE N SAMPLE N+1
SAMPLE N+5
DATA N+1
ENCODE A
ENCODE B
D7
–D0
A
D7
–D0
B
t
A
A
B
t
t
EL
EH
DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N
DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N+1
SAMPLE N+2 SAMPLE N+3 SAMPLE N+4
1/
f
S
t
PD
t
V
DATA N+1
Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
REV. 0
–5–
Page 6
AD9288
AINA, AINB
ENCODE A
ENCODE B
–D0
D7
A
–D0
D7
B
SAMPLE N SAMPLE N+1
t
A
t
EH
A
B
DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N
DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N+1
t
EL
SAMPLE N+2 SAMPLE N+3 SAMPLE N+4
1/
f
S
t
PD
SAMPLE N+5
t
V
DATA N+1
Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
–6–
REV. 0
Page 7
SAMPLE
0
dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
ENCODE = 100MSPS
A
IN
1 = 9.3MHz
A
IN
2 = 10.3MHz
IMD = –60.0dBc
Typical Performance Characteristics–
AD9288
dB
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
ENCODE = 100MSPS
A
= 10.3MHz
IN
SNR = 48.52dB
SINAD = 48.08dB
2ND HARMONIC = –62.54dBc
3RD HARMONIC = –63.56dBc
SAMPLE
Figure 4. Spectrum: fS = 100 MSPS, fIN = 10 MHz,
Single-Ended Input
0
ENCODE = 100MSPS
= 41MHz
A
IN
–10
SNR = 47.87dB
SINAD = 46.27dB
–20
2ND HARMONIC = –54.10dBc
3RD HARMONIC = –55.46dBc
–30
–40
dB
–50
–60
–70
–80
–90
SAMPLE
dB
72.00
68.00
64.00
60.00
56.00
52.00
48.00
44.00
40.00
2ND
3RD
0
10 20 30 40 50 60 70 80 90
ENCODE RATE = 100MSPS
MHz
Figure 7. Harmonic Distortion vs. AIN Frequency
Figure 5. Spectrum: fS = 100 MSPS, fIN = 41 MHz,
Figure 8. Two-Tone Intermodulation Distortion
Single-Ended Input
0
ENCODE = 100MSPS
= 76MHz
A
IN
–10
SNR = 47.1dB
SINAD = 43.2dB
–20
2ND HARMONIC = –52.2dBc
3RD HARMONIC = –51.5dBc
–30
–40
dB
–50
–60
–70
–80
–90
SAMPLE
Figure 6. Spectrum: fS = 100 MSPS, fIN = 76 MHz,
dB
50.00
48.00
46.00
44.00
42.00
40.00
38.00
36.00
SINAD
10 20 30 40 50 60 70 80 90
0
ENCODE RATE = 100MSPS
SNR
MHz
Figure 9. SINAD/SNR vs. AIN Frequency
Single-Ended Input
REV. 0
–7–
Page 8
AD9288
49.00
AIN = 10.3MHz
48.00
47.00
dB
46.00
45.00
30 40 50 60 70 80 90 100 110
SNR
SINAD
MSPS
Figure 10. SINAD/SNR vs. Encode Rate
50.00
46.00
42.00
dB
38.00
34.00
30.00
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0
SNR
SINAD
ENCODE HIGH PULSEWIDTH – ns
AIN = 10.3MHz
Figure 11. SINAD/SNR vs. Encode Pulsewidth High
190
185
180
175
170
165
160
POWER – mW
155
150
145
140
10 20 30 40 50 60 70 80 90
0
MSPS
AIN = 10.3MHz
100
Figure 13. Analog Power Dissipation vs. Encode Rate
dB
48.0
47.5
47.0
46.5
46.0
45.5
45.0
44.5
44.0
43.5
–40 25 85
TEMPERATURE – 8C
ENCODE RATE = 100MSPS
A
= 10.3MHz
IN
SNR
SINAD
Figure 14. SINAD/SNR vs. Temperature
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
dB
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
0 100 200 300 400 500 600
BANDWIDTH – MHz
ENCODE RATE = 100MSPS
–3dB
Figure 12. ADC Frequency Response: fS = 100 MSPS
0.6
0.4
0.2
0
–0.2
% GAIN
–0.4
–0.6
–0.8
–1.0
–40 25 85
TEMPERATURE – 8C
ENCODE RATE = 100MSPS
A
= 10.3MHz
IN
Figure 15. ADC Gain vs. Temperature (with External
+1.25 V Reference)
–8–
REV. 0
Page 9
2.0
V
BIAS
REF
IN
V
D
V
D
ENCODE
V
D
OUT
1.5
1.0
0.5
V
A
D
28kV
IN
12kV
AD9288
28kV
A
IN
12kV
LSB
0.0
LSB
–0.5
–1.0
–1.5
–2.0
CODE
Figure 16. Integral Nonlinearity
1.00
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
–1.00
CODE
Figure 17. Differential Nonlinearity
Figure 19. Equivalent Analog Input Circuit
Figure 20. Equivalent Reference Input Circuit
Figure 21. Equivalent Encode Input Circuit
V
DD
OUT
1.3
1.2
1.1
– V
1.0
REFOUT
V
0.9
0.8
0.7
0.25 0.5 0.75 1 1.25 1.5 1.75
0
LOAD – mA
ENCODE = 100MSPS
V
= 3.0V
D
= +258C
T
A
Figure 18. Voltage Reference Out vs. Current Load
REV. 0
Figure 22. Equivalent Digital Output Circuit
Figure 23. Equivalent Reference Output Circuit
–9–
Page 10
AD9288
APPLICATION NOTES
THEORY OF OPERATION
The AD9288 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 5 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction allowing optimization of comparator accuracy. The input buffers are differential
and both sets of inputs are internally biased. This allows the
most flexible use of ac or dc and differential or single-ended
input modes. The output staging block aligns the data, carries
out the error correction and feeds the data to output buffers.
The set of output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. There is no
discernible difference in performance between the two channels.
USING THE AD9288
Good high speed design practices must be followed when using
the AD9288. To obtain maximum benefit, decoupling capacitors
should be physically as close to the chip as possible, minimizing
trace and via inductance between chip pins and capacitor (0603
surface mount caps are used on the AD9288/PCB evaluation
board). It is recommended to place a 0.1 µF capacitor at each
power-ground pin pair for high frequency decoupling, and in-
clude one 10 µF capacitor for local low frequency decoupling.
The VREF IN pin should also be decoupled by a 0.1 µF capaci-
tor. It is also recommended to use a split power plane and
contiguous ground plane (see evaluation board section). Data
output traces should be short (<1 inch), minimizing on-chip
noise at switching.
ENCODE Input
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer. Any noise, distortion or timing
jitter on the clock will be combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the ENCODE input of the AD9288, and
the user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs
The digital outputs are TTL/CMOS compatible for lower
power consumption. During standby, the output buffers transition to a high impedance state. A data format selection option
supports either twos complement (set high) or offset binary
output (set low) formats.
Analog Input
The analog input to the AD9288 is a differential buffer. For
best dynamic performance, impedance at A
and AIN should
IN
match. Special care was taken in the design of the analog input
stage of the AD9288 to prevent damage and corruption of
data when the input is overdriven. The nominal input range is
1.024 V p-p centered at V
Voltage Reference
× 0.3.
D
A stable and accurate 1.25 V voltage reference is built into the
AD9288 (REF
is used by strapping Pins 5 (REF
(REF
). The input range can be adjusted by varying the
OUT
). In normal operation, the internal reference
OUT
A) and 7 (REFINB) to Pin 6
IN
reference voltage applied to the AD9288. No appreciable degradation in performance occurs when the reference is adjusted
±5%. The full-scale range of the ADC tracks reference voltage,
which changes linearly.
Timing
The AD9288 provides latched data outputs, with four pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (see Figures 1, 2
and 3). The length of the output data lines and loads placed on
them should be minimized to reduce transients within the
AD9288. These transients can detract from the converter’s
dynamic performance.
The minimum guaranteed conversion rate of the AD9288 is
1 MSPS. At clock rates below 1 MSPS, dynamic performance
will degrade. Typical power-up recovery time after standby
mode is 15 clock cycles.
User Select Options
Two pins are available for a combination of operational modes.
These options allow the user to place both channels in standby,
excluding the reference, or just the B channel. Both modes place
the output buffers and clock inputs in high impedance states.
The other option allows the user to skew the B channel output
data by 1/2 a clock cycle. In other words, if two clocks are fed to
the AD9288 and are 180° out of phase, enabling the data align
will allow Channel B output data to be available at the rising
edge of Clock A. If the same encode clock is provided to both
channels and the data align pin is enabled, then output data
from Channel B will be 180° out of phase with respect to Chan-
nel A. If the same encode clock is provided to both channels
and the data align pin is disabled, then both outputs are delivered on the same rising edge of the clock.
EVALUATION BOARD
The AD9288 evaluation board offers an easy way to test the
AD9288. It provides a means to drive the analog inputs singleendedly or differentially. The two encode clocks are easily
accessible at on-board SMB connectors J2, J7. These clocks are
buffered on the board to provide the clocks for an on-board
DAC and latches. The digital outputs and output clocks are
available at a standard 37-pin connector, P2. The board has
several different modes of operation, and is shipped in the following configuration:
• Single-Ended Analog Input
• Normal Operation Timing Mode
• Internal Voltage Reference
Power Connector
Power is supplied to the board via a detachable 6-pin power
strip, P1.
VREFA – Optional External Reference Input (1.25 V/1 µA)
VREFB – Optional External Reference Input (1.25 V/1 µA)
VDL – Supply for Support Logic and DAC (3 V/215 mA)
VDD – Supply for ADC Outputs (3 V/15 mA)
VD – Supply for ADC Analog (3 V/30 mA)
Analog Inputs
The evaluation board accepts a 1 V analog input signal centered
at ground at each analog input. These can be single-ended signals using SMB connectors J5 (channel A) and J1 (Channel B).
In this mode use jumpers E4–E5 and E6–E7. (E1–E2 and E9–
E10 jumpers should be lifted.)
Differential analog inputs use SMB connectors J4 and J6. Input
is 1 V centered at ground. The single-ended input is converted
–10–
REV. 0
Page 11
to differential by transformers T1, T2—allowing the ADC performance for differential inputs to be measured using a singleended source. In this mode use jumpers E1–E2, E3–E4, E7–E8
and E9–E10. (E4–E5 and E6–E7 jumpers should be lifted.)
Each analog input is terminated on the board with 50 Ω to
ground. Each input is ac-coupled on the board through a 0.1 µF
capacitor to an on-chip resistor divider that provides dc bias.
Note that the inverting analog inputs are terminated on the
board with 25 Ω (optimized for single-ended operation). When
driving the board differentially these resistors can be changed to
50 Ω to provide balanced inputs.
Encode
The encode clock for channel A uses SMB connector J7. Channel B encode is at SMB connector J2. Each clock input is termi-
nated on the board with 50 Ω to ground. The input clocks are
fed directly to the ADC and to buffers U5, U6 which drive the
DAC and latches. The clock inputs are TTL compatible, but
should be limited to a maximum of V
Voltage Reference
.
D
The AD9288 has an internal 1.25 V voltage reference. An external reference for each channel may be employed instead. The
evaluation board is configured for the internal reference (use
jumpers E18–E41 and E17–E19. To use external references,
connect to VREFA and VREFB pins on the power connector
P1 and use jumpers E20–E18 and E21–E19.
Normal Operation Mode
In this mode both converters are clocked by the same encode
clock; latency is four clock cycles (see timing diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set at jumpers E22–E29 and E26–E23.
Data Align Mode
In this mode channel B output is delayed an additional 1/2 cycle.
Signal S1 (Pin 8) and signal S2 (Pin 9) are both held high. This
is set at jumpers E22–E29 and E26–E28.
Data Format Select
Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 4) low at E30–E27 sets the output
format to be offset binary; setting DFS high at E30–E25 sets
the output to be twos complement.
Data Outputs
The ADC digital outputs are latched on the board by two 574s,
the latch outputs are available at the 37-pin connector at Pins
22–29 (Channel A) and Pins 30–37 (Channel B). A latch output clock (data ready) is available at Pin 2 or 21 on the output
connector. The data ready signal can be aligned with clock A
input by connecting E31–E32 or aligned with clock B input by
connecting E31–E33.
AD9288
PIN 22 (DATA)
1
PIN 2 (CLOCK)
Ch1 2.00V CH2 2.00V M 10.0ns CH4 40mV
Figure 24. Data Output and Clock at 37-Pin Connector
DAC Outputs
Each channel is reconstructed by an on-board dual channel
DAC, an AD9763. This DAC is intended to assist in debug—it
should not be used to measure the performance of the ADC. It
is a current output DAC with on-board 50 Ω termination resis-
tors. Figure 25 is representative of the DAC output with a full-
scale analog input. The scope setting was low bandwidth, 50 Ω
termination.
1
Ch1 500mVV
Figure 25. AD9763 Reconstruction DAC Output
Troubleshooting
If the board does not seem to be working correctly, try the
following:
• Verify power at IC pins.
• Check that all jumpers are in the correct position for the
desired mode of operation.
• Verify VREF is at 1.25 V
• Try running encode clock and analog inputs at low speeds
(10 MSPS/1 MHz) and monitor 574 outputs, DAC outputs,
and ADC outputs for toggling.
The AD9288 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
B
W
M 50.0ns CH1 380mV
REV. 0
–11–
Page 12
AD9288
BILL OF MATERIALS
# QTY REFDES DEVICE PACKAGE VALUE
1 22 C1–C15, C20–C25, C27 Ceramic Cap 0603 0.1 µF
2 5 C16–C19, C26 Tantalum Cap TAJD 10 µF
3 43 E1–E43 W-HOLE W-HOLE
4 8 J1–J8 SMBPN SMBP
5 1 P1 TB6 TB6
6 1 P2 37DRFP C37DRFP
7 10 R1, R3, R5–R7, R10–R14 Resistor R1206 50 Ω
8 2 R2, R4 Resistor R1206 25 Ω
9 2 R8, R9 Resistor R1206 2 kΩ
10 2 R15, R16 Resistor R1206 0 Ω
11 2 T1, T2 Transformer T1–1T
12 1 U1 AD9288 LQFP48
13 1 U2 AD9763 LQFP48
14 2 U3, U4 74ACQ574 DIP20\SOL
15 2 U5, U6 SN74LCX86 SO14
–12–
REV. 0
Page 13
AD9288
GND
GND
R12
50V
DAC OUTPUT A
J3
GND
GND
GND
GND
GND
J8
R14
50V
DAC OUTPUT B
GND
GND
GND
C26
10mF
VREFBVREFA
C19
10mF
C18
10mF
DL
V
C17
10mF
DD
V
C16
10mF
GND
D0A
DB1–P2
DB2–P2
U2
AD9763
DB4–P1
DB3–P1
D2B
D1B
V
D1A
D2A
DB3–P2
DB4–P2
DB2–P1
DB1–P1
D0B
GND
D
D3A
D4A
DB5–P2
DB6–P2
DB0–P1NCNC1
101112
GND
D5A
25
DB7–P2
DB8–P2
DB9–P2
DVDD2
DCOM2
WRT2/IQSEL
CLK2/IQRESET
CLK1/IQCLK
WRT1/IQWRT
DVDD1
DCOM1
NC3
NC2
13 14 15 16 17 18 19 20 21 22 23 24
D6A
BV
REF
V
AV
REF
DL
P1
23456
1
DD
V
D
V
GND
GND
3635343332313029282726
NC7
NC6
NC5
NC4
DB0–P2
GND
GND
V
V
C21 0.1mF
DL
V
C20
0.1mF
GND
SLEEP
ACOM
A2
B2
R10 50
FSADJ2
R8 2k
REFIO
REFIO
FSADJ1
R9 2kV
B1
R13 50V
A1
AVDD
MODE
48 47 46 45 44 43 42 41 40 39 38 37
DB9–P1
DB8–P1
123456789
DL
V
D7B
D6B
DB7–P1
DB6–P1
D5B
D4B
DB5–P1
D3B
VDL
C25
0.1mF
GND
GND
14
CC
4B
V
123456789
GND
D7AD6AD5AD4AD3AD2AD1AD0
DL
V
C14
0.1mF
GND
CC
Q0Q1Q2Q3Q4Q5Q6
V
74ACQ574
OUT_END0D1D2D3D4D5D6D7
D7D6D5D4D3D2D1
GND
D7A
GND
C22
0.1mF
DL
V
GND
CLKDACB
CLKDACB
CLKDACA
CLKDACA
GND
GND
C23
GND
GND
DL
V
E38E39
GND
E37
CLKDACA
CLKLATA
8910
111213
4A4Y3B
3Y
3A
U3
GND
D
V
DL
V
0.1mF
U6
1A1B1Y2A2B2YGND
A
ENC
74LCX86
R16
00
123
ENCODE A
567
4
GND
R11
50V
J7
GND
GND
E36E35
DL
V
GND
CLKCONA
GND
E34
GND
101112131415161718192021222324252627282930313233343536
GND
E31
E32
E33
CLKCONA
LSB
A
CLKLATA
Q7
CLOCK
GND
D0
GND
D0
D1
D2
D3
D4
D5
D6
D7
0.1mF
GND
C8
A
ENC
DD
V
48 47 46 45 44 43 42 4 1 4 0 3 9 38 3 7
0.1mF
C7
GND
mF
C10
0.1
GND
R1
50V
E4
E5
A
IN
A
J5
SINGLE-ENDED
CLKCONB
D
DD
V
V
V
C3
0.1mF
GND
C4
0.1mF
GND
GND7
AB
IN
A
2
DD
V
2COMP
GND
GND6
A
IN
REF
GND
2
D
V
AD9288
OUT
REF
1
V
U1
B
REF
GND
3635343332313029282726
AD0A
D1
A
D2
A
D3
A
D4
A
D5
A
D6
A
D7
A
D8
A
D9
GND
DD
V
3
A
ENC
D
V
3
A
IN
GND1
A
123456789
GND
E41
GND GND
C24
C27
0.1mF
0.1mF
E20
VREFA
E18
E17
VREFB
GND
E30E25
GND
E27
GND
D
V
C9
0.1mF
GND
R2
25V
1
2
GND
GND
GND
T1–1T
6
R5
3
4
E2
50V
J4
T2
E1
A
IN
A
DIFFERENTIAL
E3
D
D
IN
E19E21
E24
C2
V
GND
GND
0.1mF
GND
GND5
S1
D
E23
E29 E22
GND
V
R6
DD
V
C1
1
DD
V
S2
E28 E26
D
3
T1
4
E9
50V
GND
0.1mF
GND
B
D0
GND4
B
BB
IN
IN
A
A
101112
C12
0.1mF
R4
25V
1
2
6
E10
B
IN
A
J6
C15
GND
74ACQ574
GND
25
B
D1
B
D2
B
D3
B
D4
B
D5
B
D6
B
D7
B
D8
B
D9
GND3
DD
V
B
ENC
D
V
13 14 15 16 17 18 19 20 21 22 23 24
GND2
GND
GND
GND
R3
50V
E8
T1–1T
GND
GND
DIFFERENTIAL
D0BD1BD2BD3BD4BD5BD6BD7
DL
V
0.1mF
201918171615141312
CC
Q0Q1Q2Q3Q4Q5Q6
V
U4
OUT_END0D1D2D3D4D5D6D7
567
123
4
GND
0.1mF
GND
C6
B
ENC
D
V
0.1mF
C5
GND
GND
C11
0.1mF
E7
E6
J1
B
ENC
B
IN
A
SINGLE-ENDED
P2
C37DRPF
37
MSB
B
CLKLATB
E43 E42
E40
11
Q7
CLOCK
GND
8
9
10
GND
GND
DD
V
DL
V
C13
0.1mF
GND
12
13
14
CC
4B
V
1A1B1Y2A2B2YGND
74LCX86
123
GND
R15
00
R7
50V
J2
ENCODE B
CLKLATA
E11E15
CLKLATB
11
4A4Y3B
U5
567
4
E16E13
GND
GND
DL
V
3A
CLKCONB
DL
V
GND
E12
CLKDACB
8910
3Y
GND
GND
E14
REV. 0
Figure 26 . Dual Evaluation Board Schematic
–13–
Page 14
AD9288
Figure 27. Printed Circuit Board Top Side Copper
Figure 28. Printed Circuit Board Bottom Side Silkscreen
Figure 29. Printed Circuit Board Ground Layer
Figure 30. Printed Circuit Board “Split” Power Layer
–14–
REV. 0
Page 15
AD9288
Figure 31. Printed Circuit Board Bottom Side Copper
Figure 32. Printed Circuit Board Top Side Silkscreen
REV. 0
–15–
Page 16
AD9288
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP
(ST-48)
0.030 (0.75)
0.018 (0.45)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0° – 7°
0.063 (1.60) MAX
0.030 (0.75)
0.057 (1.45)
0.018 (0.45)
0.053 (1.35)
0° MIN
0.007 (0.18)
0.004 (0.09)
0.354 (9.00) BSC
0.276 (7.0) BSC
48
1
TOP VIEW
(PINS DOWN)
12
13
0.019 (0.5)
BSC
37
36
25
24
0.011 (0.27)
0.006 (0.17)
0.276 (7.0) BSC
0.354 (9.00) BSC
C3546–8–4/99
–16–
PRINTED IN U.S.A.
REV. 0
Loading...