8-Bit, 50 MSPS/80 MSPS/100 MSPS
REF
TIMING
V
D
PWRDWN
V
DD
A
IN
GND
REF
OUT
REF
IN
ADC
OUTPUT
STAGING
ENCODE
AD9283
8
D7–D0
T/H
A
IN
a
FEATURES
8-Bit, 50, 80 and 100 MSPS ADC
Low Power: 90 mW at 100 MSPS
On-Chip Reference and Track/Hold
475 MHz Analog Bandwidth
SNR = 46.5 dB @ 41 MHz at 100 MSPS
1 V p-p Analog Input Range
Single +3.0 V Supply Operation (2.7 V–3.6 V)
Power-Down Mode: 4.2 mW
APPLICATIONS
Battery Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
GENERAL DESCRIPTION
The AD9283 is an 8-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is optimized for low cost, low power, small size and ease of use. The
product operates at a 100 MSPS conversion rate, with outstanding dynamic performance over its full operating range.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
3 V A/D Converter
AD9283
FUNCTIONAL BLOCK DIAGRAM
The encoder input is TTL/CMOS compatible. A power-down
function may be exercised to bring total consumption to
4.2 mW. In power-down mode, the digital outputs are driven
to a high impedance state.
Fabricated on an advanced CMOS process, the AD9283 is
available in a 20-lead surface mount plastic package (SSOP)
specified over the industrial temperature range (–40°C to +85°C).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD9283–SPECIFICATIONS
(VDD = 3.0 V, VD = 3.0 V; single-ended input; external reference, unless otherwise noted)
Test AD9283BRS-100 AD9283BRS-80 AD9283BRS-50
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Units
RESOLUTION 8 8 8 Bits
DC ACCURACY
Differential Nonlinearity +25°CI ±0.5 +1.25 ±0.5 +1.25 ±0.5 +1.25 LSB
Full VI +1.50 +1.50 +1.50 LSB
Integral Nonlinearity +25°C I –1.25 ±0.75 +1.25 –1.25 ±0.75 +1.25 –1.25 ± 0.75 +1.25 LSB
Full VI +2.25 +1.50 +1.50 LSB
No Missing Codes Full VI Guaranteed Guaranteed Guaranteed
Gain Error
Gain Tempco
1
1
+25°CI –6 ±2.5 +6 –6 ±2.5 +6 –6 ±2.5 +6 % FS
Full VI –8 +8 –8 +8 –8 +8 % FS
Full VI 80 80 80 ppm/°C
ANALOG INPUT
Input Voltage Range
(With Respect to A
) Full V ±512 ±512 ±512 mV p-p
IN
Common-Mode Voltage Full V ±200 ±200 ±200 mV
Input Offset Voltage +25°C I –35 ±10 35 –35 ±10 35 –35 ±10 35 mV
Full VI ±40 ±40 ±40 mV
Reference Voltage Full VI 1.2 1.25 1.3 1.2 1.25 1.3 1.2 1.25 1.3 V
Reference Tempco Full VI ±130 ±130 ±130 ppm/°C
Input Resistance +25°C I 7 10 13 7 10 13 7 10 13 kΩ
Full VI 5 16 5 16 5 16 kΩ
Input Capacitance +25°CV222pF
Full VI µA
Analog Bandwidth, Full Power +25°C V 475 475 475 MHz
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 100 80 50 MSPS
Minimum Conversion Rate +25°CIV111MSPS
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t
) +25°CV000ns
A
Aperture Uncertainty (Jitter) +25°C V 5 5 5 ps rms
Output Valid Time (t
) +25°C IV 4.3 1000 5.0 1000 8.0 1000 ns
EH
) +25°C IV 4.3 1000 5.0 1000 8.0 1000 ns
EL
2
)
V
Full VI 2.0 3.0 2.0 3.0 2.0 3.0 ns
Output Propagation Delay (tPD)2Full VI 4.5 7.0 4.5 7.0 4.5 7.0 ns
DIGITAL INPUTS
Logic “1” Voltage Full VI 2.0 2.0 2.0 V
Logic “0” Voltage Full VI 0.8 0.8 0.8 V
Logic “1” Current Full VI ±1 ±1 ±1 µA
Logic “0” Current Full VI ±1 ±1 ±1 µA
Input Capacitance +25°C V 2.0 2.0 2.0 pF
DIGITAL OUTPUTS
Logic “1” Voltage Full VI 2.95 2.95 2.95 V
Logic “0” Voltage Full VI 0.05 0.05 0.05 V
Output Coding Offset Binary Code Offset Binary Code Offset Binary Code
POWER SUPPLY
Power Dissipation
3, 4
Full VI 90 120 90 115 80 100 mW
Power-Down Dissipation Full VI 4.2 7 4.2 7 4.2 7 mW
Power Supply Rejection Ratio
(PSRR) +25°C I 18 18 18 mV/V
–2– REV. B
AD9283
WARNING!
ESD SENSITIVE DEVICE
Test AD9283BRS-100 AD9283BRS-80 AD9283BRS-50
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Units
DYNAMIC PERFORMANCE
Transient Response +25°CV 2 2 2 ns
Overvoltage Recovery Time +25°CV 2 2 2 ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
= 10.3 MHz +25°C I 46.5 47 44 47 dB
f
IN
= 27 MHz +25°C I 46.5 44 47 47 dB
f
IN
= 41 MHz +25°C I 43.5 46.5 47 dB
f
IN
= 76 MHz +25°C V 46.0 dB
f
IN
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
= 10.3 MHz +25°C I 45 47 43.5 46.5 dB
f
IN
= 27 MHz +25°C I 45.5 43.5 46.5 46 dB
f
IN
= 41 MHz +25°C I 42.5 45 42 dB
f
IN
= 76 MHz +25°C V 42.5 dB
f
IN
Effective Number of Bits
= 10.3 MHz +25°C I 7.3 7.5 7.6 Bits
f
IN
= 27 MHz +25°C I 7.4 7.5 7.5 Bits
f
IN
= 41 MHz +25°C I 7.3 7.5 Bits
f
IN
= 76 MHz +25°C V 6.9 Bits
f
IN
2nd Harmonic Distortion
= 10.3 MHz +25°C I 57 60 55 60 dBc
f
IN
= 27 MHz +25°C I 60 55 60 56 dBc
f
IN
= 41 MHz +25°C I 50 58 55 dBc
f
IN
= 76 MHz +25°CV 46 dBc
f
IN
3rd Harmonic Distortion
= 10.3 MHz +25°C I 54.5 70 55 70 dBc
f
IN
= 27 MHz +25°C I 55 55 62.5 60 dBc
f
IN
= 41 MHz +25°C I 47 52.5 60 dBc
f
IN
= 76 MHz +25°CV 53 dBc
f
IN
Two-Tone Intermod Distortion
(IMD)
f
= 10.3 MHz +25°C V 52 52 52 dBc
IN
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2
tV and tPD are measured from the 1.5 V level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 10 pF or a dc current of ± 40 µA.
3
Power dissipation measured with encode at rated speed and a dc analog input.
4
Typical thermal impedance for the RS style (SSOP) 20-lead package: θJC = 46°C/W, θCA = 80°C/W, θJA = 126°C/W.
5
SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range.
Specifications subject to change without notice.
5
ABSOLUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
D
+ 0.5 V
DD
+ 0.5 V
D
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Ranges Descriptions Options
AD9283BRS
-50, -80, -100 –40°C to +85°C 20-Lead SSOP RS-20
AD9283/PCB +25°C Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9283 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–3–REV. B
AD9283
EXPLANATION OF TEST LEVELS
Test Level
I 100% production tested.
II 100% production tested at +25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes for
military devices.
PIN CONFIGURATION
VREF IN
GND
A
A
GND
1
2
3
4
5
V
D
6
IN
7
IN
8
V
D
9
10
PWRDWN
VREF OUT
ENCODE
Table I. Output Coding (VREF = +1.25 V)
Step AIN–A
IN
255 0.512 1111 1111
• ••
• ••
128 0.002 1000 0000
127 –0.002 0111 1111
• ••
• ••
0 –0.512 0000 0000
20
D0 (LSB)
19
D1
18
D2
17
D3
16
15
14
13
12
11
GND
V
DD
D4
D5
D6
D7 (MSB)
AD9283
TOP VIEW
(Not to Scale)
Digital Output
PIN FUNCTION DESCRIPTIONS
Pin Number Name Function
1 PWRDWN Power-down function select; Logic HIGH for power-down mode (digital outputs go to
high impedance state).
2 VREF OUT Internal Reference Output (+1.25 V typ); Bypass with 0.1 µF to Ground.
3 VREF IN Reference Input for ADC (+1.25 V typ).
4, 9, 16 GND Ground.
5, 8 V
6A
D
IN
Analog +3 V Power Supply.
Analog Input for ADC (Can be left open if operating in single-ended mode, but recom-
mend connection to a 0.1 µF capacitor and a 25 Ω resistor in series to ground for better
input matching).
7A
IN
Analog Input for ADC
10 ENCODE Encode Clock for ADC (ADC samples on rising edge of ENCODE).
11–14, 17–20 D7–D4, D3–D0 Digital Outputs of ADC.
15 V
DD
Digital output power supply. Nominally +2.5 V to +3.6 V.
–4– REV. B
AD9283
OUT
V
DD
33.3kV
A
IN
14.3kV
A
ENCODE
D7–D0
SAMPLE N
IN
t
A
t
EH
SAMPLE N+1
t
EL
DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N+1
Figure 2. Equivalent Analog Input Circuit
1/
SAMPLE N+2
fS
SAMPLE N+3
Figure 1. Timing Diagram
V
DD
33.3kV
A
IN
14.3kV
SAMPLE N+4
t
PD
SAMPLE N+5
t
V
Figure 5. Equivalent Digital Output Circuit
V
D
V
BIAS
REF IN
Figure 3. Equivalent Reference Input Circuit
V
D
ENCODE
Figure 4. Equivalent Encode Input Circuit
V
D
OUT
Figure 6. Equivalent Reference Output Circuit
–5–REV. B
AD9283
FREQUENCY – A
IN
10 20 30 40 50 60 80 100
70
65
dB
45
40
30
55
50
60
2ND
3RD
35
ENCODE = 100 MSPS
FREQUENCY
0
–10
–90
dB
–50
–60
–70
–80
–30
–40
–20
ENCODE = 100 MSPS
A
IN
1 = 9MHz
A
IN
2 = 10MHz
IMD = 52dBc
FREQUENCY
10 20 30 40 50 60 80 90
55
dB
45
40
35
30
50
100
SNR
SINAD
ENCODE = 100 MSPS
0
–10
–20
–30
–40
–50
dB
–60
–70
–80
–90
–100
FREQUENCY
ENCODE = 100 MSPS
A
= 10.3MHz
IN
SNR = 46.5dB
SINAD = 45dB
2nd = 57dBc
3rd = 54.5dBc
Figure 7. Spectrum: fS = 100 MSPS, fIN = 10.3 MHz
0
ENCODE = 100 MSPS
–10
A
= 41MHz
IN
SNR = 46.5dB
–20
SINAD = 45dB
2nd = 58dBc
–30
3rd = 52.5dBc
–40
dB
–50
–60
–70
–80
–90
Figure 8. Spectrum: fS = 100 MSPS, fIN = 40 MHz
0
ENCODE = 100 MSPS
–10
A
= 76MHz
IN
SNR = 46dB
–20
SINAD = 42.5dB
2nd = 46dBc
–30
3rd = 53dBc
–40
dB
–50
–60
–70
–80
–90
Figure 9. Spectrum: fS = 100 MSPS, fIN = 76 MHz
Figure 10. Harmonic Distortion vs. AIN Frequency
FREQUENCY
Figure 11. Two-Tone Intermodulation Distortion
FREQUENCY
Figure 12. SINAD/SNR vs. AIN Frequency
–6– REV. B
AD9283
ENCODE RATE
10 20 30 40 50 60 70 80
120
POWER – mW
40
20
0
80
60
100
90 100
AIN = 10.3MHz
TEMPERATURE – 8C
–40 –20 0 20 40 60 80
49
48
dB
44
46
45
47
–60 100
SINAD
SNR
CODE
1.00
0.75
LSB
–0.25
–0.50
–0.75
–1.00
0.25
0.00
0.50
49
48
47
46
dB
45
44
43
10 100
SNR
SINAD
20 30 40 50 60 70 80 90
ENCODE RATE
AIN = 10.3MHz
Figure 13. SINAD/SNR vs. Encode Rate
dB
60
50
SNR
40
30
SINAD
ENCODE = 100 MSPS
AIN = 10.3MHz
Figure 16. Analog Power Dissipation vs. Encode Rate
20
10
0
6.5 6 4.5 4
7 5.5 5 3.5 3
ENCODE PULSEWIDTH HIGH – ns
Figure 14. SINAD/SNR vs. Encode Pulsewidth High
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
dB
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
0
100 200 300 400 500
Figure 15. ADC Frequency Response: fS = 100 MSPS
BANDWIDTH – MHz
Figure 17. SINAD/SNR vs. Temperature
600
Figure 18. Differential Nonlinearity
–7–REV. B
AD9283
2.0
1.5
1.0
0.5
0.0
LSB
–0.5
–1.0
–1.5
–2.0
CODE
Figure 19. Integral Nonlinearity
APPLICATIONS
Theory of Operation
The analog signal is applied differentially or single-endedly to
the inputs of the AD9283. The signal is buffered and fed forward to an on-chip sample-and-hold circuit. The ADC core
architecture is a bit-per-stage pipeline type converter utilizing
switch capacitor techniques. The bit-per-stage blocks determine
the 5 MSBs and drive a FLASH converter to encode the 3 LSBs.
Each of the 5 MSB stages provides sufficient overlap and error
correction to allow optimization of performance with respect to
comparator accuracy. The output staging block aligns the data,
carries out the error correction and feeds the data to the eight
output buffers. The AD9283 includes an on-chip reference
(nominally 1.25 V) and generates all clocking signals from one
externally applied encode command. This makes the ADC easy
to interface with and requires very few external components for
operation.
ENCODE Input
The ENCODE input is fully TTL/CMOS compatible with a
nominal threshold of 1.5 V. Care was taken on the chip to
match clock line delays and maintain sharp clock logic transitions. Any high speed A/D converter is extremely sensitive to
the quality of the sampling clock provided by the user. This
ADC uses an on-chip sample-and-hold circuit which is essentially a mixer. Any timing jitter on the ENCODE will be combined with the desired signal and degrade the high frequency
performance of the ADC. The user is advised to give commensurate thought to the clock source.
Analog Input
The analog input to the ADC is fully differential and both inputs are internally biased. This allows the most flexible use of ac
or dc and differential or single-ended input modes. For peak
performance the inputs are biased at 0.3 × V
. See the specifi-
D
cation table for allowable common-mode range when dc coupling the input. The inputs are also buffered to reduce the load
the user needs to drive. For best dynamic performance, the
impedances at A
and AIN should be matched. The importance
IN
of this increases with sampling rate and analog input frequency.
The nominal input range is 1.024 V p-p.
Digital Outputs
The digital outputs are TTL/CMOS compatible. The output
buffers are powered from a separate supply, allowing adjustment
of the output voltage swing to ease interfacing with 2.5 V or
3.3 V logic. The AD9283 goes into a low power state within two
clock cycles following the assertion of the PWRDWN input.
PWRDWN is asserted with a logic high. During power-down
the outputs transition to a high impedance state. The time it
takes to achieve optimal performance after disabling the powerdown mode is approximately 15 clock cycles. Care should be
taken when loading the digital outputs of any high speed ADC.
Large output loads create current transients on the chip that can
degrade the converter’s performance.
Voltage Reference
A stable and accurate 1.25 V voltage reference is built into the
AD9283 (VREF OUT). In normal operation, the internal reference is used by strapping Pins 2 and 3 of the AD9283 together.
The input range can be adjusted by varying the reference voltage applied to the AD9283. No degradation in performance
occurs when the reference is adjusted ±5%. The full-scale range
of the ADC tracks reference voltage changes linearly. Whether
used or not, the internal reference (Pin 2) should be bypassed
with a 0.1 µF capacitor to ground.
Timing
The AD9283 provides latched data outputs with four pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (Figure 1. Timing
Diagram). The minimum guaranteed conversion rate to the
ADC is 1 MSPS. The dynamic performance of the converter
will degrade at encode rates below this sample rate.
Evaluation Board
The AD9283 evaluation board offers an easy way to test the
AD9283. It only requires a 3 V supply, an analog input and
encode clock to test the AD9283. The board is shipped with the
100 MSPS grade ADC.
The analog input to the board accepts a 1 V p-p signal centered
at ground. J1 should be used (Jump E3–E4, E18–E19) to drive
the ADC through Transformer T1. J2 should be used for singleended input drive (Jump E19–E21).
Both J1 and J2 are terminated to 50 Ω on the PCB. Each analog
path is ac-coupled to an on-chip resistor divider which provides
the required dc bias.
A (TTL/CMOS Level) sample clock is applied to connector
J3 which is terminated through 50 Ω on the PCB. This clock is
buffered by U5 which also provides the clocks for the 574
latches, DAC, and the off-card latch clock CLKCON. (Timing
can be modified at E17.)
There is a reconstruction DAC (AD9760) on the PCB. The
DAC is on the board to assist in debug only—the outputs
should not be used to measure performance of the ADC.
–8– REV. B
AD9283
Figure 20. Printed Circuit Board Top Side Silkscreen
Figure 21. Printed Circuit Board Bottom Side Silkscreen
Figure 22. Printed Circuit Board Top Side Copper
Figure 23. Printed Circuit Board “Split” Power Layer
–9–REV. B
AD9283
Figure 24. Printed Circuit Board Ground Layer
EVALUATION BOARD BILL OF MATERIALS — GS01717
# QTY REFDES DEVICE PACKAGE VALUE
1 15 C1, C4–C17 Ceramic Cap 0603 0.1 µF
2 4 C18–C21 Tantalum Cap BCAPTAJD 10 µF
3 24 E1–E6, E8–E10, E12–E19,
E21, E34–E39 W-HOLE
4 4 J1, J2, J3, J5 Connector SMB
5 1 P1 5-Pin Connector Wieland Connector
6 1 P2 37-Pin Connector AMP-747462-2
7 5 R4, R9, R10, R21, R22 Resistor 1206 50
8 1 R7 Resistor 1206 25
9 1 R23 Resistor 1206 2K
10 1 T1 Transformer Mini-Circuits T1-1T-KK81
11 1 U1 AD9283 SSOP-20
12 1 U3 AD9760 SOIC-28
13 1 U4 74ACQ574 SOIC-20
14 1 U5 SN74LVC86 SO14
Figure 25. Printed Circuit Board Bottom Side Copper
(P/N #25.602.2553.0 Top
P/N #Z5.530.0525.0 Bottom)
–10– REV. B
123456789
C21
10mF
VDAC
C20
10mF
VDL
C19
10mF
VD
C18
10mF
VA
PWDN
E8
E9
VA
P1
CLKCON
VDL
C16
0.1mF
201918171615141312
VCC
U4
74ACQ574
OUT_END0D1D2D3D4D5D6D7
123456789
20
19
18
D0
D1
U1
AD9283
PWDN
REFOUT
1
2
3
E1 E2
E5E6
E10
VDL VDAC
12345
VA VD GND
101112131415161718192021222324252627282930313233343536
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
CLKLAT
C11
0.1mF
Q0Q1Q2Q3Q4Q5Q6
VD
C9
0.1mF
17
16
15
D2
REFIN
C5
D3
GND
4
0.1mF
5
GND
VA
VDD
AIN
6
C1
0.1mF
11
Q7
CLOCK
GND
10
14
13
12
D4
D5
D6
AIN
VA1
VA
8
C4
C8
VA
T1
J1
GND
9
0.1mF
0.1mF
C6
321
456
E4
E3
0.1mF
7
E38
E39
C10
E37
E35
0.1mF
CLKDAC
28272625242322212019181716
CLK
U3
AD9760
DB9
123456789
DA7
C13
U5
R9
50V
E36
E34
11
D7
10
ENC
R7
25V
C7
0.1mF
C17
0.1mF
E19
E18
E21
J2
R4
50V
37
VDAC
DVDD
DCOM
DB8
DB7
DA6
DA5
0.1mF
VCC
SN74LVC86
J3
VDAC
P2
C37DRPF
J5
0.1mF
AVDD
COMP2
DB5
DB4
DA3
DA2
VDL
4A4Y3B
ENC
R10
C14
IOUTA
IOUTB
DB3
DB2
DA1
DA0
VDL
E13
E14
CLKLAT
CLKCON
E17E15
VDL
50V
0.1mF
ACOM
DB1
E12
3A
E16
C15
NC5
DB6
DA4
131412111098
4B
1B1A1Y2A2B2YGND
2134567
R21
50V
R22
50V
VDAC
FSADJ
COMP1
DB0
NC1
101112
CLKDAC
3Y
AD9283
R23
2kV
C12
15
REFIO
SLEEP
REFLO
NC2
NC3
NC4
14
13
0.1mF
Figure 26. Printed Circuit Board Schematic
–11–REV. B
AD9283
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Shrink Small Outline Package (SSOP)
(RS-20)
0.295 (7.50)
0.271 (6.90)
20 11
C3389b–0–9/99
0.311 (7.9)
0.301 (7.64)
0.078 (1.98)
0.068 (1.73)
0.008 (0.203)
0.002 (0.050)
PIN 1
0.0256
(0.65)
BSC
101
0.07 (1.78)
0.066 (1.67)
SEATING
PLANE
0.212 (5.38)
0.205 (5.21)
0.009 (0.229)
0.005 (0.127)
8°
0°
0.037 (0.94)
0.022 (0.559)
–12–
PRINTED IN U.S.A.
REV. B
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