Datasheet AD9281 Datasheet (ANALOG DEVICES)

Dual Channel 8-Bit

REV. F

©1999-2011 Analog Devices, Inc. All rights reserved.

781/461-3113

a

FEATURES
Complete Dual Matching ADC
Low Power Dissipation: 225 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.1 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 49.2 dB
Over Seven Effective Bits
Spurious-Free Dynamic Range: –65 dB
No Missing Codes Guaranteed
28-Lead SSOP

PRODUCT DESCRIPTION

The AD9281 is a complete dual channel, 28 MSPS, 8-bit
CMOS ADC. The AD9281 is optimized specifically for applica­tions where close matching between two ADCs is required (e.g.,
I/Q channels in communications applications). The 28 MHz
sampling rate and wide input bandwidth will cover both narrow­band and spread-spectrum channels. The AD9281 integrates
two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal
voltage reference and multiplexed digital output buffers.

Each ADC incorporates a simultaneous sampling sample-and­hold amplifier at its input. The analog inputs are buffered; no
external input buffer op amp will be required in most applica­tions. The ADCs are implemented using a multistage pipeline
architecture that offers accurate performance and guarantees no
missing codes. The outputs of the ADCs are ported to a multi­plexed digital output buffer.

The AD9281 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and
consumes 225 mW of power (on 3 V supply). The AD9281
input structure accepts either single-ended or differential signals,
providing excellent dynamic performance up to and beyond
14 MHz Nyquist input frequencies.

Resolution CMOS ADC

AD9281

FUNCTIONAL BLOCK DIAGRAM

IINA

IINB

IREFB

IREFT

QREFB
QREFT

VREF

REFSENSE

QINB

QINA

AVDD AVSS

"I" ADC

REFERENCE

BUFFER

"Q" ADC

CLOCK

I

REGISTER

ASYNCHRONOUS

MULTIPLEXER

1V

Q

REGISTER

PRODUCT HIGHLIGHTS

1. Dual 8-Bit, 28 MSPS ADC
A pair of high performance 28 MSPS ADCs that are opti­mized for spurious free dynamic performance are provided for
encoding of I and Q or diversity channel information.

2. Low Power
Complete CMOS Dual ADC function consumes a low
225 mW on a single supply (on 3 V supply). The AD9281
operates on supply voltages from 2.7 V to 5.5 V.

3. On-Chip Voltage Reference
The AD9281 includes an on-chip compensated bandgap
voltage reference pin programmable for 1 V or 2 V.

4. On-chip analog input buffers eliminate the need for external
op amps in most applications.

5. Single 8-Bit Digital Output Bus
The AD9281 ADC outputs are interleaved onto a single
output bus saving board space and digital pin count.

6. Small Package
The AD9281 offers the complete integrated function in a
compact 28-lead SSOP package.

7. Product Family
The AD9281 dual ADC is pin compatible with a dual 10-bit
ADC (AD9201).

DVDD DVSS

AD9281

THREE-

STATE
OUTPUT
BUFFER

SLEEP

SELECT

DATA
8 BITS

CHIP
SELECT

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax:

AD9281–SPECIFICATIONS

REV. F

(AVDD = +3 V, DVDD = +3 V, F
unless otherwise noted)

= 28 MSPS, VREF = 2 V, INB = 0.5 V, T

SAMPLE

MIN

to T

Parameter Symbol Min Typ Max Units Condition

RESOLUTION 8 Bits

CONVERSION RATE F

S

28 MHz (32 MHz at +25°C)

DC ACCURACY

Differential Nonlinearity DNL ± 0.1 LSB REFT = 1.0 V, REFB = 0.0 V
Integral Nonlinearity INL ± 0.25 LSB
Differential Nonlinearity (SE)
Integral Nonlinearity (SE)
Zero-Scale Error, Offset Error E
Full-Scale Error, Gain Error E

1

1

DNL ±0.2 ± 1.0 LSB REFT = 1.0 V, REFB = 0.0 V
INL ± 0.3 ± 1.5 LSB

ZS

FS

± 1 ± 3.2 % FS
± 1.2 ± 5.4 % FS

Gain Match ± 0.2 LSB
Offset Match ± 1.2 LSB

ANALOG INPUT

Input Voltage Range AIN –0.5 AVDD/2 V
Input Capacitance C
Aperture Delay t
Aperture Uncertainty (Jitter) t

IN

AP

AJ

2pF
4ns

2ps
Aperture Delay Match 2 ps
Input Bandwidth (–3 dB) BW

Small Signal (–20 dB) 240 MHz
Full Power (0 dB) 245 MHz

INTERNAL REFERENCE

Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF
Output Voltage Tolerance (1 V Mode) ± 10 mV
Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND
Output Voltage Tolerance (2 V Mode) ± 15 mV
Load Regulation (1 V Mode) VREF ±10 ± 35 mV 1 mA Load Current
Load Regulation (2 V Mode) ± 15 mV 1 mA Load Current

POWER SUPPLY

Operating Voltage AVDD 2.7 3 5.5 V

DVDD 2.7 3 5.5 V

Supply Current I

Power Consumption P

AVDD

I

DVDD

D

75 mA

0.1 mA

225 260 mW
Power-Down 16 mW STBY = AVDD, Clock Low
Power Supply Rejection PSR 0.15 0.75 % FS

DYNAMIC PERFORMANCE

2

Signal-to-Noise and Distortion SINAD

f = 3.58 MHz 46.4 49.1 dB
f = 14 MHz 48 dB

Signal-to-Noise SNR

f = 3.58 MHz 47.8 49.2 dB
f = 14 MHz 48.5 dB

Total Harmonic Distortion THD

f = 3.58 MHz –67.5 –49.5 dB
f = 14 MHz –60 dB

Spurious Free Dynamic Range SFDR

f = 3.58 MHz 49.6 65 dB
f = 14 MHz 56 dB

Two-Tone Intermodulation Distortion

3

IMD –58 dB f = 44.9 MHz and 45.52 MHz
Differential Phase DP 0.2 Degree NTSC 40 IRE Mod Ramp
Differential Gain DG 0.08 % F

= 14.3 MHz

S

Crosstalk Rejection –62 dB

MAX

–2–

Parameter Symbol Min Typ Max Units Condition

REV. F

DYNAMIC PERFORMANCE (SE)

1

Signal-to-Noise and Distortion SINAD

f = 3.58 MHz 47.2 dB

Signal-to-Noise SNR

f = 3.58 MHz 48 dB

Total Harmonic Distortion THD

f = 3.58 MHz –55 dB

Spurious Free Dynamic Range SFDR

f = 3.58 MHz –58 dB

DIGITAL INPUTS

High Input Voltage V
Low Input Voltage V
DC Leakage Current I
Input Capacitance C

IH

IL

IN

IN

2.4 V

0.3 V

± 6 µA

2pF

LOGIC OUTPUT (with DVDD = 3 V)

High Level Output Voltage

(I

= 50 µA) V

OH

OH

2.88 V

Low Level Output Voltage

(IOL = 1.5 mA) V

OL

0.095 V

LOGIC OUTPUT (with DVDD = 5 V)

High Level Output Voltage

(I

= 50 µA) V

OH

OH

4.5 V

Low Level Output Voltage

(I

= 1.5 mA) V

OL

Data Valid Delay t
MUX Select Delay t
Data Enable Delay t

OL

OD

MD

ED

0.4 V
11 ns
7ns
13 ns CL = 20 pF. Output Level to

90% of Final Value

Data High-Z Delay t

DHZ

13 ns

CLOCKING

Clock Pulsewidth High t
Clock Pulsewidth Low t

CH

CL

16.9 ns

16.9 ns

Pipeline Latency 3.0 Cycles

NOTES

1

SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.

2

AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.

3

IMD referred to larger of two input signals.

Specifications subject to change without notice.

AD9281

CLOCK

INPUT

SELECT

INPUT

DATA

OUTPUT

t

OD

ADC SAMPLE
#1

SAMPLE #1-3

Q CHANNEL

ADC SAMPLE#2ADC SAMPLE

Q CHANNEL

OUTPUT ENABLED

OUTPUT

#3

t

MD

SAMPLE #1-1

Q CHANNEL

OUTPUT

SAMPLE #1-2

Q CHANNEL

OUTPUT

Figure 1. ADC Timing

–3–

ADC SAMPLE
#4

SAMPLE #1-1
I CHANNEL
OUTPUT

SAMPLE #1
Q CHANNEL
OUTPUT

SAMPLE #1
I CHANNEL
OUTPUT

ADC SAMPLE
#5

I CHANNEL
OUTPUT ENABLED

SAMPLE #2
Q CHANNEL
OUTPUT

AD9281

REV. F

DNC

DNC

DNC

DNC

Do not connect

Do not connect

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Parameter to Min Max Units

AVDD AVSS –0.3 +6.5 V
DVDD DVSS –0.3 +6.5 V
AVSS DVSS –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLK AVSS –0.3 AVDD + 0.3 V
Digital Outputs DVSS –0.3 DVDD + 0.3 V
AINA, AINB AVSS –1.0 AVDD + 0.3 V
VREF AVSS –0.3 AVDD + 0.3 V
REFSENSE AVSS –0.3 AVDD + 0.3 V
REFT, REFB AVSS –0.3 AVDD + 0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature

10 sec +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.

PIN CONFIGURATION

DVSS

DVDD

(LSB) D0

(MSB) D7

SELECT

CLOCK

AD9281

D1

TOP VIEW

(Not to Scale)

D2

D3

D4

D5

D6

NC = NO CONNECT

CHIP-SELECT

INA-Q

INB-Q

REFT-Q

REFB-Q

AVDD

VREF

REFSENSE

AVSS

REFB-I

REFT-I

INB-I

INA-I

SLEEP

PIN FUNCTION DESCRIPTIONS

P

in

No. Name Description

1 DVSS Digital Ground
2 DVDD Digital Supply
3
4
5 D0 Bit 0 (LSB)
6 D1 Bit 1
7 D2 Bit 2
8 D3 Bit 3
9 D4 Bit 4
10 D5 Bit 5
11 D6 Bit 6
12 D7 Bit 7 (MSB)

13 SELECT Hi I Channel Out, Lo Q Channel Out
14 CLOCK Clock
15 SLEEP Hi Power Down, Lo Normal Operation

16 INA-I I Channel, A Input
17 INB-I I Channel, B Input
18 REFT-I Top Reference Decoupling, I Channel
19 REFB-I Bottom Reference Decoupling, I Channel
20 AVSS Analog Ground
21 REFSENSE Reference Select
22 VREF Internal Reference Output
23 AVDD Analog Supply
24 REFB-Q Bottom Reference Decoupling, Q Channel
25 REFT-Q Top Reference Decoupling, Q Channel
26 INB-Q Q Channel B Input
27 INA-Q Q Channel A Input
28 CHIP-SELECT Hi-High Impedance, Lo-Normal Operation

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code transi­tion. “Full scale” is defined as a level 1 1/2 LSBs beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9281 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

AVDD

REV. F

DRVDD

AVDD

AVDD

AVDD

AD9281

AVDD

AVSS

DRVSS

DRVSS

AVSS

AVSS

AVSS

a. D0–D9 b. Three-State Standby c. CLK

AVDD

AVDD

AVSS

AVSS

AVDD

AVSS

AVDD

AVSS

AVSS

AVDD

IN

AVDD

REFBS

AVSS

REFBF

d. INA, INB e. Reference f. REFSENSE g. VREF

Figure 2. Equivalent Circuits

OFFSET ERROR

The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-

scale. Gain error is the deviation of the actual difference be­tween first and last code transitions and the ideal difference
between the first and last code transitions.

tion from that point.

GAIN MATCH

OFFSET MATCH

The change in gain error between I and Q channels.

The change in offset error between I and Q channels.

PIPELINE DELAY (LATENCY)

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the num­ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

It is possible to get a measure of performance expressed as N,
the effective number of bits.

The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising clock edge.

MUX SELECT DELAY

The delay between the change in SELECT pin data level and
valid data on output pins.

Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.

POWER SUPPLY REJECTION

The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value

TOTAL HARMONIC DISTORTION (THD)

with the supply at its maximum limit.

THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of the measured input signal and
is expressed as a percentage or in decibels.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.

APERTURE DELAY

Aperture delay is a measure of the Sample-and-Hold Amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.

AVSS

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.

GAIN ERROR

The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full

–5–

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO

S/N+D is the ratio of the rms value of the measured input sig­nal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.

AD9281

REV. F

–Typical Characteristic Curves

(AVDD = +3 V, DVDD = +3 V, FS = 28 MHz (50% duty cycle), 2 V input span from –0.5 V to +1.5 V, 2 V internal reference unless otherwise noted)

1

0

LSB

–1

16 32 48 64 80 96 112 128 144160 176 192 208 224 240

0

CODE OFFSET

Figure 3. Typical INL

1

0

LSB

55

50

45

40

SNR – dB

35

30

25

1.0E+05

1.0E+06 1.0E+07 1.0E+08
INPUT FREQUENCY – Hz

Figure 6. SNR vs. Input Frequency

55

50

45

40

SNR – dB

35

–0.5dB

–6dB

–0.5dB

–6dB

–20dB

–1

16 32 48 64 80 96 112 128 144160 176 192 208 224 240

0

CODE OFFSET

Figure 4. Typical DNL

1.00

0.80

0.60

0.40

0.20

0.00

– nA

B

I

–0.20

–0.40

–0.60

–0.80

–1.00

–1.0 2.0–0.5

0 0.5 1.0 1.5

INPUT VOLTAGE – Volts

Figure 5. Input Bias Current vs. Input Voltage

30

25

1.0E+05

–20dB

1.0E+06 1.0E+07 1.0E+08
INPUT FREQUENCY – Hz

Figure 7. SINAD vs. Input Frequency

–30

–35

–40

–45

–50

THD – dB

–55

–60

–65

–70

1.0E+05

1.0E+06 1.0E+07 1.0E+08
INPUT FREQUENCY – Hz

–20dB

–6dB

–0.5dB

Figure 8. THD vs. Input Frequency

–6–

AD9281

INPUT FREQUENCY – Hz

0

1.00E+06

AMPLITUDE – dB

–3

–6

–9

–12

–15

–21

1.00E+07 1.00E+08 1.00E+09

–24

–27

–18

REV. F

70

65

60

55

50

45

THD – dB

40

35

30

25

20

1.00E+06 1.00E+081.00E+07
CLOCK FREQUENCY – Hz

Figure 9. THD vs. Clock Frequency

1.013

1.012

1.011

– Volts

REF

1.010

V

1.20E+07

1.00E+07

8.00E+06

6.00E+06

HITS

4.00E+06

2.00E+06

0.00E+00

10000000

12050

N

CODE

800

N+1N–1

Figure 12. Grounded Input Histogram

1.009

1.008
–40 100–20

020406080

TEMPERATURE – 8C

Figure 10. Voltage Reference Error vs. Temperature

240

235

230

225

220

215

210

205

200

POWER CONSUMPTION – mW

195

190

185

0324

8 1216 202428

CLOCK FREQUENCY – MHz

Figure 11. Power Consumption vs. Clock Frequency

Figure 13. Full Power Bandwidth

50

–0.5dB

45

–6dB

40

SNR – dB

35

30

–20dB

25

1.00E+05

1.00E+06 1.00E+07 1.00E+08
INPUT FREQUENCY – Hz

Figure 14. SNR vs. Input Frequency (Single-Ended)

–7–

AD9281

REV. F

10.0

0.0

–10.0

–20.0

–30.0

–40.0

–50.0

SNR – dB

–60.0

–70.0

–80.0

–90.0

–100.0

–110.0

0.0E+0

FUND

5TH

9TH

3RD

8TH

4TH

7TH

2ND

2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6

6TH

Figure 15a. Simultaneous Operation of I and Q Channels

10.0
FUND

0.0

–10.0

–20.0

–30.0

–40.0

–50.0

SNR – dB

–60.0

–70.0

–80.0

–90.0

–100.0

–110.0

2ND

2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6

0.0E+0

3RD

4TH

5TH

6TH

7TH

8TH

Figure 15b. Simultaneous Operation of I and Q Channels

converter to readily accommodate either single-ended or differ­ential input signals. This differential structure makes the part
capable of accommodating a wide range of input signals.

The AD9281 also includes an on-chip bandgap reference and
reference buffer. The reference buffer shifts the ground-referred
reference to levels more suitable for use by the internal circuits
of the converter. Both converters share the same reference and
reference buffer. This scheme provides for the best possible gain
match between the converters while simultaneously minimizing
the channel-to-channel crosstalk.

Each A/D converter has its own output latch, which updates on
the rising edge of the input clock. A logic multiplexer, con­trolled through the SELECT pin, determines which channel is
passed to the digital output pins. The output drivers have their
own supply, allowing the part to be interfaced to a variety of
logic families. The outputs can be placed in a high impedance
state using the CHIP SELECT pin.

The AD9281 has great flexibility in its supply voltage. The
analog and digital supplies may be operated from 2.7 V to 5.5 V,
independently of one another.

ANALOG INPUT

Figure 16 shows an equivalent circuit structure for the analog
input of one of the A/D converters. PMOS source-followers
buffer the analog input pins from the charge kickback problems
normally associated with switched capacitor ADC input struc­tures. This produces a very high input impedance on the part,
allowing it to be effectively driven from high impedance sources.
This means that the AD9281 could even be driven directly by a
passive antialias filter.

THEORY OF OPERATION

The AD9281 integrates two A/D converters, two analog input
buffers, an internal reference and reference buffer, and an out­put multiplexer. For clarity, this data sheet refers to the two
converters as “I” and “Q.” The two A/D converters simulta­neously sample their respective inputs on the rising edge of the
input clock. The two converters distribute the conversion opera­tion over several smaller A/D sub-blocks, refining the conversion
with progressively higher accuracy as it passes the result from
stage to stage. As a consequence of the distributed conversion,
each converter requires a small fraction of the 256 comparators
used in a traditional flash-type 8-bit ADC. A sample-and-hold
function within each of the stages permits the first stage to oper­ate on a new input sample while the following stages continue to
process previous samples. This results in a “pipeline processing”
latency of three clock periods between when an input sample is
taken and when the corresponding ADC output is updated into
the output registers.

The AD9281 integrates input buffer amplifiers to drive the
analog inputs of the converters. In most applications, these
input amplifiers eliminate the need for external op amps for the
input signals. The input structure is fully differential, but the
SHA common-mode response has been designed to allow the

IINA

IINB

BUFFER

BUFFER

SHA

+FS LIMIT =

V

REF

V

REF

+V

REF/2

+FS

LIMIT

ADC

CORE

–FS

LIMIT

–FS LIMIT =
V

REF

OUTPUT

WORD

–V

REF/2

Figure 16. Equivalent Circuit for AD9281 Analog Inputs

The source followers inside the buffers also provide a level-shift
function of approximately 1 V, allowing the AD9281 to accept
inputs at or below ground. One consequence of this structure is
that distortion will result if the analog input comes within 1.4 V
of the positive supply. For optimum high frequency distortion
performance, the analog input signal should be centered accord­ing to Figure 27.

The capacitance load of the analog input pin is 4 pF to the
analog supplies (AVSS, AVDD).

Full-scale setpoints may be calculated according to the following
algorithm (V

= V

–F

S

+F

= V

S

V

SPAN

may be internally or externally generated):

REF

REF

REF

= V

– (V

+ (V

REF

REF

REF

/2)

/2)

–8–

The AD9281 can accommodate a variety of input spans be-

0.1mF

10mF

0.1mF

0.1mF

ANALOG

INPUT

1.0mF 0.1mF

1kV

1.5V

0.5V

I OR QREFT

I OR QREFB

IINA

IINB

VREF

AD9281

REFSENSE

DVDD

I OR QREFT

I OR QREFB

AVDD

0.1mF

10mF

0.1mF10mF

AD9281

0.1mF

0.1mF

0.1mF10mF

V ANALOG V DIGITAL

REV. F

tween 1 V and 2 V. For spans of less than 1 V, expect a propor­tionate degradation in SNR. Use of a 2 V span will provide the
best noise performance. 1 V spans will provide lower distortion
when using a 3 V analog supply. Users wishing to run with larger
full-scales are encouraged to use a 5 V analog supply (AVDD).

Single-Ended Inputs: For single-ended input signals, the
signal is applied to one input pin and the other input pin is tied
to a midscale voltage. This midscale voltage defines the center
of the full-scale span for the input signal.

EXAMPLE: For a single-ended input range from 0 V to 1 V
applied to IINA, we would configure the converter for a 1 V
reference (see Figure 17) and apply 0.5 V to IINB.

1V

INPUT

MIDSCALE

VOLTAGE

= 0.5V (1V)

5kV 5kV

0V

IINA

I OR QREFT

0.1mF

I OR QREFB

10mF

IINB

0.1mF

AD9281

VREF

REF SENSE

0.1mF

10mF

0.1mF

10mF

0.1mF

Figure 17. Example Configuration for 0 V–1 V Single­Ended Input Signal

Note that since the inputs are high impedance, this reference
level can easily be generated with an external resistive divider
with large resistance values (to minimize power dissipation). A
decoupling capacitor is recommended on this input to minimize
the high frequency noise-coupling onto this pin. Decoupling
should occur close to the ADC.

Differential Inputs

Use of differential input signals can provide greater flexibility in
input ranges and bias points, as well as offering improvements in
distortion performance, particularly for high frequency input
signals. Users with differential input signals will probably want
to take advantage of the differential input structure of the AD9281.
Performance is still very good for single-ended inputs. Convert­ing a single-ended input to a differential signal for application to
the converter is probably only worth considering for very high
frequency input signals.

AC-Coupled Inputs

If the signal of interest has no dc component, ac coupling can be
easily used to define an optimum bias point. Figure 18 illustrates
one recommended configuration. The voltage chosen for the dc
bias point (in this case the 1 V reference) is applied to both

IINA and IINB pins through 1 kΩ resistors (R1 and R2). IINA

is coupled to the input signal through Capacitor C1, while IINB is
decoupled to ground through Capacitor C2.

AD9281

Figure 18. Example Configuration for 0.5 V–1.5 V ac
Coupled Single-Ended Inputs

Transformer Coupled Inputs

Another option for input ac coupling is to use a transformer.
This not only provides dc rejection, but also allows truly differ­ential drive of the AD9281’s analog inputs, which will provide
the optimal distortion performance. Figure 19 shows a recom­mended transformer input drive configuration. Resistors R1 and
R2 define the termination impedance of the transformer cou­pling. The center tap of the transformer secondary is tied to the
common-mode voltage, establishing the dc bias point for the
analog inputs.

AD9281

I OR QREFT

I OR QREFB

QINA

QINB

QINA

R2

QINB

0.1mF

0.1mF10mF

0.1mF

IINA

R1

IINB

COMMON

MODE

VOLTAGE

10mF

0.1mF

VREF

REFSENSE

Figure 19. Example Configuration for Transformer
Coupled Inputs

Crosstalk: The internal layout of the AD9281, as well as its
pinout, was configured to minimize the crosstalk between the
two input signals. Users wishing to minimize high frequency
crosstalk should take care to provide the best possible decoupling
for input pins (see Figure 20). R and C values will make a pole
dependant on antialiasing requirements. Decoupling is also
required on reference pins and power supplies (see Figure 21).

IINA

AD9281

IINB

Figure 20. Input Loading

Figure 21. Reference and Power Supply Decoupling

–9–

AD9281

REV. F

REFERENCE AND REFERENCE BUFFER

The reference and buffer circuitry on the AD9281 is configured
for maximum convenience and flexibility. An illustration of the
equivalent reference circuit is show in Figure 26. The user can
select from five different reference modes through appropriate
pin-strapping (see Table I below). These pin strapping options
cause the internal circuitry to reconfigure itself for the appropri­ate operating mode.

Table I. Table of Modes

Mode Input Span REFSENSE Pin Figure

1 V 1 V VREF 22
2 V 2 V AGND 23
Programmable 1 + (R1/R2) See Figure 24
External = External Ref AVDD 25

1 V Mode (Figure 22)—provides a 1 V reference and 1 V input
full scale. Recommended for applications wishing to optimize
high frequency performance, or any circuit on a supply voltage
of less than 4 V. The part is placed in this mode by shorting the
REFSENSE pin to the VREF pin.

1V

0V

5kV

0.1mF

10mF

5kV

10mF

0.1mF

1V

IINA

IINB

AD9281

VREF

REFSENSE

I OR QREFT

I OR QREFB

QINA

QINB

1V

0V

0.1mF

0.1mF10mF

0.1mF

Figure 22. 0 V to 1 V Input

2 V Mode (Figure 23)—provides a 2 V reference and 2 V input
full scale. Recommended for noise sensitive applications on 5 V
supplies. The part is placed in 2 V reference mode by ground­ing (shorting to AVSS) the REFSENSE pin.

2V

0V

5kV

0.1mF

10mF

5kV

10mF

0.1mF

IINA

IINB

AD9281

VREF

I OR QREFT

I OR QREFB

REFSENSE

QINA

QINB

2V

0V

0.1mF

0.1mF10mF

0.1mF

Externally Set Voltage Mode (Figure 24)—this mode uses
the on-chip reference, but scales the exact reference level though
the use of an external resistor divider network. VREF is wired to
the top of the network, with the REFSENSE wired to the tap
point in the resistor divider. The reference level (and input full
scale) will be equal to 1 V × (R1 + R2)/R1. This method can be
used for voltage levels from 0.7 V to 2.5 V.

1mF

0.1mF

VREF = 1 +

VREF

R2

REFSENSE

R1

AVSS

R2
R1

+
–

AD9281

I OR QREFT

I OR QREFB

1V

+

–

0.1mF

0.1mF10mF

0.1mF

Figure 24. Programmable Reference

External Reference Mode (Figure 25)—in this mode, the on­chip reference is disabled, and an external reference applied to
the VREF pin. This mode is achieved by tying the REFSENSE
pin to AVDD.

1V

0V

EXT

REFERENCE

5kV

1V

10mF

10mF

0.1mF

5kV

0.1mF

AVDD

IINA

IINB

AD9281

VREF

I OR QREFT

I OR QREFB

REFSENSE

QINA

QINB

1V

0V

0.1mF

0.1mF10mF

0.1mF

Figure 25. External Reference

Reference Buffer—The reference buffer structure takes the
voltage on the VREF pin and level-shifts and buffers it for use
by various sub-blocks within the two A/D converters. The two
converters share the same reference buffer amplifier to maintain
the best possible gain match between the two converters. In the
interests of minimizing high frequency crosstalk, the buffered
references for the two converters are separately decoupled on
the IREFB, IREFT, QREFB and QREFT pins, as illustrated in
Figure 26.

Figure 23. 0 V to 2 V Input

–10–

ADC

–15

–0.5

THD – dB

–25

–35

–45

–55

–65

0 0.5 1 1.5

CML – V

2V

1V

–15

–0.5

THD – dB

–25

–35

–45

–55

–65

0 0.5 1 1.5

CML – V

2V

1V

2 2.5

REV. F

CORE

0.1mF

0.1mF

IREFT

0.1mF10mF

IREFB

VREF

0.1mF1.0mF

REFSENSE

AVSS

10kV

10kV

1V

INTERNAL

CONTROL

LOGIC

AD9281

QREFT

0.1mF10mF

QREFB

0.1mF

0.1mF

Figure 26. Reference Buffer Equivalent Circuit and
External Decoupling Recommendation

For best results in both noise suppression and robustness
against crosstalk, the 4-capacitor buffer decoupling arrangement
shown in Figure 26 is recommended. This decoupling should

–3

AD9281

feature chip capacitors located close to the converter IC. The
capacitors are connected to either IREFT/IREFB or QREFT/
QREFB. A connection to both sides is not required.

COMMON-MODE PERFORMANCE

Attention to the common-mode point of the analog input volt­age can improve the performance of the AD9281. Figure 27
illustrates THD as a function of common-mode voltage (center
point of the analog input span) and power supply.

Inspection of the curves will yield the following conclusions:

1. An AD9281 running with AVDD = 5 V is the easiest to
drive.

2. Differential inputs are the most insensitive to common-mode
voltage.

3. An AD9281 powered by AVDD = 3 V and a single ended
input, should have a 1 V span with a common-mode voltage
of 0.75 V.

–13

–23

–33

2V

–43

THD – dB

–53

1V

–63

–73

–0.5

–35

–40

–45

–50

–55

THD – dB

–60

–65

–70

–0.5

0 0.5 1 1.5

CML – V

a. Differential Input, 3 V Supplies

2V

1V

0 0.5 1 1.5

CML – V

2 2.5

b. Differential Input, 5 V Supplies

c. Single-Ended Input, 3 V Supplies

d. Single-Ended Input, 5 V Supplies

Figure 27. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz)

–11–

AD9281

REV. F

DIGITAL INPUTS AND OUTPUTS

Each of the AD9281 digital control inputs, CHIP SELECT,
CLOCK, SELECT and SLEEP are referenced to AVDD and
AVSS. Switching thresholds will be AVDD/2.

The format of the digital output is straight binary. A low power
mode feature is provided such that for STBY = HIGH and the
clock disabled, the static power of the AD9281 will drop below
22 mW.

CLOCK INPUT

The AD9281 clock input is internally buffered with an inverter
powered from the AVDD pin. This feature allows the AD9281
to accommodate either +5 V or +3.3 V CMOS logic input sig­nal swings with the input threshold for the CLK pin nominally
at AVDD/2.

The pipelined architecture of the AD9281 operates on both
rising and falling edges of the input clock. To minimize duty
cycle variations the logic family recommended to drive the clock
input is high speed or advanced CMOS (HC/HCT, AC/ACT)
logic. CMOS logic provides both symmetrical voltage threshold
levels and sufficient rise and fall times to support 28 MSPS
operation. Running the part at slightly faster clock rates may be
possible, although at reduced performance levels. Conversely,
some slight performance improvements might be realized by
clocking the AD9281 at slower clock rates.

The power dissipated by the output buffers is largely propor­tional to the clock frequency; running at reduced clock rates
provides a reduction in power consumption.

DIGITAL OUTPUTS

Each of the on-chip buffers for the AD9281 output bits (D0–D9)
is powered from the DVDD supply pin, separate from AVDD.
The output drivers are sized to handle a variety of logic families
while minimizing the amount of glitch energy generated. In all
cases, a fan-out of one is recommended to keep the capacitive
load on the output data bits below the specified 20 pF level.

For DVDD = 5 V, the AD9281 output signal swing is compat­ible with both high speed CMOS and TTL logic families. For
TTL, the AD9281 on-chip, output drivers were designed to
support several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below 28 MSPS, other TTL
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD9281 sustains 28 MSPS operation with
DVDD = 3 V. In all cases, check your logic family data sheets
for compatibility with the AD9281’s Specification table.

A 2 ns reduction in output delays can be achieved by limiting
the logic load to 5 pF per output line.

THREE-STATE OUTPUTS

The digital outputs of the AD9281 can be placed in a high
impedance state by setting the CHIP SELECT pin to HIGH.
This feature is provided to facilitate in-circuit testing or evaluation.

SELECT

When the select pin is held LOW, the output word will present
the “Q” level. When the select pin is held HIGH, the “I” level
will be presented to the output word (see Figure 1).

The AD9281’s select and clock pins may be driven by a com­mon signal source. The data will change in 5 ns to 11 ns after
the edges of the input pulse. The user must make sure the inter­face latches have sufficient hold time for the AD9281’s delays
(see Figure 28).

CLOCK

CLOCK

SOURCE

SELECT

CLK

DATA

OUT

I LATCH

DATA

DATA

Q LATCH

CLOCK

I

PROCESSING

Q

PROCESSING

Figure 28. Typical De-Mux Connection

APPLICATIONS
USING THE AD9281 FOR QAM DEMODULATION

QAM is one of the most widely used digital modulation schemes in
digital communication systems. This modulation technique
can be found in both FDMA as well as spread spectrum (i.e.,
CDMA) based systems. A QAM signal is a carrier frequency
which is both modulated in amplitude (i.e., AM modulation)
and in phase (i.e., PM modulation). At the transmitter, it can
be generated by independently modulating two carriers of iden­tical frequency but with a 90° phase difference. This results in
an inphase (I) carrier component and a quadrature (Q) carrier
component at a 90° phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier or IF frequency. Figure 29 shows
a typical analog implementation of a QAM modulator using a
dual 10-bit DAC with 2× interpolation, the AD9761. A QAM
signal can also be synthesized in the digital domain thus requir­ing a single DAC to reconstruct the QAM signal. The AD9853
is an example of a complete (i.e., DAC included) digital QAM
modulator.

IOUT

DSP

OR

ASIC

10

AD9761

QOUT

CARRIER

FREQUENCY

NYQUIST
FILTERS

0

90

QUADRATURE

MODULATOR

TO
MIXER

Figure 29. Typical Analog QAM Modulator Architecture

–12–

ANALOG

CIRCUITS

DIGITAL

LOGIC

ICs

DV

AA

D

DVSSAVSS

A

B

I

A

I

D

AVDD

DVDD

LOGIC

SUPPLY

D

A

V

IN

C

STRAY

C

STRAY

GND

A

= ANALOG

D

= DIGITAL

ADC

IC

DIGITAL

CIRCUITS

A A

DATA

ANALOG
GROUND

DIGITAL

GROUND

LOGIC

ADC

AIN

BIN

RF

GROUND

REV. F

At the receiver, the demodulation of a QAM signal back into its
separate I and Q components is essentially the modulation
process explain above but in the reverse order. A common and
traditional implementation of a QAM demodulator is shown in
Figure 30. In this example, the demodulation is performed in
the analog domain using a dual, matched ADC and a quadra­ture demodulator to recover and digitize the I and Q baseband
signals. The quadrature demodulator is typically a single IC
containing two mixers and the appropriate circuitry to generate
the necessary 90° phase shift between the I and Q mixers’ local
oscillators. Before being digitized by the ADCs, the mixed
down baseband I and Q signals are filtered using matched ana­log filters. These filters, often referred to as Nyquist or Pulse­Shaping filters, remove images-from the mixing process and any
out-of-band. The characteristics of the matching Nyquist filters
are well defined to provide optimum signal-to-noise (SNR)
performance while minimizing intersymbol interference. The
ADC’s are typically simultaneously sampling their respective
inputs at the QAM symbol rate or, most often, at a multiple of it
if a digital filter follows the ADC. Oversampling and the use of
digital filtering eases the implementation and complexity of the
analog filter. It also allows for enhanced digital processing for
both carrier and symbol recovery and tuning purposes. The use
of a dual ADC such as the AD9281 ensures excellent gain,
offset, and phase matching between the I and Q channels.

I

ADC

DSP

OR

ASIC

Q

ADC

DUAL MATCHED

ADC

CARRIER

FREQUENCY

NYQUIST

FILTERS

LO

DEMODULATOR

90°C

QUADRATURE

FROM
PREVIOUS
STAGE

Figure 30. Typical Analog QAM Demodulator

GROUNDING AND LAYOUT RULES

As is the case for any high performance device, proper ground­ing and layout techniques are essential in achieving optimal
performance. The analog and digital grounds on the AD9281
have been separated to optimize the management of return
currents in a system. Grounds should be connected near the
ADC. It is recommended that a printed circuit board (PCB) of
at least four layers, employing a ground plane and power planes,
be used with the AD9281. The use of ground and power planes
offers distinct advantages:

1. The minimization of the loop area encompassed by a signal
and its return path.

2. The minimization of the impedance associated with ground
and power paths.

3. The inherent distributed capacitor formed by the power plane,
PCB insulation and ground plane.

AD9281

Figure 31. Ground and Power Consideration

These characteristics result in both a reduction of electro­magnetic interference (EMI) and an overall improvement in
performance.

It is important to design a layout that prevents noise from cou­pling onto the input signal. Digital signals should not be run in
parallel with the input signal traces and should be routed
away from the input circuitry. Separate analog and digital
grounds should be joined together directly under the AD9281 in
a solid ground plane. The power and ground return currents
must be carefully managed. A general rule of thumb for mixed
signal layouts dictates that the return currents from digital cir­cuitry should not pass through critical analog circuitry.

Transients between AVSS and DVSS will seriously degrade
performance of the ADC.

If the user cannot tie analog ground and digital ground together
at the ADC, he should consider the configuration in Figure 32.

Another input and ground technique is shown in Figure 32. A
separate ground plane has been split for RF or hard to manage
signals. These signals can be routed to the ADC differentially or
single ended (i.e., both can either be connected to the driver or
RF ground). The ADC will perform well with several hundred
mV of noise or signals between the RF and ADC analog ground.

Figure 32. RF Ground Scheme

–13–

AD9281

REVISION HISTORY

1/11—Rev. E to Rev. F

Updated Format .................................................................. Universal

Changes to Pin Configuration Diagram ........................................ 4

Changes to Pin Function Descriptions Table ................................ 4

Removed Evaluation Boards; Renumbered

Sequentially ............................................................................ 14 to 18

Changes to Ordering Guide ........................................................... 15

8/99—Rev. D to Rev. E

Rev. F | Page 14 of 15

AD9281

15 of 15

OUTLINE DIMENSIONS

10.50

10.20

9.90

0.38

0.22

15

5.60

5.30

8.20

5.00

7.80

1.85

1.75

1.65

SEATING
PLANE

7.40

0.25

0.09

8°
4°
0°

0.95

0.75

0.55

14

2.00 MAX

0.05 MIN

COPLANARITY

0.10

28

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AH

Figure 33. 28-Lead Shrink Small Outline Package [SSOP]

(RS-28)

Dimensions shown in millimeters

ORDERING GUIDE

1, 2

Model

AD9281ARS −40°C to +85°C 28-Lead SSOP RS-28
AD9281ARSRL −40°C to +85°C 28-Lead SSOP RS-28
AD9281ARSZ −40°C to +85°C 28-Lead SSOP RS-28
AD9281ARSZRL −40°C to +85°C 28-Lead SSOP RS-28

1

Z = RoHS Compliant Part.

2

RS = Shrink Small Outline.

Temperature Range Package Description Package Option

060106-A

©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00583-0-1/11(F)

Rev. F | Page