Datasheet AD9273 Datasheet (ANALOG DEVICES)

Page 1
Octal LNA/VGA/AAF/ADC

FEATURES

8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA)
Input-referred noise voltage = 1.26 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB Single-ended input; V
550 mV p-p/367 mV p-p Dual-mode active input impedance matching Bandwidth (BW) > 100 MHz Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 50 MSPS SNR = 70 dB SFDR = 75 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) 70 mW per channel in CW Doppler Flexible power-down modes Overload recovery in <10 ns Fast recovery from low power standby mode, <2 μs 100-lead TQFP and 144-ball BGA

APPLICATIONS

Medical imaging/ultrasound Automotive radar

GENERAL DESCRIPTION

The AD9273 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a low noise preamplifier (LNA) with a variable gain amplifier (VGA); an antialiasing filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to­digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.
maximum = 733 mV p-p/
IN
and Crosspoint Switch
AD9273

FUNCTIONAL BLOCK DIAGRAM

AVDD1
AVDD2
LOSW-A
LO-A
LI-A
LG-A
LOSW-B
LO-B
LI-B
LG-B
LOSW-C
LO-C
LI-C
LG-C
LOSW-D
LO-D
LI-D
LG-D
LOSW-E
LO-E
LI-E
LG-E
LOSW-F
LO-F
LI-F
LG-F
LOSW-G
LO-G
LI-G
LG-G
LOSW-H
LO-H
LI-H
LG-H
LNA
LNA
LNA
LNA
LNA
LNA
LNA
LNA
SWITCH
ARRAY
AND
CWD[7:0]+
VGA
VGA
VGA
VGA
VGA
VGA
VGA
VGA
GAIN–
GAIN+
CWD[7:0]–
The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input-referred noise voltage is typically
1.26 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise voltage of the entire channel is 1.42 nV/√Hz at typical gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is about 91 dB. In CW Doppler mode, the LNA output drives a transconductance amp that is switched through an 8 × 8 differential crosspoint switch. The switch is programmable through the SPI.
STBY
PDWN
AAF
AAF
AAF
AAF
AAF
AAF
AAF
AAF
REFERENCE
VREF
RBIAS
Figure 1.
AD9273
12-BIT
ADC
12-BIT
ADC
12-BIT
ADC
12-BIT
ADC
12-BIT
ADC
12-BIT
ADC
12-BIT
ADC
12-BIT
ADC
SERIAL
CSB
DRVDD
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
DATA
PORT
INTERFACE
SDIO
SCLK
DOUTA+ DOUTA–
DOUTB+ DOUTB–
DOUTC+ DOUTC–
DOUTD+ DOUTD–
DOUTE+ DOUTE–
DOUTF+ DOUTF–
DOUTG+ DOUTG–
DOUTH+ DOUTH–
FCO+ FCO–
RATE
DCO+
MULTIPLIER
DCO–
CLK–
CLK+
07030-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Page 2
AD9273

TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications ..................................................................................... 4
AC Specifications .......................................................................... 4
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
ADC Timing Diagrams ................................................................. 10
Absolute Maximum Ratings .......................................................... 11
Thermal Impedance ................................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 19
Theory of Operation ...................................................................... 21
Ultrasound .................................................................................. 21
Channel Overview ..................................................................... 22
Input Overdrive .......................................................................... 25
CW Doppler Operation ............................................................. 25
TGC Operation ........................................................................... 27
ADC ............................................................................................. 31
Clock Input Considerations ...................................................... 31
Serial Port Interface (SPI) .............................................................. 38
Hardware Interface ..................................................................... 38
Memory Map .................................................................................. 40
Reading the Memory Map Table .............................................. 40
Reserved Locations .................................................................... 40
Default Values ............................................................................. 40
Logic Levels ................................................................................. 40
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 45

REVISION HISTORY

7/09—Rev. A to Rev. B
Added BGA Package .......................................................... Universal
Changes to Features and General Description Sections .............. 1
Changes to Product Highlights Section ......................................... 3
Changes to Full-Channel (TGC) Characteristics Parameter,
Table 1 ............................................................................................ 4
Changes to Gain Control Interface Parameter and to CW
Doppler Mode Parameter, Table 1 .............................................. 6
Change to Wake-Up Time (Standby), GAIN+ = 0.8 V
Parameter ....................................................................................... 9
Changes to Figure 2 and Figure 3 ................................................. 10
Changes to Table 4 .......................................................................... 11
Addded Figure 5; Renumbered Sequentially .............................. 12
Changes to Table 6 .......................................................................... 13
Changes to Figure 34 and Figure 35 ............................................. 20
Changes to Ultrasound Section .................................................... 21
Changes to Low Noise Amplifier (LNA) Section ....................... 22
Changes to Active Impedance Matching Section and
Figure 40 ...................................................................................... 23
Changes to LNA Noise Section .................................................... 24
Changes to Input Overload Protection Section and Figure 44 ....... 25
Changes to Figure 48 ...................................................................... 28
Changes to Figure 49 and Figure 50............................................. 29
Changes to Clock Input Considerations Section and to
Figure 56 to Figure 59 ................................................................ 31
Changes to Digital Outputs and Timing Section ....................... 33
Changes to CSB Pin Section ......................................................... 36
Changes to Reading the Memory Map Table Section ............... 40
Updated Outline Dimensions ....................................................... 44
Changes to Ordering Guide .......................................................... 45
4/09—Revision A: Initial Version
Rev. B | Page 2 of 48
Page 3
AD9273
The AD9273 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.
Powering down individual channels is supported to increase battery life for portable applications. There is also a standby mode option that allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The power of the time gain control (TGC) path scales with selectable speed grades.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9273 is available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP or a 144-ball BGA. It is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight channels are contained in a small,
space-saving package. A full TGC path, ADC, and crosspoint switch contained within a 100-lead, 16 mm × 16 mm TQFP or a 144-ball BGA.
2. Low Power of 109 mW per Channel at 40 MSPS.
3. Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW Doppler mode.
4. Ease of Use. A data clock output (DCO±) operates up to
300 MHz and supports double data rate (DDR) operation.
5. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter. This filter is
placed between the VGA and the ADC and is programmable from 8 MHz to 18 MHz.
Rev. B | Page 3 of 48
Page 4
AD9273

SPECIFICATIONS

AC SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias =mid­high (default), PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = f ANSI-644 LVDS mode, unless otherwise noted.
Table 1.
AD9273-25 AD9273-40 AD9273-50 Parameter
LNA CHARACTERISTICS
FULL-CHANNEL (TGC)
1
Gain Single-ended
Single-ended
Input Voltage Range LNA gain =
Input Common
Mode Input Resistance RFB = 250 Ω 50 50 50 Ω R R Input Capacitance LI-x 22 22 22 pF
−3 dB Bandwidth 70 70 70 MHz Input-Referred
Noise Voltage
Input Noise Current RFB = 1 1 1 pA/√Hz 1 dB Input Com-
pression Point
Noise Figure LNA gain =
Active Termina-
tion Matched
Unterminated RFB = 6.3/5.3/4.4 6.3/5.3/4.4 6.3/5.3/4.4 dB
CHARACTERISTICS AAF Low-Pass Filter
Cutoff Out of range,3
Conditions Min Typ Max Min Typ Max Min Typ Max Unit
input to differential output
input to single-ended output
15.6 dB/
17.9 dB/
21.3 dB, LNA output limited to
4.4 V p-p differential output
0.9 0.9 0.9 V
= 500 Ω 100 100 100
FB
= 15 15 15 kΩ
FB
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB, R
= 0 Ω,
S
R
= ∞
FB
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB, GAIN+ = 0 V
15.6 dB/
17.9 dB/
21.3 dB RS = 50 Ω,
= 200 Ω/
R
FB
250 Ω/350 Ω
In range, −3 dB, programmable
−3 dB, pro­grammable, >>AAF band­width tolerance
15.6/17.9/21.3 15.6/17.9/21.3 15.6/17.9/21.3 dB
9.6/11.9/15.3 9.6/11.9/15.3 9.6/11.9/15.3 dB
733/550/367 733/550/367 733/550/367 mV p-p
1.6/1.42/1.26 1.6/1.42/1.26 1.6/1.42/1.26 nV/√Hz
1.0/0.8/0.5 1.0/0.8/0.5 1.0/0.8/0.5 mV p-p
5.8/5.1/4.3 5.8/5.1/4.3 5.8/5.1/4.3 dB
8 to 18 8 to 18 8 to 18 MHz
5 to 8, 18 to 35 5 to 8, 18 to 35 5 to 8, 18 to 35 MHz
/3 (default), HPF = LPF cutoff/20.7 (default), full temperature,
SAMPLE
2
SE
Rev. B | Page 4 of 48
Page 5
AD9273
AD9273-25 AD9273-40 AD9273-50 Parameter
PGA GAIN Differential
1
AAF Bandwidth
Conditions Min Typ Max Min Typ Max Min Typ Max Unit
In range ±10 ±10 ±10 %
Tolerance
Group Delay
Variation
f = 1 MHz to 18 MHz,
±2 ±2 ±2 ns
GAIN+ = 0 V to
1.6 V
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
1.94/1.64/1.38 1.94/1.64/1.38 1.94/1.64/1.38 nV/√Hz
17.9 dB/
21.3 dB, R
= ∞
FB
Noise Figure LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
Active Termina-
tion Matched
RS = 50 Ω, R
= 200 Ω/
FB
10.3/8.7/6.8 10.3/8.6/6.7 10.3/8.6/6.7 dB
250 Ω/350 Ω
Unterminated RFB = 7.1/6.0/4.8 7.1/5.9/4.8 7.1/5.9/4.8 dB
Correlated Noise
Ratio
No signal, correlated/
−30 −30 −30 dB
uncorrelated Output Offset −35 +35 −35 +35 −35 +35 LSB Signal-to-Noise
Ratio (SNR)
fIN = 5 MHz at
−10 dBFS,
65.5 64 63.5 dBFS
GAIN+ = 0 V
f
= 5 MHz at
IN
58.5 57 56.5 dBFS
−1 dBFS,
GAIN+ = 1.6 V Harmonic Distortion
Second
Harmonic
fIN = 5 MHz at
−10 dBFS,
−55 −52 −52 dBc
GAIN+ = 0 V
f
= 5 MHz at
IN
−67 −62 −58 dBc
−1 dBFS,
GAIN+ = 1.6 V
Third Harmonic fIN = 5 MHz at
−56 −50 −47 dBc
−10 dBFS,
GAIN+ = 0 V
f
= 5 MHz at
IN
−61 −56 −55 dBc
−1 dBFS,
GAIN+ = 1.6 V Two-Tone IMD3
(2 × F1 − F2) Distortion
f
= 5.0 MHz at
IN1
−1 dBFS,
f
= 5.01 MHz
IN2
−75 −75 −75 dBc
at −21 dBFS,
GAIN+ = 1.6 V,
LNA gain =
21.3 dB
Channel-to-Channel
Crosstalk
Overrange
Channel-to-Channel
Delay Variation
f
= 5.0 MHz at
IN1
−1 dBFS
condition
4
Full TGC path,
= 5 MHz,
f
IN
−70 −70 −70 dB
−65 −65 −65 dB
0.3 0.3 0.3 Degrees
GAIN+ = 0 V to
1.6 V 21/24/27/30 21/24/27/30 21/24/27/30 dB
input to differential output
Rev. B | Page 5 of 48
Page 6
AD9273
AD9273-25 AD9273-40 AD9273-50 Parameter
GAIN ACCURACY 25°C
1.44 V < GAIN+
GAIN CONTROL
CW DOPPLER MODE
POWER SUPPLY
1
Gain Law Confor-
mance Error
0.16 V < GAIN+
Conditions Min Typ Max Min Typ Max Min Typ Max Unit
0 V < GAIN+
1.5 1.5 1.5 dB
< 0.16 V
−1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB
< 1.44 V
−2.5 −2.5 −2.5 dB
< 1.6 V
Linear Gain Error GAIN+ = 0.8 V,
−1.6 +1.6 −1.6 +1.6 −1.7 +1.7 dB normalized for ideal AAF loss
Channel-to-Channel
Matching
0.16 V < GAIN+ < 1.44 V
0.1 0.1 0.1 dB
INTERFACE Normal Operating
0 1.6 0 1.6 0 1.6 V
Range
Gain Range GAIN+ =
42 42 42 dB
0 V to 1.6 V
Scale Factor 28 28 28 dB/V Response Time 42 dB change 750 750 750 ns Gain+ Impedance Single ended 10 10 10 MΩ Gain− Impedance Single ended 70 70 70 kΩ
Transconductance Differential,
5.4/7.3/10.9 5.4/7.3/10.9 5.4/7.3/10.9 mA/V LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
Output Level Range Differential,
1.5 3.6 1.5 3.6 1.5 3.6 V CW Doppler output pins
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
2.6/2.1/1.6 2.6/2.1/1.6 2.6/2.1/1.6 nV/√Hz
17.9 dB/
21.3 dB, R
= 0 Ω,
S
R
= ∞,
FB
= 675 Ω
R
L
Input-Referred
Dynamic Range
LNA gain =
15.6 dB/
160/159/158 160/159/158 160/159/158 dBFS/√Hz
17.9 dB/
21.3 dB, R
= 0 Ω,
S
= ∞
R
FB
Two-Tone IMD3
(2 × F1 − F2) Distortion
f
= 5.0 MHz at
IN1
−1 dBFS (FS at LNA input), f
−70 −70 −70 dBc
=
IN2
5.01 MHz at
−21 dBFS (FS at LNA input), LNA gain = 21.3 dB
Output DC Bias Single ended,
2.4 2.4 2.4 mA per channel
Maximum Output
Swing
Single ended, per channel
±2 ±2 ±2 mA p-p
AVDD1 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V AVDD2 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V I
Full-channel
AVDD1
158 186 223 mA
mode
CW Doppler
32 32 32 mA mode with four channels enabled
Rev. B | Page 6 of 48
Page 7
AD9273
AD9273-25 AD9273-40 AD9273-50 Parameter
ADC RESOLUTION 12 12 12 Bits ADC REFERENCE
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
SE = single ended.
3
AAF settings < 5 MHz are out of range and are not supported.
4
The overrange condition is specified as being 6 dB more than the full-scale input range.
1
I
Full-channel
AVDD2
Conditions Min Typ Max Min Typ Max Min Typ Max Unit
150 150 150 mA
mode
CW Doppler
70 70 70 mA mode with four channels enabled
I
47 49 50 mA
DRVDD
Total Power
Dissipation
Includes output drivers, full­channel mode,
819 940 873 996 943 1072 mW
no signal
CW Doppler
275 275 275 mW mode with four channels enabled
Power-Down
5 5 5 mW
Dissipation
Standby Power
148 158 170 mW
Dissipation
Power Supply
1.6 1.6 1.6 mV/V
Rejection Ratio (PSRR)
Output Voltage Error VREF = 1 V ±20 ±20 ±20 mV Load Regulation At 1.0 mA,
2 2 2 mV VREF = 1 V
Input Resistance 6 6 6 kΩ
Rev. B | Page 7 of 48
Page 8
AD9273

DIGITAL SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 2.
1
Parameter
Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage
2
Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO)
3
Logic 1 Voltage (IOH = 800 A) Full 1.79 V Logic 0 Voltage (IOL = 50 A) Full 0.05 V
DIGITAL OUTPUTS (DOUTx+, DOUTx−) IN ANSI-644 MODE
1
Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary
DIGITAL OUTPUTS (DOUTx+, DOUTx−) WITH
LOW POWER, REDUCED-SIGNAL OPTION
1
Logic Compliance LVDS Differential Output Voltage (VOD) Full 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 V Output Coding (Default) Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Specified for LVDS and LVPECL only.
3
Specified for 13 SDIO pins sharing the same connection.
Rev. B | Page 8 of 48
Page 9
AD9273

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3.
1
Parameter
CLOCK
2
Temp Min Typ Max Unit
Clock Rate Full 10 50 MSPS Clock Pulse Width High (tEH) Full 10 ns Clock Pulse Width Low (tEL) Full 10 ns
2, 3
OUTPUT PARAMETERS
Propagation Delay (tPD) Full (t Rise Time (tR) (20% to 80%) Full Fall Time (tF) (20% to 80%) Full FCO± Propagation Delay (t DCO± Propagation Delay (t DCO± to Data Delay (t DCO± to FCO± Delay (t Data-to-Data Skew
DATA -MAX
− t
DATA -MIN
(t Wake-Up Time (Standby), GAIN+ = 0.8 V 25°C Wake-Up Time (Power-Down) 25°C Pipeline Latency Full
APERTURE
Aperture Uncertainty (Jitter) 25°C
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI.
3
Measurements were made using a part soldered to FR-4 material.
4
t
/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
SAMPLE
) Full (t
FCO
4
)
Full t
CPD
4
)
Full (t
DATA
4
)
Full (t
FRAME
)
Full
/2) + 1.5 (t
SAMPLE
300 300
/2) + 1.5 (t
SAMPLE
/24) − 300 (t
SAMPLE
/24) − 300 (t
SAMPLE
±100 ±350
<2 1 8
<1
/2) + 2.3 (t
SAMPLE
/2) + 2.3 (t
SAMPLE
+ (t
FCO
SAMPLE
/24) (t
SAMPLE
/24) (t
SAMPLE
/2) + 3.1 ns
SAMPLE
ps ps
/2) + 3.1 ns
SAMPLE
/24) ns
/24) + 300 ps
SAMPLE
/24) + 300 ps
SAMPLE
ps
µs ms Clock cycles
ps rms
Rev. B | Page 9 of 48
Page 10
AD9273

ADC TIMING DIAGRAMS

N – 1
AIN
N
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
DOUTx–
DOUTx+
AIN
N – 1
t
FCO
t
t
EH
t
CPD
t
FRAME
PD
MSB
D10
N – 8
N – 8D9N – 8D8N – 8D7N – 8D6N – 8D5N – 8D4N – 8D3N – 8D2N – 8D1N – 8D0N – 8
t
EL
t
DATA
D10
MSB
N – 7
N – 7
07030-002
Figure 2. 12-Bit Data Serial Stream (Default)
N
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
DOUTx–
DOUTx+
t
EH
t
CPD
t
FCO
t
PD
t
FRAME
D0
(LSB)D1N – 8D2N – 8D3N – 8D4N – 8D5N – 8D6N – 8D7N – 8D8N – 8D9N – 8
t
EL
t
DATA
D10
D11
N – 8
(MSB)
07030-004
Figure 3. 12-Bit Data Serial Stream, LSB First
Rev. B | Page 10 of 48
Page 11
AD9273

ABSOLUTE MAXIMUM RATINGS

Table 4.
With
Parameter
Electrical
AVDD1 GND −0.3 V to +2.0 V AVDD2 GND −0.3 V to +3.9 V DRVDD GND −0.3 V to +2.0 V GND GND −0.3 V to +0.3 V AVDD2 AVDD1 −2.0 V to +3.9 V AVDD2 DRVDD −2.0 V to +3.9 V AVDD1 DRVDD −2.0 V to +2.0 V Digital Outputs
(DOUTx+, DOUTx−,
DCO+, DCO−,
FCO+, FCO−) CLK+, CLK−, GAIN+,
GAIN− LI-x, LO-x, LOSW-x LG-x −0.3 V to +2.0 V CWDx−, CWDx+ GND −0.3 V to +3.9 V PDWN, STBY, SCLK, CSB GND −0.3 V to +3.9 V RBIAS, VREF, SDIO GND −0.3 V to +2.0 V
Environmental
Operating Temperature
Range (Ambient) Storage Temperature
Range (Ambient) Maximum Junction
Temperature Lead Temperature
(Soldering, 10 sec)
Respect To Rating
GND −0.3 V to +2.0 V
GND −0.3 V to +3.9 V
−40°C to +85°C
−65°C to +150°C
150°C
300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL IMPEDANCE

Table 5.
Airflow Velocity (m/sec) θ
0.0 20.3 N/A N/A °C/W
1.0 14.4 7.6 4.7 °C/W
2.5 12.9 N/A N/A °C/W
1
θJA is for a 4-layer PCB with a solid ground plane (simulated). The exposed
pad is soldered to the PCB.
1
θ
JA
θJC Unit
JB

ESD CAUTION

Rev. B | Page 11 of 48
Page 12
AD9273

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LOSW-DLO-D
CWD0–
CWD0+
CWD1–
CWD1+
CWD2–
CWD2+
CWD3–
CWD3+
AVDD2
GAIN–
GAIN+
VREF
RBIAS
CWD4–
AD9273
TOP VIEW
(Not to Scale)
76
LI-D
75
LG-D
74
AVDD2
73
AVDD1
72
LO-C
71
LOSW-C
70
LI-C
69
LG-C
68
AVDD2
67
AVDD1
66
LO-B
65
64
LOSW-B
63
LI-B LG-B
62
AVDD2
61
AVDD1
60 59
LO-A
58
LOSW-A
57
LI-A LG-A
56
AVDD2
55 54
AVDD1
53
CSB
52
SDIO
51
SCLK
LI-E
LG-E AVDD2 AVDD1
LO-F
LOSW-F
LI-F
LG-F AVDD2 AVDD1
LO-G
LOSW-G
LI-G
LG-G AVDD2 AVDD1
LO-H
LOSW-H
LI-H
LG-H AVDD2 AVDD1
CLK– CLK+
AVDD1
CWD5–
CWD5+
CWD6–
CWD6+
CWD7–
CWD7+
LO-E
LOSW-E
9998979695949392919089888786858483828180797877
100
PIN 1
1
INDICATOR
2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)
CWD4+
2627282930313233343536373839404142434445464748
FCO–
DRVDD
DOUTH–
DOUTH+
DOUTG–
NOTES
1. THE EXPOSED PAD SHOULD BE T IED TO A QUIET ANALOG GROUND.
DOUTF+
DOUTG+
DOUTF–
DCO–
DOUTE–
DOUTE+
FCO+
DCO+
DOUTD–
DOUTD+
DOUTC–
DOUTC+
DOUTA+
DOUTB+
DRVDD
DOUTA–
DOUTB–
50
49
STBY
PDWN
AVDD1
07030-005
Figure 4. TQFP Pin Configuration
4
2
1357
A B C
D
E
F G
H
J
K
L M
(Not to S cale)
Figure 5. BGA Pin Configuration
6
TOP VIEW
10 12
8
9
11
07030-300
Rev. B | Page 12 of 48
Page 13
AD9273
Table 6. Pin Function Descriptions
Pin No.
TQFP BGA Name Description
0 N/A GND Ground (the exposed paddle should be tied to a quiet analog ground) N/A
4, 10, 16, 22, 25, 50, 54, 60, 66, 72
3, 9, 15, 21, 55, 61, 67, 73, 86
26, 47 L1, L12 DRVDD 1.8 V Digital Output Driver Supply 1 A1 LI-E LNA Analog Input for Channel E 2 B1 LG-E LNA Ground for Channel E 5 C2 LO-F LNA Analog Inverted Output for Channel F 6 D2 LOSW-F LNA Analog Switched Output for Channel F 7 A2 LI-F LNA Analog Input for Channel F 8 B2 LG-F LNA Ground for Channel F 11 C3 LO-G LNA Analog Inverted Output for Channel G 12 D3 LOSW-G LNA Analog Switched Output for Channel G 13 A3 LI-G LNA Analog Input for Channel G 14 B3 LG-G LNA Ground for Channel G 17 C4 LO-H LNA Analog Inverted Output for Channel H 18 D4 LOSW-H LNA Analog Switched Output for Channel H 19 A4 LI-H LNA Analog Input for Channel H 20 B4 LG-H LNA Ground for Channel H 23 H1 CLK− Clock Input Complement 24 J1 CLK+ Clock Input True 27 M2 DOUTH− ADC H Digital Output Complement 28 L2 DOUTH+ ADC H Digital Output True 29 M3 DOUTG− ADC G Digital Output Complement 30 L3 DOUTG+ ADC G Digital Output True 31 M4 DOUTF− ADC F Digital Output Complement 32 L4 DOUTF+ ADC F Digital Output True 33 M5 DOUTE− ADC E Digital Output Complement 34 L5 DOUTE+ ADC E Digital Output True 35 M6 DCO− Digital Clock Output Complement 36 L6 DCO+ Digital Clock Output True 37 M7 FCO− Frame Clock Digital Output Complement 38 L7 FCO+ Frame Clock Digital Output True 39 M8 DOUTD− ADC D Digital Output Complement 40 L8 DOUTD+ ADC D Digital Output True 41 M9 DOUTC− ADC C Digital Output Complement 42 L9 DOUTC+ ADC C Digital Output True 43 M10 DOUTB− ADC B Digital Output Complement 44 L10 DOUTB+ ADC B Digital Output True
B5, B6, B8, C5, C6, C7, C8, D5, D6, D7, D8, E1, E5, E6, E7, E8, E12, F2, F4, F6, F7, F9, F11, G1, G3, G5, G6, G7, G8, G10, G12, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, J2, K1, K2, M1, M12
F1, F3, F5, F8, F10, F12, G2, G4, G9, G11
B7, E2, E3, E4, E9, E10, E11
GND Ground
AVDD1 1.8 V Analog Supply
AVDD2 3.0 V Analog Supply
Rev. B | Page 13 of 48
Page 14
AD9273
Pin No.
TQFP BGA Name Description
45 M11 DOUTA− ADC A Digital Output Complement 46 L11 DOUTA+ ADC A Digital Output True 48 K11 STBY Standby Power-Down 49 J11 PDWN Full Power-Down 51 K12 SCLK Serial Clock 52 J12 SDIO Serial Data Input/Output 53 H12 CSB Chip Select Bar 56 B9 LG-A LNA Ground for Channel A 57 A9 LI-A LNA Analog Input for Channel A 58 D9 LOSW-A LNA Analog Switched Output for Channel A 59 C9 LO-A LNA Analog Inverted Output for Channel A 62 B10 LG-B LNA Ground for Channel B 63 A10 LI-B LNA Analog Input for Channel B 64 D10 LOSW-B LNA Analog Switched Output for Channel B 65 C10 LO-B LNA Analog Inverted Output for Channel B 68 B11 LG-C LNA Ground for Channel C 69 A11 LI-C LNA Analog Input for Channel C 70 D11 LOSW-C LNA Analog Switched Output for Channel C 71 C11 LO-C LNA Analog Inverted Output for Channel C 74 B12 LG-D LNA Ground for Channel D 75 A12 LI-D LNA Analog Input for Channel D 76 D12 LOSW-D LNA Analog Switched Output for Channel D 77 C12 LO-D LNA Analog Inverted Output for Channel D 78 K10 CWD0− CW Doppler Output Complement for Channel 0 79 J10 CWD0+ CW Doppler Output True for Channel 0 80 K9 CWD1− CW Doppler Output Complement for Channel 1 81 J9 CWD1+ CW Doppler Output True for Channel 1 82 K8 CWD2− CW Doppler Output Complement for Channel 2 83 J8 CWD2+ CW Doppler Output True for Channel 2 84 K7 CWD3− CW Doppler Output Complement for Channel 3 85 J7 CWD3+ CW Doppler Output True for Channel 3 87 A8 GAIN− Gain Control Voltage Input Complement 88 A7 GAIN+ Gain Control Voltage Input True 89 A6 RBIAS External Resistor to Set the Internal ADC Core Bias Current 90 A5 VREF Voltage Reference Input/Output 91 K6 CWD4− CW Doppler Output Complement for Channel 4 92 J6 CWD4+ CW Doppler Output True for Channel 4 93 K5 CWD5− CW Doppler Output Complement for Channel 5 94 J5 CWD5+ CW Doppler Output True for Channel 5 95 K4 CWD6− CW Doppler Output Complement for Channel 6 96 J4 CWD6+ CW Doppler Output True for Channel 6 97 K3 CWD7− CW Doppler Output Complement for Channel 7 98 J3 CWD7+ CW Doppler Output True for Channel 7 99 C1 LO-E LNA Analog Inverted Output for Channel E 100 D1 LOSW-E LNA Analog Switched Output for Channel E
Rev. B | Page 14 of 48
Page 15
AD9273

TYPICAL PERFORMANCE CHARACTERISTICS

f
= 40 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = mid-high, PGA gain = 24 dB, AAF LPF cutoff = f
SAMPLE
HPF = LPF cutoff/20.7 (default), GAIN− = 0.8 V
2.0
14
SAMPLE
/3,
1.5
1.0
0.5
0
–0.5
GAIN ERROR (dB)
–1.0
–1.5
–2.0
0 0.2 0.4 0.6 0.8 1.0
–40°C
+25°C
+85°C
GAIN+ (V)
Figure 6. Gain Error vs. GAIN+ at Three Temperatures
20
18
16
14
12
10
8
6
PERCENTAGE OF UNITS (%)
4
2
0
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
0
–0.3
GAIN ERROR (dB)
0.1
–0.2
–0.1
0.2
0.3
Figure 7. Gain Error Histogram, GAIN+ = 0.16 V
1.2 1.4 1.6
0.4
0.5
0.6
0.7
0.8
12
10
8
6
4
PERCENTAGE OF UNITS (%)
2
0
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
07030-114
–0.4
0
–0.3
GAIN ERROR (dB)
0.1
–0.2
–0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
07030-186
Figure 9. Gain Error Histogram, GAIN+ = 1.44 V
25
20
15
10
PERCENTAGE OF UNITS (%)
5
0.9
1.0
07030-184
0
–1.25 –1.00 –0.75
–0.50 –0.25 0
CHANNEL-TO-CHANNEL GAIN MATCHI NG (dB)
0.25 0.50 0.75 1.00 1.25
07030-180
Figure 10. Gain Match Histogram, GAIN+ = 0.3 V
14
12
10
8
6
4
PERCENTAGE OF UNITS (%)
2
0
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
0
–0.3
–0.2
–0.1
GAIN ERROR (dB)
Figure 8. Gain Error Histogram, GAIN+ = 0.8 V
25
20
15
10
PERCENTAGE OF UNITS (%)
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
07030-185
–1.25 –1.00 –0.75
Figure 11. Gain Match Histogram, GAIN+ = 1.3 V
–0.50 –0.25 0
CHANNEL-TO-CHANNEL GAIN MATCHI NG (dB)
0.25 0.50 0.75 1.00 1.25
07030-181
Rev. B | Page 15 of 48
Page 16
AD9273
A
500k
450k
400k
350k
300k
250k
200k
NUMBER OF HITS
150k
100k
50k
0
–7 –6 –5 –4
–3–2–101234567
CODES
Figure 12. Output-Referred Noise Histogram, GAIN+ = 0.0 V
07030-115
128 –129 –130 –131 –132 –133 –134 –135 –136 –137
OUTPUT-RE FERRED NOISE ( dBFS/Hz)
–138 –139
00.20.40.60.8 GAIN+ (V)
LNA GAIN = 12×
LNA GAIN = 8×
LNA GAIN = 6×
1.0 1.2 1.4 1.6
Figure 15. Short-Circuit, Output-Referred Noise vs. GAIN+
07030-117
200k
180k
160k
140k
120k
100k
80k
NUMBER OF HITS
60k
40k
20k
0
–7 –6 –5 –4
–3–2–101234567
CODES
07030-116
Figure 13. Output-Referred Noise Histogram, GAIN+ = 1.6 V
3.0
2.5
Hz)
2.0
1.5
1.0
0.5
INPUT-REFERRED NOISE (nV/
0
12345678910
LNA GAIN = 15.6dB
LNA GAIN = 21.3dB
FREQUENCY (MHz)
LNA GAIN = 17.9dB
07030-187
Figure 14. Short-Circuit, Input-Referred Noise vs. Frequency,
PGA Gain = 30 dB, GAIN+ = 1.6 V
65
60
55
D(dBFS)
50
SNR/SIN
45
40
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
SNR
SINAD
GAIN+ (V)
Figure 16. SNR/SINAD vs. GAIN+, AIN = −1.0 dBFS
0
–2
–4
–6
–8
–10
–12
AMPLITUDE ( d BF S)
–14
–16
–18
–20
0 5 10 15 20 25
25MSPS
FREQUENCY (MHz)
50MSPS
40MSPS
Figure 17. Antialiasing Filter (AAF) Pass-Band Response,
LPF Cutoff = 1 × (1/3) × f
SAMPLE
07030-118
07030-120
Rev. B | Page 16 of 48
Page 17
AD9273
A
150
0
125
100
75
50
GROUP DELAY (ns)
25
0
0 5 10 15 20 25 30 35 40
GAIN+ = 1.6V GAIN+ = 0.8V GAIN+ = 0V
FREQUENCY (MHz )
Figure 18. Antialiasing Filter (AAF) Group Delay Response
0
–10
–20
–30
–40
–50
RMONIC DISTORTION (dBFS)
–60
–70
–80
–90
SECOND-ORDER H
–100
0 2 4 6 8 10 12 14 16
GAIN+ = 1.0V
INPUT FREQUENCY (MHz)
GAIN+ = 0.5V
GAIN+ = 1.6V
Figure 19. Second-Order Harmonic Distortion vs. Input Frequency,
AIN = −1.0 dBFS
–20
–40
–60
GAIN+ = 1.6V
–80
–100
SECOND-ORDER HARMO NI C DIS T O RT I O N ( d BF S)
–120
–40 –35 –30 –25 –20 –15 –10 –5 0
07030-121
ADC OUTPUT LEVEL (dBFS)
GAIN+ = 0V
GAIN+ = 0.8V
07030-124
Figure 21. Second-Order Harmonic Distortion vs. ADC Output Level
0
–20
–40
–60
–80
–100
THIRD-ORDER HARMONIC DISTORTION (dBFS)
–120
–40 –35 –30 –25 –20 –15 –10 –5 0
07030-122
ADC OUTP U T LEVEL (d BFS)
GAIN+ = 0V
GAIN+ = 0.8V
GAIN+ = 1.6V
07030-125
Figure 22. Third-Order Harmonic Distortion vs. ADC Output Level
0
–10
–20
–30
–40
–50
–60
–70
THIRD-ORDER HARMONIC DISTO RTION (dBFS)
–80
0246810121416
GAIN+ = 1.6V
GAIN+ = 1.0V
INPUT FREQ UE NCY ( M Hz )
GAIN+ = 0.5V
Figure 20. Third-Order Harmonic Distortion vs. Input Frequency,
07030-123
0
f
=
f
+0.01MHz
IN1
–10
–20
–30
–40
–50
IMD3 (dBFS)
–60
–70
–80
–90
0.5 0.6 0.7 0.9 1.1 1.3 1.50.8 1.0 1.2 1.4 1.6
IN2
1 = –1dBFS, AIN2 = –21dBFS
A
IN
5MHz
2.3MHz
GAIN+ (V)
Figure 23. IMD3 vs. GAIN+
8MHz
07030-126
AIN = −1.0 dBFS
Rev. B | Page 17 of 48
Page 18
AD9273
0
f
= 5.00MHz, f
IN1
FUND2 LEVEL = FUND1 LEVEL – 20dB
–20
–40
–60
IMD3 (dBFS )
–80
–100
–120
–40 –35 –30 –25 –20 –15 –10 –5 0
= 5.01MHz
IN2
GAIN+ = 0V
FUND1 LEVEL (dBFS)
Figure 24. IMD3 vs. Fundamental 1 Amplitude (FUND1) Level
GAIN+ = 0.8V
GAIN+ = 1.6V
7030-127
Rev. B | Page 18 of 48
Page 19
AD9273
V
S
A

EQUIVALENT CIRCUITS

LI-x,
LG-x
AVDDx
CM
15k
Figure 25. Equivalent LNA Input Circuit
AVDDx
LO-x,
LOSW-x
10
Figure 26. Equivalent LNA Output Circuit
VDDx
DIO
07030-073
350
30k
07030-008
Figure 28. Equivalent SDIO Input Circuit
DRVDD
V
DOUTx– DOUTx+
V
07030-075
DRGND
V
V
07030-009
Figure 29. Equivalent Digital Output Circuit
CLK+
CLK–
10
10k
10k
10
Figure 27. Equivalent Clock Input Circuit
1.25V
SCLK, PDWN,
OR STBY
07030-007
1k
30k
07030-010
Figure 30. Equivalent SCLK, PDWN, or STBY Input Circuit
Rev. B | Page 19 of 48
Page 20
AD9273
A
V
C
A
V
G
A
V
DDx
RBIAS
100
Figure 31. Equivalent RBIAS Circuit
DDx
70k
SB
1k
Figure 32. Equivalent CSB Input Circuit
VDD2
AIN+
07030-011
50
7030-276
Figure 34. Equivalent GAIN+ Input Circuit
0.8
AVDD2
GAIN–
07030-012
70k
50
7030-176
Figure 35. Equivalent GAIN− Input Circuit
VREF
6k
07030-014
Figure 33. Equivalent VREF Circuit
CWDx+,
CWDx–
Figure 36. Equivalent CWDx± Output Circuit
10
+0.5V
07030-076
Rev. B | Page 20 of 48
Page 21
AD9273

THEORY OF OPERATION

ULTRASOUND

The primary application for the AD9273 is medical ultrasound. Figure 37 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution.
Key requirements in an ultrasound signal chain are very low noise, active input termination, fast overload recovery, low power, and differential drive to an ADC. Because ultrasound machines use beam-forming techniques requiring a large binary-weighted number of channels (for example, 32 to 512 channels), using the lowest power at the lowest possible noise is of chief importance.
Most modern machines use digital beam forming. In this technique, the signal is converted to digital format immediately
Tx HVAMPs
following the TGC amplifier, and then beam forming is accomplished digitally.
The ADC resolution of 12 bits with up to 50 MSPS sampling satisfies the requirements of both general-purpose and high­end systems.
Power conservation and low cost are two of the most important factors in low-end and portable ultrasound machines, and the AD9273 is designed to meet these criteria.
For additional information regarding ultrasound systems, refer to “How Ultrasound System Considerations Influence Front-End Component Choice,” Analog Dialogue, Volume 36, Number 3, May–July 2002, and “The AD9271—A Revolutionary Solution for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 3, July 2007.
Tx BEAM FORMER
BEAM-FORMER
CENTRAL CONT RO L
MULTICHANNELS
AD9273
TRANSDUCER
ARRAY
128, 256, ET C.,
ELEMENTS
HV
MUX/
DEMUX
BIDIRECTIONAL
CABLE
T/R
SWITCHES
VGALNA
CW
CW (ANALOG)
BEAM FORMER
AUDIO
OUTPUT
AAF
ADC
SPECTRAL
DOPPLER
PROCESSING
MODE
Rx BEAM FORMER
(B AND F MODES)
IMAGEAND
MOTION
PROCESSING
(B MODE)
DISPLAY
COLOR
DOPPL ER (PW)
PROCESSING
(F MODE)
07030-077
Figure 37. Simplified Ultrasound System Block Diagram
Rev. B | Page 21 of 48
Page 22
AD9273
R
LO-x
FB1
C
FB
T/R
SWITCH
C
S
C
SH
TRANSDUCER
LOSW-x
R
FB2
LI-x
LNA
LG-x
C
LG
15.6dB,
17.9dB,
21.3dB
ATTENUATOR –42dB TO 0dB
INTERPOLATOR
Figure 38. Simplified Block Diagram of a Single Channel

CHANNEL OVERVIEW

Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides user­adjustable input impedance termination. The CW Doppler path includes a transconductance amplifier and a crosspoint switch. The TGC path includes a differential X-AMP® VGA, an antialiasing filter, and an ADC. Figure 38 shows a simplified block diagram with external components.
The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNA is designed to be driven from a single-ended signal source.

Low Noise Amplifier (LNA)

Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input impedance matching.
A simplified schematic of the LNA is shown in Figure 39. LI-x is capacitively coupled to the source. An on-chip bias generator establishes dc input bias voltages of around 0.9 V and centers the output common-mode levels at 1.5 V (AVDD2 divided by
2). A capacitor, C capacitor, C
T/R
SWITCH
, of the same value as the input coupling
LG
, is connected from the LG-x pin to ground.
S
C
FB
R
VO+
V
CM
C
S
LI-x
C
SH
FB1
R
FB2
V
O
LOSW-x
V
CM
LO-x
LG-x
C
LG
g
m
GAIN
SWITCH
ARRAY
AD9273
SERIAL
LVDS
POSTAMP
21dB 24dB, 27dB, 30dB
GAIN–
GAIN+
FILTER
PIPELINE
ADC
The LNA supports differential output voltages as high as
4.4 V p-p with positive and negative excursions of ±1.1 V from a common-mode voltage of 1.5 V. The LNA differential gain sets the maximum input signal before saturation. One of three gains is set through the SPI. The corresponding full-scale input for the gain settings of 6, 8, and 12 is 733 mV p-p, 550 mV p-p, and 367 mV p-p, respectively. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection.
Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input-referred noise voltage of 1.26 nV/√Hz at a gain of 21.3 dB. This is achieved with a current consumption of only 10 mA per channel (30 mW). On-chip resistor matching results in precise single-ended gains, which are critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low second-order harmonic distortion is particularly important in second-order harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order distortion.
Recommendation
It is highly recommended that the LG-x pins form a Kelvin type connection to the input or probe connection ground. Simply connecting the LG pin to ground near the device may allow differences in potential to be amplified through the LNA. This generally shows up as a dc offset voltage that can vary from channel to channel and part to part, depending on the application and layout of the PCB (see Figure 38).
CWD[7:0]+ CWD[7:0]–
DOUTx+ DOUTx–
07030-071
TRANSDUCER
07030-101
Figure 39. Simplified LNA Schematic
Rev. B | Page 22 of 48
Page 23
AD9273

Active Impedance Matching

The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output available externally. For example, with a fixed gain of 8× (17.9 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This well-known technique is used for interfacing multiple probe impedances to a single system. The input resistance is shown in Equation 1.
R
R
IN
FB
= (1)
A
)
1(
+
2
where A/2 is the single-ended gain or the gain from the LI-x inputs to the LO-x outputs, and R of the R
FB1
and R
combination (see Figure 39).
FB2
is the resulting impedance
FB
Because the amplifier has a gain of 8× from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the gain of the amplifier, or 12.1 dB (4×). The input resistance is reduced by an internal bias resistor of 15 kΩ in parallel with the source resistance connected to Pin LI-x while Pin LG-x is ac grounded. Equation 2 can be used to calculate the needed R for a desired R
R
IN
For example, to set R
, even for higher values of RIN.
IN
R
FB
= k15||
+
)31(
(2)
Ω
to 200 Ω, the value of RFB must be
IN
FB
1000 Ω. If the simplified equation (Equation 2) is used to calculate R
, the value is 188 Ω, resulting in a gain error less
IN
than 0.6 dB. Some factors, such as the presence of a dynamic source resistance, might influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the LNA needs to be considered. The user must determine the level of matching accuracy and adjust R
accordingly.
FB
The bandwidth (BW) of the LNA is greater than 100 MHz. Ultimately, the BW of the LNA limits the accuracy of the synthesized R
. For RIN = RS up to about 200 Ω, the best match
IN
is between 100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac-coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and R Figure 40 shows R
vs. frequency for various values of RFB.
IN
limit the BW at higher frequencies.
S
1k
RS = 500, RFB = 2k
RS = 200, RFB = 800
RS = 100, RFB = 400Ω, CSH = 20pF
100
RS = 50, RFB = 200Ω, CSH = 70pF
INPUT RESI STANCE (Ω)
10
100k 1M 10M 100M
Figure 40. R
(Effects of R
FREQUENCY (Hz)
vs. Frequency for Various Values of RFB
IN
and CSH Are Also Shown)
S
07030-188
Note that at the lowest value (50 Ω), RIN peaks at frequencies greater than 10 MHz. This is due to the BW roll-off of the LNA, as mentioned previously.
However, as can be seen for larger R
values, parasitic capacitance
IN
starts rolling off the signal BW before the LNA can produce peaking. C not be used for values of R lists the recommended values for R
C
is needed in series with RFB because the dc levels at Pin LO-x
FB
further degrades the match; therefore, CSH should
SH
that are greater than 100 Ω. Tabl e 7
IN
and CSH in terms of RIN.
FB
and Pin LI-x are unequal.
Table 7. Active Termination External Component Values
LNA Gain (dB) R
(Ω) RFB (Ω)
IN
Minimum CSH (pF) BW (MHz)
15.6 50 200 90 57
17.9 50 250 70 69
21.3 50 350 50 88
15.6 100 400 30 57
17.9 100 500 20 69
21.3 100 700 10 88
15.6 200 800 N/A 72
17.9 200 1000 N/A 72
21.3 200 1400 N/A 72
Rev. B | Page 23 of 48
Page 24
AD9273

LNA Noise

The short-circuit noise voltage (input-referred noise) is an impor­tant limit on system performance. The short-circuit input-referred noise voltage for the LNA is 1.4 nV/√Hz at a gain of 21.3 dB, including the VGA noise at a VGA postamp gain of 27 dB. These measurements, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in Figure 41.
UNTERMINATED
R
IN
R
S
LI-x
+ –
V
OUT
Figure 42 shows the relative noise figure performance. In this graph, the input impedance was swept with R
to preserve the
S
match at each point. The noise figures for a source impedance of 50  are 7.3 dB, 4.2 dB, and 2.8 dB for the resistive termination, active termination, and unterminated configurations, respectively. The noise figures for 200  are 4.5 dB, 1.7 dB, and 1.0 dB, respectively.
Figure 43 shows the noise figure as it relates to R of R
, which is helpful for design purposes.
IN
for various values
S
12.0
10.5
RESISTI VE TERMINATI ON
R
IN
R
S
+
LI-x
ACTIVE IMP EDANCE MAT CH
R
S
+
LI-x
RIN=
R
IN
R
1 + A/2
R
S
R
FB
V
OUT
FB
V
OUT
7030-104
Figure 41. Input Configurations
Figure 42 and Figure 43 are simulations of noise figure vs. source resistance (R
) results using these configurations and an input-
S
referred noise voltage of 6 nV/√Hz for the VGA. Unterminated
= ∞) operation exhibits the lowest equivalent input noise
(R
FB
and noise figure. Figure 43 shows the noise figure vs. R
—where the LNA voltage noise is large compared with the
low R
S
source noise—and at high R
. The lowest NF is achieved when RS matches RIN.
R
FB
due to the noise contribution from
S
rising at
S
The main purpose of input impedance matching is to improve the transient response of the system. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA’s input voltage noise generator. With active impedance matching, however, the contributions of both are smaller (by a factor of 1/(1 + LNA Gain)) than they would be for resistive termination.
9.0
7.5
6.0
4.5
NOISE FIGURE (dB)
UNTERMINATED
3.0
1.5
0
10 100 1k
Figure 42. Noise Figure vs. R
SHUNT TERMINATION
ACTIVE TERMINATION
()
R
S
for Shunt Termination,
S
Active Termination Matched, and Unterminated Inputs, V
12.0
10.5
9.0
7.5
6.0
4.5
NOISE FIGURE (dB)
3.0
1.5
0
10 100 1k
Figure 43. Noise Figure vs. R
UNTERMINATED R
= 200
IN
R
= 100
IN
R
= 75
IN
R
= 50
IN
()
R
S
for Various Fixed Values of RIN,
S
Active Termination Matched Inputs, V
GAIN
= 0.8 V
GAIN
= 0.8 V
07030-182
07030-183
Rev. B | Page 24 of 48
Page 25
AD9273
V

INPUT OVERDRIVE CW DOPPLER OPERATION

Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event.

Input Overload Protection

As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages.
In Figure 44, a simplified ultrasound transducer interface is shown. A common transducer element serves the dual functions of transmitting and receiving ultrasound energy. During the transmitting phase, high voltage pulses are applied to the ceramic elements. A typical transmit/receive (T/R) switch can consist of four high voltage diodes in a bridge configuration. Although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and the resulting leakage transients imposed on the LI-x inputs can be problematic.
Because ultrasound is a pulse system and time-of-flight is used to determine depth, quick recovery from input overloads is essential. Overload can occur in the preamp and the VGA. Immediately following a transmit pulse, the typical VGA gains are low, and the LNA is subject to overload from T/R switch leakage. With increasing gain, the VGA can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone.
Figure 44 illustrates an external overload protection scheme. A pair of back-to-back signal diodes is installed prior to installing the ac-coupling capacitors. Keep in mind that all diodes shown in this example are prone to exhibiting some amount of shot noise. Many types of diodes are available for achieving the desired noise performance. The configuration shown in Figure 44 tends to add 2 nV/√Hz of input-referred noise. Decreasing the 5 kΩ resistor and increasing the 2 kΩ resistor may improve noise contribution, depending on the application. With the diodes shown in Figure 44, clamping levels of ±0.5 V or less significantly enhance the overload performance of the system.
+5
Tx
DRIVER
TRANSDUCER
5k
HV
2k
5k
–5V
Figure 44. Input Overload Protection
10nF
10nF
AD9273
LNA
07030-100
Modern ultrasound machines used for medical applications
N
employ a 2
binary array of receivers for beam forming, with typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When used in multiples, the desired signals from each channel can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), and the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beam-former design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole.
Beam forming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals that are generated from a common source but received at different times by a multielement ultrasound transducer. Beam forming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived.
The AD9273 includes the front-end components needed to implement analog beam forming for CW Doppler operation. These components allow CW channels with similar phases to be coherently combined before phase alignment and down mixing, thus reducing the number of delay lines or adjustable phase shifters/ down mixers (
AD8333 or AD8339) required. Next, if delay lines
are used, the phase alignment is performed, and then the channels are coherently summed and down converted by a dynamic range I/Q demodulator. Alternatively, if phase shifters/down mixers, such as the AD8333 and AD8339, are used, phase alignment and downconversion are done before coherently summing all channels into I/Q signals. In either case, the resultant I and Q signals are filtered and sampled by two high resolution ADCs, and the sampled signals are processed to extract the relevant Doppler information.
Alternately, the LNA of the AD9273 can directly drive the AD8333 or AD8339 without the crosspoint switch. The LO-x pins present the inverting LNA output, and the LOSW-x pins can be configured via Register 0x2C (see Tabl e 17) to connect to the noninverting output to provide a differential output of the LNA. The LNA output full-scale voltage of the AD9273 is 4.4 V p-p, and the input full­scale voltage is 2.7 V p-p. If no attenuation is provided between the LNA output and the demodulator, the LNA input full-scale voltage must be limited.
Rev. B | Page 25 of 48
Page 26
AD9273
V
AD9273
LNA
g
m
LNA
8 × CHANNEL
LNA
LNA
LNA
LNA
8 × CHANNEL
LNA
LNA
g
m
g
m
g
m
AD9273
g
m
g
m
g
m
g
m
SWITCH
ARRAY
SWITCH
ARRAY
2.5V
2.5V
2.5V
2.5V
600µH 600µH
600µH 600µH
600µH 600µH
600µH 600µH
700
700
700
700
AD8333
AD8333
I
Q
16-BIT
ADC
16-BIT
ADC
07030-096
Figure 45. Typical Connection Interface with the AD8333 or AD8339 using the CWDx± Outputs
AD9273
LNA
LO-A
LOSW-A
500
500
1nF
1nF
2.5
5k 5k
2.5V
AD8339
5k 5k
1nF
500LOS-B
LNA
LOSW-B
LNA
LOSW-H
500
500LO-H
500
1nF
1nF
1nF
2.5V
5k 5k
AD8339
I
Q
16-BIT
ADC
16-BIT
ADC
07030-111
Figure 46. Typical Connection Interface with the AD8333 or AD8339 using the LO-x and LOSW-x Outputs
Rev. B | Page 26 of 48
Page 27
AD9273
V
+
=

Crosspoint Switch

Each LNA is followed by a transconductance amp for voltage­to-current conversion. Currents can be routed to one of eight pairs of differential outputs or to 16 single-ended outputs for summing. Each CWD output pin sinks 2.4 mA dc current, and the signal has a full-scale current of ±2 mA for each channel selected by the crosspoint switch. For example, if four channels are summed on one CWD output, the output sinks 9.6 mA dc and has a full-scale current output of ±8 mA.
The maximum number of channels combined must be considered when setting the load impedance for current-to-voltage conversion to ensure that the full-scale swing and common-mode voltage are within the operating limits of the AD9273. When interfacing to the AD8339, a common-mode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are desired. This can be accomplished by connecting an inductor between each CWD output and a 2.5 V supply, and then connecting either a single-ended or differential load resistance to the CWDx± outputs. The value of resistance should be calculated based on the maximum number of channels that can be combined.
CWDx± outputs are required under full-scale swing to be greater than 1.5 V and less than AVDD2 (3.0 V supply).

TGC OPERATION

The TGC signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA input to the differential ADC input. A simple exercise in understanding the maximum and minimum gain requirements is shown in Figure 47.
MINIMUM GAIN
LNA FS
(0.55V p-p SE)
91dB
LNA
LNA INPUT-REFERRED
(5.4µV rms) @ AAF BW = 1 5MHz
LNA + VGA NOISE = 1.4nV/ Hz
Figure 47. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC
NOISE FLOOR
ADC FS (2
~10dB MARGIN
70dB
>11dB MARGIN
ADC NOISE FL OOR (224µV rms)
MAXIMUM GAIN
VGA GAIN RANGE > 42dB MAX CHANNEL GAIN > 48dB
p-p)
ADC
7030-097
The maximum gain required is determined by
(ADC Noise Floor/VGA Input Noise Floor) + Margin = 20 log(224/5.4) + 11 dB = 43 dB
The minimum gain required is determined by
(ADC Input FS/VGA Input FS) + Margin = 20 log(2/0.55) – 10 dB = 3 dB
Therefore, 42 dB of gain range for a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth should suffice in achieving the dynamic range required for most of today’s ultrasound systems.
The system gain is distributed as listed in Table 8.
Table 8. Channel Gain Distribution
Section Nominal Gain (dB)
LNA 15.6/17.9/21.3 Attenuator −42 to 0 VGA Amp 21/24/27/30 Filter 0 ADC 0
The linear-in-dB gain (law conformance) range of the TGC path is 42 dB. The slope of the gain control interface is 28 dB/V, and the gain control range is −0.8 V to +0.8 V. Equation 3 is the expression for the differential voltage V
, and Equation 4 is
GAIN
the expression for the channel gain.
GAIN
GAINGAINVV
dB
28)dB(
GAIN
V
)()()(
(3)
(4)
ICPTVGain
+=
where ICPT is the intercept point of the TGC gain. In its default condition, the LNA has a gain of 21.3 dB (12×) and
the VGA postamp gain is 24 dB if the voltage on the GAIN+ pin is 0 V and the voltage on the GAIN− pin is 0.8 V (42 dB attenuation). This gives rise to a total gain (or ICPT) of 3.6 dB through the TGC path if the LNA input is unmatched, or of −2.4 dB if the LNA is matched to 50 Ω (R
= 350 Ω). If the voltage on the
FB
GAIN+ pin is 1.6 V and the voltage on the GAIN− pin is 0.8 V (0 dB attenuation), however, the VGA gain is 24 dB. This results in a total gain of 45 dB through the TGC path if the LNA input is unmatched, or in a total gain of 39 dB if the LNA input is matched.
Each LNA output is dc-coupled to a VGA input. The VGA consists of an attenuator with a range of −42 dB to 0 dB followed by an amplifier with 21 dB, 24 dB, 27 dB, or 30 dB of gain. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion.
Rev. B | Page 27 of 48
Page 28
AD9273
Table 9. Sensitivity and Dynamic Range of Trade-Offs
LNA
Gain
Full-Scale Input
(V/V) (dB) GAIN+ = 0 V
(V p-p)
Input-Referred Noise Voltage (nV/√Hz)
6 15.6 0.733 1.6 21 65.9 62.3 1.98 24 64.1 59.7 1.91 27 61.8 57.0 1.87 30 59.2 54.1 1.85 8 17.9 0.550 1.42 21 65.9 61.6 1.66 24 64.1 58.9 1.61 27 61.8 56.2 1.58 30 59.2 53.3 1.57 12 21.3 0.367 1.26 21 65.9 60.1 1.35 24 64.1 57.3 1.32 27 61.8 54.4 1.31 30 59.2 51.5 1.30
1
LNA: output full scale = 4.4 V p-p differential.
2
Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V.
3
ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input.
4
Output dynamic range at minimum VGA gain (VGA dominated).
5
Output dynamic range at maximum VGA gain (LNA dominated).
6
Channel noise at maximum VGA gain.
Table 9 demonstrates the sensitivity and dynamic range of trade-offs that can be achieved relative to various LNA and VGA gain settings.
For example, when the VGA is set for the minimum gain voltage, the TGC path is dominated by VGA noise and achieves the maximum output SNR. However, as the postamp gain options are increased, the input-referred noise is reduced and the SNR is degraded.
If the VGA is set for the maximum gain voltage, the TGC path is dominated by LNA noise and achieves the lowest input­referred noise, but with degraded output SNR. The higher the TGC (LNA + VGC) gain, the lower the output SNR. As the postamp gain is increased, the input-referred noise is reduced.
At low gains, the VGA should limit the system noise perfor­mance (SNR); at high gains, the noise is defined by the source and the LNA. The maximum voltage swing is bound by the full­scale peak-to-peak ADC input voltage (2 V p-p).
Both the LNA and VGA have full-scale limitations within each section of the TGC path. These limitations are dependent on the gain setting of each function block and on the voltage applied to the
1, 2, 3
VGA Postamp Gain (dB)
Channel
Typical Output Dynamic Range
4
GAIN+ = 1.6 V
Input-Referred Noise6 @
5
GAIN+ = 1.6 V (nV/√Hz)
GAIN+ and GAIN− pins. The LNA has three limitations, or full­scale settings, that can be applied through the SPI. Similarly, the VGA has four postamp gain settings that can be applied through the SPI. The voltage applied to the GAIN± pins determines which amplifier (the LNA or VGA) saturates first. The maximum signal input level that can be applied as a function of voltage on the GAIN± pins for the selectable gain options of the SPI is shown in Figure 48 to Figure 50.
0.40
0.35
0.30
0.25 PGA GAIN = 27dB
0.20
0.15
0.10
INPUT FULL-SCALE (V p-p)
0.05
0
Figure 48. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations
PGA GAIN = 30dB
00.20.40.60.8 GAIN+ (V)
PGA GAIN = 21dB
PGA GAIN = 24dB
1.0 1.2 1.4 1.6
07030-117
Rev. B | Page 28 of 48
Page 29
AD9273
G
0.6
0.5
0.4
0.3
0.2 PGA GAIN = 27dB
INPUT FULL-SCALE (V p-p)
0.1
PGA GAIN = 30dB
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
PGA GAIN = 21dB
PGA GAIN = 24dB
GAIN+ (V)
07030-178
Figure 49. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations
0.9
0.8
0.7
0.6
0.5
0.4
0.3
INPUT FULL-SCALE (V p-p)
0.2 PGA GAIN = 27dB
0.1
PGA GAIN = 30dB
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
PGA GAIN = 21dB
PGA GAIN = 24dB
GAIN+ (V)
07030-179
Figure 50. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations

Variable Gain Amplifier

The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 6 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 51.
AIN±
VIP
VIN
g
m
3dB
GAIN INTERPOLATOR
POSTAMP
+
per side is 180 Ω nominally for a total differential resistance of 360 Ω. The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA to the VGA without introducing large offsets due to common­mode differences. However, any offset from the LNA becomes amplified as the gain increases, producing an exponentially increasing VGA output offset.
The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, deter­mines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from −42 dB to 0 dB. This circuit technique results in linear-in-dB gain law conformance and low distortion levels—only deviating ±0.5 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply.
The X-AMP inputs are part of a programmable gain feedback amplifier that completes the VGA. Its bandwidth is approximately 100 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting.

Gain Control

The gain control interface, GAIN±, is a differential input. V
GAIN
varies the gain of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. For GAIN− at 0.8 V, the nominal GAIN+ range for 28 dB/V is 0 V to 1.6 V, with the best gain linearity from about 0.16 V to
1.44 V, where the error is typically less than ±0.5 dB. For GAIN+ voltages greater than 1.44 V and less than 0.16 V, the error increases. The value of GAIN+ can exceed the supply voltage by 1 V without gain foldover.
Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain.
There are two ways in which the GAIN+ and GAIN− pins can be interfaced. With the single-ended method, a Kelvin type of connection to ground can be used as shown in Figure 52. For driving multiple devices, it is preferable to use the differential method shown in Figure 53. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accommodate a 1.6 V full-scale input.
POSTAMP
Figure 51. Simplified VGA Schematic
The input of the VGA is a 14-stage differential resistor ladder with
3.5 dB per tap. The resulting total gain range is 42 dB, which
AD9273
GAIN+
07030-078
GAIN–
0.01µF
0.01µF
Figure 52. Single-Ended GAIN± Pins Configuration
100
KELVIN
CONNECTION
50
0V TO 1.6V DC
7030-109
allows for range loss at the endpoints. The effective input resistance
Rev. B | Page 29 of 48
Page 30
AD9273
AD9273
±0.4VDC AT
100
GAIN+
GAIN–
Figure 53. Differential GAIN± Pins Configuration
0.01µF 100
0.01µF
0.8V CM
±0.4VDC AT
0.8V CM
499
AD8138
499
499
0.8V CM 523
AVDD2
31.3k
10k
50
±0.8V DC

VGA Noise

In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This latter limit is set in accordance with the total noise floor of the ADC.
Output-referred noise as a function of GAIN+ is shown in Figure 15 for the short-circuit input conditions. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range.
The output-referred noise is a flat 90 nV/√Hz (postamp gain = 24 dB) over most of the gain range because it is dominated by the fixed output-referred noise of the VGA. At the high end of the gain control range, the noise of the LNA and of the source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input­referred contribution of the VGA is miniscule.
At lower gains, the input-referred noise, and therefore the noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC.
Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and is usually evident only when a large signal is present. The gain interface includes an on-chip noise filter, which significantly reduces this effect at frequencies greater than 5 MHz. Care should be taken to minimize noise impinging at the GAIN± inputs. An external RC filter can be used to remove V
GAIN
source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.

Antialiasing Filter

The filter that the signal reaches prior to the ADC is used to reject dc signals and to band limit the signal for antialiasing. Figure 54 shows the architecture of the filter.
The antialaising filter is a combination of a single-pole high­pass filter and a second-order low-pass filter. The high-pass filter can be configured at a ratio of the low-pass filter cutoff. This is selectable through the SPI.
The filter uses on-chip tuning to trim the capacitors and in turn set the desired cutoff frequency and reduce variations. The
07030-098
default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1,
1.2, or 1.3 times this frequency through the SPI. The cutoff tolerance is maintained from 8 MHz to 18 MHz.
4k
C
30C
30C
C = 0.8pF TO 5.1p F n = 0 TO 7
Figure 54. Simplified Filter Schematic
4k
10k/n
4k
4C
2k
2k
4k
C
7030-110
Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift.
There is a total of eight SPI-programmable settings that allow the user to vary the high-pass filter cutoff frequency as a function of the low-pass cutoff frequency. Two examples are shown in Table 10: one is for an 8 MHz low-pass cutoff frequency, and the other is for an 18 MHz low-pass cutoff frequency. In both cases, as the ratio decreases, the amount of rejection on the low-end frequencies increases. Therefore, making the entire AAF frequency pass band narrow can reduce low frequency noise or maximize dynamic range for harmonic processing.
Table 10. SPI-Selectable High-Pass Filter Cutoff Options
High-Pass Cutoff
SPI Setting Ratio1
Low-Pass Cutoff = 8 MHz
Low-Pass Cutoff = 18 MHz
0 20.65 387 kHz 872 kHz 1 11.45 698 kHz 1.571 MHz 2 7.92 1.010 MHz 2.273 MHz 3 6.04 1.323 MHz 2.978 MHz 4 4.88 1.638 MHz 3.685 MHz 5 4.10 1.953 MHz 4.394 MHz 6 3.52 2.270 MHz 5.107 MHz 7 3.09 2.587 MHz 5.822 MHz
1
Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.
Rev. B | Page 30 of 48
Page 31
AD9273
*
*
V
V
ADC
The AD9273 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock.
The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clocks.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9273 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or using capacitors. These pins are biased internally and require no additional bias.
Figure 55 shows the preferred method for clocking the AD9273. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50MHz, is converted from single ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9273 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9273, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance.
3.3V
OUT
VFAC3
Figure 55. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 56. The AD951x/AD952x family of clock drivers offers excellent jitter performance.
3.3V 50
VFAC3
OUT
50 RESISTOR IS OPTIONAL.
MINI-CIRCUITS
0.1µF
50
*
ADT1-1WT, 1:1Z
100
AD951x/AD952x
0.1µF CLK
PECL DRIVER
0.1µF CLK
XFMR
0.1µF
FAMILY
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSM2812
240240
100
Figure 56. Differential PECL Sample Clock
0.1µF
0.1µF
CLK+
ADC
AD9273
CLK–
CLK+
ADC
AD9273
CLK–
07030-050
07030-051
3.3V 50
VFAC3
OUT
50 RESISTOR IS OPTIONAL.
*
0.1µF
0.1µF
AD951x/AD952x
FAMILY
CLK
LVDS DRIVE R
CLK
0.1µF
100
0.1µF
CLK+
ADC
AD9273
CLK–
Figure 57. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 kΩ resistor (see Figure 58). Although the CLK+ input circuit supply is AVDDx (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible.
3.3
VFAC3
OUT
*
50 RESISTOR IS OPTIONAL.
0.1µF
50
0.1µF
Figure 58. Single-Ended 1.8 V CMOS Sample Clock
3.3
VFAC3
OUT
*
50 RESISTOR IS OPTIONAL.
0.1µF
50
0.1µF
Figure 59. Single-Ended 3.3 V CMOS Sample Clock
*
*
AD951x/AD952x
FAMILY
CLK
CMOS DRIVER
CLK
AD951x/AD952x
FAMILY
CLK
CMOS DRIVER
CLK
0.1µF
OPTIONAL
100
39k
OPTIONAL
100
0.1µF
0.1µF
0.1µF
CLK+
ADC
AD9273
CLK–
CLK+
ADC
AD9273
CLK–

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9273 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9273. When the DCS is on, noise and distortion perfor­mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See
Table 1 7 for more details on
using this feature.
07030-052
07030-053
07030-054
Rev. B | Page 31 of 48
Page 32
AD9273
G
The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f due only to aperture jitter (t
SNR Degradation = 20 × log 10[1/2 × π × f
) can be calculated by
J
A
× tJ]
A
In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 60).
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9273. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs (visit www.analog.com).
130
RMS CLOCK JITTER REQUI R E M E NT
120
110
100
90
80
SNR (dB)
70
10 BITS
60
8 BITS
50
40
30
1 10 100 1000
ANALOG INP UT FREQUENCY ( MHz)
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
16 BITS
14 BITS
12 BITS
07030-038
Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter

Power Dissipation and Power-Down Mode

As shown in Figure 62, the power dissipated by the AD9273 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.
250
I
, 50MSPS SPE E D GRADE
AVDD1
200
I
, 40MSPS SPEED GRADE
I
DRVDD
AVDD1
for fIN = 5 MHz
SAMPLE
40MSPS SPEED GRADE
for fIN = 5 MHz
SAMPLE
07030-032
07030-031
150
I
, 25MSPS SP EED GRADE
)
SUPPLY CURRENT ( mA)
100
AVDD1
50
0
0
10 3020 40 50
SAMPLING FREQUENCY (MSP S)
Figure 61. Supply Current vs. f
120
115
110
105
100
95
POWER/CHANNEL (mW)
90
85
80
0
50MSPS SPEED GRADE
25MSPS SPEED GRADE
10 3020 5040
SAMPLING FREQUENCY (MSP S)
Figure 62. Power per Channel vs. f
The AD9273 features scalable LNA bias currents (see Register 0x12 in Table 17). The default LNA bias current settings are high. Figure 63 shows the typical reduction of AVDD2 current with each bias setting. It is also recommended to adjust the LNA offset using Register 0x10 (see Table 1 7) when the LNA bias setting is low.
HIGH
MID-HIGH
MID-LOW
LNA BIAS SETTIN
LOW
0 20406080100120140160 180
TOTALAVDD2 CURRENT (mA)
7030-119
Figure 63. AVDD2 Current at Different LNA Bias Settings, AD9273-40
Rev. B | Page 32 of 48
Page 33
AD9273
By asserting the PDWN pin high, the AD9273 is placed into power-down mode. In this state, the device typically dissipates 2 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9273 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
By asserting the STBY pin high, the AD9273 is placed into a standby mode. In this state, the device typically dissipates 140 mW. During standby, the entire part is powered down except the internal references. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power this device back up is also greatly reduced. The AD9273 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on VREF are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. To restore the device to full operation, approximately 0.5 ms is required when using the recommended 1 µF and 0.1 µF decoupling capacitors on the VREF pin and a 0.01 µF capacitor on the GAIN± pins. Most of this time is dependent on the gain decoupling: higher value decoupling capacitors on the GAIN± pins result in longer wake-up times.
There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times are required. The wake-up time is slightly dependent on gain. To achieve a 1 µs wake-up time when the device is in standby mode, 0.8 V must be applied to the GAIN± pins. See Tabl e 17 for more details on using these features.

Digital Outputs and Timing

The AD9273 differential outputs conform to the ANSI-644 LVDS standard by default at power-up. This can be changed to a low power, reduced-signal option similar to the IEEE 1596.3 standard by using the SDIO pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO Pin section or Tabl e 17 for more information.
The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differ­ential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver.
The AD9273 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO, DCO, and data stream with proper trace length and position can be found in Figure 64.
CH1 500mV/DIV CH2 500mV/DIV CH3 500mV/DIV
Figure 64. LVDS Output Timing Example in ANSI-644 Mode (Default)
5.0ns/DIV
7030-034
An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on regular FR-4 material is shown in Figure 65. Figure 66 shows an example of the trace lengths exceeding 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the internal termination and therefore increase the current of all eight outputs in order to drive longer trace lengths (see Figure 67). Even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see Figure 67), the power dissipation of the DRVDD supply increases when this option is used.
In cases that require increased driver strength to the DCO± and FCO± outputs because of load mismatch, Register 0x15 allows the user to double the drive strength. To do this, set Bit 0 in Register 0x15. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 0x15 because these bits take precedence over this feature. See Tab le 17 for more details.
Rev. B | Page 33 of 48
Page 34
AD9273
600
400
EYE: ALL BITS
ULS: 2398/2398
400
300
EYE: ALL BITS
ULS: 2399/2399
200
100
0
–100
–200
EYE DIAGRAM VOLTAGE ( V )
–400
–600
–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns
25
20
15
10
TIE JITTER HISTOGRAM (Hits)
5
0
–200ps –100ps 0ps 100ps 200ps
7030-035
Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less than 24 Inches on Standard FR-4
200
100
0
–100
–200
EYE DIAGRAM VOLTAGE (V)
–300
–400
–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns
25
20
15
10
TIE JITTER HISTOGRAM (Hits)
5
0
–200ps –100ps 0ps 100ps 200ps
Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Greater than 24 Inches on Standard FR-4
07030-036
Rev. B | Page 34 of 48
Page 35
AD9273
600
EYE: ALL BITS
400
200
0
–200
EYE DIAGRAM VOLTAGE ( V )
–400
–600
–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns
25
20
15
10
TIE JITTER HISTOGRAM (Hits)
5
0
–200ps –100ps 0ps 100ps 200ps
Figure 67. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination
Resistor and Trace Lengths of Greater than 24 Inches on Standard FR-4
ULS: 2396/2396
7030-037
The format of the output data is offset binary by default. An example of the output coding format can be found in Table 11. To change the output data format to twos complement, see the Memory Map section.
Table 11. Digital Output Coding
(VIN+) − (VIN−),
Code
Input Span = 2 V p-p (V)
4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 2047 −0.000488 0111 1111 1111 0 −1.00 0000 0000 0000
Digital Output Offset Binary (D11 ... D0)
Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 600 Mbps (12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application. See Tabl e 17 for details on enabling this feature.
Two output clocks are provided to assist in capturing data from the AD9273. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9273 and must be captured on the rising and falling edges of the DCO± that supports double data rate (DDR) capturing. The frame clock output (FCO±) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information.
Table 12. Flexible Output Test Modes
Output Test Mode Bit Sequence
Pattern Name Digital Output Word 1 Digital Output Word 2
0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 0000 1000 0000 0000 Yes 0010 +Full-scale short 1111 1111 1111 1111 1111 1111 Yes 0011 −Full-scale short 0000 0000 0000 0000 0000 0000 Yes 0100 Checkerboard output 1010 1010 1010 0101 0101 0101 No 0101 PN sequence long N/A N/A Yes 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No 1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No 1001 1-/0-bit toggle 1010 1010 1010 N/A No 1010 1× sync 0000 0011 1111 N/A No 1011 One bit high 1000 0000 0000 N/A No 1100 Mixed bit frequency 1010 0011 0011 N/A No
Subject to Data Format Select
Rev. B | Page 35 of 48
Page 36
AD9273
When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in Figure 2, is 90° relative to the output data edge.
An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams and to test the device’s compatibility with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. When using the 14-bit option, the data stream stuffs two 0s at the end of the normal 14-bit serial data.
When the SPI is used, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is repre­sented first in the data output serial stream (see Figure 3).
There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Tabl e 12 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
The PN sequence short pattern produces a pseudorandom
9
bit sequence that repeats itself every 2
− 1 bits, or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value is a specific value instead of all 1s (see Table 13 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
23
sequence that repeats itself every 2
− 1 bits, or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s and the AD9273 inverts the bit stream with relation to the ITU standard (see Tab le 13 for the initial values).
Table 13. PN Sequence
Initial
Sequence
PN Sequence Short 0x0DF 0xDF9, 0x353, 0x301 PN Sequence Long 0x29B80A 0x591, 0xFD7, 0x0A3
Value
First Three Output Samples (MSB First)
Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI.

SDIO Pin

This pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current.

SCLK Pin

This pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant.

CSB Pin

This pin is required to operate the SPI port interface. It has an internal 70 kΩ pull-up resistor that pulls this pin high and is both
1.8 V and 3.3 V tolerant.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using other than the recommended 10.0 kΩ resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance.

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the AD9273. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, this device does not support ADC full-scale ranges below 2.0 V p-p.
When applying the decoupling capacitors to the VREF pin, use ceramic low-ESR capacitors. These capacitors should be close to the reference pin and on the same layer of the PCB as the AD9273. The VREF pin should have both a 0.1 µF capacitor and a 1 µF capacitor connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample.
The reference settings can be selected using the SPI. The settings allow two options: using the internal reference or using an external reference. The internal reference option is the default setting and has a resulting differential span of 2 V p-p.
Table 14. SPI-Selectable Reference Settings
Resulting
SPI-Selected Mode
External Reference N/A 2 × external reference Internal Reference (Default) 1.0 2.0
VREF (V)
Resulting Differential Span (V p-p)
Rev. B | Page 36 of 48
Page 37
AD9273

Power and Ground Recommendations

When connecting power to the AD9273, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one 1.8 V supply is available, it should be routed to the AVDD1 first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace lengths.
A single PC board ground plane should be sufficient when using the AD9273. With proper decoupling and smart parti­tioning of the PC board’s analog, digital, and clock sections, optimum performance can be achieved easily.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD9273. An exposed continuous copper plane on the PCB should mate to
the AD9273 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the device and PCB, partition the continuous copper pad by overlaying a silk­screen or solder mask to divide this into several uniform sections. This ensures several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the AD9273 and PCB. See Figure 68 for a PCB layout example. For more detailed infor­mation on packaging and for more PCB layout examples, see the AN-772 Application Note.
SILKSCREEN PARTITION
PIN 1 INDICATOR
07030-069
Figure 68. Typical PCB Layout
Rev. B | Page 37 of 48
Page 38
AD9273

SERIAL PORT INTERFACE (SPI)

The AD9273 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as doc­umented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
There are three pins that define the serial port interface (SPI): the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the device’s internal memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 15).
Table 15. Serial Port Pins
Pin Function
SCLK
Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes.
SDIO
Serial data input/output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame.
CSB
Chip select bar (active low). This control gates the read and write cycles.
The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 70 and Tab le 16 .
During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructtions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction.
Rev. B | Page 38 of 48
In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode, as defined in the SDIO Pin and SCLK Pin sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Inter facing to High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Tabl e 15 constitute the physical interface between the user’s programming device and the serial port of the AD9273. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.
In cases where multiple SDIO pins share a common connection, care should be taken to ensure that proper V Figure 69 shows the number of SDIO pins that can be connected together, assuming the same load as the AD9273, as well as the resulting V
(V)
OH
V
level.
OH
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715 0302010 40 50 60 70 80 90 100
NUMBER OF SDIO PINS CONNECT E D TOGETHE R
Figure 69. SDIO Pin Loading
levels are met.
OH
07030-113
Page 39
AD9273
This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user with an alternative method, other than a full SPI controller, for programming the device (see the AN-812 Application Note).
If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions when the CSB is strapped to AVDD during device power-up. See the SDIO Pin and SCLK Pin sections for details on which pin-strappable functions are supported on the SPI pins.
t
HI
t
CLK
t
LO
D5 D4 D3 D2 D1 D0
CSB
SCLK
SDIO
DON’T CA RE
t
DS
t
S
R/W W1 W0 A12 A11 A10 A9 A8 A7
t
DH
Figure 70. Serial Timing Details
Table 16. Serial Timing Definitions
Parameter Minimum Timing (ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK tDH 2 Hold time between the data and the rising edge of SCLK t
40 Period of the clock
CLK
tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK tHI 16 Minimum period that SCLK should be in a logic high state tLO 16 Minimum period that SCLK should be in a logic low state t
10
EN_SDIO
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 70)
t
10
DIS_SDIO
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 70)
t
H
DON’T CA RE
DON’T CA REDON’T CA RE
07030-068
Rev. B | Page 39 of 48
Page 40
AD9273

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04 to Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x2D).
The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address followed by an 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers.

Caution

All registers except Register 0x00, Register 0x02, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

RESERVED LOCATIONS

Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

After a reset, critical registers are automatically loaded with default values. These values are indicated in Tabl e 17, where an X refers to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”
Rev. B | Page 40 of 48
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AD9273
Table 17. AD9273 Memory Map Register
Addr. (Hex) Register Name
Chip Configuration Registers
00 CHIP_PORT_CONFIG 0 LSB first
01 CHIP_ID Chip ID Bits[7:0]
02 CHIP_GRADE X X Child ID[5:4]
Device Index and Transfer Registers
04 DEVICE_INDEX_2 X X X X Data
05 DEVICE_INDEX_1 X X Clock
FF DEVICE_UPDATE X X X X X X X SW
ADC Functions Registers
08 Modes X X X X 0 Internal power-down mode
09 Clock X X X X X X X Duty
0D TEST_IO User test mode
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
1 = on 0 = off (default)
00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once
Soft reset 1 = on 0 = off (default)
(identify device variants of Chip ID) 00 = 40 MSPS (default) 01 = 25 MSPS 10 = 50 MSPS
Channel DCO± 1 = on 0 = off (default)
Reset PN long gen 1 = on 0 = off (default)
1 1 Soft
(AD9273 = 0x2F, default)
Clock Channel FCO± 1 = on 0 = off (default)
Reset PN short gen 1 = on 0 = off (default)
Rev. B | Page 41 of 48
reset 1 = on 0 = off (default)
X X X X 0x00 Child ID used to
Data Channel H 1 = on (default) 0 = off
Data Channel D 1 = on (default) 0 = off
Output test mode—see Table 12 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the OUTPUT_MODE register)
Channel
G
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
LSB first 1 = on 0 = off (default)
Data Channel F 1 = on (default) 0 = off
Data Channel B 1 = on (default) 0 = off
Bit 0 (LSB)
0 0x18 The nibbles
Data Channel E 1 = on (default) 0 = off
Data Channel A 1 = on (default) 0 = off
transfer 1 = on 0 = off (default)
cycle stabilizer 1 = on (default) 0 = off
Default Value
Read only
0x0F Bits are set to
0x0F Bits are set to
0x00 Synchronously
0x00 Determines
0x01 Turns the internal
0x00 When this register
Default Notes/ Comments
should be mirrored so that LSB- or MSB-first mode is set cor­rectly regardless of shift mode.
Default is unique chip ID, different for each device. This is a read-only register.
differentiate graded devices.
determine which on-chip device receives the next write command.
determine which on-chip device receives the next write command.
transfers data from the master shift register to the slave.
various generic modes of chip operation (global).
duty cycle stabilizer on and off (global).
is set, the test data is placed on the output pins in place of normal data. (Local, expect for PN sequence.)
Page 42
AD9273
Addr. (Hex) Register Name
0F FLEX_CHANNEL_
INPUT
10 FLEX_OFFSET X X 6-bit LNA offset adjustment
11 FLEX_GAIN X X X X PGA gain
12 BIAS_CURRENT X X X X 1 X LNA bias
14 OUTPUT_MODE X 0 = LVDS
15 OUTPUT_ADJUST X X Output driver
16 OUTPUT_PHASE X X X X 0011 = output clock phase adjust
18 FLEX_VREF X 0 =
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Filter cutoff frequency control 0000 = 1.3 × 1/3 × f 0001 = 1.2 × 1/3 × f 0010 = 1.1 × 1/3 × f 0011 = 1.0 × 1/3 × f 0100 = 0.9 × 1/3 × f 0101 = 0.8 × 1/3 × f 0110 = 0.7 × 1/3 × f
1000 = 1.3 × 1/4.5 × f 1001 = 1.2 × 1/4.5 × f 1010 = 1.1 × 1/4.5 × f 1011 = 1.0 × 1/4.5 × f 1100 = 0.9 × 1/4.5 × f 1101 = 0.8 × 1/4.5 × f 1110 = 0.7 × 1/4.5 × f
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
(default)
X X X X 0x30 Antialiasing filter
10 0000 = LNA bias high, mid-high, mid-low (default) 10 0001 = LNA bias low
LNA gain 00 = 21 dB 01 = 24 dB (default) 10 = 27 dB 11 = 30 dB
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
00 = high
01 = mid-high
(default)
10 = mid-low
11 = low
ANSI-644 (default) 1 = LVDS low power,
X X X Output
invert 1 = on 0 = off (default)
00 = offset binary
(default)
01 = twos
complement
(IEEE
1596.3 similar)
X X X DCO±
termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω
(0000 through 1010) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge (default) 0100 = 240° relative to data edge 0101 = 300° relative to data edge 0110 = 360° relative to data edge 0111 = 420° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge
X X X X X X 0x00 Select internal internal reference 1 = external reference
Bit 0 (LSB)
and FCO± 2× drive strength 1 = on 0 = off (default)
Default Value
Default Notes/ Comments
cutoff (global).
0x20 LNA force offset
correction (local).
0x06 LNA and PGA
gain adjustment (global).
0x08 LNA bias current
adjustment (global).
0x00 Configures the
outputs and the format of the data (Bits[7:3] and Bits[1:0] are global; Bit 2 is local).
0x00 Determines LVDS
or other output properties. Pri­marily functions to set the LVDS span and common­mode levels in place of an external resistor (Bits[7:1] are global; Bit 0 is local).
0x03 On devices that
utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected.
reference (recommended default) or external reference (global).
Rev. B | Page 42 of 48
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AD9273
Addr. (Hex) Register Name
19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
21 SERIAL_CONTROL LSB first
22 SERIAL_CH_STAT X X X X X X Channel
2B FLEX_FILTER X Enable
2C ANALOG_INPUT X X X X X X LOSW-x connect
2D CROSS_POINT_
SWITCH
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
1 = on 0 = off (default)
X X X <10
MSPS, low encode rate mode
000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits
100 = 14 bits 1 = on 0 = off (default)
output reset 1 = on 0 = off (default)
X X High-pass filter cutoff automatic low-pass tuning 1 = on (self­clearing)
0000 = f 0001 = f 0010 = f 0011 = f 0100 = f 0101 = f 0110 = f 0111 = f
/20.7
LP
/11.5
LP
/7.9
LP
/6.0
LP
/4.9
LP
/4.1
LP
/3.5
LP
/3.1
LP
00 = high-Z 01 = (−)LNA output 10 = (+)LNA output 11 = high-Z
X X Crosspoint switch enable
10 0000 = CWD0± (differential)
10 0001 = CWD1± (differential)
10 0010 = CWD2± (differential)
10 0011 = CWD3± (differential)
10 0100 = CWD4± (differential)
10 0101 = CWD5± (differential)
10 0110 = CWD6± (differential)
10 0111 = CWD7± (differential)
11 0000 = CWD0+ (single ended)
11 0001 = CWD1+ (single ended)
11 0010 = CWD2+ (single ended)
11 0011 = CWD3+ (single ended)
11 0100 = CWD4+ (single ended)
11 0101 = CWD5+ (single ended)
11 0110 = CWD6+ (single ended)
11 0111 = CWD7+ (single ended)
11 1000 = CWD0− (single ended)
11 1001 = CWD1− (single ended)
11 1010 = CWD2− (single ended)
11 1011 = CWD3− (single ended)
11 1100 = CWD4− (single ended)
11 1101 = CWD5− (single ended)
11 1110 = CWD6− (single ended)
11 1111 = CWD7− (single ended)
0x xxxx = power down CW channel (default)
Bit 0 (LSB)
Channel power­down 1 = on 0 = off (default)
Default Value
Default Notes/ Comments
pattern, 1 LSB (global).
pattern, 1 MSB (global).
pattern, 2 LSB (global).
pattern, 2 MSB (global).
0x00 Serial stream
control. Default causes MSB first and the native bit stream (global).
0x00 Used to power
down individual sections of a converter (local).
0x00 Filter cutoff
(global). (f
=
LP
low-pass filter cutoff frequency.)
0x00 LNA active
termination/input impedance (global).
0x00 Crosspoint switch
enable (local).
Rev. B | Page 43 of 48
Page 44
AD9273
A

OUTLINE DIMENSIONS

0.75
0.60
0.45
1.20
MAX
16.00 BSC SQ
100 1
PIN 1
14.00 BSC SQ
76
76 100
75
75
1
1.05
1.00
0.95
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
0° MIN
0.08 MAX COPLANARITY
0.20
0.09
3.5°
BOTTOM VIEW
0.50 BSC
LEAD PITCH
EXPOSED
PAD
(PINS UP)
0.27
0.22
0.17
TOP VIEW
(PINS DOWN)
51
25
26 50
VIEW A
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
51
9.50 SQ
25
2650
FOR PROPE R CONNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DES CRIPTIONS SECTION OF THIS DATA SHEET.
100908-A
Figure 71. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters
1 CORNER
INDEX AREA
321
5
4
A B C D E F G H J K L M
1.00
0.85
1.40 MAX
10.10
10.00
9.90
BALL A1 INDICATOR
TOP VIEW
DETAIL A
8.80
BSC SQ
0.80 BSC
9
121110 876
BOTTOM VIEW
DETAIL A
0.43 MAX
0.25 MIN
0.55
0.50
0.45
SEATING PLANE
COPLANARITY
0.12 MAX
BALL DIAMETER
COMPLIANT WITH JEDEC STANDARDS MO-205-AC.
012006-0
Figure 72. 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]
(BC-144-1)
Dimensions shown in millimeters
Rev. B | Page 44 of 48
Page 45
AD9273

ORDERING GUIDE

Model
AD9273BSVZ-50 AD9273BSVZRL-50 AD9273BSVZ-40 AD9273BSVZRL-40 AD9273BSVZ-25 AD9273BSVZRL-25 AD9273BBCZ-25 AD9273BBCZ-40 AD9273BBCZ-50 AD9273-50EBZ
1
Z = RoHS Compliant Part.
1
−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3
1
1
−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3
1
1
−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3
1
1
−40°C to +85°C 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-144-1
1
−40°C to +85°C 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-144-1
1
−40°C to +85°C 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-144-1
1
Evaluation Board, 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
Temperature Range Package Description
−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3
−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3
−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3
Package Option
Rev. B | Page 45 of 48
Page 46
AD9273
NOTES
Rev. B | Page 46 of 48
Page 47
AD9273
NOTES
Rev. B | Page 47 of 48
Page 48
AD9273
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07030-0-7/09(B)
Rev. B | Page 48 of 48
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