Datasheet AD9271 Datasheet (ANALOG DEIVCES)

Octal LNA/VGA/AAF/ADC

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FEATURES

8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA)

Input-referred noise = 1.1 nV/√Hz @ 5 MHz typical,

gain = 18 dB SPI-programmable gain = Single-ended input; V

333 mV p-p/250 mV p-p Dual-mode active input impedance matching Bandwidth (BW) > 70 MHz Full-scale (FS) output = 2 V p-p differential

Variable gain amplifier (VGA)

Gain range = −6 dB to +24 dB Linear-in-dB gain control

Antialiasing filter (AAF)

rd

-order Butterworth cutoff

3 Programmable from 8 MHz to 18 MHz

Analog-to-digital converter (ADC)

12 bits at 10 MSPS to 50 MSPS SNR = 70 dB SFDR = 80 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs

Includes crosspoint switch to support

ontinuous wave (CW) Doppler

c

Low power, 150 mW per channel at 12 bits/40 MSPS (TGC) 90 mW per channel in CW Doppler Single 1.8 V supply (3.3 V supply for CW Doppler output bias) Flexible power-down modes Overload recovery in <10 ns Fast recovery from low power standby mode, <2 μs 100-lead TQFP

APPLICATIONS

Medical imaging/ultrasound Automotive radar

GENERAL DESCRIPTION

The AD9271 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with low noise preamplifier (LNA); an antialiasing filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC).

Each channel features a variable gain range of 30 dB, a fully

ifferential signal path, an active input preamplifier termination, a

d maximum gain of up to 40 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.

14 dB/15.6 dB/18 dB

maximum = 400 mV p-p/

IN

and Crosspoint Switch

AD9271

FUNCTIONAL BLOCK DIAGRAM

AVDD

LOSW-A

LO-A

LI-A

LG-A

LOSW-B

LO-B

LI-B

LG-B

LOSW-C

LO-C

LI-C

LG-C

LOSW-D

LO-D

LI-D

LG-D

LOSW-E

LO-E

LI-E

LG-E

LOSW-F

LO-F

LI-F

LG-F

LOSW-G

LO-G

LI-G

LG-G

LOSW-H

LO-H

LI-H

LG-H

LNA

SWITCH

ARRAY

CWVDD

VGA

GAIN–

GAIN+

CWD[5:0]+/–

The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.2 nV/√Hz, and the combined input-referred noise of the entire channel is 1.4 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 15.6 dB LNA gain, the input SNR is roughly 86 dB. In CW Doppler mode, the LNA output drives a transconductance amp that is switched through an 8 × 6 differential crosspoint switch. The switch is programmable through the SPI.

PDWN

AAF

REFERENCE

VREF

REFB

SENSE

Figure 1.

STBY

REFT

AD9271

12-BIT

ADC

12-BIT

ADC

12-BIT

ADC

12-BIT

ADC

12-BIT

ADC

12-BIT

ADC

12-BIT

ADC

12-BIT

ADC

SERIAL

CSB

RBIAS

DRVDD

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

DATA

PORT

INTERFACE

SDIO

CLK+

SCLK

DOUTA+ DOUTA–

DOUTB+ DOUTB–

DOUTC+ DOUTC–

DOUTD+ DOUTD–

DOUTE+ DOUTE–

DOUTF+ DOUTF–

DOUTG+ DOUTG–

DOUTH+ DOUTH–

FCO+

FCO–

RATE

DCO+

MULTIPLIER

DCO–

CLK–

06304-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

12/07—Rev. 0 to Rev. A

Change to AC Specifications Text .................................................. 4

Added Input Noise Current ............................................................ 4

Added Noise Figure.......................................................................... 4

Changes to Signal-to-Noise Ratio Units........................................ 4

Changes to Harmonic Distortion Units ........................................5

Added Endnote 3.............................................................................. 6

Changes to Table 6.......................................................................... 11

Inserted Figure 19 and Figure 21.................................................. 16

Changes to Figure 20...................................................................... 16

Changes to Theory of Operation Section.................................... 20

Changes to Figure 40 and Figure 41............................................. 21

Change to Active Impedance Matching Section ........................22

Changes to LNA Noise Section..................................................... 22

Changes to Figure 43...................................................................... 22

Rev. A | Page 2 of 60

Change to Input Overload Protection Section ........................... 23

Changes to TGC Operation Section ............................................ 25

Changes to Gain Control Section................................................. 26

Changes to Figure 52...................................................................... 26

Change to Table 11 ......................................................................... 33

Changes to Serial Interface Port (SPI) Section........................... 35

Changes to Hardware Interface Section...................................... 35

Changes to Reading the Memory Map Table Section ............... 37

Added Applications Information and

Design Guidelines Sections...................................................... 41

Change to Input Signals Section................................................... 42

Changes to Figure 73...................................................................... 42

Changes to Table 16 ....................................................................... 55

6/07—Revision 0: Initial Version

AD9271

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The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for

he appropriate LVDS serial data rate. A data clock (DCO±) for

t capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.

Powering down individual channels is supported to increase ba

ttery life for portable applications. There is also a standby mode option that allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable speed grades.

The ADC contains several features designed to maximize flexibility

nd minimize system cost, such as a programmable clock, data

a alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the serial port interface.

Fabricated in an advanced CMOS process, the AD9271 is a

vailable in a 16 mm × 16 mm, RoHS compliant, 100-lead

TQFP. It is specified over the industrial temperature range of

−40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight channels are contained in a small,

space-saving package. Full TGC path, ADC, and crosspoint switch contained within a 100-lead, 16 mm × 16 mm TQFP.

ow Power of 150 mW per Channel at 40 MSPS.

2. L

3. In

tegrated Crosspoint Switch. This switch allows numerous multichannel configuration options to enable the CW Doppler mode.

ase of Use. A data clock output (DCO±) operates up to

4. E

300 MHz and supports double data rate (DDR) operation.

5. U

ser Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

ntegrated Third-Order Antialiasing Filter. This filter is placed

6. I

between the TGC path and the ADC and is programmable from 8 MHz to 18 MHz.

Rev. A | Page 3 of 60

AD9271

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SPECIFICATIONS

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 15.6 dB (6), AAF LPF cutoff = 1/3 × f

Table 1.

AD9271-25 AD9271-40 AD9271-50 Parameter

LNA CHARACTERISTICS

FULL-CHANNEL (TGC)

1

Gain = 5/6/8 Single-ended input

Single-ended input

Input Voltage Range,

Gain = 5/6/8

Input Common

Mode

Input Resistance RFB = 200 Ω 50 50 50 Ω RFB = 400 Ω 100 100 100 Ω RFB = ∞ 15 15 15 kΩ Input Capacitance LI-x 15 15 15 pF

−3 dB Bandwidth 40 60 70 MHz Input Noise Current,

Gain = 5/6/8

Input Noise Voltage,

Gain = 5/6/8

1 dB Input

Compression Point, Gain = 5/6/8

Noise Figure

Active Termination

Match

Unterminated RFB = ∞ 4.9 4.4 4.2 dB

CHARACTERISTICS AAF High-Pass Cutoff −3 dB DC/350/700 DC/350/700 DC/350/700 kHz AAF Low-Pass Cutoff −3 dB, programmable 1/3 × f

Bandwidth Tolerance ±15 ±15 ±15 % Group Delay Variation f = 1 to 18 MHz,

Input-Referred Noise

Voltage

Correlated Noise Ratio No signal, correlated/

Output Offse t AAF high pass =

Signal-to-Noise Ratio

(SNR) fIN = 5 MHz

at −7 dBFS fIN = 5 MHz

at −1 dBFS

, HPF cutoff = 700 kHz, full temperature, unless otherwise noted.

S

Conditions Min Typ Max Min Typ Max Min Typ Max Unit

to differential output

to single-ended output

LNA output limited to 2 V p-p differential output

1.4 1.4 1.4 V

1.1 1.1 1.1 pA/√Hz

RS = 0 Ω, RFB = ∞ 1.4/1.4/1.3 1.3/1.2/1.1 1.3/1.2/1.1 nV/√Hz

V

= 0 V 770/650/495 770/650/495 770/650/495 mV p-p

GAIN

RS = 50 Ω, RFB = 200 Ω 6.7 6.7 6.7 dB

gain = 0 V to 1 V LNA gain = 5/6/8,

RFB = ∞

uncorrelated

700 kHz

V

= 0 V 65.8 64.4 63.7 dBFS

GAIN

V

= 1 V 62 59.7 59 dBFS

GAIN

14/15.6/18 14/15.6/18 14/15.6/18 dB

8/9.6/12 8/9.6/12 8/9.6/12 dB

400/333/250 400/333/250 400/333/250 mV p-p

SAMPLE

(8 to 18)

±2 ±2 ±2 ns

1.7/1.6/1.5 1.6/1.4/1.3 1.6/1.4/1.2 nV/√Hz

−30 −30 −30 dB

−50 +50 −35 +35 −35 +35 LSB

1/3 × f

(8 to 18)

SAMPLE

1/3 × f

(8 to 18)

SAMPLE

MHz

2

SE

Rev. A | Page 4 of 60

AD9271

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AD9271-25 AD9271-40 AD9271-50 Parameter

GAIN ACCURACY 25°C

0.9 V < V

GAIN CONTROL

CW DOPPLER MODE

1

Conditions Min Typ Max Min Typ Max Min Typ Max Unit

Harmonic Distortion

Second Harmonic

f

= 5 MHz

IN

= 0 V −73 −71 −71 dBFS

V

GAIN

at −7 dBFS

Second Harmonic

= 5 MHz

f

IN

V

= 1 V −80 −72 −68 dBFS

GAIN

at −1 dBFS

Third Harmonic

= 5 MHz

f

IN

V

= 0 V −81 −77 −74 dBFS

GAIN

at −7 dBFS

Third Harmonic

f

= 5 MHz

IN

= 1 V −65 −63 −66 dBFS

V

GAIN

at −1 dBFS

Two-Tone IMD3

= 1 V −54.6 −63.4 −68.5 dBc

V

GAIN

(2 × F1 − F2) Distortion f

= 5.0 MHz

IN1

at −7 dBFS, f

= 6.0 MHz

IN2

at −7 dBFS

Channel-to-Channel

−70 −70 −70 dB

Crosstalk

Channel-to-Channel

Crosstalk (Overrange Condition)

Overload Recovery Full TGC path,

−70 −70 −70 dB

3

5 5 5 Degrees

= 1 MHz to 10 MHz,

f

IN

gain = 0 V to 1 V

Gain Law Confor-

0 < V

< 0.1 V +0.8 +0.8 +0.8 dB

GAIN

mance Error

0.1 V < V

Linear Gain Error V

GAIN

< 0.9 V −1.2 +1.2 −1.2 +1.2 −1.2 +1.2 dB

GAIN

< 1 V −1.2 −1.2 −1.2 dB

GAIN

= 0.5 V,

−1.3 +1.3 −1.3 +1.3 −1.3 +1.3 dB normalized for ideal AAF loss

Channel-to-Channel

0.1 V < V

< 0.9 V 0.2 0.2 0.2 dB

GAIN

Matching

INTERFACE Normal Operating

0 1 0 1 0 1 V

Range

Gain Ran ge 0 V to 1 V, normalized

10 to 40 10 to 40 10 to 40 dB

for ideal AAF loss

Scale Factor 31.6 31.6 31.6 dB/V Response Time 30 dB change 350 350 350 ns

Transconductance LNA gain = 5/6/8 10/12/16 10/12/16 10/12/16 mA/V Common Mode CW Doppler

1.5 3.6 1.5 3.6 1.5 3.6 V output pins

Input-Referred Noise

Voltage

LNA gain = 5/6/8,

= 0 Ω, RFB = ∞

R

S

1.8 /1.7/1.5 1.7 /1.5/1.4 1.7 /1.5/1.3 nV/√Hz

Output DC Bias Per channel 2.4 2.4 2.4 mA Maximum Output

Per channel ±2 ±2 ±2 mA p-p

Swing

Rev. A | Page 5 of 60

AD9271

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AD9271-25 AD9271-40 AD9271-50 Parameter

POWER SUPPLY

ADC RESOLUTION 12 12 12 Bits ADC REFERENCE

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

SE = single ended.

3

The overrange condition is specified as being 6 dB more than the full-scale input range.

1

AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V CWVDD 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 I

Full-channel mode 505 613 742 mA

AVDD

CW Doppler mode

I

DRVDD

Total Power

Dissipation (Including Output Drivers)

CW Doppler mode

Power-Down

Dissipation

Standby Power

Dissipation

Power Supply

Rejection Ratio (PSRR)

Output Voltage Error

(VREF = 1 V)

Load Regulation @

1.0 mA (VREF = 1 V)

Input Resistance 6 6 6 kΩ

Conditions Min Typ Max Min Typ Max Min Typ Max Unit

with four channels enabled

46.7 48.7 50 mA Full-channel mode,

l

no signa

with four channels enabled

4.5 4.5 4.5 mW

101.7 112.5 120.6 mW

1 1 1 mV/V

±20 ±20 ±20 mV

3 3 3 mV

136 160 170 mA

993 1063 1190 1280 1425 1494 mW

192 216 224 mW

Rev. A | Page 6 of 60

AD9271

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DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

Parameter

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF

LOGIC INPUTS (PDWN, STBY, SCLK)

Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF

LOGIC INPUT (SDIO)

Logic 1 Voltage Full 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF

LOGIC OUTPUT (SDIO)

Logic 1 Voltage (IOH = 800 A) Full 1.79 V Logic 0 Voltage (IOL = 50 A) Full 0.05 V

DIGITAL OUTPUTS (D+, D−), (ANSI-644)

Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 V Output Coding (Default) Offset binary

DIGITAL OUTPUTS (D+, D−),

(LOW POWER, REDUCED SIGNAL OPTION) Logic Compliance LVDS Differential Output Voltage (VOD) Full 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 V Output Coding (Default) Offset binary

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO pins sharing the same connection.

1

2

3

1

Temperature Min Typ Max Unit

Full 250 mV p-p

Rev. A | Page 7 of 60

AD9271

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SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

Parameter

CLOCK

1

2

Temp Min Typ Max Unit

Maximum Clock Rate Full 50 MSPS Minimum Clock Rate Full 10 MSPS Clock Pulse Width High (tEH) Full 10.0 ns Clock Pulse Width Low (tEL) Full 10.0 ns

OUTPUT PARAMETERS

2, 3

Propagation Delay (tPD) Full 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (t DCO Propagation Delay (t

DCO to Data Delay (t DCO to FCO Delay (t Data-to-Data Skew (t Wake-Up Time (Standby), V

) Full 1.5 2.3 3.1 ns

FCO

4

DATA

FRAME

DATA-MAX

)

CPD

4

)

4

)

− t

GAIN

) Full ±50 ±200 ps

DATA-MIN

= 0.5 V 25°C 1 µs

Full

Full (t Full (t

/24) − 300 (t

SAMPLE

/24) − 300 (t

SAMPLE

t

FCO

(t

+

SAMPLE

/24) /24) (t /24) (t

ns

/24) + 300 ps

SAMPLE

/24) + 300 ps

SAMPLE

Wake-Up Time (Power-Down) 25°C 1 ms Pipeline Latency Full 8

Clock

cles

cy

APERTURE

Aperture Uncertainty (Jitter) 25°C <1 ps rms

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be adjusted via the SPI interface.

3

Measurements were made using a part soldered to FR-4 material.

4

t

/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.

SAMPLE

Rev. A | Page 8 of 60

AD9271

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ADC TIMING DIAGRAMS

N – 1

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

DOUTx–

DOUTx+

N – 1

t

A

N

t

EH

t

CPD

t

FCO

t

PD

t

FRAME

MSB

D10

N – 9

N – 9D9N – 9D8N – 9D7N – 9D6N – 9D5N – 9D4N – 9D3N – 9D2N – 9D1N – 9D0N – 9

t

EL

t

DATA

D10

MSB

N – 8

06304-002

Figure 2. 12-Bit Data Serial Stream (Default)

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

DOUTx–

DOUTx+

t

A

N

t

EH

t

CPD

t

FCO

t

PD

t

FRAME

LSB

N – 9D0N – 9D1N – 9D2N – 9D3N – 9D4N – 9D5N – 9D6N – 9D7N – 9D8N – 9D9N – 9

Figure 3. 12-Bit Data Serial Stream, LSB First

t

EL

t

DATA

D10

N – 9

LSB

N – 8

D0

N – 8

06304-004

Rev. A | Page 9 of 60

AD9271

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ABSOLUTE MAXIMUM RATINGS

Table 4.

With Respec

Parameter

ELECTRICAL

AVDD GND −0.3 V to +2.0 V DRVDD GND −0.3 V to +2.0 V CWVDD GND −0.3 V to +3.9 V GND GND −0.3 V to +0.3 V AVDD DRVDD −2.0 V to +2.0 V Digital Outputs

(DOUTx+, DOUTx−, DCO+, DCO−,

FCO+, FCO−) CLK+, CLK− GND −0.3 V to +3.9 V LI-x LG-x −0.3 V to +2.0 V LO-x LG-x −0.3 V to +2.0 V LOSW-x LG-x −0.3 V to +2.0 V CWDx−, CWDx+ GND −0.3 V to +3.9 V SDIO, GAIN+, GAIN− GND −0.3 V to +2.0 V PDWN, STBY, SCLK, CSB GND −0.3 V to +3.9 V REFT, REFB, RBIAS GND −0.3 V to +2.0 V VREF, SENSE GND −0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient) Storage Temperature

Range (Ambient) Maximum Junction

Temperature Lead Temperature

(Soldering, 10 sec)

t To

Rating

GND −0.3 V to +2.0 V

−40°C to +85°C

−65°C to +150°C

150°C

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL IMPEDANCE

Table 5.

Air Flow Velocity (m/s) θ

0.0 20.3 °C/W

1.0 14.4 7.6 4.7 °C/W

2.5 12.9 °C/W

1

θ

for a 4-layer PCB with solid ground plane (simulated). Exposed pad

JA

soldered to PCB.

1

θ

JA

JB

Unit

JC

ESD CAUTION

Rev. A | Page 10 of 60

AD9271

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LOSW-DLO-D

CWD0–

CWD0+

CWD1–

CWD1+

CWD2–

CWD2+

CWVDD

GAIN–

GAIN+

RBIAS

SENSE

VREF

REFB

REFT

AVDD

CWD3–

CWD3+

CWD4–

CWD4+

CWD5–

CWD5+

LO-E

LOSW-E

9998979695949392919089888786858483828180797877

100

76

LI-E

LG-E

AVDD

LO-F

LOSW-F

LI-F

LG-F

AVDD

LO-G

LOSW-

LI-G

LG-G

AVDD

LO-H

LOSW-H

LI-H

LG-H

AVDD

CLK–

CLK+

AVDD

PIN 1

1

INDICATOR

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

EXPOSED PADDLE, PIN 0 (BOTTOM O F PACKAGE)

AD9271

TOP VIEW

(Not to Scale)

2627282930313233343536373839404142434445464748

FCO–

DRVDD

DOUTH–

DOUTH+

DOUTG–

DOUTF+

DOUTG+

DOUTF–

DCO–

DOUTE–

DOUTE+

FCO+

DCO+

DOUTD–

DOUTD+

DOUTB–

DOUTC–

DOUTC+

49

STBY

PDWN

DRVDD

DOUTA–

DOUTA+

DOUTB+

LI-D

75

LG-D

74

AVDD

73

AVDD

72

LO-C

71

LOSW-C

70

69

LI-C

LG-C

68

AVDD

67

AVDD

66

LO-B

65

64

LOSW-B

LI-B

63

LG-B

62

AVDD

61

AVDD

60

59

LO-A

58

LOSW-A

LI-A

57

LG-A

56

AVDD

55

54

AVDD

53

CSB

52

SDIO

SCLK

51

50

AVDD

06304-005

Figure 4. 100-Lead TQFP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Name Description

0 GND Ground (exposed paddle should be tied to a quiet analog ground) 3, 4, 9, 10, 15,

AVDD 1.8 V Analog Supply 16, 21, 22, 25, 50, 54, 55, 60, 61, 66, 67, 72, 73, 92

26, 47 DRVDD 1.8 V Digital Output Driver Supply 84 CWVDD 3.3 V Analog Supply 1 LI-E LNA Analog Input for Channel E 2 LG-E LNA Ground for Channel E 5 LO-F LNA Analog Output for Channel F 6 LOSW-F LNA Analog Output Complement for Channel F 7 LI-F LNA Analog Input for Channel F 8 LG-F LNA Ground for Channel F 11 LO-G LNA Analog Output for Channel G 12 LOSW-G LNA Analog Output Complement for Channel G 13 LI-G LNA Analog Input for Channel G 14 LG-G LNA Ground for Channel G 17 LO-H LNA Analog Output for Channel H

Rev. A | Page 11 of 60

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Pin No. Name Description

18 LOSW-H LNA Analog Output Complement for Channel H 19 LI-H LNA Analog Input for Channel H 20 LG-H LNA Ground for Channel H 23 CLK− Clock Input Complement 24 CLK+ Clock Input True 27 DOUTH− ADC H Digital Output Complement 28 DOUTH+ ADC H Digital Output True 29 DOUTG− ADC G Digital Output Complement 30 DOUTG+ ADC G Digital Output True 31 DOUTF− ADC F Digital Output Complement 32 DOUTF+ ADC F Digital Output True 33 DOUTE− ADC E Digital Output Complement 34 DOUTE+ ADC E Digital Output True 35 DCO− Data Clock Digital Output Complement 36 DCO+ Data Clock Digital Output True 37 FCO− Frame Clock Digital Output Complement 38 FCO+ Frame Clock Digital Output True 39 DOUTD− ADC D Digital Output Complement 40 DOUTD+ ADC D Digital Output True 41 DOUTC− ADC C Digital Output Complement 42 DOUTC+ ADC C Digital Output True 43 DOUTB− ADC B Digital Output Complement 44 DOUTB+ ADC B Digital Output True 45 DOUTA− ADC A Digital Output Complement 46 DOUTA+ ADC A Digital Output True 48 STBY Standby Power-Down 49 PDWN Full Power-Down 51 SCLK Serial Clock 52 SDIO Serial Data Input/Output 53 CSB Chip Select Bar 56 LG-A LNA Ground for Channel A 57 LI-A LNA Analog Input for Channel A 58 LOSW-A LNA Analog Output Complement for Channel A 59 LO-A LNA Analog Output for Channel A 62 LG-B LNA Ground for Channel B 63 LI-B LNA Analog Input for Channel B 64 LOSW-B LNA Analog Output Complement for Channel B 65 LO-B LNA Analog Output for Channel B 68 LG-C LNA Ground for Channel C 69 LI-C LNA Analog Input for Channel C 70 LOSW-C LNA Analog Output Complement for Channel C 71 LO-C LNA Analog Output for Channel C 74 LG-D LNA Ground for Channel D 75 LI-D LNA Analog Input for Channel D 76 LOSW-D LNA Analog Output Complement for Channel D 77 LO-D LNA Analog Output for Channel D 78 CWD0− CW Doppler Output Complement for Channel 0 79 CWD0+ CW Doppler Output True for Channel 0 80 CWD1− CW Doppler Output Complement for Channel 1 81 CWD1+ CW Doppler Output True for Channel 1 82 CWD2− CW Doppler Output Complement for Channel 2 83 CWD2+ CW Doppler Output True for Channel 2 85 GAIN− Gain Control Voltage Input Complement

Rev. A | Page 12 of 60

AD9271

www.BDTIC.com/ADI

Pin No. Name Description

86 GAIN+ Gain Control Voltage Input True 87 RBIAS External Resistor to Set the Internal ADC Core Bias Current 88 SENSE Reference Mode Selection 89 VREF Voltage Reference Input/Output 90 REFB Differential Reference (Negative) 91 REFT Differential Reference (Positive) 93 CWD3− CW Doppler Output Complement for Channel 3 94 CWD3+ CW Doppler Output True for Channel 3 95 CWD4− CW Doppler Output Complement for Channel 4 96 CWD4+ CW Doppler Output True for Channel 4 97 CWD5− CW Doppler Output Complement for Channel 5 98 CWD5+ CW Doppler Output True for Channel 5 99 LO-E LNA Analog Output for Channel E 100 LOSW-E LNA Analog Output Complement for Channel E

Rev. A | Page 13 of 60

AD9271

V

Ω

A

S

www.BDTIC.com/ADI

EQUIVALENT CIRCUITS

CM

15kΩ

06304-073

LI-x,

LG-x

AVDD

Figure 5. Equivalent LNA Input Circuit

AVDD

LO-x,

LOSW-x

10Ω

Figure 6. Equivalent LNA Output Circuit

VDD

SDIO

350Ω

30kΩ

06304-008

Figure 8. Equivalent SDIO Input Circuit

DRVDD

V

DOUTx– DOUTx+

V

06304-075

DRGND

Figure 9. Equivalent Di

V

6304-009

gital Output Circuit

CLK+

CLK–

10

10kΩ

10Ω

Figure 7. Equivalent Clock Input Circuit

1.25V

CLK OR PDWN

OR STBY

06304-007

1kΩ

30kΩ

06304-010

Figure 10. Equivalent SCLK Input Circuit

Rev. A | Page 14 of 60

AD9271

A

V

Ω

G

Ω

C

Ω

www.BDTIC.com/ADI

AVDD

RBIAS

100Ω

Figure 11. Equivalent RBIAS Cir

DD

70kΩ

CSB

1kΩ

Figure 12. Equivalent CSB Input Circuit

cuit

AVDD

VREF

6kΩ

6304-014

06304-011

Figure 14. Equivalent VREF Circuit

GAIN+

06304-012

50

06304-074

Figure 15. Equivalent GAIN+ Input Circuit

SENSE

Figure 13. Equivalent SENSE Circuit

1kΩ

AIN–

06304-013

40k

+0.5V

06304-112

Figure 16. Equivalent GAIN− Input Circuit

WDx+,

CWDx–

Figure 17. Equivalent CWDx± Output Circu

10

06304-076

it

Rev. A | Page 15 of 60

AD9271

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

f

= 50 MSPS, fIN = 5 MHz, LPF = 1/3 × f

SAMPLE

2.0

1.5

1.0

, HPF = 700 kHz, LNA gain = 6×.

SAMPLE

25

20

SAMPLE SI ZE = 720 CHANNELS

0.5

0

–0.5

ABSOLUTE ERRO R (dB)

–1.0

–1.5

–2.0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Figure 18. Gain Error vs. V

20

18

16

14

12

10

8

6

PERCENT OF UNITS (%)

4

2

0

–0.8 –0.4 –0.2 0 0.40.2

–1.0 –0.6

Figure 19. Gain Error Histogram with V

+85°C

+25°C

–40°C

V

(V)

GAIN

at Three Temperatures

GAIN

SAMPLE SIZE = 720 CHANNELS

GAIN ERROR (dB)

GAIN

0.6 0.8 1.0

= 0.1 V

06304-019

06304-120

15

10

PERCENT OF UNIT S (%)

5

0

–1.0 –0.6

–0.8 –0.4 –0.2 0 0.40.2

GAIN ERROR (dB)

Figure 21. Gain Error Histogram with V

30

25

20

15

10

PERCENT OF UNI TS (%)

5

0

–1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25

CHANNEL-TO-CHANNEL GAIN MATCHI NG (dB)

Figure 22. Gain Match Histogram for V

0.6 0.8 1.0

= 0.9 V

GAIN

= 0.2 V

GAIN

06304-121

06304-118

16

14

12

10

8

SAMPLE SI ZE = 720 CHANNELS

30

25

20

15

6

PERCENT OF UNI TS (%)

4

2

0

–1.0

–0.9

–0.8

–0.7

–0.6

–0.5

–0.4

0

–0.3

GAIN ERROR (d B)

0.1

–0.2

–0.1

Figure 20. Gain Error Histogram with V

0.2

0.3

0.4

0.5

0.6

0.7

0.8

= 0.5 V

GAIN

06304-116

0.9

1.0

Rev. A | Page 16 of 60

10

PERCENT OF UNI TS (%)

5

0

–1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25

CHANNEL-TO-CHANNEL GAIN MATCHI NG (dB)

Figure 23. Gain Match Histogram for V

GAIN

06304-117

= 0.8 V

AD9271

–

www.BDTIC.com/ADI

2000000

1800000

1600000

1400000

1200000

1000000

800000

NUMBER OF HIT S

600000

400000

200000

0

–5 –4 –3 –2 –1 0 1 2 3 4 5

CODES

Figure 24. Output-Referred Noise Histogram with V

1200000

1000000

800000

600000

NUMBER OF HIT S

400000

200000

0

–5 –4 –3 –2 –1 0 1 2 3 4 5

CODES

Figure 25. Output-Referred Noise Histogram with V

GAIN

= 0.0 V

= 1.0 V

99

–100

–101

–102

–103

–104

–105

–106

OUTPUT-REF ERRED NOISE (dBFS/ Hz)

–107

06304-022

–108

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

LNA GAIN = 6×

V

GAIN

Figure 27. Short-Circuit, Output-Referred Noise vs. V

64.0

63.5

63.0

62.5

62.0

61.5

SNR/SINAD

61.0

60.5

60.0

06304-023

59.5

SNR (dBFS)

SINAD (dBFS)

0 0.1 0.2 0.3 0. 4 0.5 0. 6 0.7 0.8 0. 9 1.0

Figure 28. SNR/SINAD vs. V

V

GAIN

LNA GAIN = 8×

LNA GAIN = 5×

(V)

, AIN = −6.5 dBFS

06304-021

GAIN

06304-020

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

INPUT-REFERRED NOISE (n V/ Hz)

0.5

0

0 5 10 15 20 25

Figure 26. Short-Circuit, Input-R

LNA GAIN = 5×

LNA GAIN = 8×

FREQUENCY (MHz)

LNA GAIN = 6×

06304-025

eferred Noise vs. Frequency

Rev. A | Page 17 of 60

1.70

1.65

1.60

1.55

1.50

INPUT-REFERRED NOISE (nV/ Hz)

1.45

1.40 –40 –20 0 20 40 60 80

TEMPERATURE (° C)

Figure 29. Short-Circuit, Input-Referred Noise vs. Temperature

06304-024

AD9271

–

www.BDTIC.com/ADI

0

–5

–3dB LINE

–10

–15

–20

–25

FUNDAMENTAL (dBFS)

–30

–35

–40

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0

FREQUENCY (MHz )

(1/3) × 40MSPS

(1/3) × 25MSPS

(1/3) × 50MSPS

Figure 30. Antialiasing Filter (AAF) Pass-Band Response, No HPF Applied

300

250

200

150

100

GROUP DELAY (ns)

50

0

0.1 1 10 100

V

= 0.5V

GAIN

V

= 1.0V

GAIN

V

= 0V

GAIN

ANALOG INPUT FREQUENCY (MHz)

Figure 31. Antialiasing Filter (AAF) Group Delay Response

50

–55

= 1V

V

GAIN

–60

–65

–70

–75

THIRD HARMONIC (d BFS)

–80

06304-030

–85

V

GAIN

2 4 6 8 1012141

Figure 33. Third-Order Harmonic Distortion vs. Frequency, AIN = −0.5 dBFS

40

–50

–60

–70

–80

–90

SECOND HARMONIC (dBFS)

–100

06304-033

–110

–40 0–5–10–15–20–25–30–35

V

= 0.5V

GAIN

= 0.2V

f

(MHz)

IN

V

GAIN

ADC OUTPUT LEVEL (dBFS)

= 0V

V

GAIN

V

GAIN

= 1V

= 0.5V

06304-029

6

06304-114

Figure 34. Second-Order Harmonic Distortion vs. ADC Output Level

50

–55

–60

V

= 0.2V

GAIN

–65

V

= 1V

GAIN

–70

–75

SECOND HARMONIC (d BFS)

–80

–85

Figure 32. Second-Order Harmonic Distortion vs. Frequency, AIN = −0.5 dBFS

= 0.5V

V

GAIN

2 4 6 8 10121416

f

(MHz)

IN

06304-028

Rev. A | Page 18 of 60

40

–50

THIRD HARMONIC (dBFS)

–60

–70

–80

–90

–100

–110

–40 0–5–10–15–20–25–30–35

V

GAIN

ADC OUTPUT LEVEL (dBFS)

V

= 0V

GAIN

V

GAIN

= 1V

= 0.5V

Figure 35. Third-Order Harmonic Distortion vs. ADC Output Level

06304-115

AD9271

www.BDTIC.com/ADI

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

02015105

FREQUENCY (MHz)

Figure 38. Typical IMD3 and IMD2 Performance

AIN1 = AIN2 = –7d BFS

f1 = 5MHz

f2 = 6MHz IMD2 = –70.59dBc IMD3 = –64.45dBc

V

=1V

GAIN

06304-108

25

IMD3 (dBFS)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

0

0.2 1.00.90.80.70.60. 50.40.3

AIN1 = AIN2 = –7dBFS

5MHz AND 6MHz

Figure 36. IMD3 vs. V

8MHz AND 10.3MHz

V

(V)

GAIN

2.3MHz AND 3.5MHz

06304-106

IMD3 (dBFS )

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

0

f1 = 5MHz f2 = 6MHz

–60 –20 –15 –10 –5–25–30–35–40–45–50–55

V

GAIN

= 1V

INPUT AMPLITUDE (dBF S)

= 0.5V

V

GAIN

= 0V

06304-107

Figure 37. IMD3 vs. Amplitude

Rev. A | Page 19 of 60

AD9271

www.BDTIC.com/ADI

THEORY OF OPERATION

ULTRASOUND

The primary application for the AD9271 is medical ultrasound. Figure 39 shows a simplified block diagram of an ultrasound

ystem. A critical function of an ultrasound system is the time

s gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution.

Key requirements in an ultrasound signal chain are very low n

oise, active input termination, fast overload recovery, low power, and differential drive to an ADC. Because ultrasound machines use beam-forming techniques requiring large binaryweighted numbers (for example, 32 to 512) of channels, the lowest power at the lowest possible noise is of key importance.

Most modern machines use digital beam forming. In this te

chnique, the signal is converted to digital format immediately

Tx HVAMPs

following the TGC amplifier, and then beam forming is accomplished digitally.

The ADC resolution of 12 bits with up to 50 MSPS sampling sa

tisfies the requirements of both general-purpose and high-

end systems. Power consumption and low cost are of primary importance in

w-end and portable ultrasound machines, and the AD9271 is

lo designed for these criteria.

For additional information regarding ultrasound systems, refer

How Ultrasound System Considerations Influence Front-End

“

to

C

omponent Choice,” A

nalog Dialogue, Volume 36, Number 3, May–July 2002, and “The AD9271—A Revolutionary Solution for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 7, July 2007.

BEAM FORMER

CENTRAL CONT ROL

MULTICHANNELS

Rx BEAM FORMER

(B AND F MODES)

IMAGE AND

MOTION

PROCESSING

(B MODE)

DISPLAY

COLOR

DOPPLER (PW )

PROCESSING

(F MODE)

06304-077

TRANSDUCER

ARRAY

128, 256, ETC.,

ELEMENTS

HV

MUX/

DEMUX

BIDIRECTIO NAL

CABLE

Tx BEAM FO RMER

T/R

SWITCHES

Figure 39. Simplified Ultrasound System Block Diagram

VGALNA

CW

CW (ANALOG)

BEAM FORMER

AUDIO

OUTPUT

AAF

AD9271

PROCESSING

ADC

SPECTRAL

DOPPLER

MODE

Rev. A | Page 20 of 60

AD9271

R

www.BDTIC.com/ADI

RFB1

T/R

SWITCH

CS

CFB

CSH

RFB2

CLG

LO-x

LOSW-x

LI-x

LG-x

LNA

g

m

ATTENUATOR –30dB TO 0dB

TO

SWITCH

ARRAY

+24dB

AAF

12-BIT

PIPELINE

ADC

SERIAL

LVDS

CDWx+

CDWx–

DOUTx–

DOUTx+

TRANSDUCE

Figure 40. Simplified Block Diagram of a Single Channel

INTERPOL ATOR

CHANNEL OVERVIEW

Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides useradjustable input impedance termination. The CW Doppler path includes a transconductance amplifier and a crosspoint switch. The TGC path includes a differential X-AMP® VGA, an antialiasing filter, and an ADC. wi

th external components.

The signal path is fully differential throughout to maximize sig

nal swing and reduce even-order distortion; however, the

LNA is designed to be driven from a single-ended signal source.

Low Noise Amplifier (LNA)

Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input impedance matching.

A simplified schematic of the LNA is shown in Figure 41. LI-x is

pacitively coupled to the source. An on-chip bias generator

ca establishes dc input bias voltages of around 1.4 V and centers the output common-mode levels at 0.9 V (VDD/2). A capacitor, C

, of the same value as the input coupling capacitor, CS, is

LG

connected from the LG-x pin to ground.

T/R

SWITCH

TRANSDUCER

Figure 40 shows a simplified block diagram

VO+

VCM

CS

LI-x

CSH

Figure 41. Simplified LN

CFB

AVDD2

A Schematic

RFB1 RFB2

VCM

VO–

LOSW-x

LO-x

LG-x

CLG

GAIN

GAIN+

GAIN–

AD9271

06304-071

The LNA supports differential output voltages as high as 2 V p-p with positive and negative excursions of ±0.5 V from a commonmode voltage of 0.9 V. The LNA differential gain sets the maximum input signal before saturation. One of three gains is set through the SPI. The corresponding input full scale for the gain settings of 5, 6, or 8 is 400 mV p-p, 333 mV p-p, and 250 mV p-p, respectively. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection.

Low value feedback resistors and the current-driving capability o

f the output stage allow the LNA to achieve a low input-referred noise voltage of 1.2 nV/√Hz. This is achieved with a current consumption of only 16 mA per channel (30 mW). On-chip resistor matching results in precise single-ended gains, which are critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second-harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order distortion.

Active Impedance Matching

The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output externally available. For example, with a fixed gain of 6× (15.6 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This technique is well known and results in the input resistance shown in Equation 1:

R

FB

=

R

IN

1(

where A/2 is t

6304-101

inputs to the LO-x outputs.

(1)

A

)

+

2

he single-ended gain or the gain from the LI-x

Rev. A | Page 21 of 60

AD9271

www.BDTIC.com/ADI

Because the amplifier has a gain of 6× from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the gain of the amplifier, or 9.6 dB (3×). The input resistance is reduced by an internal bias resistor of 15 kΩ in parallel with the source resistance connected to Pin LI-x, with Pin LG-x ac grounded. Equation 2 can be used to calculate the needed R for a desired R

R

IN

For example, to set R

, even for higher values of RIN.

IN

R

FB

= k15||

+

)31(

(2)

Ω

to 200 Ω, the value of RFB is 845 Ω. If the

IN

simplified equation (Equation 2) is used to calculate R

IN

, the

FB

value is 190 Ω, resulting in a gain error less than 0.5 dB. Some factors, such as the presence of a dynamic source resistance, might influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the LNA needs to be considered. The user must determine the level of matching accuracy and adjust R

accordingly.

FB

The bandwidth (BW) of the LNA is about 70 MHz. Ultimately

he BW of the LNA limits the accuracy of the synthesized R

t For R

= RS up to about 200 Ω, the best match is between

IN

.

IN

100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac-coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and R Figure 42 shows R

1k

RS = 500Ω, RFB = 2kΩ

RS = 200Ω, RFB = 800Ω

RS = 100Ω, RFB = 400Ω, CSH = 20pF

100

RS = 50Ω, RFB = 200Ω, CSH = 70pF

INPUT IMPEDANCE (Ω)

10

100k 1M 10M 50M

Figure 42. R

(Effects of R

limit the BW at higher frequencies.

S

vs. frequency for various values of RFB.

IN

FREQUENCY (Hz)

vs. Frequency for Various Values of RFB

IN

and CSH Are Also Shown)

SH

06304-105

Note that at the lowest value, 50 Ω, in Figure 42, RIN peaks at frequencies greater than 10 MHz. This is due to the BW roll-off of the LNA, as mentioned previously.

However, as can be seen for larger R

values, parasitic capacitance

IN

starts rolling off the signal BW before the LNA can produce peaking. C not be used for values of R lists the recommended values for R

is needed in series with RFB because the dc levels at Pin LO-x

C

FB

further degrades the match; therefore, CSH should

SH

that are greater than 100 Ω. Table 7

IN

and CSH in terms of RIN.

FB

and Pin LI-x are unequal.

Table 7. Active Termination External Component Values

Minimum

LNA Gain RIN (Ω) RFB (Ω)

CSH (pF) BW (MHz)

5× 50 175 90 49 6× 50 200 70 59 8× 50 250 50 73 5× 100 350 30 49 6× 100 400 20 59 8× 100 500 10 73 5× 200 700 N/A 49 6× 200 800 N/A 49 8× 200 1000 N/A 49

LNA Noise

The short-circuit noise voltage (input-referred noise) is an important limit on system performance. The short-circuit noise voltage for the LNA is 1.2 nV/√Hz or 1.4 nV/√Hz (at 15.6 dB LNA gain), including the VGA noise. These measurements, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in

re simulations of noise figure vs. R

a

Figure 43. Figure 44 and Figure 45

results using these config-

S

urations and an input-referred noise voltage of 4 nV/√Hz for the VGA. Unterminated (R

= ∞) operation exhibits the lowest

FB

equivalent input noise and noise figure. Figure 45 shows the n

oise figure vs. source resistance rising at low R

—where the

S

LNA voltage noise is large compared with the source noise—and at high R NF is achieved when R

due to the noise contribution from RFB. The lowest

S

matches RIN.

S

UNTERMINATED

R

IN

R

S

+

V

IN

–

RESISTIVE TERMINATION

R

S

+

V

IN

–

ACTIVE IM PEDANCE MATCH

R

S

+

V

IN

–

RIN=

IN

R

FB

1 + A/2

R

S

R

V

OUT

V

OUT

FB

V

OUT

06304-104

Figure 43. Input Configurations

Rev. A | Page 22 of 60

AD9271

V

www.BDTIC.com/ADI

16

14

12

10

8

6

NOISE FI GURE (dB)

4

2

0

10 100 1000

Figure 44. Noise Figure vs. R

Matched, and Unterminated Inputs, V

16

14

12

10

8

6

NOISE FI GURE (dB)

4

2

0

10 100 1000

Figure 45. Noise Figure vs. R

Active Termination Matched Inputs, V

for Resistive Termination, Active Termination

S

UNTERMINATED

RESISTIVE TERMINAT ION

ACTIVE TE RMINATIO N

RS(Ω)

= 1 V, 15.6 dB LNA Gain

Gain

RIN = 50Ω

= 75Ω

R

IN

RIN = 100Ω

RIN = 200Ω

UNTERMINATED

RS(Ω)

for Various Fixed Values of RIN,

S

= 1 V, 15.6 dB LNA Gain

Gain

06304-103

06304-102

The primary purpose of input impedance matching is to improve the transient response of the system. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA’s input voltage noise generator. With active impedance matching, however, the contributions of both are smaller (by a factor of 1/(1 + LNA Gain)) than they would be for resistive termination. Figure 44 shows the relative noise figure performance. In this

raph, the input impedance was swept with R

g

to preserve the

S

match at each point. The noise figures for a source impedance of 50  are 7.1 dB, 4.1 dB, and 2.5 dB for the resistive termination, active termination, and unterminated configurations, respectively. The noise figures for 200  are 4.6 dB, 2.0 dB, and 1.0 dB, respectively.

Figure 45 shows the noise figure as it relates to R

, which is helpful for design purposes.

of R

IN

for various values

S

INPUT OVERDRIVE

Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event.

Input Overload Protection

As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages.

A block diagram of a simplified ultrasound transducer interface

wn in Figure 46. A common transducer element serves the

is sho d

ual functions of transmitting and receiving ultrasound energy. During the transmitting phase, high voltage pulses are applied to the ceramic elements. A typical transmit/receive (T/R) switch can consist of four high voltage diodes in a bridge configuration. Although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and resulting leakage transients imposed on the LI-x inputs can be problematic.

Because ultrasound is a pulse system and time-of-flight is used

determine depth, quick recovery from input overloads is

to essential. Overload can occur in the preamp and the VGA. Immediately following a transmit pulse, the typical VGA gains are low, and the LNA is subject to overload from T/R switch leakage. With increasing gain, the VGA can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone.

Figure 46 illustrates an external overload protection scheme. A p

air of back-to-back Schottky diodes is installed prior to installing the ac-coupling capacitors. Although the BAS40 diodes are shown, any diode is prone to exhibiting some amount of shot noise. Many types of diodes are available for achieving the desired noise performance. The configuration shown in Figure 46 tends to add 2 nV

/√Hz of input-referred noise. Decreasing the 5 kΩ resistor and increasing the 2 kΩ resistor may improve noise contribution, depending on the application. With the diodes shown in Figure 46, c

lamping levels of ±0.5 V or less significantly enhance the

overload performance of the system.

+5

Tx

DRIVER

TRANSDUCER

5kΩ

HV

5kΩ

–5V

Figure 46. Input Overload Protection

BAS40-04

2kΩ

10nF

AD9271

LNA

6304-100

Rev. A | Page 23 of 60

AD9271

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CW DOPPLER OPERATION

Modern ultrasound machines used for medical applications employ a 2 typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When used in multiples, the desired signals from each channel can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), and the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beam-former design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole.

Beam forming, as applied to medical ultrasound, is defined as the phas from a common source but received at different times by a multielement ultrasound transducer. Beam forming has two functions: it imparts directivity to the transducer, enhancing its

N

binary array of receivers for beam forming, with

e alignment and summation of signals that are generated

AD9271

LNA

g

m

gain, and it defines a focal point within the body from which the location of the returning echo is derived.

The AD9271 includes the front-end components needed to

plement analog beam forming for CW Doppler operation.

im These components allow CW channels with similar phases to be coherently combined before phase alignment and down mixing, thus reducing the number of delay lines or adjustable phase shifters/ down mixers ( a

re used, the phase alignment is performed and then the channels

AD8333 or AD8339) required. Next, if delay lines

are coherently summed and down converted by a dynamic range I/Q demodulator. Alternatively, if phase shifters/down mixers, such as the AD8333 and AD8339, are used, phase alignment a

nd downconversion are done before coherently summing all channels into I/Q signals. In either case, the resultant I and Q signals are filtered and sampled by two high resolution ADCs, and the sampled signals are processed to extract the relevant Doppler information.

LNA

8 × CHANNEL

LNA

8 × CHANNEL

LNA

g

m

g

m

g

m

AD9271

g

m

g

m

g

m

g

m

SWITCH

ARRAY

SWITCH

ARRAY

2.5V

600nH

700Ω

AD8333

I

Q

16-BIT

ADC

16-BIT

ADC

06304-096

Figure 47. Typical CW Doppler Sy

stem Using the AD9271 and AD8333 or AD8339

Rev. A | Page 24 of 60

AD9271

V

−+=

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Crosspoint Switch

Each LNA is followed by a transconductance amp for V/I conversion. Currents can be routed to one of six pairs of differential outputs or to 12 single-ended outputs for summing. Each CWD output pin sinks 2.4 mA dc current, and the signal has a full-scale current of ±2 mA for each channel selected by the crosspoint switch. For example, if four channels were to be summed on one CWD output, the output would sink 9.6 mA dc and have a full-scale current output of ±8 mA. The maximum number of channels combined must be considered when setting the load impedance for I/V conversion to ensure that the full-scale swing and common-mode voltage are within the operating limits of the AD9271. When interfacing to the

ode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are

m

AD8339, a common-

desired. This can be accomplished by connecting an inductor between each CWD output and a 2.5 V supply, and then connecting either a single-ended or differential load resistance to the CWD± outputs. The value of resistance should be calculated based on the maximum number of channels that can be combined.

CWD± outputs are required under full-scale swing to be greater tha

n 1.5 V and less than CWVDD (3.3 V supply).

TGC OPERATION

The TGC signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA input to the differential ADC input. A simple exercise in understanding the maximum and minimum gain requirements is shown in Figure 48.

MINIMUM GAIN

LNA FS

(0.333V p-p SE)

87dB

LNA

LNA INPUT-REF ERRED

(5.4µV r ms) @ AAF BW = 1 5MHz

LNA + VGA NOISE = 1.4nV/ Hz

NOISE FLOOR

Figure 48. Gain Requirements of TGC for a 12-Bit, 40 MSPS ADC

ADC FS (2

~5dB M ARGIN

70dB

>8dB MARGIN

ADC NOISE FL OOR (224µV rms)

MAXIMUM GAIN

VGA GAIN RANGE > 30d B MAX CHANNEL GAIN > 40dB

In summary, the maximum gain required is determined by

(ADC Nois

e Floor/VGA Input Noise Floor) + Margin =

20 log(224/5.4) + 8 dB = 40.3 dB

The minimum gain required is determined by

(ADC Input

FS/VGA Input FS) + Margin =

20 log(2/0.333) – 5 dB = 10.6 dB

Therefore, a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth

hould suffice in achieving the dynamic range required for most

s of today’s ultrasound systems.

p-p)

ADC

06304-097

The system gain is distributed as listed in Table 8.

Table 8. Channel Gain Distribution

Section Nominal Gain (dB)

LNA 14/15.6/18 Attenuator 0 to −30 VGA Amp 24 Filter ADC

0 0

Total 8.4 to 38.4/10 to 40/12.4 to 42.4

The linear-in-dB gain (law conformance) range of the TGC path is 30 dB, extending from 10 dB to 40 dB. The slope of the gain control interface is 31.6 dB/V, and the gain control range is 0 V to 1 V as specified in Equation 3. Equation 4 is the expression for channel gain.

(3)

GAIN

where ICP

GAINGAINVV

dB

6.31)(

+=

GAIN

V

T is the intercept point of the TGC gain.

5.0)()()( +−

(4)

ICPTVdBGain

In its default condition, the LNA has a gain of 15.6 dB (6×) and

he VGA gain is −6 dB if the voltage on the GAIN± pins is 0 V.

t This gives rise to a total gain (or ICPT) of 10 dB through the TGC path if the LNA input is unmatched, or of 4 dB if the LNA is matched to 50 Ω (R

= 200 Ω). If the voltage on the GAIN±

FB

pins is 1 V, however, the VGA gain is 24 dB. This gives rise to a total gain of 40 dB through the TGC path if the LNA input is unmatched, or of 34 dB if the LNA input is matched.

Each LNA output is dc-coupled to a VGA input. The VGA consists

f an attenuator with a range of 30 dB followed by an amplifier

o with 24 dB of gain for a net gain range of −6 dB to +24 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion.

At low gains, the VGA should limit the system noise perfor-

nce (SNR); at high gains, the noise is defined by the source and

ma LNA. The maximum voltage swing is bound by the full-scale peak-to-peak ADC input voltage (2 V p-p).

Both the LNA and VGA have limitations within each section of

e TGC path, depending on the voltage applied to the GAIN+ and

th GAIN− pins. The LNA has three limitations, or full-scale settings, depending on the gain selection applied through the SPI interface. When a voltage of 0.2 V or less is applied to the GAIN± pins, the LNA operates near the full-scale input range to maximize the dynamic range of the ADC without clipping the signal. When more than 0.2 V is applied to the GAIN± pins, the input signal to the LNA must be lowered to keep it within the full-scale range of the ADC (see

Figure 49).

Rev. A | Page 25 of 60

AD9271

Ω

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0.450

LNA GAIN = 5x

0.400

0.350

LNA

0.300 GAIN = 6x

0.250

0.200

LNA GAIN = 8x

0.150

INPUT FULL-SCALE (V p-p)

0.100

0.050

0

0 0.1 0.2 0.3 0. 4 0. 5 0. 6 0.7 0.8 0. 9 1. 0

Figure 49. LNA/VGA Full-Scale Limitations

V

GAIN

(V)

06304-110

Variable Gain Amplifier

The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 4 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 50.

GAIN

VIP

VIN

g

m

3dB

GAIN INTERPOLATOR

Figure 50. Simplified VGA S

chematic

POSTAMP

+

–

POSTAMP

06304-078

The input of the VGA is a 12-stage differential resistor ladder with

3.01 dB per tap. The resulting total gain range is 30 dB, which allows for range loss at the endpoints. The effective input resistance per side is 180 Ω nominally for a total differential resistance of 360 Ω. The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA to the VGA without introducing large offsets due to commonmode differences. However, any offset from the LNA will be amplified as the gain is increased, producing an exponentially increasing VGA output offset.

The input stages of the X-AMP are distributed along the ladder, a

nd a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to −30 dB. This circuit technique results in linear-in-dB gain law conformance and low distortion levels—only deviating ±0.5 dB or less from the ideal. The gain

slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply.

The X-AMP inputs are part of a 24 dB gain feedback amplifier tha

t completes the VGA. Its bandwidth is about 70 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting.

Gain Control

The gain control interface, GAIN±, is a differential input. The VGA gain, V

, is shown in Equation 3. V

GAIN

varies the gain

GAIN

of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. The nominal V

range for 30 dB/V is 0 V to 1 V, with the best gain linearity

GAIN

from about 0.1 V to 0.9 V, where the error is typically less than ±0.5 dB. For V the error increases. The value of V

voltages greater than 0.9 V and less than 0.1 V,

GAIN

can exceed the supply

GAIN

voltage by 1 V without gain foldover. Gain control response time is less than 750 ns to settle within 10%

f the final value for a change from minimum to maximum gain.

o There are two ways in which the GAIN+ and GAIN− pins can

e interfaced. Using a single-ended method, a Kelvin type of

b connection to ground can be used as shown in Figure 51. For dr

iving multiple devices, it is preferable to use a differential method, as shown in Figure 52. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accommodate a 1 V full-scale input.

AD9271

GAIN+

GAIN–

GAIN+

0.01µF

GAIN–

Figure 51. Single-Ended GAIN± Pins Configuration

Figure 52. Differential GAIN± Pins Configuration

100Ω

0.01µF

100Ω

0.01µF

±0.25DC AT

0.5V CM

±0.25DC AT

0.5V CM

100Ω

KELVIN

CONNECTION

499

AD8138

499Ω

0.5V CM

523Ω

50Ω

AVDD

26kΩ

10kΩ

0 TO 1V DC

±0.5V DC

50Ω

06304-109

VGA Noise

In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This latter limit is set in accordance with the total noise floor of the ADC.

Output-referred noise as a function of V

is shown in Figure 24

GAIN

and Figure 25 for the short-circuit input conditions. The input

6304-098

Rev. A | Page 26 of 60

AD9271

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noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range.

The output-referred noise is a flat 63 nV/√Hz over most of the

in range, because it is dominated by the fixed output-referred

ga noise of the VGA. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA is miniscule.

At lower gains, the input-referred noise and, therefore, the noise

igure increases as the gain decreases. The instantaneous dynamic

f range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC.

Gain control noise is a concern in very low noise applications.

mal noise in the gain control interface can modulate the

Ther channel gain. The resultant noise is proportional to the output signal level and is usually evident only when a large signal is present. The gain interface includes an on-chip noise filter, which significantly reduces this effect at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN± input. An external RC filter can be used to remove V

GAIN

source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.

Antialiasing Filter

The filter that the signal reaches prior to the ADC is used to reject dc signals and to band limit the signal for antialiasing. Figure 53 shows the architecture of the filter.

4kΩ

1C*

56pF/112p F

*C = 0.5pF T O 3.1pF

2kΩ 2kΩ 2kΩ

6.5C*7.5C*

2kΩ 2kΩ 2kΩ

1C*

4kΩ

Figure 53. Simplified Filter Schematic

06304-099

The filter can be configured for dc coupling or to have a single pole for high-pass filtering at either 700 kHz or 350 kHz (programmed through the SPI). The high-pass pole, however, is not tuned and can vary by ±30%.

A third-order Butterworth low-pass filter is used to reduce

oise bandwidth and provide antialiasing for the ADC. The

n filter uses on-chip tuning to trim the capacitors and in turn set the desired cutoff frequency and reduce variations. The default

−3 dB cutoff is 1/3 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. The cutoff can be set from 8 MHz to 18 MHz.

Tuning is normally off to avoid changing the capacitor settings

uring critical times. The tuning circuit is enabled and disabled

d through the SPI. Initializing the tuning of the filter must be done after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift.

ADC

The AD9271 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline except for the last consists of a low r

esolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The output staging block aligns the data, carries out error corr

ection, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock.

Rev. A | Page 27 of 60

AD9271

V

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CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9271 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias.

Figure 54 shows the preferred method for clocking the AD9271. A lo

w jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50MHz, is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9271 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9271, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance.

3.3V

OUT

EN

VFAC3

Figure 54. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 55. The AD951x family of clock drivers offers excellent ji

tter performance.

3.3V

50Ω

VFAC3

OUT

EN

*

50Ω RESISTOR IS OPTIONAL.

3.3V

*

50Ω

VFAC3

OUT

EN

*

50Ω RESISTOR IS OPTIONAL.

MINI-CIRCUITS

0.1µF

50Ω

*

ADT1-1W T, 1:1Z

100Ω

0.1µF CLK

0.1µF

CLK

PECL DRIVER

0.1µF

XFMR

0.1µF

AD951x FAMILY

SCHOTTKY

DIODES:

HSM2812

240Ω240Ω

Figure 55. Differential PECL Sample Clock

AD951x FAMILY

0.1µF

CLK

LVDS DRIVER

CLK

0.1µF

100Ω

0.1µF

Figure 56. Differential LVDS Sample Clock

0.1µF

100Ω

0.1µF

CLK+

ADC

AD9271

CLK–

CLK+

ADC

AD9271

CLK–

CLK+

ADC

AD9271

CLK–

06304-050

06304-051

06304-052

In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 kΩ resistor (see Figure 57). Although the CLK+ i

nput circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible.

3.3

AD951x FAMILY

CLK

CMOS DRIVER

CLK

0.1µF

OPTIONAL

100Ω

39kΩ

0.1µF

CLK+

ADC

AD9271

CLK–

50Ω

0.1µF

*

VFAC3

OUT

EN

*

50Ω RESISTOR IS OPTIONAL.

Figure 57. Single-Ended 1.8 V CMOS Sample Clock

3.3

AD951x FAMILY

CLK

CMOS DRIVER

CLK

OPTION AL

100Ω

0.1µF

CLK+

ADC

AD9271

CLK–

0.1µF

50Ω

0.1µF

*

OUT

EN

VFAC3

*

50Ω RESISTOR IS OPTIONAL.

Figure 58. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9271 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9271. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the m

ore details on using this feature.

Memory Map section for

The duty cycle stabilizer uses a delay-locked loop (DLL) to

eate the nonsampling edge. As a result, any changes to the

cr sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f due only to aperture jitter (t

SNR Degradation = 20 × log 10[1/2 × π ×

) can be calculated by

J

f

A

× tJ]

A

06304-054

)

06304-053

Rev. A | Page 28 of 60

AD9271

www.BDTIC.com/ADI

In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 59).

The clock input should be treated as a

n analog signal in cases where aperture jitter may affect the dynamic range of the AD9271. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step.

Refer to the AN-501 Application Note

and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs (visit www.analog.com).

130

RMS CLOCK JITT ER REQUIREMENT

120

110

100

90

80

SNR (dB)

70

10 BITS

60

8 BITS

50

40

30

1 10 100 1000

ANALOG INPUT FREQUENCY (M Hz)

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

16 BITS

14 BITS

12 BITS

06304-038

Figure 59. Ideal SNR vs. Input Frequency and Jitter

Power Dissipation and Power-Down Mode

As shown in Figure 61, the power dissipated by the AD9271 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers (Figure 60).

800

I

, 50MSPS SPEED GRADE

AVDD

700

I

, 40MSPS SPEED GRADE

AVDD

600

500

400

300

CURRENT (mA)

200

100

0

Figure 60. Supply Current vs. f

I

, 25MSPS SPEED GRADE

AVDD

I

DRVDD

10 20 30 40 50

SAMPLING FREQUENCY (M SPS)

for fIN = 7.5 MHz

SAMPLE

06304-032

190

180

170

160

150

140

130

POWER/CHANNEL (mW)

120

110

100

0

25MSPS SPEED GRADE

10 20 30 40 50

SAMPLING FREQUENCY (M SPS)

Figure 61. Power per Channel vs. f

50MSPS SPEED GRADE

40MSPS SPEED GRADE

for fIN = 7.5 MHz

SAMPLE

06304-031

By asserting the PDWN pin high, the AD9271 is placed into power-down mode. In this state, the device typically dissipates 2 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9271 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.

By asserting the STBY pin high, the AD9271 is placed into a

andby mode. In this state, the device typically dissipates

st 65 mW. During standby, the entire part is powered down except the internal references. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power the device back up is also greatly reduced. The AD9271 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.

In power-down mode, low power dissipation is achieved by

utting down the reference, reference buffer, PLL, and biasing

sh networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. To restore the device to full operation, approximately 1 ms is required when using the recommended 0.1 µF and 4.7 µF decoupling capacitors on the REFT and REFB pins and the

0.01 µF decoupling capacitors on the GAIN± pins. Most of this time is dependent on the gain decoupling; higher value decoupling capacitors on the GAIN± pins result in longer wake-up times.

There are a number of other power-down options available when usin

g the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times are required. The wake-up time is slightly dependent on gain. To achieve a 1 µs wake-up time when the device is in standby mode, 0.5 V must be applied to the GAIN± pins. See the

n using these features.

o

Memory Map section for more details

Rev. A | Page 29 of 60

AD9271

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Digital Outputs and Timing

The AD9271 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard by using the SDIO pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO Pin section or Tab le 1 5 for more info

rmation.

The LVDS driver current is derived on chip and sets the output

urrent at each output equal to a nominal 3.5 mA. A 100 Ω differ-

c ential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver.

The AD9271 LVDS outputs facilitate interfacing with LVDS

eceivers in custom ASICs and FPGAs that have LVDS capability

r for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO, DCO, and data stream with proper trace length and position can be found in

Figure 62.

Additional SPI options allow the user to further increase the in

ternal termination (and therefore increase the current) of all

eight outputs in order to drive longer trace lengths (see

ven though this produces sharper rise and fall times on the

E

Figure 65).

data edges, is less prone to bit errors, and improves frequency distribution (see Figure 65), the power dissipation of the DRVDD s

upply increases when this option is used.

In cases that require increased driver strength to the DCO± and FCO± o

utputs because of load mismatch, Register 0x15 allows the user to double the drive strength. To do this, first set the appropriate bit in Register 0x05. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 0x15 because these bits take precedence over this feature. See the

or more details.

f

600

EYE: ALL BI TS

400

200

100

0

–100

–200

EYE DIAGRAM V OLTAGE (V)

–400

Memory Map section

ULS: 2398/2398

CH1 500mV/DIV Ω CH2 500mV/DIV Ω CH3 500mV/DIV Ω

Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default)

5.0ns/DI V

06304-034

An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on regular FR-4 material is shown in Figure 63. Figure 64 shows an example of the trace len

gths exceeding 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches.

–600

–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns

25

20

15

10

TIE JITTER HISTOGRAM (Hits)

5

0

–200ps –100ps 0p s 100p s 200ps

Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mod

of Less Than 24 Inches on Standard FR-4

06304-035

e with Trace Lengths

Rev. A | Page 30 of 60

AD9271

www.BDTIC.com/ADI

400

EYE: ALL BI TS

300

200

100

0

–100

–200

EYE DIAGRAM VO LTAGE (V)

–300

–400

–1.5ns –0.5ns–1.0ns 0ns 0.5 ns 1.0ns 1.5n s

25

20

15

10

ULS: 2399/2399

600

EYE: ALL BI TS

400

200

0

–200

EYE DIAGRAM VOLTAGE (V)

–400

–600

–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns

25

20

15

10

ULS: 2396/2396

TIE JITTER HISTOGRAM (Hits)

5

0

–200ps –100ps 0p s 100p s 200ps

Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mod

of Greater Than 24 Inches on Standard FR-4

06304-036

e with Trace Lengths

TIE JIT TER HIST OGRAM (Hi ts)

5

0

–200ps –100ps 0p s 100p s 200ps

Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω

Terminat

ion On and Trace Lengths of Greater Than 24 Inches on Standard FR-4

06304-037

Rev. A | Page 31 of 60

AD9271

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The format of the output data is offset binary by default. An example of the output coding format can be found in Tab le 9 . T

o change the output data format to twos complement, see the

Memory Map section.

Table 9. Digital Output Coding

Code

(VIN+) − (VIN−), Input Span =

2 V p-p (V)

Digital Output Offset Binary (D11 ... D0)

4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 2047 −0.000488 0111 1111 1111 0 −1.00 0000 0000 0000

Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits

Table 10. Flexible Output Test Modes

Output Test Mode Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2

0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 (8 bits)

0010 +Full-scale short 1111 1111 (8 bits)

0011 −Full-scale short 0000 0000 (8 bits)

0100 Checkerboard 1010 1010 (8 bits)

0101 PN sequence long 0110 0111 One-/zero-word toggle 1111 1111 (8 bits)

1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No 1001 1-/0-bit toggle 1010 1010 (8 bits)

1010 1× sync 0000 1111 (8 bits)

1011 One bit high 1000 0000 (8 bits)

1100 Mixed bit frequency 1010 0011 (8 bits)

1

All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.

PN sequence short

1

10 0000 0000 (10 bits) 1000 0000 0000 (12 bits) 10 0000 0000 0000 (14 bits)

11 1111 1111 (10 bits)

1111 1111 1111 (12 bits) 11 1111 1111 1111 (14 bits)

00 0000 0000 (10 bits)

0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits)

10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits)

N/A N/A Yes N/A N/A Yes

11 1111 1111 (10 bits)

1111 1111 1111 (12 bits)

11 1111 1111 1111 (14 bits)

10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits)

00 0001 1111 (10 bits)

0000 0011 1111 (12 bits)

00 0000 0111 1111 (14 bits)

10 0000 0000 (10 bits)

1000 0000 0000 (12 bits)

10 0000 0000 0000 (14 bits)

10 0110 0011 (10 bits) 1010 0011 0011 (12 bits) 10 1000 0110 0111 (14 bits)

times the sample clock rate, with a maximum of 600 Mbps (12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application. See the o

n enabling this feature.

Memory Map section for details

Two output clocks are provided to assist in capturing data from

e AD9271. DCO± is used to clock the output data and is equal

th to six times the sampling clock rate. Data is clocked out of the AD9271 and must be captured on the rising and falling edges of the DCO± that supports double data rate (DDR) capturing. The frame clock output (FCO±) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information.

Subject to Data Format Select

Same Yes

0101 0101 (8 bits) 01 0101 0101 (10 bits) 0101 0101 0101 (12 bits) 01 0101 0101 0101 (14 bits)

0000 0000 (8 bits) 00 0000 0000 (10 bits) 0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits)

N/A No

No

Rev. A | Page 32 of 60

AD9271

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When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in Figure 2, is 90° relative to

the output data edge.

An 8-, 10-, and 14-bit serial stream can also be initiated from

he SPI. This allows the user to implement different serial streams

t to test the device’s compatibility with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. When using the 14-bit option, the data stream stuffs two 0s at the end of the normal 14-bit serial data.

When using the SPI, all of the data o from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in

Figure 2, the MSB is represented first in the data output serial

tream. However, this can be inverted so that the LSB is repre-

s sented first in the data output serial stream (see Figure 3).

There are 12 digital output test pattern options available that

n be initiated through the SPI. This feature is useful when

ca validating receiver capture and timing. Refer to Tab le 1 0 for the output

bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. It should be noted that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.

The PN sequence short pattern produces a pseudorandom

sequence that repeats itself every 2

bit description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value is a specific value instead of all 1s (see Table 11 for the initial values).

The PN sequence long pattern produces a pseudorandom bit s

equence that repeats itself every 2 A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s and the AD9271 inverts the bit stream with relation to the ITU standard (see Table 1 1 for the initial values).

Table 11. PN Sequence

Initial

Sequence

PN Sequence Short 0x0df 0xdf9, 0x353, 0x301 PN Sequence Long 0x29b80a 0x591, 0xfd7, 0xa3

Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI.

Va

lue

utputs can also be inverted

9

− 1 bits, or 511 bits. A

23

− 1 bits, or 8,388,607 bits.

First Three Output Samples (MSB First)

Rev. A | Page 33 of 60

SDIO Pin

This pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a

3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current.

SCLK Pin

This pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant.

CSB Pin

This pin is required to operate the SPI port interface. It has an internal 70 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor that is nominally equal to 10.0 kΩ between the RBIAS pin and ground. Using a resistor of another value degrades the performance of the device. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance.

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the AD9271. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, full-scale ranges below 2.0 V p-p are not supported by this device.

When applying the decoupling capacitors to the VREF, REFT, and

REFB pins, use ceramic low ESR capacitors. These capacitors should be close to reference pins and on the same layer of the PCB as the AD9271. The recommended capacitor values and configurations for the AD9271 reference pin can be found in Figure 66.

Table 12. Reference Settings

Resulting Selected Mode

External

Reference

Internal,

2 V p-p FSR

SENSE Voltage

AVDD N/A

AGND to 0.2 V 1.0 2.0

Resulting VREF (V)

D

Span (V p-p)

2 × external

reference

ifferential

AD9271

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Internal Reference Operation

A comparator within the AD9271 detects the potential at the

ENSE pin and configures the reference. If SENSE is grounded,

S the reference amplifier switch is connected to the internal resistor divider (see Figure 66), setting VREF to 1 V.

The REFT and REFB pins establish their input span of the ADC c

ore from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration.

VIN+

VREF

1µF 0.1µF

SENSE

VIN–

SELECT

LOGIC

ADC

CORE

0.5V

REFT

0.1µF

0.1µF 4.7µF

REFB

0.1µF

+

External Reference Operation

The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 69 shows the typical drift characteristics of the i

nternal reference in 1 V mode.

When the SENSE pin is tied to AVDD, the internal reference is

abled, allowing the use of an external reference. The external

dis reference is loaded with an equivalent 6 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal voltage of 1.0 V.

5

0

–5

–10

VREF ERROR (%)

–15

–20

EXTERNAL

REFERENCE

VREF

1µF* 0.1µF*

SENSE

*OPTIONAL.

Figure 66. Internal Reference Configuration

VIN+

VIN–

ADC

CORE

0.5V

AVD D

SELECT

LOGIC

Figure 67. External Reference Operation

REFT

0.1µF

0.1µF 4.7µF

REFB

0.1µF

06304-064

–25

033.02.52.01.51.00.5

CURRENT LOAD (mA)

06304-017

.5

Figure 68. VREF Accuracy vs. Load, AD9271-50

0.02

0

–0.02

VREF ERROR (%)

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

–0.16

–0.18

–0.20

–40 806040200–20

TEMPERATURE (° C)

Figure 69. Typical VREF Drift, AD9271-50

06304-015

+

6304-065

Rev. A | Page 34 of 60

AD9271

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SERIAL PORT INTERFACE (SPI)

The AD9271 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the

Memory Map section. Detailed operational information

n be found in the Analog Devices, Inc., AN-877 Application

ca Note, Interfacing to High Speed ADCs via SPI.

Three pins define the serial port interface, or SPI: the SCLK,

DIO, and CSB pins. The SCLK (serial clock) is used to

S synchronize the read and write data presented to the device. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the device’s internal memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 13).

Table 13. Serial Port Pins

Pin Function

SCLK

SDIO

CSB

Serial Clock. The serial shift clock input. SCLK is u synchronize serial interface reads and writes.

Serial Data Input/Output. A dual-purpose pin. The typical

ole for this pin is as an input or output, depending on

r the instruction sent and the relative position in the timing frame.

Chip Select Bar (Active Low). This control gates the read

ite cycles.

and wr

sed to

The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 71 and Tab le 1 4.

In normal operation, CSB is used to si

gnal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructtions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction.

In addition to the operation modes, the S to operate in different manners. For example, CSB can be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CSB line, streaming mode can be entered but not exited.

In addition to word length, the instruction phase determines if

ial frame is a read or write operation, allowing the serial

the ser port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.

Data can be sent in MSB- or LSB-first mo is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Tabl e 13 constitute the physical interface between the user’s programming device and the serial port of the AD9271. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.

In cases where multiple SDIO pins share a common connection,

re should be taken to ensure that proper V

ca Figure 70 shows the number of SDIO pins that can be connected t

ogether, assuming the same load as the AD9271 and the

resulting V

(V)

OH

V

level.

OH

1.800

1.795

1.790

1.785

1.780

1.775

1.770

1.765

1.760

1.755

1.750

1.745

1.740

1.735

1.730

1.725

1.720

1.715 0302010 40 50 60 70 80 90 100

NUMBER OF SDIO PINS CONNECTED TOGETHER

Figure 70. SDIO Pin Loading

PI port can be configured

de. MSB-first mode

levels are met.

OH

06304-113

Rev. A | Page 35 of 60

AD9271

www.BDTIC.com/ADI

This interface is flexible enough to be controlled by either serial P

ROMs or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the device (see the AN-812 Application Note).

t

HI

t

CLK

t

LO

Figure 71. Serial Tim

CSB

SCLK

SDIO

DON’T CARE

t

DS

t

S

R/W W1 W0 A12 A11 A10 A9 A8 A7

t

DH

Table 14. Serial Timing Definitions

Parameter Minimum Timing (ns) Description

t

DS

t

DH

t

CLK

t

S

t

H

t

HI

t

LO

t

EN_SDIO

5 Setup time between the data and the rising edge of SCLK 2 Hold time between the data and the rising edge of SCLK 40 Period of the clock 5 Setup time between CSB and SCLK 2 Hold time between CSB and SCLK 16 Minimum period that SCLK should be in a logic high state 16 Minimum period that SCLK should be in a logic low state 10

Minimum time for the SDIO pin to switch from an input t falling edge (not shown in Figure 71)

t

DIS_SDIO

10

Minimum time for the SDIO pin to switch from an output t rising edge (not shown in Figure 71)

ing Details

D5 D4 D3 D2 D1 D0

o an output relative to the SCLK

o an input relative to the SCLK

t

H

DON’T CARE

DON’T CAREDON’T CARE

06304-068

Rev. A | Page 36 of 60

AD9271

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MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04, Address 0x05, and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x2D).

The leftmost column of the memory map indicates the register address

number; the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing 0 to Bit 0 of this address followed by writing 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. All registers, except Register 0x00, Register 0x02,

Register 0x04, Register 0x05, and Register 0xFF, are buffered with a master-slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN877 Application Note, Interfacing to High Speed ADCs via SPI.

RESERVED LOCATIONS

Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have 0 written into their registers during power-up.

DEFAULT VALUES

After a reset, critical registers are automatically loaded with default values. These values are indicated in Tabl e 15, where an X r

efers to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”

Rev. A | Page 37 of 60

AD9271

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Bit 7 (MSB)

1

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

1 = on 0 = off (default)

Soft

set

re 1 = on 0 = off (default)

(identify device variants of Chip ID) 00 = 50 MSPS (default) 01

= 40 MSPS

10 = 25 MSPS

Channel DCO± 1 = on 0 = off (default)

1 1 Soft

(AD9271 = 0x13), (default)

X X X X 0x00 Child ID used

Channel H 1 =

on (default) 0 = off

on

Data Channel D

on

1 = (default) 0 = off

bypass 1 = on

off

0 = (default)

Clock Channel FCO± 1 = 0 = off (default)

set

re 1 = on 0 = off (default)

Data Channel G 1 =

on (default) 0 = off

Data Channel C

on

1 = (default) 0 = off

Internal power-down mode 000 = 001 = full power-down 010 = standby 011 = reset

100 = CW mode (TGC PDWN)

LSB first

on

1 = 0 = off (default)

Data Channel F

on

1 = (default) 0 = off

Data Channel B

on

1 = (default) 0 = off

chip run (default)

Bit 0 (LSB)

0 0x18 The nibbles

Data Channel E

on

1 = (default) 0 = off

Data Channel A

on

1 = (default) 0 = off

transfer 1 = on 0 = off (default)

stabilizer 1 = on (default) 0 = off

Default Value

Read only

0x0F Bits are set to

0x00 Synchronously

0x00 Determines

0x01 Turns the

Notes/ Comments

d be

shoul mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode.

Default is unique chip ID, different for each device. This is a readonly register.

to diff

erentiate

graded devices.

ne

determi which on-chip device receives the next write command.

ne

determi which on-chip device receives the next write command.

ers data

transf from the master shift register to the slave.

various gen modes of chip operation.

internal dut cycle stabilizer on and off.

eric

y

Table 15. Memory Map Register

Addr. (Hex)

Chip Configuration Registers

00 chip_port_config 0 LSB first

01 chip_id Chip ID Bits [7:0]

02 chip_grade X X Child ID [5:4]

Device Index and Transfer Registers

04 device_index_2 X X X X Data

05 device_index_1 X X Clock

FF device_update X X X X X X X SW

ADC Functions Registers

08 modes X X X X LNA

09 clock X X X X X X X Duty cycle

Register Name

Rev. A | Page 38 of 60

AD9271

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Addr. (Hex)

0D test_io User test mode

0F flex_channel_input Filter cutoff frequency control

10 flex_offset X X 6-bit LNA offset adjustment

11 flex_gain X X X X X X LNA gain

14 output_mode X 0 = LVDS

15 output_adjust X X Output driver

16 output_phase X X X X 0011 = output clock phase adjust

Register Name

Bit 7 (MSB)

00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once

0000 = 1.3 × 1/3 × f 0001 = 1.2 × 1/3 × f 0010 = 1.1 × 1/3 × f 0011 = 1.0 × 1/3 × f 0100 = 0.9 × 1/3 × f 0101 = 0.8 × 1/3 × f 0110 = 0.7 × 1/3 × f

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

SAMPLE

ANSI-644 (default) 1 = LVDS low power, (IEEE

1596.3 similar)

on

Reset PN

t

shor gen 1 = on 0 = off (default)

Output test mode—see 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode)

X X X X 0x30 Antialiasing

invert

on

1 = 0 = off (default)

X X X DCO±

(0000 through 1010) (Default: 180° relative to data edge) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge 0100 = 240° relative to data edge 0101 = 300° relative to data edge 0110 = 360° relative to data edge 0111 = 420° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge

Reset PN long gen 1 = 0 = off (default)

011001 = 50 MSPS speed grade 011010 = 40 MSPS speed grade 011111 = 25 MSPS speed grade

X X X Output

termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω

Bit 0 (LSB)

Table 10

00 = 5× 01 = 6× 10 = 8×

00 = offset binary (default)

twos

01 = complement

and FCO± 2× d strength 1 = on 0 = off (default)

Default Value

0x00 When this

0x20 LNA force

0x01 LNA gain

0x00 Configures the

0x00 Determines

rive

0x03 On devices that

Notes/ Comments

r

egister is set, the test data is placed on the output pins in place of normal data. (Local, expect for PN sequence.)

filter cutoff (global).

et

offs correction (local).

adjustment

al).

(glob

nd

outputs a the format of the data.

LVDS or oth output prop erties. Primarily functions to set the LVDS span and commonmode levels in place of an external resistor.

utilize global clock di determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected.

er

vide,

Rev. A | Page 39 of 60

AD9271

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Addr. (Hex)

19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined

1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined

21 serial_control LSB first

22 serial_ch_stat X X X X X X Channel

2B flex_filter X Enable

2C analog_input X X X X X X X LOSW-x

2D cross_point_switch X X X Crosspoint switch enable

1

Register Name

X = an undefined feature

Bit 7 (MSB)

1 = on 0 = off (default)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

X X X <10

automatic low-pass tuning

1 = on

off

0 = (default)

X X X X High-pass filter cutoff

0 0000 = CWD0± (differential) 0 0001 = CWD1± (differential) 0 0010 = CWD2± (differential) 0 0011 = CWD3± (differential) 0 0100 = CWD4± (differential) 0 0101 = CWD5± (differential) 0 0111 = power down CW channel 1 0000 = CWD0+ (single ended) 1 0001 = CWD1+ (single ended) 1 0010 = CWD2+ (single ended) 1 0011 = CWD3+ (single ended) 1 0100 = CWD4+ (single ended) 1 0101 = CWD5+ (single ended) 1 0111 = power down CW channel 1 1000 = CWD0− (single ended) 1 1001 = CWD1− (single ended) 1 1010 = CWD2− (single ended) 1 1011 = CWD3− (single ended) 1 1100 = CWD4− (single ended) 1 1101 = CWD5− (single ended) 1 1111 = power down CW channel

MSPS, low encode rate mode 1 = on 0 = off (default)

000 = 12 bits (default, normal bit

eam)

str 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits

output reset 1 = on 0 = off (default)

00 = dc (default) 01 = 700 kHz 10 = 350 kHz

Bit 0 (LSB)

Channel

-

power down 1 = on 0 = off (default)

1 = on 0 =

off

(default)

Default Value

0x00 Serial stream

0x00 Used to power

0x00 Filter cutoff

0x00 LNA active

0x07 Crosspoint

Notes/ Comments

pattern, 1 LSB (global).

pattern, 1 MSB (global).

pattern, 2 LSB (global).

pattern, 2 MSB (global).

ol. Default

contr causes MSB first and the native bit stream (global).

own individ

d ual sections of a converter (local).

al).

(glob

on/

terminati input impedance (global).

ch

swit enable (local).

Rev. A | Page 40 of 60

AD9271

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9271 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9271, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). The AD9271 also requires a

3.3 V supply (CWVDD) for the crosspoint section. If only one

1.8 V supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the parts with minimal trace lengths.

A single PC board ground plane should be sufficient when usin

g the AD9271. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance can be easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the device be connected to the analog ground (AGND) to achieve the best electrical and thermal performance of the AD9271. An exposed continuous copper plane on the PCB should mate to the AD9271 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy.

To maximize the coverage and adhesion between the device and

, partition the continuous copper pad by overlaying a silk-

PCB screen or solder mask to divide it into several uniform sections. This ensures several tie points between the two during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the AD9271 and PCB. See

or a PCB layout example. For more detailed information on

f packaging and for more PCB layout examples, see the AN-772 Application Note.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 72

06304-069

Figure 72. Typical PCB Layout

Rev. A | Page 41 of 60

AD9271

www.BDTIC.com/ADI

EVALUATION BOARD

The AD9271 evaluation board provides all the support circuitry required to operate the AD9271 in its various modes and configurations. The LNA is driven differentially through a transformer. Figure 73 shows the typical bench characterization setup used t

o evaluate the ac performance of the AD9271. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance.

See the Quick Start Procedure section to get started and Figure 75 to

Figure 86 for the complete schematics and layout diagrams

th

at demonstrate the routing and grounding techniques that

should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board.

When operating the evaluation board in a nondefault condition, L702 t

o L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital domains. To operate the evaluation board using the

WALL OU TL ET 100V TO 240V AC 47Hz TO 63Hz

6V DC

SWITCHING

ANALOG INPUT

ROHDE & SCHWARZ,

SMA, 2V p-p SIGNAL SYNTHESIZER

ROHDE & SCHWARZ,

FS5A20 SPECTRUM ANALYZER

POWER SUPPLY

2A MAX

BAND-PASS

FILTER

CW OUTPUT

VFAC3

OSCILLATOR

1.8V

GND

CLK

Figure 73. Evaluation Board Connection

1.8V

–+–+

AVD D_DU T

AD9271

EVALUATION BOARD

GND

SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or AVDD_3.3 V, should have a 1 A current capability.

To bias the crosspoint switch circuitry or CW section, separate

nd −5 V supplies are required at P511. These should each

+5 V a have 1 A current capability. This section cannot be biased from a 6 V, 2 A wall supply. Separate supplies are required at P511.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644B signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the specifications tables. The evaluation board is set up to be clocked from the crystal oscillator, OSC401. If a different or external clock source is desired, follow the instructions for CLOCK outlined in the

Default Operation and Jumper Selection Settings section.

ypically, most Analog Devices evaluation boards can accept

T ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Analog Devices uses TTE and K&L Microwave, Inc., band-pass filters. The filter should be connected directly to the evaluation board.

OUTPUT SIGNALS

The default setup uses the FIFO5 high speed, dual-channel FIFO data capture board (HSC-ADC-EVALCZ). Two of the eight channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO.

3.3V

–+

GND

DRVDD_DUT

CH A TO CH H

AVDD_3.3V

12-BIT

SERIAL

LVDS

SPI

–+

HSC-ADC-EVALCZ

FPGA

SPI

PS

GND

VREG

FIFO DAT A

CAPTURE

BOARD

USB

CONNECTOR

(DATA/SPI)

PC

RUNNING

ADC

ANALYZER

OR

VISUAL

ANALOG

USER

SOFTWARE

06304-070

Rev. A | Page 42 of 60

AD9271

www.BDTIC.com/ADI

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

The following is a list of the default and optional settings or modes allowed on the AD9271 Rev. B evaluation board.

• Power: Connect the switching power supply that is

supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.

• AIN: The evaluation board is set up for a transformer-

coupled analog input with an optimum 50 Ω impedance match of 18 MHz of bandwidth. For a different bandwidth response, use the antialiasing filter settings.

• VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Populate R311 and R315 with 0 Ω resistors and remove C307. Proper use of the VREF options is noted in the

Voltage Reference section. Note that ADC full-scale

nges less than 2.0 V p-p are not supported by this device.

ra

• RBIAS: RBIAS has a default setting of 10 kΩ (R301) to

ground and is used to set the ADC core bias current. However, note that using other than a 10 kΩ resistor for RBIAS may degrade the performance of the device, depending on the resistor chosen.

• Clock: The default clock input circuitry is derived from a

simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.

The evaluation board is already set up to be clocked from the cr

ystal oscillator, OSC401. This oscillator is a low phase noise oscillator from Valpey Fisher (VFAC3-BHL-50MHz). If a different clock source is desired, remove R403, set Jumper J401 to disable the oscillator from running, and connect the external clock source to the SMA connector, P401.

A differential LVPECL clock driver can also be used to

lock the ADC input using the

c

nd R407 with 0 Ω resistors and remove R415 and

R406 a R416 to disconnect the default clock path inputs. In addition, populate C405 and C406 with a 0.1 F capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set t

o a default mode of operation. Consult the AD9515 data

sheet for more information about these and other options.

AD9515 (U401). Populate

• PDWN: To enable the power-down feature, short P303 to

the on position (AVDD) on the PDWN pin.

• STBY: To enable the standby feature, short P302 to the on

position (AVDD) on the STBY pin.

• GAIN+, GAIN−: To change the VGA attenuation, drive the

GAIN+ pin from 0 V to 1 V on J301. This changes the VGA gain from 0 dB to 30 dB. This feature can also be driven from the R335 and R336 on-board resistive divider by installing a 0 Ω resistor in R337.

• Non-SPI Mode: For users who wish to operate the DUT

without using the SPI, remove the jumpers on J501. This disconnects the CSB, SCLK, and SDIO pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. Note that the device will only work in its default condition.

• CWD+, CWD−: To view the CWD2+/CWD2− and CWD3+/

CWD3− outputs, jumper together the appropriate outputs on P403. All outputs are summed together on IOP and ION buses, fed to a 1:4 impedance ratio transformer, and buffered so that the user can view the output on a spectrum analyzer. This can be configured to be viewed in singleended mode (default) or in differential mode. To set the voltage for the appropriate number of channels to be summed, change the value of R447 and R448 on the primary transformer (T402).

Upon shipment, the CWD0+/CWD0−, CWD1+/CWD1−, CWD4+ properly biased and ready to use with the AD8339 quad I/Q dem evaluation board simply snaps into place on the AD8339 evaluation board (AD8339-EVALZ). Remove the jumpers connected to P3A and P4A on the AD8339 evaluation board, and snap the standoffs labeled MH502, MH504, and MH505 that are provided with the AD9271 into the AD8339 evaluation board standoff holes in the center of the board. The standoffs automatically lock into place and create a direct connection between the AD9271 CWDx± outputs and the AD8339 inputs.

• DOUTx+, DOUTx−: If an alternative data capture method

to the setup described in Figure 80 is used, optional receiver t high speed backplane connector.

/CWD4−, and CWD5+/CWD5− outputs are

odulator and phase shifter. The AD9271

erminations, R601 to R610, can be installed next to the

Rev. A | Page 43 of 60

AD9271

www.BDTIC.com/ADI

In SPI Controller, select Controller Dialog from the

QUICK START PROCEDURE

The following is a list of the default and optional settings when using the AD9271 either on the evaluation board or at the system level design.

If an evaluation board is not being used, follow only the SPI

ntroller steps.

co When using the AD9271 evaluation board,

1.

Open ADC Analyzer on a PC, click Configuration, and

select the appropriate product configuration file. If the correct product configuration file is not available,

hoose a similar product configuration file or click

c and create a new one. See the ADC Analyzer User Manual located at www.analog.com/FIFO.

From the Config menu, choose Channel Select. To evaluate

2. Channel A on the ADC evaluation board, ensure that only the Channel B checkbox in ADC Analyzer is selected.

Channel A through Channel D cor

respond to Channel B in

ADC Analyzer. Channel E through Channel H correspond to Channel A in

C Analyzer.

AD

Click SPI in ADC Analyzer to open the SPI controller

3. software. If prompted for a configuration file, select the appropriate one. If not, look at the title bar of the window to see which configuration is loaded. If necessary, choose

Cfg Open from the File menu and select the appropriate one.

Note that the

CHIP ID(1) field may be filled in regardless of

whether the correct SPI controller configuration file is loaded.

When using the AD9271 evaluation board or system level design,

1.

Click New DUT ( ) in the SPI Controller software.

2.

In the Global tab of SPI Controller, find the CHIP

GRADE(2)

box and use the drop-down menu to select

the correct speed grade.

Cancel

4.

Config menu. In the PROGRAM CONTROL box, ensure

that

Enable Auto Channel Update is selected and click OK.

In the Global tab of SPI Controller, find the DEVICE

5.

INDEX(4/5)

box. In the ADC column, click S so that the

adjustment in the next step applies to all channels.

In the ADC A tab of SPI Controller, find the OFFSET(10)

6. box and use the drop-down menu labeled

Offset Adj to select

the correct LNA offset correction: 25 decimal for the 50 MSPS speed grade, 26 decimal for the 40 MSPS speed grade, or 31 decimal for the 25 MSPS speed grade.

Click FFT ( ) in Visual Analog.

7.

0

–10

–20

–30

–40

–50

–60

–70

–80

AMPLITUDE (dBFS)

–90

–100

–110

–120

–130

02

5101520

FREQUENCY (M Hz)

Figure 74. Typical FFT, AD9271-50

f

= 3.5MHz @ –1dBFS

IN

LNA = 6× V

= 1V

GAIN

FILTER TUNED HPF = 700kHz

8. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the reading in the left panel of the

ADC Analyzer FFT

Fund:

window.) If the GAIN± pins voltage is low (near 0 V), it may not be possible to reach full scale without distortion. Use a higher gain setting or a lower input level to avoid distortion.

06304-119

5

In the ADCGlobal 0 tab of SPI Controller, find the

3.

9.

Right-click the FFT plot and select Comments. Use this

HIGHPASS(2B) box and select the Manual Tune box to

calibrate the antialiasing filter.

Rev. A | Page 44 of 60

box to record information such as the serial number of the board, the channel, the input and clock frequencies, the GAIN± pins voltage, and the date. Press the

SCREEN

key and save the FFT screenshot if desired.

PRINT

AD9271

www.BDTIC.com/ADI

SCHEMATICS AND ARTWORK

LO- C

LOSW C

LIC

LGC

LO- D

LID

LOSW D

06304-086

R125

200

R126

1K-DN P

C111

0.1UF

C123

0.1UF

0

R163

R160

0

R120

CTC

R156

41

ADT1-1WT +

CTC

0

R103

R119

J103

0.1UF-DNP22PF

C109

0.1UF

49.9

R152

0-DNP

6

T103

AVDD

3

52

GND C

49.9-DNP

R139

0-DNP

C112

0

R124 R127

C110

0

10K-DN P

R145

R146

10K-DN P

C119

0.1UF-DNP

R121

0

0-DNP

R113R150

R134

R135

1K-DN P

C115

AIN CHD

200

0.1UF

C124

R164

R123

C113

0.1UF

0

49.9

R161

0

CTD

R157

0-DNP

25

ADT1-1WT +

14

CTD

0

R129

R128

49.9-DNP

J104

0-DNP

R136R133

C116

0

C114

22PF 0.1UF-DNP

0.1UF

0

R153

6

10K-DN P

R148

R147

10K-DN P

T10 4

AVDD

3

GNDD

R140

0

C120

0.1UF-DNP

0

R131

R122

0-DNP

LIA

LOSW A

LO- A

200

R108

R107

1K-DN P

C103

0.1UF

C121

R132

R105

ADT1-1WT +

R102

J101

AIN CHA AIN CHC

LGA

0.1UF-DNP

22PF

C101

0.1UF

0

14

0

0.1UF

49.9

R158

CTA

R154

0

R130

0-DNP

6

25

T101

AVDD

3

CTA

GND A

R101

49.9-DNP

R149

0

LO- B

LOSW B

LIB

0-DNP

R109R106

C102 C1 04

0

10K-DN P

R142

R141

10K-DN P

C117

0.1UF-DNP

0

R137

0-DNP

R116

200

R117

1K-DN P

C107

0.1UF

C122

R162

R114

ADT1-1WT +

R111

J102

AIN CHB

LGB LGD

C105

0.1UF

0

R159

49.9

0

CTB

R155

0-DNP

41

6

T102

3

52

CTB

0

GNDB

49.9-DNP

R110

C108

0-DNP

C106

22PF 0.1UF-DNP

0.1UF

R151

AVDD

R138

0

R115 R1 18

0

10K-DN P

R143

R144

10K-DN P

C118

0.1UF-DNP

R112

0

R104

0-DNP

Figure 75. Evaluation Board Schematic, DUT Analog Input Circuits

Rev. A | Page 45 of 60

AD9271

www.BDTIC.com/ADI

LO- G

LOSW G

LIG

R225

200

R226

1K-DN P

C211

0.1UF

C223

R263

R220

6

T20 3

3

R213

J20 3

AIN CHG

C209

0.1UF

0

R260

49.9

0

CTG

R256

0-DN P

25

CTG

0

49.9-DNP

R219

LGG

0.1UF-DN P

22PF

0.1UF

R251

AVDD

ADT1-1WT +

0-DN P

C212

0

R224 R227

C210

0

10K-DN P

R245

14

GNDG

R237

0

R239

R231

0-DN P

LIH

LOSW H

LO- H

200

R235

R234

1K-DN P

C215

0.1UF

C22 4

0.1UF

0

R264

R261

0

R223

CTH

R257

R246

10K-DN P

C219

0.1UF-DN P

6

T204

3

0

R229

J204

AIN CHH

52

CTH

0.1UF-DN P22PF

C21 3

0.1UF

49.9

R252

0-DN P

41

AVDD

ADT1-1WT +

GNDH

R240

49.9-DNP

0-DN P

R236R23 3

C216

0

C214

0

R247

10K-DN P

0

R253

0

0-DN P

R241

06304-087

10K-DN P

R248

C220

0.1UF-DN P

LIE

LOSW E

LO- E

R207

200

R208

1K-DN P

C203

0.1UF

C221

R232

R205

6

T201

3

R202

J201

AIN CHE

LGE

22P F 0.1U F-DN P

C201

0.1UF

0

R254

0.1UF

49.9

R258

CTE

R249

0-DN P

41

AVDD

ADT1-1WT +

52

CTE

0

GND E

R201

R203

49.9-DNP

LO- F

LOSW F

LIF

0-DN P

R209R20 6

C20 4

0

C202

0

10K-DN P

R243

R242

10K-DN P

R216

200

R217

1K-DN P

C207

0.1UF

C222

R262

R214

6

T20 2

3

C217

0

0.1UF-DN P

0

R221

R212

0-DN P

R211

J202

AIN CHF

C205

0.1UF

0

R259

49.9

0

CTF

R255

0-DN P

25

CTF

0

49.9-DNP

R210 R228

LGF LGH

0.1UF-DN P

R215 R2 18

22PF

C206 C208

0.1UF

R250

0

10K-DN P

R204

AVDD

ADT1-1WT +

14

GNDF

R230

0

R238

R222

0-DN P

0

R244

10K-DN P

C218

0.1UF-DN P

0

0-DN P

Figure 76. Evaluation Board Schematic, DUT Analog Input Circuits (Continued)

Rev. A | Page 46 of 60

AD9271

0

www.BDTIC.com/ADI

AVDD

VSENSE_DUT

SCLK_DUT

51

SCLK

2

1

AVDD

DRVDD_DUT

CHA

CHB

CHC

CHD

FCO

DCO

CHE

CHF

CHG

CHH

DRVDD_DUT

P303

1

2

P302

AVDD

50

PDWN

49

STDBY

48

DRVDD

47

DOUTA+

46

DOU TA-

45

DOUTB+

44

DOUTB-

43

42

DOUTC-

41

DOUTD+

40

DOUTD-

39

FCO+

38

FCO-

37

DCO+

36

DCO-

35

DOUTE+

34

DOUTE-

33

DOU TF+

32

DOU TF-

31

DOUTG+

30

DOUTG-

29

DOUTH+

28

DOUTH-

27

DRVDD

26

GAIN DRIVE INPUT

Reference Circuitry

1K

R309

U302

13

ADR510ARTZ

470K R308

8.06K

R335

AVDD

J301

R303

0.1UF

R336

10K

R337

0-DNP

IN

GGND

49.9

R302

100

C308

0.1UF

C309

0.1UF

10K

R301

0.1UF

C301

4.7UF

C302

C 3 03 C 3 04

V+TRIM/NC

V-

2

CW

R331

00

R304

LOSWD

LO-D

CWD0-

CWD0+

CWD1-

CWD1+

CWD2-

CWD2+

AVDD_3.3V

VSENSE_DUT

VREF_DUT

AVDD

CWD3-

CWD3+

CWD4-

CWD4+

CWD5-

CWD5+

LO-E

0.1UF LOSWE

C305

0.1UF

LGD

LID

742

751

LIDLIE

LGDLGE

LOSWD

76

LO-D

77

CWD0-

78

CWD0+

79

CWD1-

80

CWD1+

81

CWD2-

82

CWD2+

83

CWVDDDOUTC+

84

GAIN-

85

GAIN+

86

RBIAS

87

SENSE

88

VREF

89

REFB

90

REFT

91

RAVDD

92

CWD3-

93

CWD3+

94

CWD4-

95

CWD4+

96

CWD5-

97

CWD5+

98

LO-E

99

LOSWE

100

PAD

101

R311

0-DNP

R310

10K

CW

C306

0.1UF 1UF

C307

LO-B

LGC

LO-C

LIC

LOSWC

AVDD

72

733

70

68

69

71

LIC

LGC

LO-C

AVDD

LOSWC

LOSWB

AVDD

66

67

64

63

65

LO-B

AVDD

LOSWB

AD9271BSVZ-50

VREF_DUT

R312 DNP

R313 DNP

LIB

LGB

62

LIB

LGB

Vref Selec t

R315

AVDD

0-DNP

R316

0-DNP

R317

0

Remove C307 when

using external Vref

LO-A

AVDD

60

61

58

59

LO-A

AVDD

Vref=0.5V(1+R313/R312)

AVDD

LGA

LIA

LOSWA

55

56

57

LIA

LGA

LOSWA

Vref = External

Vref=1V

CSB_DUT

R338

10K

AVDD

54

AVDD

AVDDAVDD

SDIO_DUT

1K

R319

52

SDIO

6304-088

1K

R326

AVDD

1K

R325

LO-F

LOSWF

AVDD

AVDD AVDD

LIF

4

5

6

U301

LIE

LGE

AVDD

7

LIF

LO-F

LOSWF

LO-G

LOSWG

AVDD

LGF

9

8

LGF

AVDD

LIG

AVDD

11

12

10

13

LIG

LO-G

LOSWG

Figure 77. Evaluation Board Schematic, DUT, VREF, and Gain Circuitry

Rev. A | Page 47 of 60

LGH

20

LGH

AVDD

212423 53

22

AVDD

CLK- CSB

AVDD

25

CLK

AVDD

LO-H

LOSWH

AVDD

LGG

15

14

LGG

AVDD

LIH

AVDD

17

18

16

19

LIH

LO-H

LOSWH

CLK+

AD9271

www.BDTIC.com/ADI

0

R439

R441

00R443

R445

0-DNP

R437

R436

0

R438

0-DNP

R440

S8

S7

S6

AD9515Pin-strapsettings

AVDD_3.3 V

R425

R427

OPTIONAL CONNECTIO N

TO AD8339 EVAL BOARD

753

1

P405

246

8

CWD1-

CWD1+

CWD0-

CWD0+

560UH

L402

2

1

750

AVDD_2.5 V

AOUT

J403

J402

AOUT

R467

L401

560UH

2

1

L404

560UH

2

1

750

AVDD_2.5 V

R461

0-DNP

49.9

R458

R455

49.9

0-DNP

R459

R468

560UH

L403

2

1

CWD2

R463

00

R464

0.1UF

R462

R460

CWD1

R454

+5V

7

8

V+

OUT2

U402

-

-IN1

OUT1

C419 C420

750

R453

00

R451

T402

AVDD_3.3V

CW DOPPLER CIRCUITRY

135

7

P406

864

2

CWD5-

CWD5+

CWD4-

CWD4+

750

1

750

R469

1

0.1UF

C422

750

-IN2 +IN2

+

AD822ART Z

+

V-

+IN 1

35261

4

-5V

0

R452

0

25

1

E402

0

R446

CWD2-

CWD2+

8

753

ION

CWD3-

CWD3+

ADTT4-1T +

61

127

R448

43

127

R447

246

1

P403

IOP

L408

560UH

2

1

R470

560UH

L407

2

1

560UH

L406

2

L405

560UH

2

C421

0.1UF

CWD2CWD1

R450

0

R465

0-DNP

AVDD_3.3 V

0

R424

0-DNP 0

0-DNP

R426

S0

AVDD_3.3V

AVDD_2.5 V

C405

AVDD_2.5 V

OPTIONAL CLOCK DRIVE CIRCUI T

AVDD_3.3V

0

R466

R449

0-DNP

10K

R401

C401

0.1UF

Figure 78. Evaluation Board Schematic, Clock

AVDD_3.3 V

R429

00R4310R433

R428

0-DNP

R430

0-DNP

S3

S2

S1

AVDD_3.3V

CLK

LVPECLOUTPUT

C406

0.1UF-D NP

100

R422

232219

OUT0

33

GND_PAD

GND

31

VS

1

AVDD_3.3V

R414

4.12K

3

RSET

32

CLK

U401

2

10K

R410

R411

DNP

R408 R409

0-DNP

R406

OPT_CLK

J401

ENABLE

DISABLE

1

2

1

TRI-

STAT E

OSC401

VC C

4

AVDD_3.3V

and CW Doppler Circuitry

0

R442

0-DNP

R444

S10

S9

AVDD_3.3 V

R435

0

R434

0-DNP

R432

S4

S5

AVDD_3.3V

LVDSOUTPUT

C408

C407

240

R421R420

240

18

S0

25

OUT1

OUT0B

OUT1B

S1

16

S2

15

S3

14

S4

13

S5

12

S6

11

S7

10

SIGNAL=DNC;27,28

S8

9

S9

SIGNA L=AVDD_3.3V ;4,17,20,21,24,26,29,3 0

8

S10

AD9515BCPZ

7

VREF

6

CLKB

SYNCB

5

3

49.9-DN P

R413

10K

DNP

R412

R407

0-DNP

OPT_CLK

R402

10K

2

GN DOU T

3

VFAC3H -L-50MHZ

0.1UF-DNP

100

R423

AVDD_3.3 V

S0

S1

CLK

S2

S3

S4

S5

0.1UF

S6

C410

S7

S8

S9

S10

1

E401

R418

6

T401

3

R415

OPT_CLK

0.1UF

C402

0

R403

P401

ENC

CLIPSINE OUT(DEFAULT)

CR401

HSMS-281 2

2

3

1

0

25

0

49.9

R404

CLK

0.1UF

C409

0

R417

ADT1-1W+

14

0

R416

0.1UF

C403

P402

ENC

06304-089

0.1UF

C417 C418

C416C415

0.1UF 0.1UF

C414

0.1UF0.1UF

0.1UF 0.1UF

C412 C413

0.1UF

C411

OPT_CLK

R405

0

Rev. A | Page 48 of 60

AD9271

www.BDTIC.com/ADI

SDO_CHA

SDI_CHA

SCLK_CH A

CSB1_CH A

1

E704

PWR_OUT

MH501

MH502

MH503

MH504

21

D705

S2A-TP

BOARD MOUNTING HOLE S

PopulateMH501-504for standardboard evaluation

S2A-TP

D704

12

21

D703

S2A-TP

PWR_IN

CR702

S2A-TP

D702

12

245

CG

CB

CG

BNX016-0 1

L701

BIAS 1

21

F701

NANOSMDC110 F

1

P701

6V, 2A ma x

Power Supply Input

AVDD_3.3V

SPI CIRCUITRY FROM FIFO

8

6

4

2

PopulateMH503-505fordockingwith AD8339EvalBoard

+3.3v

240

R716

GREEN

6

CG

PSG 3

2A

D701

C704

10UF

2

3

7.5VPOWER

2.5MMJACK

1K

R710

SDIO_DUT

SPI BUS DISCONNECT OPTION

7

5

3

1

J501

R712

AVDD

1K

NC7WZ07P 6X_N L

OPTIONALPOWERINPUT

R713

L703

P501

L501

P511

6543

Y1

A1

1

AVDD_3.3V

C710

0.1UF

10UF

C709

2

10UH

1

DUT_AVDD

3.3V_AVD D

12345

+5V

0.1UF

C502

C501

10UF

2

10UH

1

123

CW +/- 5V

POWER INPUT

1K

Y2A2

VCC

GND

2

10K

R711

+1.8v

AVDD

2

10UH

L702

1

DUT_DRVDD

6

Z5.531.3625. 0

-5V

2

L502

10UH

1

Z5.531.3325. 0

0.1UF

C702

6 Y1

NC7WZ16P 6X_N L

U702

A1 1234

MH505

+1.8v

DRVDD_DUT

C712

0.1UF

C708

C707

10UF

C504

0.1UF

10UF

C503

CSB_DUT

AVDD

SCLK_DUT

5

Y2A2

VCC

GND

0.1UF

10UF

C711

2

L704

10UH

1

C721

100PF

U706

C703

0.1UF

U703

10K

R715

10K

R714

1

E703

1

E702

1

E701

GND Test Points

C735

0.1UF0.1UF

C734

C733C732

0.1UF

C731

0.1UF 0.1U F

0.1UF

C730

AVDD

AVDD_2.5 V

2

18

3

OUT

5

NR

ADP3335

IN

7

ADP3335ACPZ -2. 5

AVDD_3.3 V

1

E708

1

E707

1

E706

1

E705

C748

0.1UF0.1UF

C746 C747

C745C74 4

0.1UF

AVDD

1UF

SD GND

64

1UF

C722 C723

DUT_AVDD

2

L705

10UH

1UF

C715C714

1

4

OUTPUT4

GND

1

ADP3339AKCZ -1.8-R L

U707

INPUT OUTPUT1

32

AVDD_3.3 V DRVD D_DUT

3.3V_AVD D

2

L707

10UH

C720

1

4

23

OUTPUT4

ADP3339AKCZ -3.3-R L

U705

INPUT OUTPUT1

PWR_IN

C719

DUT_DRVDD

2

10UH

L706

C717

1

4

OUTPUT4

ADP3339AKCZ -1.8-R L

U704

INPUT OUTPUT1

32

06304-090

C743

0.1UF

C742

0.1UF

C751

0.1UF

C740

GND

1

1UF 1UF

1UF

GND

1

Figure 79. Evaluation Board Schematic, Pow

er Supply and SPI Interface Circuitry

Rev. A | Page 49 of 60

PWR_OUT

1UF

PWR_OUT

1UF

C716

AD9271

A

www.BDTIC.com/ADI

Digital Outputs

FIFO5: DATA BUS 1 CONNECTOR FIFO5: HS - SERIAL/SPI/AUX CONNECTOR

DCO

CHA

CHB

CHC

CHD

CHE

CHF

CHG

CHH

FCO

P601

60

C10

40

59

C9

39

58

C8

38

57

C7

37

56

C6

36

55

C5

35

54

C4

34

53

C3

33

52

C2

32

51

C1

31

30

A10

10

29

A9

9

28

A8

8

27

A7

7

26

A6

6

25

A5

5

24

A4

4

23

A3

3

22

A2

2

21

A1

1

6469169-1

GNDCD1 0

GNDCD 9

GNDCD 8

GNDCD 7

GNDCD 6

GNDCD 5

GNDCD 4

GNDCD 3

GNDCD 2

GNDCD 1

GNDAB1 0

R601 100-DNP

GNDAB 9

R602 100-DNP

GNDAB 8

GNDAB 7

R604 100-DNP

GNDAB 6

GNDAB 5

R606 100-DNP

GNDAB 4

GNDAB 3

R608 100-DNP

GNDAB 2

GNDAB 1

R610 100-DNP

D10

50

D9

49

D8

48

D7

47

D6

46

D5

45

D4

44

D3

43

D2

42

D1

41

B10

20

B9

19

100-DNPR603

B8

18

B7

17

100-DNPR605

B6

16

B5

15

100-DNPR607

B4

14

B3

13

100-DNPR609

B2

12

B1

11

R601-R610

Optional Output

Terminations

DCO

CHA

CHB

CHC

CHD

CHE

CHF

CHG

CHH

FCO

CSB1 _CHA

CSB2 _CHA

CSB3 _CHA

CSB4 _CHA

P602

60

C10

40

59

C9

39

58

C8

38

57

C7

37

56

C6

36

55

C5

35

54

C4

34

53

C3

33

52

C2

32

51

C1

31

30

A10

10

29

A9

9

28

A8

8

27

A7

7

26

A6

6

25

A5

5

24

A4

4

23

A3

3

22

A2

2

21

A1

1

6469169-1

GNDCD1 0

GNDCD 9

GNDCD 8

GNDCD 7

GNDCD 6

GNDCD 5

GNDCD 4

GNDCD 3

GNDCD 2

GNDCD 1

GNDAB1 0

GNDAB 9

GNDAB 8

GNDAB 7

GNDAB 6

GNDAB 5

GNDAB 4

GNDAB 3

GNDAB 2

GNDAB 1

D10

50

D9

49

D8

48

D7

47

D6

46

D5

45

D4

44

D3

43

D2

42

D1

41

B10

20

B9

19

B8

18

B7

17

B6

16

B5

15

B4

14

B3

13

B2

12

B1

11

SCLK_CH

SDI_CHA

SDO_CHA

06304-111

Figure 80. Evaluation Board Schema

tic, Digital Output Interface

Rev. A | Page 50 of 60

AD9271

www.BDTIC.com/ADI

Figure 81. Evaluation B

oard Layout, Top Side

6304-084

Figure 82. Evaluation Board Layout, Ground Plane (Layer 2)

Rev. A | Page 51 of 60

6304-083

AD9271

www.BDTIC.com/ADI

Figure 83. Evaluation Board Layout, Power Plane (Layer 3)

06304-081

Figure 84. Evaluation Board Layout, Power Plane (Layer 4)

Rev. A | Page 52 of 60

06304-082

AD9271

www.BDTIC.com/ADI

06304-080

Figure 85. Evaluation Board Layout, Ground Plane (Layer 5)

Figure 86. Evaluation Board Layout, Bottom Side

Rev. A | Page 53 of 60

6304-085

AD9271

www.BDTIC.com/ADI

Table 16. Evaluation Board Bill of Materials (BOM)

Item Qty. Reference Designator Device Package Description Manufacturer RoHS Part Number

1 70

C101, C103, C105, C107, C109, C111, C11

3, C115,

Capacitor 402

C121, C122, C123, C124, C201, C203, C205, C207, C209, C211, C213, C215, C221, C222, C223, C224, C301, C303, C304, C305, C306, C308, C309, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C419, C420, C421, C422, C502, C504, C702, C703, C708, C710, C712, C730, C731, C732, C733, C734, C735, C740, C742, C743, C744, C745, C746, C747, C748, C751

2 1 C302 Capacitor 603

3 9

C307, C714, C715, C716, C717, C71

9,

Capacitor 603

C720, C722, C723

4 8

C102, C106, C110, C114, C202, C206, C21

0, C214

Capacitor 402

5 1 C721 Capacitor 402

6 1 C704 Capacitor 1812

7 5

C501, C503, C707,

Capacitor 603

C709, C711

8 1 CR401 Diode SOT23

9 1 CR702 LED 603

10 5

D701, D702, D703,

Diode DO-214AB 3 A, 30 V, SMC

D704, D705

11 1 F701 Fuse 1210

12 8

13 8

L401, L402, L403, L404, L405, L406, L40

7, L408

L501, L502, L702, L703, L704, L705, L70

6, L707

Inductor 1210

Ferrite bead 1210

14 1 L701 Choke coil 5-pin

1

0.1 µF, ramic,

ce X5R, 10 V,

Panasonic AVX Murata

ECJ-0EB1A104K 0402YD104KAT2A GRM155R71C104KA88D

2

10% tol

4.7 µF, 6.3 V,

X5R, 10%

tol

1 µF, ceramic, X5R, 6.3 V,

AVX Murata

Panasonic Murata

06036D475KAT2A GRM188R60J475KE19D

2

ECJ-1VB0J105K GRM188R61C105KA93D

2

10% tol

2

22 pF, ceramic, NPO

, 5% tol,

50 V 100 pF, ceramic,

OG, 50 V,

C

Kemet AVX Murata

C0402C220J5GACTU 04025A220JAT2A GRM1555C1H220JZ01D

Murata GRM1555C1H101JZ01D

2

5% tol 10 F, X5S, 50 V,

Taiyo Yuden UMK432C106MM-T

2

20% tol

2

10 F, ceramic,

V,

X5R, 6.3

Panasonic Murata

ECJ-1VB0J106M GRM188R60J106M

2

20% tol 30 V, 20 mA,

dual Schottk

Avago

y

Technologies

HSMS-2812-TR1G

Limited (Agilent)

Green, 4 V,

Panasonic LNJ314G8TRA

2

5 m candela

2

Micro

ommercial

C

S2A-TP

Co.

6.0 V, 2.2 A

ent

trip curr

Tyco/Raychem NANOSMDC110F-2

2

resettable fuse 560 µH, test

Murata LQH32MN561J23L

2

freq 1 kHz, 5% tol, 40 mA

10 µH, test fr

eq

Murata BLM31PG500SH1L

2

100 MHz, 25% tol, 500 mA

25 V dc, 15 A,

z to 1

100 kH

Murata BNX016-01

GHz, 40 dB insertion loss

2

Rev. A | Page 54 of 60

AD9271

www.BDTIC.com/ADI

Item Qty. Reference Designator Device Package Description Manufacturer RoHS Part Number

15 2 J501, P403 Connector 8-pin

100 mil header,

, 2 × 4

male

Samtec TSW-104-08-T-D

double row straight

16 2 P302, P303 Connector 2-pin

17 2 P405, P406 Connector 8-pin

100 mil header

, 1 × 2

jumper 100 mil header,

emale, 2 × 4

f

Samtec TSW-102-07-G-S

Samtec SSW-104-06-G-D

double row straight

18 1 P511 Connector 3-pin

3.5 mm header ip, male, 1 × 3

str

Wieland Z5.531.3325.0

single row straight

19 1 J401 Connector 3-pin

20 13

J101, J102, J103, J104, J201, J202, J203,

J204,

Connector SMA

J301, J402, J403, P401, P402

21 2 P601, P602 Connector HEADER

100 mil header

, 1 × 3

jumper Side mount

SMA for

0.063 in. board

thickness 1469169-1,

ight angle

r

Samtec TSW-103-07-G-S

Samtec SMA-J-P-H-ST-EM1

Tyco/AMP

1469169-1

NEW 6469169-1 2-pair, 25 mm, header assembly

22 1 P701 Connector 0.08", PCMT

RAPC722,

er supply

pow

Switchcraft RAPC722X

connector

23 85

R102, R103, R105, R106, R111, R112,

R114, R115, R120, R121, R123, R124, R129, R130, R131, R132, R133, R137, R138, R139,

Resistor 402

0 Ω, 1/16 W, 5% tol

Panasonic

A

KO Yag eo NIC Components

ERJ-2GE0R00X RK73Z1ETTP RC0402JR-070RL NRC04Z0TRF

R140, R149, R151, R152, R153, R162, R163, R164, R202, R203, R205, R206, R211, R213, R214, R215, R220, R221, R223, R224, R229, R230, R232, R233, R237, R238, R239, R240, R249, R250, R251, R252, R253, R262, R263, R264, R304, R317, R331, R403, R405, R415, R416, R417, R418, R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445, R446, R450, R451, R452, R460, R462, R463, R464, R466

24 8

25 12

R108, R117, R126, R135, R208, R217,

R226, R235 R158, R159, R160, R161,

R258, R259,

R260, R261,

Resistor 402

200 Ω, 1/16 W, 5% tol

49.9 Ω, 1/16 W,

0.5% tol

NIC Components

Susumu Co. RR0510R-49R9-D

NRC04J201TRF

R302, R404, R455, R458

26 9

R301, R338, R401, R402, R410,

R413, R711, R714, R715

Resistor 402

10 kΩ, 1/16 W, 5% tol

Panasonic KOA Yag eo NIC

ERJ-2GEJ103X RK73B1ETTP103J RC0402JR-0710KL NRC04J103TRF

Components

2

Rev. A | Page 55 of 60

AD9271

www.BDTIC.com/ADI

Item Qty. Reference Designator Device Package Description Manufacturer RoHS Part Number

27 3 R303, R422, R423 Resistor 402

100 Ω, 1/16 W, 1% tol

Panasonic

A

KO Yag e o

ERJ-2RKF1000X RK73H1ETTP1000F RC0402FR-07100RL NRC04F1000TRF

28 7

R309, R319, R325, R326, R710, R712,

R713

Resistor 402

1 kΩ, 1/16 W, 1% tol

Panasonic KO

A Yag eo NIC

ERJ-2RKF1001X RK73H1ETTP1001F RC0402FR-071KL NRC04F1001TRF

Components

29 1 R308 Resistor 402

470 kΩ, 1/16 W, 5% tol

Panasonic

A

KO Yag eo NIC

ERJ-2GEJ474X RK73B1ETTP474J RC0402JR-07470KL NRC04J474TRF

Components

30 2 R310, R336 Potentiometer 3-lead

10 kΩ, cermet

immer

tr

Murata PVA2A103A01R00

potentiometer, 18-turn top adjust, 10%, 1/2 W

31 1 R414 Resistor 402

4.12 kΩ, 1/16 W, 1% tol

32 3 R420, R421, R716 Resistor 402

240 Ω, 1/16 W, 5% tol

33 1 R335 Resistor 402

8.06 kΩ, 1/16 W, 1% tol

34 2 R447, R448 Resistor 402

127 Ω, 1/16 W, 1% tol

35 6

R453, R454, R467, R468, R469,

R470

36 1 OSC401 Oscillator Surface mount

Resistor 402

750 Ω, 1/16 W, 5% tol

Osc clock

50.000 MH

z

Panasonic NIC

mponents

Co Yag eo

NIC

mponents

Co NIC

mponents

Co NIC

mponents

Co NIC

Co

mponents Valpey Fisher

CTS

ERJ-2RKF4121X NRC04F4121TRF

RC0402JR-07240RL NRC04J241TRF

NRC04F8061TRF

NRC04F1270TRF

NRC04J751TRF

VFAC3-BHL-50MHz CB3LV-3C-50M0000-T

SMD

37 9

T101, T102, T103, T104, T20

1, T202,

T203, T204, T401

Transformer CD542

75 Ω, 1:1 impedance ratio

Mini-Circuits® ADT1-1WT+

transformer,

0.4 MHz to 800 MHz

38 1 T402 Transformer CD637

50 Ω, 1:4 impeda

nce

Mini-Circuits ADTT4-1+

ratio transformer,

0.2 MHz to 120 MHz

39 1 U301 IC SV-100-3

Octal LNA/VGA/

Analog

evices

D

AD9271BSVZ-50

AAF/ADC and

osspoint

cr switch

40 1 U302 IC SOT23

1.0 V precision w noise

lo

Analog Devices

ADR510ARTZ

shunt voltage reference

41 1 U401 IC LFCSP32-5X5 Clock dist.

Analog

evices

D

AD9515BCPZ

2

Rev. A | Page 56 of 60

AD9271

www.BDTIC.com/ADI

Item Qty. Reference Designator Device Package Description Manufacturer RoHS Part Number

42 1 U402 IC SO8

43 1 U706 IC CP-8

44 2 U704, U707 IC SOT223-2 Regulator

45 1 U705 IC SOT223-2 Regulator

46 1 U702 IC SC88

47 1 U703 IC SC88

1

This BOM is RoHS compliant.

2

May use suitable alternative.

Dual current

eedback op

f amp, SO8

500 mA, low

, low

noise dropout reg

NC7WZ07, dual

er, SC88

buff NC7WZ16P6X,

UHS dual

er, SC88

buff

Analog D

evices

Analog Devices

Analog

evices

D Analog

evices

D Fairchild NC7WZ07P6X_NL

Fairchild NC7WZ16P6X_NL

AD812ARZ

ADP3335ACPZ-2.5

ADP3339AKCZ-1.8

ADP3339AKCZ-3.3

2

Rev. A | Page 57 of 60

AD9271

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.20 MAX

16.00 BSC SQ

1

PIN 1

14.00 BSC SQ

76100

76 100

75

1

1.05

1.00

0.95

0.15

0.05

ROTATED 90° CCW

ORDERING GUIDE

Model

AD9271BSVZ-50 AD9271BSVZRL-50 AD9271BSVZ-40 AD9271BSVZRL-40 AD9271BSVZ-25 AD9271BSVZRL-25 AD9271-50EBZ

1

Z = RoHS Compliant Part.

1

TOP VIEW

(PINS DOWN)

0° MIN

0.20

0.09

7°

3.5°

SEATING PLANE

VIEW A

NOTES:

THE PACKAGE HAS A CONDUCTIVE HE AT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABL E OPER ATION OF THE DEVICE O VER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SL UG IS EX POSED ON T HE BOTTOM OF THE PACKAGE AND ELECTRICAL LY CONNECTED TO CHIP GRO UND. IT I S RECOMMENDED THAT NO PCB SIGNAL TRACES OR VI AS BE LOCATED UNDER THE PACKAGE TH AT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WI LL REDUCE THE JUNCTIO N TEMPER ATURE OF THE DEVICE WHI CH MAY BE BENEFICIAL IN HIG H TEMPERATURE ENVIRONMENTS.

0°

0.08 MAX COPLANARIT Y

25

26 50

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

51

EXPOSED

BOTTOM VIEW

0.50 BSC

LEAD PITCH

PAD

(PINS UP)

0.27

0.22

0.17

9.50 SQ

25

2650

080706-A

Figure 87. 100-Lead Thin Quad Flat Packag

e, Exposed Pad [TQFP_EP]

(SV-100-3)

Dimensions shown in millimeters

Temperature R

ange Package Descri

ption

Package Op

tion

−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3

−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3

−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3

−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3

−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3

−40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3 Evaluation Board

Rev. A | Page 58 of 60

AD9271

www.BDTIC.com/ADI

NOTES

Rev. A | Page 59 of 60

AD9271

www.BDTIC.com/ADI

NOTES

Rev. A | Page 60 of 60

Datasheet AD9271 Datasheet (ANALOG DEIVCES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

PRODUCT HIGHLIGHTS

SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

ADC TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL IMPEDANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ULTRASOUND

CHANNEL OVERVIEW

Low Noise Amplifier (LNA)

Active Impedance Matching

LNA Noise

INPUT OVERDRIVE

Input Overload Protection

CW DOPPLER OPERATION

Crosspoint Switch

TGC OPERATION

Variable Gain Amplifier

Gain Control

VGA Noise

Antialiasing Filter

CLOCK INPUT CONSIDERATIONS

Clock Duty Cycle Considerations

Clock Jitter Considerations

Power Dissipation and Power-Down Mode

Digital Outputs and Timing

SDIO Pin

SCLK Pin

CSB Pin

RBIAS Pin

Voltage Reference

Internal Reference Operation

External Reference Operation

SERIAL PORT INTERFACE (SPI)

HARDWARE INTERFACE

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

DEFAULT VALUES

LOGIC LEVELS

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Power and Ground Recommendations

Exposed Paddle Thermal Heat Slug Recommendations

EVALUATION BOARD

POWER SUPPLIES

INPUT SIGNALS

OUTPUT SIGNALS

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

QUICK START PROCEDURE

SCHEMATICS AND ARTWORK

OUTLINE DIMENSIONS

ORDERING GUIDE