Datasheet AD9266-EP Datasheet (ANALOG DEVICES)

1.8 V Analog-to-Digital Converter

AD9266-EP

Rev. A

Trademarks and registered trademarks are the property of their respective owners.

VIN+ VIN–

VREF

SENSE

OR

D1_D0

D15_D14

8

DCO

SDIOAGND DRVDDAVDD

SCLK

SPI

PROGRAMMI NG DATA

VCM

RBIAS

PDWN DFS

CLK+ CLK–

MODE

CONTROLS

DUTY CYCLE

STABILIZER

DIVIDE

1 TO 8

MODE

CSB

REF

SELECT

ADC

CORE

CMOS

OUTPUT BUFFER

AD9266-EP

10476-001

Enhanced Product

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply SNR

77.6 dBFS at 9.7 MHz input

76.4 dBFS at 70 MHz input

SFDR

94 dBc at 9.7 MHz input 93 dBc at 70 MHz input

Low power

111 mW at 65 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = −0.5/+1.0 LSB Interleaved data output for reduced pin-count interface Serial port control options

Offset binary, Gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock output (DCO) with programmable clock and

data alignment

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline Enhanced product change notification Qualification data available on request

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imaging

Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

16-Bit, 65 MSPS,

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9266-EP operates from a single 1.8 V analog power

supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance at high input frequencies and is designed for low cost, low power, and ease of use.

3. A standard serial port interface supports various product

features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D15_D14 to D1_D0) timing and offset adjustments, and voltage reference modes.

4. The AD9266-EP is packaged in a 32-lead RoHS-compliant

LFCSP that is pin compatible with the AD9609 10-bit ADC, the AD9629 12-bit ADC, and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling at 65 MSPS.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

AD9266-EP Enhanced Product

GENERAL DESCRIPTION

The AD9266-EP is a monolithic, single-channel 1.8 V supply, 16-bit, 65 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 65 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input with a selectable internal 1-to-8 divide ratio controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The interleaved digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. CMOS levels from 1.8 V through 3.3 V are supported.

The AD9266-EP is available in a 32-lead RoHS-compliant LFCSP and is specified over the −55°C to +125°C temperature range.

Additional application and technical information can be found in the AD9266 data sheet.

This product is protected by a U.S. patent.

Rev. A | Page 3 of 12

AD9266-EP Enhanced Product

ANALOG INPUT

IAVDD2

Full 56.3

62.2

mA

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.

Table 1.

Parameter Temp Min Typ Max Unit RESOLUTION Full 16 Bits ACCURACY

No Missing Codes Full Guaranteed Offset Error Full +0.05 ±0.30 % FSR Gain Error1 25°C −1.3 % FSR Differential Nonlinearity (DNL)2 Full −0.9/+1.7 LSB 25°C −0.5/+1.0 LSB Integral Nonlinearity (INL)2 Full ±6.5 LSB 25°C ±2.6 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mo de) Full 0.983 0.995 1.007 V Load Regulation Error at 1.0 mA 25°C 2 mV

INPUT-REFERRED NOISE

VREF = 1.0 V 25°C 2.8 LSB rms

Input Span, VREF = 1.0 V 25°C 2 V p-p Input Capacitance3 25°C 6.5 pF Input Common-Mode Voltage 25°C 0.9 V

Input Common-Mode Range Full 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 kΩ POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 V

Supply Current

IDRVDD2 (1.8 V) 25°C 5.2 mA

IDRVDD2 (3.3 V) 25°C 9.3 mA

POWER CONSUMPTION

DC Input 25°C 107 mW

Sine Wave Input2 (DRVDD = 1.8 V) Full 111 122 mW

Sine Wave Input2 (DRVDD = 3.3 V) 25°C 132 mW

Standby Power4 25°C 44 mW

Power-Down Power 25°C 0.5 mW

1

Measured with 1.0 V external reference.

2

Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between the differential inputs.

4

Standby power is measured with a dc input and the CLK active.

Rev. A | Page 4 of 12

Enhanced Product AD9266-EP

fIN = 30.5 MHz

25°C 77.2 dBFS

Full

−80

dBc

fIN = 9.7 MHz

25°C 94 dBc

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.

Table 2.

Parameter1 Temp Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 9.7 MHz 25°C 77.6 dBFS fIN = 30.5 MHz 25°C 77.4 dBFS Full 76.5 dBFS fIN = 70 MHz 25°C 76.4 dBFS

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

fIN = 9.7 MHz 25°C 77.4 dBFS

Full 76.0 dBFS fIN = 70 MHz 25°C 76.3 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 9.7 MHz 25°C 12.6 Bits fIN = 30.5 MHz 25°C 12.5 Bits Full 12.3 Bits fIN = 70 MHz 25°C 12.4 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 9.7 MHz 25°C −94 dBc fIN = 30.5 MHz 25°C −93 dBc

fIN = 70 MHz 25°C −93 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 30.5 MHz 25°C 93 dBc Full 80 dBc fIN = 70 MHz 25°C 93 dBc

WORST OTHER (HARMONIC OR SPUR)

fIN = 9.7 MHz 25°C −92 dBc fIN = 30.5 MHz 25°C −101 dBc Full −88 dBc fIN = 70 MHz 25°C −98 dBc

TWO-TONE SFDR

fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 dBc

ANALOG INPUT BANDWIDTH 25°C 700 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

Rev. A | Page 5 of 12

AD9266-EP Enhanced Product

Input Resistance

Full 26 kΩ

DIGITAL SPECIFICATIONS

AVDD = 1 .8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.

Table 3.

Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL

Internal Common-Mode Bias Full 0.9 V

Differential Input Voltage Full 0.2 3.6 V p-p

Input Voltage Range Full GND − 0.3 AVDD + 0.2 V

High Level Input Current Full −10 +10 µA

Low Level Input Current Full −10 +10 µA

Input Resistance Full 8 10 12 kΩ

Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1

High Level Input Voltage Full 1.2 DRVDD + 0.3 V

Low Level Input Voltage Full 0 0.8 V

High Level Input Current Full −50 −75 µA

Low Level Input Current Full −10 +10 µA

Input Resistance Full 30 kΩ

Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2

High Level Input Voltage Full 1.2 DRVDD + 0.3 V

Low Level Input Voltage Full 0 0.8 V

High Level Input Current Full −10 +10 µA

Low Level Input Current Full 40 135 µA

Input Capacitance Full 2 pF DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage, IOH = 50 µA Full 3.29 V High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V

DRVDD = 1.8 V

High Level Output Voltage, IOH = 50 µA Full 1.79 V High Level Output Voltage, IOH = 0.5 mA Full 1.75 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 µA Full 0.05 V

1

Internal 30 kΩ pull-down.

2

Internal 30 kΩ pull-up.

Rev. A | Page 6 of 12

Enhanced Product AD9266-EP

SKEW

10476-002

t

CLK

t

A

t

DCO

t

SKEW

t

SKEW

t

PD

V

IN

CLK+ CLK–

DCO

D1_D0

N – 1

N

N + 1

N + 2

N + 3

N + 5

N + 6

N + 7

N + 8

D1

N–9

D0

N–9

D1

N–8

D0

N–8

D1

N–7

D0

N–7

D1

N–6

D0

N–6D1N–5

D0

N–5D1N–4

D0

N–4

D15

N–9

D14

N–9

D15

N–8

D14

N–8

D15

N–7

D14

N–7

D15

N–6

D14

N–6

D15

N–5

D14

N–5

D15

N–4

D14

N–4

D15_D14

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.

Table 4.

Parameter Temp Min Typ Max Unit CLOCK INPUT PARAMETERS

Input Clock Rate Full 520 MHz Conversion Rate1 Full 3 65 MSPS CLK Period—Divide-by-1 Mode (t CLK Pulse Width High (tCH) 7.69 ns Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) Full 3 ns DCO Propagation Delay (t DCO to Data Skew (t

) Full 0.1 ns Pipeline Delay (Latency) Full 9 Cycles Wake-Up Time2 Full 350 µs Standby Full 300 ns

OUT-OF-RANGE RECOVERY TIME Full 2 Cycles

1

Conversion rate is the clock rate after the CLK divider.

2

Wake-up time is dependent on the value of the decoupling capacitors.

) Full 15.38 ns

CLK

) Full 3 ns

DCO

Figure 2. CMOS Output Data Timing

Rev. A | Page 7 of 12

AD9266-EP Enhanced Product

CLK

tS

Setup time between CSB and SCLK

2

ns

HIGH

LOW

TIMING SPECIFICATIONS

Table 5.

Parameter Test Conditions/Comments Min Typ Max Unit

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

tH Hold time between CSB and SCLK 2 ns t

SCLK pulse width high 10 ns

t

SCLK pulse width low 10 ns

t

Time required for the SDIO pin to switch from an input to an output

EN_SDIO

relative to the SCLK falling edge

t

Time required for the SDIO pin to switch from an output to an input

DIS_SDIO

relative to the SCLK rising edge

10 ns

Rev. A | Page 8 of 12

Enhanced Product AD9266-EP

SENSE to AGND

−0.3 V to AVDD + 0.2 V

MODE/OR to AGND

−0.3 V to DRVDD + 0.3 V

Operating Temperature Range (Ambient)

−55°C to +125°C

JA

JC

JB

Ψ

JT

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD to AGND −0.3 V to +2.0 V DRVDD to AGND −0.3 V to +3.9 V VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V VREF to AGND −0.3 V to AVDD + 0.2 V

VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V SDIO/PDWN to AGND −0.3 V to DRVDD + 0.3 V

D1_D0 Through D15_D14 to AGND DCO to AGND

−0.3 V to DRVDD + 0.3 V

Maximum Junction Temperature Under Bias 150°C Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle is the only ground connection for the chip. The exposed paddle must be soldered to the AGND plane of the us e r’s circuit board. Soldering the exposed paddle to the us e r’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 7. Thermal Resistance

Package Type

32-Lead LFCSP

5 mm × 5 mm

1

Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Airflow Velocity (m/sec)

1, 2

1, 3

θ

1, 4

θ

1, 2

Unit

0 37.1 3.1 20.7 0.3 °C/W

1.0 32.4 0.5 °C/W

2.5 29.1 0.8 °C/W

Typ i cal θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes reduces the θ

.

JA

ESD CAUTION

Rev. A | Page 9 of 12

AD9266-EP Enhanced Product

Pin No.

Mnemonic

Description

NOTES

1. NC = NO CONNE C T. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PADDLE (PIN 0) IS THE ONLY GND CONNECTION ON THE CHIP AND M US T BE CONNECTED TO THE P CB AGND.

10476-003

CLK+ CLK–

AVDD

CSB

SCLK/DFS

SDIO/PDWN

NC NC

AVDD MODE/OR DCO (MSB) D15_D14 D13_D12 D11_D10 D9_D8 D7_D6

NC

DRVDD

D1_D0 (LSB)

D3_D2

D5_D4

AVDD

VIN+

VIN–

AVDD

RBIAS

VCM

SENSE

VREF

TOP VIEW

(Not to S cale)

AD9266-EP

24 23 22 21 20 19 18 17

1 2 3 4 5 6 7 8

9

10111213141516

32313029282726

25

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 8. Pin Function Descriptions

0 Exposed Paddle AGND. The exposed paddle is the only ground connection on the chip. It must be soldered to the analog

1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for ADC Core Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.

6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.

7 to 12 NC No Connect. Do not connect to this pin. 14 to 21 D1_D0 (LSB) to

(MSB) D15_D14 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).

25 VREF 1.0 V Voltage Reference Input/Output. 26 SENSE Reference Mode Selection. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs.

Figure 3. Pin Configuration

ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.

Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output.

Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.

ADC Digital Outputs.

Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100b). Chip standby (SPI Register 0x08, Bits[7:5] = 101b). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b). Out-of-range (OR) digital output only in non-SPI mode.

Rev. A | Page 10 of 12

Enhanced Product AD9266-EP

I

S

0.30

5.10

OUTLINE DIMENSIONS

PIN 1

NDICATOR

0.80

0.75

0.70

EATING

PLANE

5.00 SQ

4.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM COPLANARITY

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION.

0.08

24

17

0.25

0.18

25

16

32

1

EXPOSED

PAD

8

BOTTOMVIEWTOP VIEW

9

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

PIN 1 INDICATOR

*

3.75

3.60 SQ

3.55

0.25 MIN

08-16-2010-B

Figure 4. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9266TCPZ-65EP −55°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266TCPZRL7-65EP −55°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12

1

Z = RoHS Compliant Part.

Rev. A | Page 11 of 12

AD9266-EP Enhanced Product

NOTES

registered trademarks are the property of their respective owners. D10476-0-7/12(A)

Rev. A | Page 12 of 12

Datasheet AD9266-EP Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

ENHANCED PRODUCT FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTLINE DIMENSIONS

ORDERING GUIDE