Low power: 55 mW per channel at 65 MSPS with scalable
power options
SNR = 75.5 dB (to Nyquist)
SFDR = 91.6 dBc (to Nyquist)
DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
1.8 V Analog-to-Digital Converter
AD9257
FUNCTIONAL BLOCK DIAGRAM
DD
VIN+ A
VIN– A
VIN+ B
VIN– B
VIN+ C
VIN– C
VIN+ D
VIN– D
VIN+ E
VIN– E
VIN+ F
VIN– F
VIN+ G
VIN– G
VIN+ H
VIN– H
VREF
SENSE
VCM
SYNC
AD9257
REF
SELECT
RBIASAGNDCSBCLK+ CLK–SDIO/
PDWNDRVDD
14
ADC
14
ADC
14
ADC
14
ADC
14
ADC
14
ADC
14
ADC
14
ADC
1.0V
SERIAL PORT
INTERFACE
DFS
Figure 1.
SERIAL
LVD S
SERIAL
LVD S
SERIAL
LVD S
SERIAL
LVD S
SERIAL
LVD S
SERIAL
LVD S
SERIAL
LVD S
SERIAL
LVD S
SCLK/
DTP
DATA
RATE
MULTIPLIER
D+ A
D– A
D+ B
D– B
D+ C
D– C
D+ D
D– D
D+ E
D– E
D+ F
D– F
D+ G
D– G
D+ H
D– H
FCO+
FCO–
DCO+
DCO–
10206-001
GENERAL DESCRIPTION
The AD9257 is an octal, 14-bit, 40 MSPS and 65 MSPS analogto-digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9257 is available in an RoHS-compliant, 64-lead LFCSP.
It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2. Low Power of 55 mW/Channel at 65 MSPS with Scalable
Power Options.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 455 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5. Pin Compatible with the AD9637 (12-Bit Octal ADC).
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Can be controlled via the SPI.
Min Typ Max Min Typ Max Unit
Rev. 0 | Page 3 of 40
Page 4
AD9257 Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2.
AD9257-40 AD9257-65
Parameter1 Temp
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz 25°C 75.9 75.7 dBFS
fIN = 19.7 MHz Full 73.5 75.8 73.3 75.6 dBFS
fIN = 30.5 MHz 25°C 75.7 75.5 dBFS
fIN = 63.5 MHz 25°C 74.9 dBFS
fIN = 69.5 MHz 25°C 74.7 dBFS
fIN = 123.4 MHz 25°C 73.2 dBFS
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 9.7 MHz 25°C 74.8 74.7 dBFS
fIN = 19.7 MHz Full 72.5 74.7 72.0 74.6 dBFS
fIN = 30.5 MHz 25°C 74.6 74.4 dBFS
fIN = 63.5 MHz 25°C 73.8 dBFS
fIN = 69.5 MHz 25°C 73.5 dBFS
fIN = 123.4 MHz 25°C 71.8 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz 25°C 12.1 12.1 Bits
fIN = 19.7 MHz Full 11.7 12.1 11.7 12.1 Bits
fIN = 30.5 MHz 25°C 12.1 12.1 Bits
fIN = 63.5 MHz 25°C 12.0 Bits
fIN = 69.5 MHz 25°C 11.9 Bits
fIN = 123.4 MHz 25°C 11.6 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz 25°C 97 96 dBc
fIN = 19.7 MHz Full 80 95 79 96 dBc
fIN = 30.5 MHz 25°C 97 91 dBc
fIN = 63.5 MHz 25°C 95 dBc
fIN = 69.5 MHz 25°C 87 dBc
fIN = 123.4 MHz 25°C 83 dBc
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz 25°C −99 −99 dBc
fIN = 19.7 MHz Full −96 −80 −98 −79 dBc
fIN = 30.5 MHz 25°C −100 −91 dBc
fIN = 63.5 MHz 25°C −98 dBc
fIN = 69.5 MHz 25°C −87 dBc
fIN = 123.4 MHz 25°C −83 dBc
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz 25°C −99 −98 dBFS
fIN = 19.7 MHz Full −99 −86 −98 −88 dBFS
fIN = 30.5 MHz 25°C −99 −98 dBFS
fIN = 63.5 MHz 25°C −98 dBFS
fIN = 69.5 MHz 25°C −98 dBFS
fIN = 123.4 MHz 25°C −94 dBFS
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1
AND AIN2 = −7.0 dBFS
f
= 8 MHz, f
IN1
f
= 30 MHz, f
IN1
= 10 MHz 25°C 95 dBc
IN2
= 32 MHz 25°C 92 dBc
IN2
Unit Min Typ Max Min Typ Max
Rev. 0 | Page 4 of 40
Page 5
Data Sheet AD9257
AD9257-40 AD9257-65
Parameter1 Temp
CROSSTALK 25°C −100 −98 dB
Crosstalk (Overrange Condition)2 25°C −92 −94 dB
ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Overrange condition is specified with 3 dB of the full-scale input range.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1 Temp Min Typ Max
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) 25°C 15 kΩ
Input Capacitance 25°C 4 pF
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (SDIO)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 5 pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA) Full 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 V
DIGITAL OUTPUTS (D± x), ANSI-644
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 247 350 454 mV
Output Offset Voltage (VOS) Full 1.13 1.21 1.38 V
Output Coding (Default) Twos complement
DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL
OPTION
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 150 200 250 mV
Output Offset Voltage (VOS) Full 1.13 1.21 1.38 V
Output Coding (Default) Twos complement
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO/DFS pins sharing the same connection.
Unit Min Typ Max Min Typ Max
Unit
Rev. 0 | Page 5 of 40
Page 6
AD9257 Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter
1, 2
Temp Min Typ Max Unit
CLOCK3
Input Clock Rate Full 10 520 MHz
Conversion Rate Full 10 40/65 MSPS
Clock Pulse Width High (tEH) Full 12.5/7.69 ns
Clock Pulse Width Low (tEL) Full 12.5/7.69 ns
OUTPUT PARAMETERS3
Propagation Delay (tPD) Full 2.3 ns
Rise Time (tR) (20% to 80%) Full 300 ps
Fall Time (tF) (20% to 80%) Full 300 ps
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DATA
DCO to FCO Delay (t
Data to Data Skew
DATA-MAX
− t
DATA-MIN
(t
) Full 1.5 2.3 3.1 ns
FCO
)4 Full t
CPD
)4 Full (t
)4 Full (t
FRAME
/28) − 300 (t
SAMPLE
/28) − 300 (t
SAMPLE
+ (t
FCO
SAMPLE
/28) (t
SAMPLE
/28) (t
SAMPLE
/28) ns
/28) + 300 ps
SAMPLE
/28) + 300 ps
SAMPLE
Full ±50 ±200 ps
)
Wake-Up Time (Standby) 25°C 35 μs
Wake-Up Time (Power-Down)5 25°C 375 μs
Pipeline Latency Full 16
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Measured on standard FR-4 material.
3
Can be adjusted via the SPI.
4
t
/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. t
SAMPLE
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
SAMPLE
= 1/fS.
TIMING SPECIFICATIONS
Table 5.
Parameter Description Limit
SYNC TIMING REQUIREMENTS
t
SYNC to rising edge of CLK+ setup time 0.24 ns typ
SSYNC
t
SYNC to rising edge of CLK+ hold time 0.40 ns typ
HSYNC
SPI TIMING REQUIREMENTS See Figure 61
tDS Setup time between the data and the rising edge of SCLK 2 ns min
tDH Hold time between the data and the rising edge of SCLK 2 ns min
t
Period of the SCLK 40 ns min
CLK
tS Setup time between CSB and SCLK 2 ns min
tH Hold time between CSB and SCLK 2 ns min
t
SCLK pulse width high 10 ns min
HIGH
t
SCLK pulse width low 10 ns min
LOW
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an output
10 ns min
relative to the SCLK falling edge (not shown in Figure 61)
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an input
10 ns min
relative to the SCLK rising edge (not shown in Figure 61)
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
Digital Outputs
−0.3 V to +2.0 V
(D± x, DCO+, DCO−, FCO+, FCO−) to
AGND
CLK+, CLK− to AGND −0.3 V to +2.0 V
VIN+ x, VIN− x to AGND −0.3 V to +2.0 V
SCLK/DTP, SDIO/DFS, CSB to AGND −0.3 V to +2.0 V
SYNC, PDWN to AGND −0.3 V to +2.0 V
RBIAS to AGND −0.3 V to +2.0 V
VREF, SENSE to AGND −0.3 V to +2.0 V
Environmental
Operating Temperature Range (Ambient) −40°C to +85°C
Maximum Junction Temperature 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Storage Temperature Range (Ambient) −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints and maximizes the
thermal capability of the package.
Table 7. Thermal Resistance
Airflow
Velocity
Package Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
(m/sec) θ
0 22.3 1.4 N/A 0.1 °C/W
1.0 19.5 N/A 11.8 0.2 °C/W
2.5 17.5 N/A N/A 0.2 °C/W
1, 2
JA
θ
JC
1, 3
θ
1, 4
JB
Ψ
1, 2
Unit
JT
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown Tabl e 7, airflow improves heat dissipation,
which reduces θ
. In addition, metal in direct contact with the
JA
package leads from metal traces, through holes, ground, and
power planes reduces θ
.
JA
ESD CAUTION
Rev. 0 | Page 8 of 40
Page 9
Data Sheet AD9257
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN+ F
VIN– F
AVD D
VIN– E
VIN+ E
AVD D
SYNC
VCM
VREF
SENSE
RBIAS
VIN+ D
VIN– D
AVD D
VIN– C
VIN+ C
49
AVD D
48
VIN+ B
47
VIN– B
46
AVD D
45
VIN– A
44
VIN+ A
43
AVD D
42
PDWN
41
CSB
40
SDIO/DFS
39
SCLK/DTP
38
AVD D
37
DNC
36
DRVDD
35
D+ A
34
D– A
33
PIN 1
INDICATOR
AVD D
VIN+ G
VIN– G
AVD D
VIN– H
VIN+ H
AVD D
AVD D
CLK–
CLK+
AVD D
AVD D
DNC
DRVDD
D– H
D+ H
646362616059585756555453525150
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD9257
TOP VIEW
(Not to Scale)
171819202122232425262728293031
D– F
D+ F
D– E
D– G
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
D+ E
D+ G
D– D
FCO–
FCO+
DCO–
DCO+
32
D– C
D– B
D+ D
D+ C
D+ B
10206-005
Figure 5. Pin Configuration, Top View
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
0, EP AGND, Exposed Pad
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package
provides the analog ground for the part. This exposed pad must be connected to ground
for proper operation.
1, 4, 7, 8, 11, 12, 37,
AVDD 1.8 V Analog Supply.
42, 45, 48, 51, 59, 62
13, 36 DNC Do Not Connect.
14, 35 DRVDD 1.8 V Digital Output Driver Supply.
2, 3 VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement.
5, 6 VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True.
9, 10 CLK−, CLK+ Input Clock Complement, Input Clock True.
15, 16 D− H, D+ H ADC H Digital Output Complement, ADC H Digital Output True.
17, 18 D− G, D+ G ADC G Digital Output Complement, ADC G Digital Output True.
19, 20 D− F, D+ F ADC F Digital Output Complement, ADC F Digital Output True.
21, 22 D− E, D+ E ADC E Digital Output Complement, ADC E Digital Output True.
23, 24 DCO−, DCO+ Data Clock Digital Output Complement, Data Clock Digital Output True.
25, 26 FCO−, FCO+ Frame Clock Digital Output Complement, Frame Clock Digital Output True.
27, 28 D− D, D+ D ADC D Digital Output Complement, ADC D Digital Output True.
29, 30 D− C, D+ C ADC C Digital Output Complement, ADC C Digital Output True.
31, 32 D− B, D + B ADC B Digital Output Complement, ADC B Digital Output True.
33, 34 D− A, D+ A ADC A Digital Output Complement, ADC A Digital Output True.
38 SCLK/DTP Serial Clock (SCLK)/Digital Test Pattern (DTP).
39 SDIO/DFS Serial Data Input/Output (SDIO)/Data Format Select (DFS).
40 CSB Chip Select Bar.
41 PDWN Power-Down.
43, 44 VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement.
46, 47 VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True.
49, 50 VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement.
52, 53 VIN− D, VIN+ D ADC D Analog Input Complement, ADC D Analog Input True.
Rev. 0 | Page 9 of 40
Page 10
AD9257 Data Sheet
Pin No. Mnemonic Description
54 RBIAS Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
55 SENSE Reference Mode Selection.
56 VREF Voltage Reference Input/Output.
57 VCM Analog Output Voltage at Midsupply. Sets common mode of the analog inputs.
58 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
60, 61 VIN+ E, VIN− E ADC E Analog Input True, ADC E Analog Input Complement.
63, 64 VIN− F, VIN+ F ADC F Analog Input Complement, ADC F Analog Input True.
Rev. 0 | Page 10 of 40
Page 11
Data Sheet AD9257
TYPICAL PERFORMANCE CHARACTERISTICS
AD9257-65
0
–15
–30
–45
–60
–75
–90
AMPLITUDE ( d BFS)
–105
–120
–135
3
69121518 212427 30
FREQUENCY (MHz)
65MSPS
9.7MHz AT –1d BFS
SNR = 74.7dB ( 75.7dBFS)
SFDR = 93.5d Bc
Figure 6. Single-Tone 16k FFT with fIN = 9.7 MHz, f
SAMPLE
10206-006
= 65 MSPS
0
65MSPS
19.7MHz AT –1dBFS
–15
SNR = 74.7dB (75. 7dBFS)
SFDR = 96.7dBc
–30
–45
–60
–75
–90
AMPLITUDE (dBFS)
–105
–120
–135
691215 18 2124 2730
3
FREQUENCY (MHz)
Figure 9. Single-Tone 16k FFT with fIN = 19.7 MHz, f
SAMPLE
10206-009
= 65 MSPS
0
–15
–30
–45
–60
–75
–90
AMPLITUDE ( d BFS)
–105
–120
–135
3
691215 1821 2427 30
FREQUENCY (MHz)
Figure 7. Single-Tone 16k FFT with f
0
–15
–30
–45
–60
–75
–90
AMPLIT UDE ( dBFS)
F2 – F1
F1 + F2
–105
–120
–135
691215 18 21 2427 30
3
FREQUENCY ( MHz)
Figure 8. Two-Tone 16k FFT with f
f
= 65 MSPS
SAMPLE
65MSPS
63.5MHz AT –1d BFS
SNR = 73.9dB ( 74.9dBFS)
SFDR = 95.4d Bc
= 63.5 MHz, f
IN
= 30 MHz and f
IN1
SAMPLE
2F2 + F 1
2F2 – F1
2F1 + F 2
2F1–F2
= 32 MHz,
IN2
= 65 MSPS
0
65MSPS
30.5MHz AT –1dBFS
–15
SNR = 74.7dB (75. 7dBFS)
SFDR = 96.7dBc
–30
–45
–60
–75
–90
AMPLITUDE (dBFS)
–105
–120
–135
10206-007
Figure 10. Single-Tone 16k FFT with f
0
–15
–30
–45
–60
–75
–90
AMPLITUDE ( d BFS)
–105
–120
–135
10206-008
Figure 11. Single-Tone 16k FFT with fIN = 123.4 MHz, f
691215 18 2124 2730
3
3
FREQUENCY (MHz)
= 30.5 MHz, f
IN
65MSPS
123.4MHz AT –1dBFS
SNR = 72.2dB ( 73.2dBFS)
SFDR = 83.0d Bc
691215 1821 2427 30
FREQUENCY (MHz)
SAMPLE
SAMPLE
= 65 MSPS
= 65 MSPS
10206-109
10206-010
Rev. 0 | Page 11 of 40
Page 12
AD9257 Data Sheet
0
105
–20
SFDR (dBc)
–40
–60
–80
SFDR/IMD3 (dBc/dBFS)
–100
–120
–90–78–66–54–42–6–18–30
IMD3 (dBc)
SFDR (dBFS)
IMD3 (dBFS)
INPUT AMPLITUDE (dBFS)
Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
= 30 MHz and f
f
IN1
120
100
80
60
40
SNR/SFDR (dBFS/dBc)
20
0
–90–80 –70–60–50 –40–30–20–10
Figure 13. SNR/SFDR vs. Analog Input Level, f
= 32 MHz, f
IN2
SFDRFS
SNRFS
SFDR
SNR
INPUT AMPLITUDE (dBFS)
SAMPLE
IN
= 65 MSPS
= 9.7 MHz, f
SAMPLE
10206-011
0
10206-012
= 65 MSPS
100
SFDR (dBc)
95
90
85
SNR/SFDR (dBFS/dBc)
80
SNR (dBFS)
75
70
–4085
Figure 15. SNR/SFDR vs. Temperature, f
110
100
90
80
70
60
50
40
SNR/SFDR (dBF S/dBc)
30
20
10
0
0200
–15103560
Figure 16. SNR/SFDR vs. f
TEMPERATURE (°C)
IN
SFDR (dBc)
SNR (dBFS)
INPUT FREQUENCY (MHz)
100 120 14080204060180160
, f
IN
= 9.7 MHz, f
SAMPLE
= 65 MSPS
SAMPLE
= 65 MSPS
10206-014
10206-015
105
100
95
90
85
SNR/SFDR (dBFS/dBc)
80
75
70
2030405060
Figure 14. SNR/SFDR vs. Encode, f
SFDR
SNRFS
SAMPLE FREQUENCY (MSPS)
= 19.7 MHz
IN
10206-013
Rev. 0 | Page 12 of 40
105
100
95
90
85
SNR/SFDR (dBFS/dBc)
80
75
70
2030405060
Figure 17. SNR/SFDR vs. Encode, f
SFDR
SNRFS
SAMPLE FREQUENCY (MSPS)
= 30.5 MHz
IN
10206-016
Page 13
Data Sheet AD9257
450,000
400,000
350,000
300,000
250,000
200,000
NUMBER OF HI TS
150,000
100,000
50,000
0
N – 9
N – 8
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 10
N – 1
OUTPUT CO DE
Figure 18. Input-Referred Noise Histogram, f
0.936 LSB RMS
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N + 10
10206-017
= 65 MSPS
SAMPLE
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0
1500
3000
Figure 20. DNL, f
6000
4500
OUTPUT CODE
= 9.7 MHz, f
IN
7500
9000
10500
12000
13500
15000
16500
10206-019
= 65 MSPS
SAMPLE
2.0
1.6
1.2
0.8
0.4
INL (LSB)
–0.4
–0.8
–1.2
–1.6
–2.0
0
0
Figure 19. INL, f
1500
3000
6000
4500
OUTPUT CODE
= 9.7 MHz, f
IN
7500
9000
10500
12000
13500
15000
16500
10206-018
= 65 MSPS
SAMPLE
Rev. 0 | Page 13 of 40
Page 14
AD9257 Data Sheet
AD9257-40
0
–15
–30
–45
–60
–75
–90
AMPLITUDE ( d BFS)
–105
–120
–135
2
4681012141618
FREQUENCY (MHz)
40MSPS
9.7MHz AT –1d BFS
SNR = 74.8dB ( 75.8dBFS)
SFDR = 96.9d Bc
Figure 21. Single-Tone 16k FFT with fIN = 9.7 MHz, f
Figure 24. Single-Tone 16k FFT with fIN = 19.7 MHz, f
SAMPLE
10206-023
= 40 MSPS
0
–15
–30
–45
–60
–75
–90
AMPLITUDE ( d BFS)
–105
–120
–135
24681012141618
FREQUENCY (MHz)
40MSPS
30.5MHz AT –1d BFS
SNR = 74.6dB ( 75.6dBFS)
SFDR = 98.8d Bc
Figure 22. Single-Tone 16k FFT with fIN = 30.5 MHz, f
0
–15
–30
–45
–60
–75
–90
AMPLIT UDE ( dBFS)
–105
–120
–135
F2 – F12F2 – F1
24681012141618
Figure 23. Two-Tone 16k FFT with f
+
FREQUENCY ( MHz)
IN1
= 40 MSPS
f
SAMPLE
2F1 + F2
2F1 – F2
= 8 MHz and f
SAMPLE
2F2 + F1
= 40 MSPS
F1 + F2
= 10 MHz,
IN2
0
–15
–30
–45
–60
–75
–90
AMPLITUDE ( d BFS)
–105
–120
–135
10206-021
24681012141618
FREQUENCY (MHz)
Figure 25. Single-Tone 16k FFT with fIN = 69.5 MHz, f
0
–20
SFDR (dBc)
–40
–60
–80
SFDR/IMD3 (dBc/dBFS)
–100
–120
–90–78–66–54–42–6–18–30
10206-022
IMD3 (dBc)
SFDR (dBFS)
IMD3 (dBF S )
INPUT AMPLITUDE (dBFS)
40MSPS
69.5MHz AT –1d BFS
SNR = 73.7dB ( 74.7dBFS)
SFDR = 87.9d Bc
= 40 MSPS
SAMPLE
10206-024
10206-025
Figure 26. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
f
= 30 MHz and f
IN1
= 32 MHz, f
IN2
SAMPLE
= 40 MSPS
Rev. 0 | Page 14 of 40
Page 15
Data Sheet AD9257
120
100
80
60
40
SNR/SFDR (dBFS/dBc)
20
0
–90–80 –70–60–50 –40–30–20–10
SFDRFS
SNRFS
SFDR
SNR
INPUT AMPLITUDE (dBFS)
Figure 27. SNR/SFDR vs. Analog Input Level, f
= 9.7 MHz, f
IN
SAMPLE
0
10206-026
= 40 MSPS
110
100
90
80
70
60
50
40
SNR/SFDR (dBFS/dBc)
30
20
10
0
0200
SFDR (dBc)
SNR (dBFS)
100 120 14080204060180160
INPUT FREQUENCY (MHz)
Figure 30. SNR/SFDR vs. f
IN
, f
SAMPLE
= 40 MSPS
10206-029
105
100
95
90
85
SNR/SFDR (dBFS/dBc)
80
75
70
203040
Figure 28. SNR/SFDR vs. Encode, f
105
100
SNR/SFDR (dBFS/dBc)
SFDR (dBc)
95
90
85
80
SNR (dBFS)
75
70
–4085
–15103560
Figure 29. SNR/SFDR vs. Temperature, f
SFDR
SNRFS
2535
SAMPLE FREQUENCY (MSPS)
= 19.7 MHz
IN
TEMPERATURE (°C)
= 9.7 MHz, f
IN
SAMPLE
= 40 MSPS
105
100
95
90
85
SNR/SFDR (dBFS/dBc)
80
75
70
20
10206-027
Figure 31. SNR/SFDR vs. Encode, f
500,000
450,000
400,000
350,000
300,000
250,000
200,000
NUMBER OF HIT S
150,000
100,000
50,000
0
N – 9
10206-028
N – 8
N – 10
Figure 32. Input-Referred Noise Histogram, f
SFDR
SNRFS
SAMPLE FREQUENCY (MSPS)
N – 7
N – 6
N – 5
30402535
N – 4
N – 3
N – 2
OUTPUT CO DE
N
N – 1
N + 1
= 30.5 MHz
IN
0.846 LSB RMS
N + 2
N + 3
N + 4
N + 5
SAMPLE
N + 6
N + 7
N + 8
= 40 MSPS
10206-030
N + 9
N + 10
10206-031
Rev. 0 | Page 15 of 40
Page 16
AD9257 Data Sheet
2.0
1.6
1.2
0.8
0.4
0
INL (LSB)
–0.4
–0.8
–1.2
–1.6
–2.0
0
1500
3000
Figure 33. INL, f
6000
4500
OUTPUT CODE
= 9.7 MHz, f
IN
7500
9000
10500
12000
13500
15000
16500
10206-032
SAMPLE
= 40 MSPS
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0
1500
3000
Figure 34. DNL, f
6000
4500
OUTPUT CODE
= 9.7 MHz, f
IN
7500
9000
10500
12000
13500
15000
16500
10206-033
SAMPLE
= 40 MSPS
Rev. 0 | Page 16 of 40
Page 17
Data Sheet AD9257
A
VDDV
A
V
A
V
A
V
A
A
V
A
V
A
V
EQUIVALENT CIRCUITS
DD
IN± x
Figure 35. Equivalent Analog Input Circuit
DD
CLK+
AVD D
CLK–
5
15k
0.9V
15k
5
Figure 36. Equivalent Clock Input Circuit
DD
30k
SDIO/DFS
350
30k
SCLK/DTP, SYNC,
AND PDWN
10206-034
350
30k
10206-038
Figure 39. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit
DD
RBIAS
ND VCM
10206-035
375
10206-039
Figure 40. Equivalent RBIAS, VCM Circuit
DD
30k
CSB
350
Figure 37. Equivalent SDIO/DFS Input Circuit
DRVDD
V
D– xD+ x
V
DRGND
V
V
10206-037
Figure 38. Equivalent Digital Output Circuit
10206-036
Figure 41. Equivalent CSB Input Circuit
DD
VREF
7.5k
375
Figure 42. Equivalent VREF Circuit
10206-040
10206-041
Rev. 0 | Page 17 of 40
Page 18
AD9257 Data Sheet
V
V
THEORY OF OPERATION
The AD9257 is a multistage, pipelined ADC. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stage. The quantized outputs from each stage are
combined into a final 14-bit result in the digital correction
logic. The serializer transmits this converted data in a 14-bit
output. The pipelined architecture permits the first stage to
operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9257 is a differential switchedcapacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
H
C
PAR
IN+ x
IN– x
C
PAR
Figure 43. Switched-Capacitor Input Circuit
C
SAMPLE
SS
SS
C
SAMPLE
H
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 43). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
H
H
10206-042
the output stage of the driving source. In addition, low Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and, therefore,
achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a differential capacitor or
two single-ended capacitors can be placed on the inputs to provide
a matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more
information. In general, the precise values depend on the
application.
Input Common Mode
The analog inputs of the AD9257 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that V
= AVDD/2 is
CM
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 44.
An on-board, common-mode voltage reference is included in
the design and is available from the VCM pin. The VCM pin
must be decoupled to ground by a 0.1 μF capacitor, as described
in the Applications Information section.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9257, the largest input span available is 2 V p-p.
100
90
80
70
60
50
SNR/SFDR (dBFS/dBc)
40
30
20
0.5
Figure 44. SNR/SFDR vs. Common-Mode Voltage,
SFDR
SNRFS
0.70.91.11.3
= 9.7 MHz, f
f
IN
VCM (V)
SAMPLE
= 65 MSPS
10206-043
Rev. 0 | Page 18 of 40
Page 19
Data Sheet AD9257
A
Differential Input Configurations
There are several ways to drive the AD9257 either actively or
passively. However, optimum performance is achieved by driving
the analog input differentially. Using a differential double balun
configuration to drive the AD9257 provides excellent performance
and a flexible interface to the ADC (see Figure 46) for baseband
applications.
For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see
Figure 47), because the noise performance of most amplifiers is
not adequate to achieve the true performance of the AD9257.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
It is not recommended to drive the AD9257 input single-ended.
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9257. VREF can be configured using either the internal 1.0 V
reference or an externally applied 1.0 V reference voltage. The
various reference modes are summarized in the sections that
follow. The VREF pin should be externally decoupled to ground
with a low ESR, 1.0 F capacitor in parallel with a low ESR,
0.1 F ceramic capacitor.
Internal Reference Connection
A comparator within the AD9257 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Tabl e 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 45), setting VREF to 1.0 V.
Table 9. Reference Configuration Summary
Resulting
CORE
0.5V
Differential
Span (V p-p)
2.0
ADC
Selected Mode
Fixed Internal
Reference
Fixed External
Reference
SENSE
Voltage (V)
Resulting
VREF (V)
AGND to 0.2 1.0 internal 2.0
AVDD 1.0 applied
to external
VREF pin
VIN+ x
VIN– x
VREF
0.1µF1.0µF
SENSE
SELECT
LOGIC
ADC
10206-044
Figure 45. Internal Reference Configuration
*C1
R0.1µ F
33
33
C
33
0.1µF0.1µF
5pF
R
33
*C1
R
200
*C1 IS OPTIONAL
VIN+ x
VIN– x
ADC
VCM
C
10206-045
2V p-p
0.1µF
ET1-1-I3
C
0.1µF
C
Figure 46. Differential Double Balun Input Configuration for Baseband Applications
If the internal reference of the AD9257 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 48 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
–2.0
–2.5
ERROR (%)
–3.0
REF
V
–3.5
–4.0
–4.5
–5.0
02.52.01. 51.00.5
Figure 48. V
LOAD CURRENT (mA)
Error vs. Load Current
REF
INTERNAL V
REF
= 1V
3.0
10206-047
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 49 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
2
0
–2
ERROR (mV)
REF
–4
V
–6
–8
–4085
–15103560
TEMPERATURE (° C)
Figure 49. Typical V
REF
Drift
10206-048
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 42). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V. It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9257 sample clock inputs,
CLK+ and CLK−, with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK− pins via a transformer or
capacitors. These pins are biased internally (see Figure 36) and
require no external bias.
Clock Input Options
The AD9257 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the utmost concern, as described in the Jitter Considerations
section.
Figure 50 and Figure 51 show two preferred methods for clocking the AD9257 (at clock rates of up to 520 MHz prior to the
internal CLK divider). A low jitter clock source is converted
from a single-ended signal to a differential signal using either
an RF transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 65 MHz and 520 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9257 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9257 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance. However, the diode capacitance comes
into play at frequencies above 500 MHz. Care must be taken in
choosing the appropriate signal limiting diode.
XFMR
0.1µF
®
0.1µF0.1µF
0.1µF
0.1µF0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
SCHOTTKY
DIODES:
HSMS2822
CLK+
CLK–
CLK+
CLK–
ADC
ADC
10206-050
Mini-Circuits
ADT1-1WT, 1:1 Z
CLOCK
INPUT
50
100
Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
50
0.1µF
Figure 51. Balun-Coupled Differential Clock (65 MHz to 520 MHz)
10206-049
Rev. 0 | Page 20 of 40
Page 21
Data Sheet AD9257
C
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 52. The AD9510/AD9511/AD9512/
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 53. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 F capacitor (see
Figure 54).
Input Clock Divider
The AD9257 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9257 clock divider can be synchronized using the
external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9257 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the performance of the AD9257. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS on.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
CLOCK
INPUT
CLOCK
INPUT
0.1µF
0.1µF
50k50k
AD951x
PECL DRIVER
0.1µF
CLK+
100
0.1µF
240240
CLK–
ADC
10206-051
Figure 52. Differential PECL Sample Clock (Up to 520 MHz)
CLOCK
INPUT
CLOCK
INPUT
0.1µF
0.1µF
50k50k
AD951x
LVDS DRIVE R
0.1µF
100
0.1µF
CLK+
CLK–
ADC
10206-052
Figure 53. Differential LVDS Sample Clock (Up to 520 MHz)
V
CC
0.1µF
1k
1k
AD951x
CMOS DRIVER
LOCK
INPUT
1
50
1
50 RESISTOR IS OPTIONAL.
Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
OPTIONAL
100
0.1µF
0.1µF
CLK+
CLK–
ADC
10206-053
Rev. 0 | Page 21 of 40
Page 22
AD9257 Data Sheet
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
) due only to aperture jitter (tJ) can be calculated by
A
SNR Degradation = 20 log
⎛
⎜
10
⎜
π
2
⎝
⎞
1
⎟
⎟
××
tf
J
A
⎠
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 55).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9257.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
130
RMS CLOCK JITTER REQUIREMENT
120
110
100
90
80
SNR (dB)
70
10 BITS
60
8 BITS
50
40
30
1101001000
Figure 55. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPU T FREQU ENCY (M Hz)
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
16 BITS
14 BITS
12 BITS
10206-054
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 56, the power dissipated by the AD9257 is
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
400
350
65MSPS
80MSPS
10206-055
300
250
ANALOG CO RE POW ER (mW)
200
20MSPS
150
15 20 2530 3540 4550 55 6065
10
Figure 56. Analog Core Power vs. f
SAMPLE RATE (MSPS)
40MSPS
50MSPS
for fIN = 9.7 MHz
SAMPLE
The AD9257 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 1 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the AD9257 to its normal operating
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down cycles
result in proportionally shorter wake-up times. When using the
SPI port interface, the user can place the ADC in power-down
mode or standby mode. Standby mode allows the user to keep
the internal reference circuitry powered when faster wake-up
times are required. See the Memory Map section for more
details on using these features.
Rev. 0 | Page 22 of 40
Page 23
Data Sheet AD9257
DIGITAL OUTPUTS AND TIMING
The AD9257 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
The AD9257 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and the
differential output traces be close together and at equal lengths.
An example of the FCO and data stream with proper trace
length and position is shown in Figure 57. An example of LVDS
output timing in reduced range mode is shown in Figure 58.
FCO 500mV/DI V
DCO 500mV/DIV
DATA 500mV/DIV
Figure 57. LVDS Output Timing Example in ANSI-644 Mode (Default)
5ns/DIV
10206-056
FCO 500mV/DI V
DCO 500mV/DIV
DATA 500mV/DIV
Figure 58. LVDS Output Timing Example in Reduced Range Mode
5ns/DIV
10206-057
Rev. 0 | Page 23 of 40
Page 24
AD9257 Data Sheet
Figure 59 shows an example of the LVDS output using the
ANSI-644 standard (default) data eye and a time interval error
(TIE) jitter histogram with trace lengths of less than 24 inches
on standard FR-4 material.
400
EYE: ALL BITS
300
200
100
0
–100
–200
EYE DIAG RAM VOL TAGE (mV)
–300
–400
–0.8ns
–1.0ns
2.5k
–0.6ns
–0.4ns
–0.2ns
0ns
ULS: 7000:400354
0.4ns
0.2ns
0.8ns
0.6ns
1.0ns
to drive longer trace lengths, which can be achieved by programming Register 0x15. Even though this option produces sharper
rise and fall times on the data edges and is less prone to bit errors,
it also increases the power dissipation of the DRVDD supply.
300
EYE: ALL BITS
200
100
0
–100
–200
EYE DIAG RAM VOLT AGE (mV )
–300
–0.8ns
–1.0ns
2.5k
–0.6ns
–0.4ns
–0.2ns
0ns
ULS: 7000/18200
0.4ns
0.2ns
0.8ns
0.6ns
1.0ns
2.0k
1.5k
1.0k
TIE JITTER HISTOGRAM (Hits)
0.5k
0
0ps
20ps
–60ps
–40ps
–20ps
40ps
s
60ps
80p
10206-058
Figure 59. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less Than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
Figure 60 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Note that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
It is the responsibility of the user to determine if the waveforms
meet the timing budget of the design when the trace lengths exceed
24 inches. Additional SPI options allow the user to further increase
the internal termination (increasing the current) of all eight outputs
2.0k
1.5k
1.0k
TIE JITTER HISTOGRAM (Hits)
0.5k
0
–60ps
–80ps
–40ps
0ps
–20ps
s
20ps
40p
Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
The default format of the output data is twos complement. Tab l e 1 0
shows an example of the output coding format. To change the
output data format to offset binary, see the Memory Map section.
Data from each ADC is serialized and provided on a separate
channel in DDR mode. The data rate for each serial stream is equal
to 14 bits times the sample clock rate, quantity divided by 2,
with a maximum of 455 Mbps (14 bits × 65 MSPS)/2 = 455 Mbps.
The lowest typical conversion rate is 10 MSPS. See the Memory
Map section for details on enabling this feature.
Two output clocks are provided to assist in capturing data from
the AD9257. The DCO is used to clock the output data and is
equal to 7× the sample clock (CLK) rate for the default mode of
operation. Data is clocked out of the AD9257 and must be captured
on the rising and falling edges of the DCO that supports double
data rate (DDR) capturing. The FCO is used to signal the start
of a new output byte and is equal to the sample clock rate (see
the Timing Diagrams section).
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
A 12-bit serial stream can also be initiated from the SPI. This
allows the user to implement and test compatibility to lower
Table 11. Flexible Output Test Modes
Output Test
Mode Bit
Sequence
0000 Off (default) N/A N/A N/A
0001 Midscale short
0010 +Full-scale short
0011 −Full-scale short
0100 Checkerboard
0101 PN sequence long1 N/A N/A Yes PN23
0110 PN sequence short1 N/A N/A Yes PN9
0111
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle
1010 1× sync
1011 One bit high
1100 Mixed frequency
1
All test mode options except PN sequence short and PN sequence long can support 12-bit to 14-bit word lengths to verify data capture to the receiver.
Pattern Name Digital Output Word 1 Digital Output Word 2
resolution systems. When changing the resolution to a 12-bit
serial stream, the data stream is shortened. See Figure 3 for the
12-bit example.
In default mode, as shown in Figure 2, the MSB is first in the
data output serial stream. This can be inverted so that the LSB is
first in the data output serial stream by using the SPI.
There are 12 digital output test pattern options available that can
be initiated through the SPI. This is a useful feature when validating
receiver capture and timing (see Tabl e 11 for the output bit
sequencing options that are available). Some test patterns have
two serial sequential words and can be alternated in various ways,
depending on the test pattern chosen. Note that some patterns
do not adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in Register 0x19,
Register 0x1A, Register 0x1B, and Register 0x1C.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2
9
− 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value
is all 1s (see Tabl e 12 for the initial values). The output is a
parallel representation of the serial PN9 sequence in MSB-first
format. The first output word is the first 14 bits of the PN9
sequence in MSB alig
ned form.
Table 12. PN Sequence
Initial
Sequence
PN Sequence Short 0x1FE0 0x1DF1, 0x3CC8, 0x294E
PN Sequence Long 0x1FFF 0x1FE0, 0x2001, 0x1C00
Value
First Three Output Samples
(MSB First) Twos Complement
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
23
− 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Tab le 1 2 for the initial values) and the
AD9257 inverts the bit stream with relation to the ITU standard.
The output is a parallel representation of the serial PN23 sequence
in MSB-first format. The first output word is the first 14 bits of the
PN23 sequence in MSB aligned format.
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
SDIO/DFS Pin
For applications that do not require SPI mode operation, the
CSB pin is tied to AVDD, and the SDIO/DFS pin controls the
output data format select according to Tab le 1 3.
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test pattern
if it and the CSB pin are both held high during device power-up.
When SCLK/DTP is tied to AVDD, the ADC channel outputs
shift out the following pattern: 10 0000 0000 0000. The FCO and
DCO function normally while all channels shift out the repeatable
test pattern. This pattern allows the user to perform timing
alignment adjustments among the FCO, DCO, and output data.
This pin has an internal 30 kΩ resistor to GND. It can be left
unconnected for normal operation.
Table 14. Digital Test Pattern Pin Settings
Selected DTP DTP Voltage Resulting D± x
Normal Operation No connect Normal operation
DTP AVDD 10 0000 0000 0000
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map section
for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that
do not require SPI mode operation. Tying CSB high causes
all SCLK and SDIO information to be ignored.
RBIAS Pin
To set the internal core bias current of the ADC, place a
10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin.
Table 13. Output Data Format Select Pin Settings
DFS Pin Voltage Output Mode
AVDD Twos complement
GND (Default) Offset binary
Rev. 0 | Page 26 of 40
Page 27
Data Sheet AD9257
BUILT-IN OUTPUT TEST MODES
The AD9257 includes a built-in test feature designed to enable
verification of the integrity of each data output channel, as well
as to facilitate board level debugging. Various output test options
are provided to place predictable values on the outputs of the
AD9257.
OUTPUT TEST MODES
The output test options are described in Ta ble 1 7 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back-end blocks and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Rev. 0 | Page 27 of 40
Page 28
AD9257 Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD9257 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DTP pin, the
SDIO/DFS pin, and the CSB pin (see Table 15). The SCLK
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO (serial data input/
output) is a dual-purpose pin that allows data to be sent to and
read from the internal ADC memory map registers. The CSB
(chip select bar) is an active low control that enables or disables
the read and write cycles.
Table 15. Serial Port Interface Pins
Pin Function
SCLK
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
CSB
Chip select bar. An active low control that gates the read
and write cycles.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 61
and Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB first is the default on
power-up and can be changed via the SPI port configuration
register. For more information about this and other features,
see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CSB
SCLK
SDIO
DON’T CARE
t
t
DS
t
S
R/WW1W0A12A11A10A9A8A7
HIGH
t
LOW
t
DH
Figure 61. Serial Port Interface Timing Diagram
t
CLK
Rev. 0 | Page 28 of 40
D5D4D3D2D1D0
t
H
DON’T CARE
DON’T CAREDON’T CARE
10206-060
Page 29
Data Sheet AD9257
HARDWARE INTERFACE
The pins described in Ta b l e 15 comprise the physical interface
between the user programming device and the serial port of the
AD9257. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9257 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Tab l e 1 6 describes the strappable functions supported
on the AD9257.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DFS pin, the SCLK/DTP pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
pins as static control lines for the output data format, output
digital test pattern, and power-down feature control. In this
mode, CSB should be connected to AVDD, which disables the
serial port interface.
When the device is in SPI mode, the PDWN pin (if enabled)
remains active. For SPI control of power-down, the PDWN pin
should be set to its default state.
SPI ACCESSIBLE FEATURES
Tabl e 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9257 part-specific features are described in detail
in the Memory Map Register Descriptions section following
Tabl e 17 , the external memory map register table.
Table 16. Features Accessible Using the SPI
Feature Name Description
Mode
Clock
Offset
Tes t I /O
Output Mode Allows the user to set the output mode
Output Phase Allows the user to set the output clock polarity
ADC Resolution
and Speed Grade
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the clock
divider, set the clock divider phase, and enable
the sync
Allows the user to digitally adjust the converter
offset
Allows the user to set test modes to have
known data on output bits
Scalable power consumption options based on
resolution and speed grade selection
Rev. 0 | Page 29 of 40
Page 30
AD9257 Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit
locations. The memory map is roughly divided into three
sections: the chip configuration registers (Address 0x00
to Address 0x02); the device index and transfer registers
(Address 0x05 and Address 0xFF); and the global ADC
functions registers, including setup, control, and test
(Address 0x08 to Address 0x109).
The memory map register table (see Tab l e 1 7 ) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x05, the device
index register, has a hexadecimal default value of 0x3F. This
means that in Address 0x05, Bits[7:6] = 0, and the remaining
Bits[5:0] = 1. This setting is the default channel index setting.
The default value results in both ADC channels receiving the
next write command. For more information on this function
and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF. The
remaining registers are documented in the Memory Map
Register Descriptions section.
Open Locations
All address and bit locations that are not included in Tab l e 1 7
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open or not listed in Tabl e 17 (for example, Address 0x13) this
address location should not be written.
Default Values
After the AD9257 is reset, critical registers are loaded with
default values. The default values for the registers are given in
Tabl e 17 , the memory map register table.
Logic Levels
An explanation of logic level terminology follows:
• “Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated
for each channel. These registers and bits are designated in
Tabl e 17 as local. These local registers and bits can be accessed
by setting the appropriate data channel bits (A, B, C, or D) and
the clock channel DCO/FCO bits (Bits[5:4]) in Register 0x05. If
all the bits are set, the subsequent write affects the registers of
all channels and the DCO/FCO clock channels. In a read cycle,
only one of the channels, A, B, C, or D, should be set to read
one of the four registers. If all the bits are set during a SPI read
cycle, the part returns the value for Channel A. Registers and
bits designated as global in Tabl e 17 affect the entire part or the
channel features for which independent settings are not allowed
between channels. The settings in Register 0x05 do not affect
the global registers and bits.
Rev. 0 | Page 30 of 40
Page 31
Data Sheet AD9257
MEMORY MAP REGISTER TABLE
The AD9257 uses a 3-wire interface and 16-bit addressing and,
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Register 0x00, Bit 5 is set high, the
Table 17. Memory Map Register Table
Reg.
Addr.
(Hex)
Chip Configuration Registers
0x00
0x01 Chip ID (global) 8-bit chip ID, Bits[7:0]
0x02
Device Index and Transfer Registers
0x04 Device Index 2 Open Open Open Open
0x05 Device Index 1 Open Open
0xFF Transfer Open Open Open Open Open Open Open
Global ADC Functions
0x08
0x09 Clock (global) Open Open Open Open Open Open Open
Register Name
SPI port
configuration
Chip grade
(global)
Power modes
(global)
Bit 7
(MSB)
0 = SDO
active
Open Speed grade ID, Bits[6:4]
Open Open
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
LSB first Soft reset
AD9257 0x92 = octal 14-bit, 40 MSPS/65 MSPS serial LVDS
001 = 40 MSPS
011 = 65 MSPS
Clock
Channel
DCO
External
powerdown pin
function
0 = full
powerdown
1 =
standby
1 =
16-bit
address
Clock
Channe
l FCO
Open Open Open
SPI enters a soft reset, where all of the user registers revert to
their default values and Bit 2 is automatically cleared.
Default
1 = 16-bit
address
Open Open Open Open
Data
Channel H
Data
Channel D
Soft reset LSB first
Data
Channel G
Data
Channel C
Data
Channel F
Data
Channel B
Internal power-down
00 = chip run
01 = full power-down
10 = standby
11 = reset
0 = SDO
active
Data
Channel E
Data
Channel A
Initiate
override
mode
Duty cycle
stabilize
0 = off
1 = on
Value
(Hex)
0x18
Read
only
0x92
Read
only
0xF
0x3F
0x00
0x00
0x01
Comments
The nibbles
are mirrored
so that LSB
or MSB first
mode registers
correctly. The
default for the
ADCs is 16-bit
mode.
Unique chip ID
that is used to
differentiate
devices; read
only.
Unique
speed grade
ID used to
differentiate
graded
devices.
Read only.
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Set resolution/
sample rate
override.
Determines
various
generic modes
of chip
operation.
Turns duty
cycle stabilizer
on or off.
Rev. 0 | Page 31 of 40
Page 32
AD9257 Data Sheet
Reg.
Addr.
(Hex)
0x0B Clock divide
0x0C
0x0D
0x10 Offset adjust (local)
0x14 Output mode Open
0x15 Output adjust Open Open
0x16 Output phase Open Input clock phase adjust, Bits[6:4]
0x18 V
Register Name
(global)
Enhancement
control
Test mode (local
except for PN
sequence resets)
Open Open Open Open Open Internal V
REF
Bit 7
(MSB)
Open Open Open Open Open
Open Open Open Open Open
User input test mode
(affects user input test
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Reset PN
00 = single
01 = alternate
10 = single once
11 = alternate once
mode only,
Bits[3:0] = 1000)
Offset adjust in LSBs from +127 to −128 (twos complement format)
LVDS-ANSI/
LVDS-IEEE
option
0 = LVDSANSI
1 = LVDSIEEE reduced
range link
(global);
(see Table 18)
(value is number of input clock cycles
long gen
Open Open Open
of phase delay)
(see Table 19)
8-bit device offset adjustment, Bits[7:0] (local)
Output driver
Reset
PN
short
gen
termination,
Bits[1:0]
00 = none
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
Clock divide ratio, Bits[2:0]
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
Output
invert
(local)
Open Open Open
Output clock phase adjust, Bits[3:0]
(Setting = 0000 through 1011)
Open Open 0x00
Open
(see Table 20)
adjustment
REF
digital scheme, Bits[2:0]
000 = 1.0 V p-p
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.6 V p-p
100 = 2.0 V p-p
Output
format
0 = offset
binary
1 = twos
complement
(global)
Output
drive
0 = 1×
drive
1 = 2×
drive
Default
Value
(Hex)
0x00
0x00
0x00
0x01
0x00
0x03
0x04
Comments
The divide
ratio is the
value plus 1.
Enables/
disables chop
mode.
When set, the
test data is
placed on the
output pins in
place of
normal data.
Device offset
trim.
Configures the
outputs and
the format of
the data.
Determines
LVDS or
other output
properties.
On devices
that use global
clock divide,
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal
latching is
unaffected.
Selects and/or
adjusts the
V
.
REF
Rev. 0 | Page 32 of 40
Page 33
Data Sheet AD9257
Reg.
Addr.
(Hex)
0x19
0x1A
0x1B
0x1C
0x21
0x22
0x100
0x101 User I/O Control 2 Open Open Open Open Open Open Open
Serial stream
control.
Default causes
MSB first and
the native bit
stream.
Used to power
down
individual
sections of
a converter.
Resolution/
sample rate
override
(requires
transfer bit,
0xFF).
Disables SDIO
pull-down.
Rev. 0 | Page 33 of 40
Page 34
AD9257 Data Sheet
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Device Index (Register 0x04 and Register 0x05)
There are certain features in the map that can be set
independently for each channel, whereas other features apply
globally to all channels (depending on context), regardless of
which are selected. The first four bits in Register 0x04 and
Register 0x05 can be used to select which individual data channels
are affected. The output clock channels can be selected in
Register 0x05, as well. A smaller subset of the independent
feature list can be applied to those devices.
Transfer (Register 0xFF)
All registers except Register 0x100 are updated the moment
they are written. Setting Bit 0 of this transfer register high
initializes the settings in the ADC sample rate override register
(Address 0x100).
Power Modes (Register 0x08)
Bits[7:6]—Open
Bit 5—External Power-Down Pin Function
If set, the external PDWN pin initiates standby mode. If cleared,
the external PDWN pin initiates power-down mode.
Bits[4:2]—Open
Bits[1:0]—Internal Power-Down Mode
In normal operation (Bits[1:0] = 00), all ADC channels are
active.
In power-down mode (Bits[1:0] = 01), the digital data path clocks
are disabled while the digital data path is reset. Outputs are
disabled.
In standby mode (Bits[1:0] = 10), the digital data path clocks
and the outputs are disabled.
During a digital reset (Bits[1:0] = 11), all the digital data path
clocks and the outputs (where applicable) on the chip are reset,
except the SPI port. Note that the SPI is always left under
control of the user, that is, it is never automatically disabled or
in reset (except by power-on reset).
Enhancement Control (Register 0x0C)
Bits[7:3]—Open
Bit 2—Chop Mode
For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct conversion
receivers, chopping in the first stage of the AD9257 is a feature
that can be enabled by setting Bit 2. In the frequency domain,
chopping translates offsets and other low frequency noise to
f
/2, where they can be filtered.
CLK
Bits[1:0]—Open
Rev. 0 | Page 34 of 40
Output Mode (Register 0x14)
Bit 7—Open
Bit 6—LVDS-ANSI/LVDS-IEEE Option
Setting this bit chooses the LVDS-IEEE (reduced range) option.
The default setting is LVDS-ANSI. As described in Ta b le 1 8,
when LVDS-ANSI or LVDS-IEEE reduced range link is selected,
the user can select the driver termination. The driver current
is automatically selected to give the proper output swing.
Table 18. LVDS-ANSI/LVDS-IEEE Options
Output
Mode,
Bit[6] Output Mode
0 LVDS-ANSI
1
LVDS-IEEE
reduced range
link
Output
Driver
Termination
User
selectable
User
selectable
Output Driver
Current
Automatically
selected to give
proper swing
Automatically
selected to give
proper swing
Bits[5:3]—Open
Bit 2—Output Invert
Setting this bit inverts the output bit stream.
Bit 1—Open
Bit 0—Output Format
By default, this bit is set to send the data output in twos
complement format. Resetting this bit changes the output mode
to offset binary.
Output Adjust (Register 0x15)
Bits[7:6]—Open
Bits[5:4]—Output Termination
These bits allow the user to select the internal termination
resistor.
Bits[3:1]—Open
Bit 0—Output Drive
Bit 0 of the output adjust register controls the drive strength on
the LVDS driver of the FCO and DCO outputs only. The default
values set the drive to 1×. The drive can be increased to 2× by
setting the appropriate channel bit in Register 0x05 and then
setting Bit 0. These features cannot be used with the output driver
termination select. The termination selection takes precedence
over the 2× driver strength on FCO and DCO when both the
output driver termination and output drive are selected.
DCO Phase Adjustment
(Degrees Relative to D± x Edge)
Resolution/Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 k pull-down on the
SDIO pin, which can be used to limit loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.
Bits[2:0]—Open
Rev. 0 | Page 35 of 40
Page 36
AD9257 Data Sheet
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9257 as a system,
it is recommended that the designer become familiar with these
guidelines, which describes the special circuit connections and
layout requirements that are needed for certain pins.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9257, it is recommended that
two separate 1.8 V supplies be used. Use one supply for analog
(AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9257. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed pad on the underside of the ADC be
connected to analog ground (AGND) to achieve the best electrical
and thermal performance of the AD9257. An exposed continuous
copper plane on the PCB should mate to the AD9257 exposed
pad, Pin 0. The copper plane should have several vias to achieve
the lowest possible resistive thermal path for heat dissipation to
flow through the bottom of the PCB. These vias should be
solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
guarantees only one tie point. For detailed information on
packaging and the PCB layout of chip scale packages, see the
AN-772 Application Note, A Design and Manufacturing Guide for
the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 F
capacitor.
REFERENCE DECOUPLING
The VREF pin should be externally decoupled to ground with a
low ESR, 1.0 F capacitor in parallel with a low ESR, 0.1 F
ceramic capacitor.
SPI PORT
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9257 to keep these signals from transitioning at the con-
verter inputs during critical sampling periods.
Rev. 0 | Page 36 of 40
Page 37
Data Sheet AD9257
OUTLINE DIMENSIONS
49
48
0.60 MAX
EXPOSED PAD
(BOTTOM VIEW)
PIN 1
64
INDICATOR
1
6.35
6.20 SQ
6.05
PIN 1
INDICATOR
9.00
BSC SQ
TOP VIEW
8.75
BSC SQ
0.60
MAX
0.50
BSC
1.00
0.85
0.80
SEATING
PLANE
12° MAX
0.50
0.40
0.30
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
0.05 MAX
0.02 NOM
0.20 REF
33
32
7.50
REF
16
17
FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIO NS
SECTION O F THIS DAT A SHEET.
0.25 MIN
091707-C
Figure 62. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9257BCPZ-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4
AD9257BCPZRL7-40 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4
AD9257BCPZ-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4
AD9257BCPZRL7-65 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4
AD9257-65EBZ Evaluation Board