1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.4 dBm/Hz small signal input noise with 200 Ω input
impedance @ 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
1.8 V Analog-to-Digital Converter
AD9255
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and
TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
PRODUCT HIGHLIGHTS
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs .
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
5. Pin compatibility with the AD9265, allowing a simple
migration up to 16 bits.
FUNCTIONAL BLOCK DIAGRAM
RBIASSENSEPDWN
VREF
VCM
VIN+
VIN–
DITHER
CLK+
CLK–
SYNC
REFERENCE
TRACK-AND-HOLD
CLOCK
MANAGEMENT
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter
(ADC). The AD9255 is designed to support communications
applications where high performance combined with low cost,
small size, and versatility is desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic to
provide 14-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
The ADC features a wide bandwidth differential sample-andhold analog input amplifier supporting a variety of user-selectable
input ranges. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9255 is suitable for applications in communications,
instrumentation, and medical imaging.
A differential clock input controls all internal conversion cycles. A
duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to
maintain excellent performance over a wide range of input
clock duty cycles. An integrated voltage reference eases design
considerations.
The ADC output data format is either parallel 1.8 V CMOS or
LVDS (DDR). A data output clock is provided to ensure proper
latch timing with receiving logic.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface. Flexible power-down options
allow significant power savings, when desired. An optional onchip dither function is available to improve SFDR performance
with low power analog input signals.
The AD9255 is available in a Pb-free, 48-lead LFCSP and is
specified over the industrial temperature range of −40°C to +85°C.
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND AVDD V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Capacitance Full 4 pF
Input Resistance Full 8 10 12 kΩ
SYNC INPUT
Logic Compliance CMOS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Capacitance Full 1 pF
Input Resistance Full 12 16 20 kΩ
Rev. A | Page 6 of 44
Page 7
AD9255
Parameter Temperature Min Typ Max Unit
LOGIC INPUT (CSB)1
High Level Input Voltage Full 1.22 SVDD V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 40 132 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK/DFS)2
High Level Input Voltage Full 1.22 SVDD V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current (VIN = 1.8 V) Full −92 −135 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage Full 1.22 SVDD V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 38 128 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
High Level Output Voltage Full 1.70 V
Low Level Output Voltage Full 0.2 V
LOGIC INPUTS (OEB, PDWN, DITHER, LVDS, LVDS_RS)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current (VIN = 1.8 V) Full −90 −134 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS (DRVDD = 1.8 V)
CMOS Mode
High Level Output Voltage
IOH = 50 μA Full 1.79 V
IOH = 0.5 mA Full 1.75 V
Low Level Output Voltage
IOL = 1.6 mA Full 0.2 V
IOL = 50 μA Full 0.05 V
LVDS Mode
ANSI Mode
Differential Output Voltage (VOD) Full 290 345 400 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Reduced Swing Mode
Differential Output Voltage (VOD) Full 160 200 230 mV
Output Offset Voltage (VOS) Full 1.15 1.25 1.35 V
Enabled or DCS Disabled3
Aperture Delay (tA) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.07 0.07 0.07 ps rms
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay (tPD) Full 2.4 2.8 3.4 2.4 2.8 3.4 2.4 2.8 3.4 ns
DCO Propagation Delay (t
DCO to Data Skew (t
SKEW
Pipeline Delay (Latency) Full 12 12 12 Cycles
LVDS Mod e
Data Propagation Delay (tPD) Full 2.6 3.4 4.2 2.6 3.4 4.2 2.6 3.4 4.2 ns
DCO Propagation Delay (t
DCO to Data Skew (t
SKEW
Pipeline Delay (Latency) Full 12.5 12.5 12.5 Cycles
Wake-Up Time5 Full 500 500 500 μs
OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles
1
The suffix following the part number refers to the model found in the section. Ordering Guide
2
Conversion rate is the clock rate after the divider.
3
See the section for additional information on using the DCS with the input clock divider. Input Clock Divider
4
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see). Table 17
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
) Full 12.5 9.5 8 ns
CLK
3
Full 0.8 0.8 0.8 ns
Full 0.8 0.8 0.8 ns
)4 Full 2.7 3.4 4.2 2.7 3.4 4.2 2.7 3.4 4.2 ns
DCO
) Full 0.3 0.6 0.9 0.3 0.6 0.9 0.3 0.6 0.9 ns
)4 Full 3.3 3.8 4.3 3.3 3.8 4.3 3.3 3.8 4.3 ns
DCO
) −0.3 +0.4 +1.2 −0.3 +0.4 +1.2 −0.3 +0.4 +1.2
Rev. A | Page 8 of 44
Page 9
AD9255
TIMING SPECIFICATIONS
Table 5.
Parameter Conditions Min Typ Max Unit
SYNC TIMING REQUIREMENTS
t
SYNC to rising edge of CLK setup time 0.30 ns
SSYNC
t
SYNC to rising edge of CLK hold time 0.40 ns
HSYNC
SPI TIMING REQUIREMENTS1
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
t
Period of the SCLK 40 ns
CLK
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
t
SCLK pulse width high 10 ns
HIGH
t
SCLK pulse width low 10 ns
LOW
t
EN_SDIO
t
DIS_SDIO
1
Refer to for a detailed timing diagram. Figure 84
Timing Diagrams
D0/1+ TO D12/D13+
D0/1– TO D12/D13–
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
VIN
CLK+
CLK–
DCO/DCO+
DCO–
LVDS (DDR) MODE
CMOS MODE
D0 TO D13
NOTES
1. DEx DENOTES EVEN BIT.
2. DOx DENOTES ODD BIT .
N – 1
t
CHtCL
t
DCO
t
A
N
N + 1
t
CLK
t
SKEW
t
PD
DEx
DOx
– 12
– 12
Dx – 12Dx – 11Dx – 10Dx – 9Dx – 8
DEx
– 11
N + 2
DOx
– 11
DEx
– 10
N + 3
DOx
– 10
Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing
10 ns
10 ns
DEx
N + 4
DOx
– 9
– 9
DEx
N + 5
DOx
– 8
– 8
08505-002
CLK+
t
HSYNC
08505-104
SYNC
t
SSYNC
Figure 3. SYNC Input Timing Requirements
Rev. A | Page 9 of 44
Page 10
AD9255
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0V
SVDD to AGND −0.3 V to +3.6 V
VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to AGND −0.3 V to AVDD + 0.2 V
VREF to AGND −0.3 V to AVDD + 0.2 V
SENSE to AGND −0.3 V to AVDD + 0.2 V
VCM to AGND −0.3 V to AVDD + 0.2 V
RBIAS to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to SVDD +0.3 V
SCLK/DFS to AGND −0.3 V to SVDD +0.3 V
SDIO/DCS to AGND −0.3V to SVDD + 0.3 V
OEB to AGND −0.3 V to DRVDD + 0.2 V
PDWN to AGND −0.3 V to DRVDD + 0.2 V
LVDS to AGND −0.3 V to AVDD + 0.2 V
LVD S_RS to AG ND −0.3 V to AVDD + 0.2 V
DITHER to AGND −0.3 V to AVDD + 0.2 V
D0 through D13 to AGND
DCO to AGND
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
Environmental
Operating Temperature Range
−40°C to +85°C
(Ambient)
Maximum Junction Temperature
150°C
Under Bias
Storage Temperature Range
−65°C to +150°C
(Ambient)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Typical θ
plane. As shown, airflow improves heat dissipation, which
reduces θ
leads from metal traces, through holes, ground, and power
planes, reduces the θ
Table 7. Thermal Resistance
Packa ge Type
48-Lead LFCSP
(CP-48-8)
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
ESD CAUTION
is specified for a 4-layer PCB with a solid ground
JA
. In addition, metal in direct contact with the package
JA
.
JA
Airflow
Veloc ity
(m/s) θ
1, 2
1, 3
θ
JA
JC
1, 4
θ
JB
0 24.5 1.3 12.7 °C/W
1.0 21.4 °C/W
2.5 19.2 °C/W
Unit
Rev. A | Page 10 of 44
Page 11
AD9255
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PDWN
RBIAS
VCM
AVDD
LVDS
VIN–
VIN+
LVDS_RS
DNC
DNC
VREF
4847464544434241403938
SENSE
37
D11
AVDD36
35
DITHER
34
AVDD
33
SVDD
32
CSB
31
SCLK/DFS
30
SDIO/DCS
29
DRVDD
28
DNC
27
OR
26
D13 (MSB)
25
D12
08505-003
SYNC
1
CLK+
2
CLK–
3
AVDD
4
AVDD
5
OEB
6
DNC
7
DCO
8
DNC
9
DNC
10
D0 (LSB)
11
D1
12
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERM AL P AD ON THE BOTTOM OF THE PACKAGE
PROVIDES T HE ANALOG GRO UND F OR THE INPUT. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPE R OPERATIO N.
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No. Mnemonic Type Description
ADC Power Supplies
13, 20, 29 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
4, 5, 34, 36, 45 AVDD Supply Analog Power Supply (1.8 V Nominal).
33 SVDD Supply SPI Input/Output Voltage
7, 9, 10, 28, 39, 40 DNC Do Not Connect.
0 AGND Ground
Analog Ground. The exposed thermal pad on the bottom of the package provides
the analog ground for the input. This exposed pad must be connected to ground for
proper operation.
ADC Analog
42 VIN+ Input Differential Analog Input Pin (+).
43 VIN− Input Differential Analog Input Pin (−).
38 VREF Input/output Voltage Reference Input/Output.
37 SENSE Input Voltage Reference Mode Select. See Ta ble 11 for details.
47 RBIAS Input/output External Reference Bias Resistor.
46 VCM Output Common-Mode Level Bias Output for Analog Inputs.
2 CLK+ Input ADC Clock Input—True.
3 CLK− Input ADC Clock Input—Complement.
Digital Input
1 SYNC Input Digital Synchronization Pin. Slave mode only.
Digital Outputs
11 D0 (LSB) Output CMOS Output Data.
12 D1 Output CMOS Output Data.
14 D2 Output CMOS Output Data.
15 D3 Output CMOS Output Data.
16 D4 Output CMOS Output Data.
17 D5 Output CMOS Output Data.
18 D6 Output CMOS Output Data.
19 D7 Output CMOS Output Data.
21 D8 Output CMOS Output Data.
In external pin mode, this pin sets dither to on (active high). Pull low for control via
SPI in SPI mode.
In external pin mode, this pin sets LVDS reduced swing output mode (active high).
Pull low for control via SPI in SPI mode.
In external pin mode, this pin sets LVDS output mode (active high). Pull low for
control via SPI in SPI mode.
Power-down input in external pin mode. In SPI mode, this input can be configured
as power-down or standby.
Rev. A | Page 12 of 44
Page 13
AD9255
PDWN
RBIAS
VCM
AVDD
LVDS
VIN–
VIN+
LVDS_RS
DNC
DNC
VREF
4847464544434241403938
SENSE
37
D10/11+
AVDD36
35
DITHER
34
AVDD
33
SVDD
32
CSB
31
SCLK/DFS
30
SDIO/DCS
29
DRVDD
28
OR+
27
OR–
26
D12/13+
25
D12/13–
08505-004
SYNC
1
CLK+
2
CLK–
3
AVDD
4
AVDD
5
OEB
6
DCO–
7
DCO+
8
DNC
9
DNC
10
D0/1–
11
D0/1+
12
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THE RM AL PAD ON THE BOTTOM O F THE PACKAGE
PROVIDES T HE ANALOG GRO UND F OR THE PART. THIS EXPOSED PAD
MUST BE CONNECT E D TO GROUND FOR PROPER O PE RATION.
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No. Mnemonic Type Description
ADC Power Supplies
13, 20, 29 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
4, 5, 34, 36, 45 AVDD Supply Analog Power Supply (1.8 V Nominal).
33 SVDD Supply SPI Input/Output Voltage.
9, 10, 39, 40 DNC Do Not Connect.
0 AGND Ground
Analog Ground. The exposed thermal pad on the bottom of the package provides the
analog ground for the input. This exposed pad must be connected to ground for proper
operation.
ADC Analog
42 VIN+ Input Differential Analog Input Pin (+).
43 VIN− Input Differential Analog Input Pin (−).
38 VREF Input/output Voltage Reference Input/Output.
37 SENSE Input Voltage Reference Mode Select. See Table 11 for details.
47 RBIAS Input/output External Reference Bias Resistor.
46 VCM Output Common-Mode Level Bias Output for Analog Inputs.
2 CLK+ Input ADC Clock Input—True.
3 CLK− Input ADC Clock Input—Complement.
Digital Input
1 SYNC Input Digital Synchronization Pin. Slave mode only.
Digital Outputs
12 D0/1+ Output LVDS Output Data Bit 0/Bit 1 (LSB)—True.
11 D0/1− Output LVDS Output Data Bit 0/Bit 1 (LSB)—Complement.
15 D2/3+ Output LVDS Output Data Bit 2/Bit 3—True.
14 D2/3− Output LVDS Output Data Bit 2/Bit 3—Complement.
17 D4/5+ Output LVDS Output Data Bit 4/Bit 5—True.
16 D4/5− Output LVDS Output Data Bit 4/Bit 5—Complement.
19 D6/7+ Output LVDS Output Data Bit 6/Bit 7—True.
18 D6/7− Output LVDS Output Data Bit 6/Bit 7—Complement.
22 D8/9+ Output LVDS Output Data Bit 8/Bit 9 —True.
21 D8/9− Output LVDS Output Data Bit 8/Bit 9—Complement.
Rev. A | Page 13 of 44
Page 14
AD9255
Pin No. Mnemonic Type Description
24 D10/11+ Output LVDS Output Data Bit 10/Bit 11—True.
23 D10/11− Output LVDS Output Data Bit 10/Bit 11—Complement.
26 D12/13+ (MSB) Output LVDS Output Data Bit 12/Bit 13—True.
25 D12/13− (MSB) Output LVDS Output Data Bit 12/Bit 13—Complement.
28 OR+ Output LVDS Overrange Output—True.
27 OR− Output LVDS Overrange Output—Complement.
8 DCO+ Output LVDS Data Clock Output—True.
7 DCO− Output LVDS Data Clock Output—Complement.
SPI Control
31 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
30 SDIO/DCS Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
32 CSB Input SPI Chip Select (Active Low).
ADC Configuration
6 OEB Input Output Enable Input (Active Low).
35 DITHER Input
41 LVDS_RS Input
44 LVDS Input
48 PDWN Input
In external pin mode, this pin sets dither to on (active high). Pull low for control via SPI
in the SPI mode.
In external pin mode, this pin sets LVDS reduced swing output mode (active high). Pull
low for control via SPI in the SPI mode.
In external pin mode, this pin sets LVDS output mode (active high). Pull low for control
via SPI in the SPI mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as
power-down or standby.
Rev. A | Page 14 of 44
Page 15
AD9255
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, sample rate = 125 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input,
VIN = −1.0 dBFS, and 32k sample, T
Figure 31. AD9255-125 Single-Tone FFT with fIN = 30.3 MHz
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
0 102030605040
08505-130
SECOND
HARMONIC
FREQUENCY (MHz)
THIRD
HARMONIC
08505-133
Figure 33. AD9255-125 Single-Tone FFT with fIN = 140.1 MHz
0
125MSPS
200.3MHz @ –1dBF S
SNR = 74.5dB (75.5d BFS)
–20
SFDR = 80.0dBc
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
0 102030605040
08505-131
THIRD
HARMONIC
SECOND
HARMONIC
FREQUENCY (MHz)
08505-134
Figure 34. AD9255-125 Single-Tone FFT with fIN = 200.3 MHz
0
125MSPS
70.1MHz @ –1dBFS
SNR = 77.3dB (78.3d BFS)
–20
SFDR = 93.9dBc
–40
–60
–80
SECOND
HARMONIC
AMPLITUDE (dBFS)
–100
–120
–140
0 102030605040
THIRD
HARMONIC
FREQUENCY (MHz)
Figure 32. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz
08505-132
Rev. A | Page 19 of 44
0
125MSPS
220.1MHz @ –1dBF S
SNR = 74.2dB (75.2d BFS)
–20
SFDR = 79.8dBc
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
0 102030605040
FREQUENCY (MHz)
THIRD
HARMONIC
SECOND
HARMONIC
Figure 35. AD9255-125 Single-Tone FFT with fIN = 220.1 MHz
08505-135
Page 20
AD9255
0
125MSPS
70.1MHz @ –6dBFS
SNR = 72.6dB (78.6d BFS)
–20
SFDR = 99.7dBc
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
SECOND
HARMONIC
THIRD
HARMONIC
120
100
80
60
40
SNR/SFDR (d Bc AND d BFS)
20
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS )
SNR (dBc)
–140
0 102030605040
FREQUENCY (MHz)
08505-136
Figure 36. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz @ −6 dBFS with
Dither Enabled
125MSPS
0
70.1MHz @ –23dBFS
SNR = 56.4dBc (79.4dBFS)
–15
SFDR = 75.8dBc
–30
–45
–60
–75
AMPLITUDE (dBFS)
–90
–105
–120
–135
2
+
5
FREQUENCY (MHz)
3
4
6
6054484236302418126
08505-137
Figure 37. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS with
Dither Disabled, 1M Sample
125MSPS
0
70.1MHz @ –23dBFS
SNR = 55.9dBc (78.9dBFS)
–15
SFDR = 86.6dBc
–30
–45
–60
–75
–90
AMPLITUDE (dBFS)
–105
–120
–135
+
2
4
5
3
6
0
–100–80–90–70 –60 –50 –40 –30 –20 –100
INPUT AMPL ITUDE (dBFS )
08505-139
Figure 39. AD9255-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
= 2.4 MHz
f
IN
120
100
80
60
40
SNR/SFDR (d Bc AND d BFS)
20
0
–100–80–90–70 –60 –50 –40 –30 –20 –100
SNR (dBFS)
SFDR (dBc)
INPUT AMPL ITUDE (dBFS )
SFDR (dBFS )
SNR (dBc)
08505-140
Figure 40. AD9255-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
= 98.12 MHz
f
IN
120
SFDRF S (DITHER ON)
110
100
90
SNR/SFDR (dBFS)
80
SFDRFS (DITHER OFF)
SNRFS (DITHER O F F )
SNRFS (DITHE R ON)
FREQUENCY (MHz)
6054484236302418126
08505-138
Figure 38. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS with
Dither Enabled, 1M Sample
Rev. A | Page 20 of 44
70
–100–80–90–70 –60 –50 –40 –30 –20 –100
INPUT AMPL ITUDE (dBFS )
08505-141
Figure 41. AD9255-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
= 30 MHz With and Without Dither Enabled
f
IN
Page 21
AD9255
SNR/SFDR (dBFS/dBc)
100
95
90
85
80
75
70
SFDR @ –40°C
SFDR @ +25°C
SFDR @ +85°C
SNR @ –40°C
SNR @ +25°C
SNR @ +85°C
SFDR/IM D3 ( dBc AND dBFS)
–20
–40
–60
–80
–100
–120
0
IMD3 (dBc)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBFS)
65
050100150200250300
INPUT FREQ UE NCY ( M Hz )
Figure 42. AD9255-125 Single-Tone SNR/SFDR vs.
Input Frequency (f
95
90
85
80
75
SNR/SFDR (dBFS/dBc)
70
65
030025020015010050
) and Temperature with 2 V p-p Full Scale
IN
SFDR
SNR
INPUT FREQ UE NCY ( M Hz )
Figure 43. AD9255-125 Single-Tone SNR/SFDR vs.
) with 1 V p-p Full Scale
IN
0
–20
–40
IMD3 (dBc)
–60
Input Frequency (f
SFDR (dBc)
–140
–90–6–18–30–42–54–66–78
08505-142
INPUT AMPL ITUDE (dBFS)
08505-145
Figure 45. AD9255-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
= 169.1 MHz, f
with f
IN1
0
125MSPS
29.1MHz @ –7dBFS
32.1MHz @ –7dBFS
–20
SFDR = 94.4dBc
–40
–60
–80
AMPLITUDE (dBFS)
–100
–120
–140
08505-143
(101.4dBFS)
0 102030605040
Figu re 46. AD9255-125 Two-Tone FFT with f
0
125MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
–20
SFDR = 79.5d Bc (86.5dBFS )
–40
–60
= 172.1 MHz, fS = 125 MSPS
IN2
FREQUENCY (MHz)
= 29.1 MHz and f
IN1
= 32.1 MHz
IN2
08505-146
–80
SFDR (dBFS )
IMD3 (dBFS)
INPUT AMPL ITUDE (dBFS)
SFDR/IM D3 ( dBc AND dBFS)
–100
–120
–140
–90–6–18–30–42–54–66–78
Figure 44. AD9255-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with f
= 29.1 MHz, f
IN1
= 32.1 MHz, fS = 125 MSPS
IN2
08505-144
Rev. A | Page 21 of 44
–80
AMPLITUDE (dBFS)
–100
–120
–140
0 102030605040
FREQUENCY (MHz)
Figure 47. AD9255-125 Two-Tone FFT with f
f
= 172.1 MHz
IN2
= 169.1 MHz and
IN1
08505-147
Page 22
AD9255
105
100
95
0.50
0.25
90
85
SNR/SFDR (dBFS/dBc)
80
75
2512511510595857565554535
SFDR
SNR
SAMPLE RATE (MSPS)
Figure 48. AD9255-125 Single-Tone SNR/SFDR vs. Sample Rate (fS)
= 70.1 MHz
with f
IN
1.4M
1.2M
1.0M
800k
600k
NUMBER OF HITS
400k
200k
0
N – 3N – 2N – 1NN + 1N + 2N + 3
OUTPUT CODE
0.63 LSB RMS
Figure 49. AD9255-125 Grounded Input Histogram
1.0
0.8
0.6
0.4
0.2
–0.2
INL ERROR (LS B)
–0.4
–0.6
–0.8
–1.0
INL WITHOUT DITHER
INL WITH DITHER
0
016,00014,00012,00010,0008000600040002000
OUTPUT CO DE
Figure 50. AD9255-125 INL with fIN = 12.5 MHz
0
DNL ERROR (LSB )
–0.25
–0.50
016,00014,00012,00010,0008000600040002000
08505-148
OUTPUT CO DE
08505-151
Figure 51. AD9255-125 DNL with fIN = 12.5 MHz
100
90
80
70
60
SNR/SFDR (d BFS AND dBc)
50
40
0.751.201.151.101.051.000.950.900.850.80
08505-149
INPUT COMMON-MODE VOLTAGE (V)
SFDR (dBc)
SFDR (dBFS)
08505-152
Figure 52. AD9255-125 SNR/SFDR vs. Input Common Mode (VCM)
= 30 MHz
with f
IN
08505-150
Rev. A | Page 22 of 44
Page 23
AD9255
EQUIVALENT CIRCUITS
DRVDD
VIN+ OR
VIN–
PAD
CLK+
Figure 53. Equivalent Analog Input Circuit
AVDD
0.9V
10kΩ10kΩ
Figure 54. Equivalent Clock Input Circuit
AVDD
VREF
6kΩ
Figure 55. Equivalent VREF Circuit
AVDD
08505-005
08505-007
Figure 57. Digital Output
SVDD
26kΩ
CLK–
SDIO/DCS
08505-006
350Ω
8505-008
Figure 58. Equivalent SDIO/DCS Circuit
SVDD
SCLK/DFS
08505-012
350Ω
26kΩ
08505-009
Figure 59. Equivalent SCLK/DFS Input Circuit
SVDD
SENSE
350Ω
Figure 56. Equivalent SENSE Circuit
08505-010
Rev. A | Page 23 of 44
26kΩ
CSB
350Ω
08505-011
Figure 60. Equivalent CSB Input Circuit
Page 24
AD9255
A
PDWN
350Ω
26kΩ
Figure 61. Equivalent PDWN Circuit
DRVDD
DITHER,
LVDS OR
LVDS_RS
08505-061
Figure 63. Equivalent DITHER, LVDS, and LVDS_RS Input Circuit
VDD
350Ω
26kΩ
08505-063
OEB
26kΩ
350Ω
08505-062
Figure 62. Equivalent OEB Input Circuit
Rev. A | Page 24 of 44
Page 25
AD9255
THEORY OF OPERATION
With the AD9255, the user can sample any fS/2 frequency
segment from dc to 200 MHz, using appropriate low-pass or
band-pass filtering at the ADC inputs with little loss in ADC
performance. Operation to 300 MHz analog input is permitted,
but occurs at the expense of increased ADC noise and distortion.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9255 are accomplished
using a 3-wire SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9255 architecture consists of a front-end sample-andhold input network, followed by a pipelined, switched-capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier.
The residue amplifier magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage can be ac- or dc-coupled in differential or
single-ended modes. The output staging block aligns the data,
corrects errors, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing. During power-down,
the output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9255 is a differential switchedcapacitor network that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternatively switches between sample mode
and hold mode (see Figure 64). When the input is switched into
sample mode, the signal source must be capable of charging the
sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject (see www.analog.com).
BIAS
VIN+
VIN–
C
C
PAR1
PAR1
S
C
S
C
PAR2
H
C
S
C
PAR2
S
Figure 64. Switched-Capacitor Input
BIAS
S
C
FB
S
C
S
FB
S
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, and the inputs should be
differentially balanced.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9255 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that V
= 0.5 × AVDD is
CM
recommended for optimum performance, but the device
functions over a wider range with reasonable performance (see
Figure 52). An on-board common-mode voltage reference is
included in the design and is available from the VCM pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCM pin voltage
(typically 0.5 × AVDD). The VCM pin must be decoupled to
ground by a 0.1 µF capacitor, as described in the Applications
Information section.
08505-037
Rev. A | Page 25 of 44
Page 26
AD9255
Dither
The AD9255 has an optional dither mode that can be selected
either using the DITHER pin or using the SPI bus. Dithering is
the act of injecting a known but random amount of white noise,
commonly referred to as dither, into the input of the ADC.
Dithering has the effect of improving the local linearity at
various points along the ADC transfer function. Dithering can
significantly improve the SFDR when quantizing small signal
inputs, typically when the input level is below −6 dBFS.
As shown in Figure 65, the dither that is added to the input of
the ADC through the dither DAC is precisely subtracted out
digitally to minimize SNR degradation. When dithering is
enabled, the dither DAC is driven by a pseudorandom number
generator (PN gen). In the AD9255, the dither DAC is precisely
calibrated to result in only a very small degradation in SNR and
SINAD. The typical SNR and SINAD degradation values, with
dithering enabled, are only 1 dB and 0.8 dB, respectively.
VIN
DITHER
DAC
PN GEN
Figure 65. Dither Block Diagram
ADC CORE
DITHER ENABLE
Large Signal FFT
In most cases, dithering does not improve SFDR for large signal
inputs close to full scale, for example, with a −1 dBFS input. For
large signal inputs, the SFDR is typically limited by front-end
sampling distortion, which dithering cannot improve. However,
even for such large signal inputs, dithering may be useful for
certain applications because it makes the noise floor whiter.
As is common in pipeline ADCs, the AD9255 contains small
DNL errors caused by random component mismatches that
produce spurs or tones that make the noise floor somewhat
randomly colored part-to-part. Although these tones are typically
at very low levels and do not limit SFDR when the ADC is
quantizing large-signal inputs, dithering converts these tones to
noise and produces a whiter noise floor.
Small Signal FFT
For small signal inputs, the front-end sampling circuit typically
contributes very little distortion, and, therefore, the SFDR is likely
to be limited by tones caused by DNL errors due to random component mismatches. Therefore, for small signal inputs (typically,
those below −6 dBFS), dithering can significantly improve
SFDR by converting these DNL tones to white noise.
DOUT
08505-038
Static Linearity
Dithering also removes sharp local discontinuities in the INL
transfer function of the ADC and reduces the overall peak-topeak INL.
In receiver applications, utilizing dither helps to reduce DNL errors
that cause small signal gain errors. Often, this issue is overcome
by setting the input noise at 5 dB to 10 dB above the converter
noise. By utilizing dither within the converter to correct the
DNL errors, the input noise requirement can be reduced.
Differential Input Configurations
Optimum performance is achieved while driving the AD9255 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and ADA4938-2 differential drivers provide
excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9255 (see Figure 66), and the
driver can be configured in the filter topology shown to provide
band limiting of the input signal.
15pF
200Ω
76.8Ω
VIN
0.1µF
Figure 66. Differential Input Configuration Using the ADA4938-2
90Ω
ADA4938-2
120Ω
200Ω
33Ω
33Ω
5pF
15pF
15Ω
15Ω
VIN–
VIN+
AVDD
ADC
VCM
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 67. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9255. For applications in
08505-039
08505-040
Rev. A | Page 26 of 44
Page 27
AD9255
which SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 68). In this
configuration, the input is ac-coupled and the CML is provided
to each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
In the double balun and transformer configurations, the value of
the input capacitors and resistors is dependent on the input frequency and source impedance and may need to be reduced or
removed. Ta b l e 1 0 displays recommended values to set the RC
network. However, these values are dependent on the input
signal and should be used only as a starting guide.
Table 10. Example RC Network
Frequency
Range
(MHz)
R1 Series
(Ω Each)
C1 Differential
(pF)
R2 Series
(Ω Each)
C2 Shunt
(pF Each)
0 to 100 15 18 15 Open
100 to 300 10 10 10 10
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone and higher is to use the ADL5562
differential driver. The ADL5562 provides three selectable gain
options up to 15.5 dB. An example circuit is shown in Figure 69;
additional filtering between the ADL5562 output and the AD9255
input may be required to reduce out-of-band noise. See the
Figure 69. Differential Input Configuration Using the ADL5562
5, 6, 7, 8
ADL5562
9
0.1µF
0.1µF
20Ω
11
0.1µF
10
20Ω
Rev. A | Page 27 of 44
Page 28
AD9255
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9255.
The input range can be adjusted by varying the reference voltage
applied to the AD9255, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the sections that follow. The Reference
Decoupling section describes the best practices PCB layout of
the reference.
Internal Reference Connection
A comparator within the AD9255 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Tabl e 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p fullscale input. In this mode, with SENSE grounded, the full scale can
also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of
Register 0x18. These bits can be used to change the full scale to
1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p,
as shown in Tab l e 17 .
Connecting the SENSE pin to the VREF pin switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output for a 1 V p-p full-scale input.
VIN+
VIN–
ADC
CORE
VREF
0.1µF1.0µF
SENSE
SELECT
LOGIC
the reference amplifier in a noninverting mode with the VREF
output defined as follows:
R2
⎞
⎛
VREF15.0
+×=
⎟
⎜
R1
⎠
⎝
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN+
VIN–
ADC
CORE
VREF
0.1µF1.0µF
Figure 71. Programmable Reference Configuration
R2
SENSE
R1
SELECT
LOGIC
ADC
0.5V
08505-044
If the internal reference of the AD9255 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 72 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
VREF = 0.5V
VREF = 1V
0.5V
ADC
Figure 70. Internal Reference Configuration
08505-043
If a resistor divider is connected external to the chip, as shown
in Figure 71, the switch again sets to the SENSE pin. This puts
–2.0
–2.5
REFERENCE VOL TAGE ERROR (%)
–3.0
0.20.40.60.81.01.21.41.61.82.0
LOAD CURRENT (mA)
Figure 72. VREF Accuracy vs. Load
Table 11. Reference Configuration Summary
Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 73 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
2.0
1.5
1.0
0.5
0
–0.5
–1.0
REFERENCE VOL TAGE ERROR (mV)
–1.5
–2.0
–40–20020406080
VREF = 1.0V
TEMPERATURE ( °C)
Figure 73. Typical VREF Drift
08505-046
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 55). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9255 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 74) and require no external bias.
AVDD
0.9V
CLK+
Figure 74. Equivalent Clock Input Circuit
CLK–
4pF4pF
08505-047
Clock Input Options
The AD9255 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 75 and Figure 76 show two preferred methods for clocking
the AD9255. A low jitter clock source is converted from a singleended signal to a differential signal using either an RF
transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
at 625 MHz and the RF transformer is recommended for clock
frequencies from 10 MHz to 200 MHz. The back-to-back
Schottky diodes across the transformer/balun secondary limit
clock excursions into the AD9255 to approximately 0.8 V p-p
differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9255 while
preserving the fast rise and fall times of the signal that are critical
to low jitter performance.
XFMR
0.1µF
®
0.1µF0.1µF
0.1µF
0.1µF1nF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
SCHOTTKY
DIODES:
HSMS2822
AD9255
CLK+
CLK–
ADC
AD9255
CLK+
CLK–
ADC
08505-049
Mini-Circuits
ADT1-1W T, 1:1Z
CLOCK
INPUT
50Ω
100Ω
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 77. The AD9510/AD9511/AD9512/
Figure 78. Differential LVDS Sample Clock (Up to the Rated Sample Rate)
0.1µF
0.1µF
AD95xx
LVDS DRIVER
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 78. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518/AD9520/AD9522 clock drivers offer excellent jitter
performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass
the CLK− pin to ground with a 0.1 F capacitor (see Figure 79).
V
CC
0.1µF
1kΩ
1kΩ
AD95xx
CMOS DRIVE R
CLOCK
INPUT
1
50Ω RESISTOR IS OPTIONAL.
1
50Ω
Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
OPTIONAL
100Ω
0.1µF
0.1µF
CLK+
ADC
AD9255
CLK–
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9255 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9255. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS
enabled. Jitter in the rising edge of the input is still of paramount
concern and is not easily reduced by the internal stabilization
circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 µs to 5 µs is required after a dynamic clock frequency increase
or decrease before the DCS loop is relocked to the input signal.
During the time period that the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the duty
cycle of the input clock signal. In such applications, it may be
appropriate to disable the duty cycle stabilizer. The DCS can
0.1µF
CLK+
100Ω
0.1µF
ADC
AD9255
CLK–
08505-051
also be disabled in some cases when using the input clock
divider circuit, see the Input Clock Divider section for additional information. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
The DCS is enabled by setting the SDIO/DCS pin high when
operating in the external pin mode (see Ta b le 1 2 ). If the SPI
mode is enabled, the DCS is enabled by default and can be
disabled by writing a 0x00 to Address 0x09.
Input Clock Divider
The AD9255 contains an input clock divider with the ability to
divide the input clock by integer values between 2 and 8. For
clock divide ratios of 2, 4, 6, or 8, the duty cycle stabilizer (DCS)
is not required because the output of the divider inherently produces a 50% duty cycle. Enabling the DCS with the clock divider in
these divide modes may cause a slight degradation in SNR so
disabling the DCS is recommended. For other divide ratios,
08505-052
divide-by-3, divide-by-5, and divide-by-7 the duty cycle output
from the clock divider is related to the input clock’s duty cycle.
In these modes, if the input clock has a 50% duty cycle, the DCS
is again not required. However, if a 50% duty cycle input clock
is not available the DCS must be enabled for proper part
operation.
To synchronize the AD9255 clock divider, use an external sync
signal applied to the SYNC pin. Bit 1 and Bit 2 of Register 0x100
allow the clock divider to be resynchronized on every SYNC
signal or only on the first SYNC signal after the register is written.
A valid signal at the SYNC pin causes the clock divider to reset
to its initial state. This synchronization feature allows multiple
parts to have their clock dividers aligned to guarantee simultaneous input sampling. If the SYNC pin is not used, it should be
tied to AGND.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low frequency SNR (SNR
jitter (t
) can be calculated by
JRMS
= −10 log[(2π × f
SNR
HF
) at a given input frequency (f
LF
× t
INPUT
)2 + 10]
JRMS
INPUT
) due to
)10/(LFSNR−
In this equation, the rms aperture jitter represents the clock
input jitter specification. IF undersampling applications are
particularly sensitive to jitter, as illustrated in Figure 80.
Rev. A | Page 30 of 44
Page 31
AD9255
80
0.5
0.20
75
MEASURED
70
65
SNR (dBc)
60
55
50
1101001k
INPUT FREQ UE NCY ( M Hz)
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
08505-053
Figure 80. SNR vs. Input Frequency and Jitter
Treat the clock input as an analog signal in cases in which
aperture jitter may affect the dynamic range of the AD9255. To
avoid modulating the clock signal with digital noise, separate
power supplies for clock drivers from the ADC output driver
supplies. Low jitter, crystal controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), the output clock should
be retimed by the original clock at the last step.
Refer to AN-501 Application Note, Aperture Uncertainty and ADC
System Performance, and AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter(see
www.analog.com) for more information about jitter performance
as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 81, the power dissipated by the AD9255 is
proportional to its sample rate. In CMOS output mode, the digital
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be approximately
calculated as
IDRVDD = VDRVDD × C
where N is the number of output bits (14 output bits plus
one DCO).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
/2. In practice, the DRVDD current is established
CLK
by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog
input signal.
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 81,
Figure 82, and Figure 83 was taken using a 70 MHz analog input
signal, with a 5 pF load on each output driver.
LOAD
× f
CLK
× N
0.4
0.3
0.2
TOTAL POWER (W)
0.1
0
251257510050
IAVDD
TOTAL
POWER
IDRVDD
CLOCK FREQ UENCY ( M S P S )
0.16
0.12
0.08
SUPPLY CURRENT (A)
0.04
0
Figure 81. AD9255-125 Power and Current vs. Sample Rate
0.20
0.16
0.12
0.08
SUPPLY CURRENT (A)
0.04
0
TOTAL POWER (W)
0.5
0.4
0.3
0.2
0.1
0
2510595857565554535
IAVDD
TOTAL
POWER
IDRVDD
CLOCK FREQ UENCY ( M S P S )
Figure 82. AD9255-105 Power and Current vs. Sample Rate
0.5
0.4
0.3
0.2
TOTAL POWER (W)
0.1
0
257565554535
IAVDD
TOTAL
POWER
IDRVDD
ENCODE FREQUENCY (MSPS)
0.15
0.12
0.09
0.06
SUPPLY CURRENT (A)
0.03
0
Figure 83. AD9255-80 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9255 is placed in power-down
mode. In this state, the ADC typically dissipates 0.05 mW.
During power-down, the output drivers are placed in a high
impedance state; asserting the PDWN pin low returns the
AD9255 to its normal operating mode.
08505-179
08505-180
08505-181
Rev. A | Page 31 of 44
Page 32
AD9255
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. In addition, when using the SPI
mode, the user can change the function of the external PDWN pin
to either place the part in power-down or standby mode. See the
Memory Map Register Descriptions section for more details.
DIGITAL OUTPUTS
The AD9255 output drivers can be configured to interface with
1.8 V CMOS logic families. The AD9255 can also be configured
for LVDS outputs using a DRVDD supply voltage of 1.8 V. The
AD9255 defaults to CMOS output mode but can be placed into
LVDS mode either by setting the LVDS pin high or by using the
SPI port to place the part into LVDS mode. Because most users do
not toggle between CMOS and LVDS mode during operation, use
of the LVDS pin is recommended to avoid any power-up loading
issues on the CMOS configured outputs.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies, which may affect converter performance. Applications
requiring the ADC to drive large capacitive loads or large
fanouts may require external buffers or latches.
In LVDS output mode, two output drive levels can be selected,
either ANSI LVDS or reduced swing LVDS mode. Using the
reduced swing LVDS mode lowers the DRVDD current and
reduces power consumption. The reduced swing LVDS mode
can be selected by asserting the LVDS_RS pin or by selecting
this mode via the SPI port.
The output data format is selected for either offset binary or
twos complement by setting the SCLK/DFS pin when operating in
the external pin mode (see Tabl e 1 2).
As detailed in AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
The AD9255 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI interface. If the OEB pin is low, the output data
drivers and DCOs are enabled. If the OEB pin is high, the output
data drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data and DCO outputs can be
three-stated by using the output enable bar bit in Register 0x14.
TIMING
The AD9255 provides latched data with a pipeline delay of
12 clock cycles (12.5 clock cycles in LVDS mode). Data outputs
are available one propagation delay (t
the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9255. These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9255 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9255 provides a single data clock output (DCO) pin in
CMOS output mode and two differential data clock output (DCO)
pins in LVDS mode intended for capturing the data in an external
register. In CMOS output mode, the data outputs are valid on the
rising edge of DCO, unless the DCO clock polarity has been
changed via the SPI. In LVDS output mode, data is output as
double data rate with the even numbered output bits transitioning
near the rising edge of DCO and the odd numbered output bits
transitioning near the falling edge of DCO. See Figure 2 for a
graphical timing description.
The AD9255 includes built-in self-test features designed to
enable verification of the integrity of the part as well as facilitate
board level debugging. A built-in self-test (BIST) feature is included
that verifies the integrity of the digital datapath of the AD9255.
Various output test options are also provided to place predictable
values on the outputs of the AD9255.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9255 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value is placed in
Register 0x24 and Register 0x25.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the part configuration.
OUTPUT TEST MODES
The output test options are shown in Tabl e 17 . When an output
test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Rev. A | Page 33 of 44
Page 34
AD9255
SERIAL PORT INTERFACE (SPI)
The AD9255 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to, or read from, via the port. Memory is organized
into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational
information, see AN-877Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Tab l e 14 ). The SCLK/DFS
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent
and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles.
Table 14. Serial Port Interface Pins
Pin Mnemonic Function
SCLK/DFS
SDIO/DCS
CSB
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. See Figure 84
and Tab le 5 for an example of the serial timing and its definitions.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes
to allow for additional external timing. When CSB is tied high
at power-up, SPI functions are placed in high impedance mode.
This mode turns on any SPI pin secondary functions. When
CSB is toggled low after power-up, the part remains in SPI
mode and does not revert back to pin mode.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
Serial clock. The SCLK function of the pin is for
the serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO is the serial data input/output function
of the pin. A dual-purpose pin that typically
serves as an input or an output, depending on
the instruction being sent and the relative
position in the timing frame.
Chip select bar. An active low control that
gates the read and write cycles.
All data is composed of 8-bit words. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. This allows the serial
data input/output (SDIO) pin to change direction from an input
to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Ta b l e 14 comprise the physical interface
between the user programming device and the serial port of the
AD9255. When using the SPI interface, the SCLK pin and the
CSB pin function as inputs. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during
readback.
The AD9255 has a separate supply pin for the SPI interface, SVDD.
The SVDD pin can be set at any level between 1.8 V and 3.3 V
to enable operation with a SPI bus at these voltages without
requiring level translation. If the SPI port is not used, SVDD
can be tied to the DRVDD voltage.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9255 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are tied to AVDD or ground during
device power-on, they are associated with a specific function.
The Digital Outputs section describes the alternate functions
that are supported on the AD9255.
Rev. A | Page 34 of 44
Page 35
AD9255
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the duty cycle stabilizer and output data format
feature control. In this mode, connect the CSB chip select to
AVDD, which disables the serial port interface.
The OEB pin, the DITHER pin, the LVDS pin, the LVDS_RS
pin, and the PDWN pin are active control lines in both external
pin mode and SPI mode. The input from these pins or the SPI
register setting (the logical OR of the SPI bit and the pin function)
is used to determine the mode of operation for the part.
Tabl e 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9255 part-specific features are described in detail
following Tab l e 1 7 , the external memory map register table.
Table 16. Features Accessible Using the SPI
Feature Name Description
Mode
Clock
Offset
Tes t I /O
Output Mode Allows the user to set the output mode
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF Allows the user to set the reference voltage
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the SYNC input
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
CSB
SCLK
SDIO
DON’T CARE
t
t
DS
t
S
R/WW1W0A12A11A10A9A8A7
t
DH
HIGH
t
LOW
Figure 84. Serial Port Interface Timing Diagram
t
CLK
Rev. A | Page 35 of 44
D5D4D3D2D1D0
t
H
DON’T CARE
DON’T C AREDON’T CARE
08505-055
Page 36
AD9255
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
transfer register (Address 0xFF); the ADC functions registers,
including setup, control, and test (Address 0x08 to Address 0x30);
and the digital feature control registers (Address 0x100).
The memory map register table (see Tab l e 17 ) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading, Bit 7 (MSB), is the start of the
default hexadecimal value given. For example, Address 0x18, the
VREF select register, has a hexadecimal default value of 0xC0. This
means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This
setting is the default reference selection setting. The default value
uses a 2.0 V p-p reference. For more information on this function
and others, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by
Register 0x00 to Register 0x30. The remaining register, at
Register 0x100, is documented in the Memory Map Register
Descriptions section.
Open Locations
All address and bit locations that are not included in Tab l e 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
After the AD9255 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Tab l e 17 .
Logic Levels
An explanation of logic level terminology follows:
•“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
•“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
Rev. A | Page 36 of 44
Page 37
AD9255
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Tab l e 17 are not currently supported for this device.
Table 17. Memory Map Registers
Default
Addr.
(Hex)
Chip Configuration Registers
0x00 SPI port
0x01 Chip ID 8-Bit Chip ID[7:0], AD9255 = 0x65 (default) 0x65 Read only
0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed grade ID
Transfer Register
0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously
ADC Functions Registers
0x08 Power
0x09 Global clock Open Open Open Open Open Open Open Duty
0x0D Test mode Open Open Reset PN23
0x0E BIST enable Open Open Open Open Open Reset BIST
Register
Name
configuration
modes
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 LSB first Soft reset 1 1 Soft reset LSB
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
1 Open External power-
down pin
function
0 = powerdown
1 = standby 01 = full power-
10 = standby
11 = normal
generator
Open Open Open Internal
Reset PN9
generator
Open Output test mode 0x00 When this
100 = alternating checkerboard
111 = one/zero word toggle
sequence
first
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
101 = PN 23 sequence
110 = PN 9 sequence
Open BIST
0 0x18 The nibbles are
power-down
mode
00 = normal
operation
down
operation
cycle
stabilizer
(default)
enable
Value
(Hex)
0x80 Determines
0x01
0x04
Default Notes/
Comments
mirrored so
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
used to
differentiate
devices; read
only
transfers data
from the
master shift
register to the
slave
various generic
modes of chip
operation
register is set,
the test data is
placed on the
output pins in
place of normal
data
Rev. A | Page 37 of 44
Page 38
AD9255
Addr.
(Hex)
0x14 Output
0x16 Clock phase
0x17 DCO output
0x18 VREF select Reference voltage
0x24 BIST
0x25 BIST
0x30 Dither
Digital Feature Control Register
0x100 Sync control Open Open Open Open Open Clock
Register
Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
mode
control
delay
signature LSB
signature
MSB
enable
Drive
strength
0 = ANSI
LVDS
1 = reduced
LVDS
01 = gray code
11 = offset binary
Invert DCO
clock
Open Open Open DCO clock delay 0x00
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
Open Open Open Dither
Output
type
0 =
CMOS
1 = LVDS 01 = twos
Open Open Open Open Input clock divider phase adjust 0x00 Allows
selection of
clock delays
into the input
clock divider
Rev. A | Page 38 of 44
Page 39
AD9255
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Reserved
These bits are reserved.
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to sync to the first sync pulse it receives
and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used, this bit should remain low to
conserve power.
Rev. A | Page 39 of 44
Page 40
AD9255
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9255 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9255, it is recommended that
two separate 1.8 V supplies be used. Use one supply for analog
(AVDD); use a separate supply for the digital outputs (DRVDD).
Several different decoupling capacitors can be used to cover both
high and low frequencies. Locate these capacitors close to the
point of entry at the PCB level and close to the pins of the part,
with minimal trace length. The power supply for the SPI port,
SVDD, should not contain excessive noise and should also be
bypassed close to the part.
A single PCB ground plane should be sufficient when using the
AD9255. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
LVDS Operation
The AD9255 can be configured for CMOS or LVDS output mode
on power-up using the LVDS pin, Pin 44. If LVDS operation is
desired, connect Pin 44 to AVDD. LVDS operation can also be
enabled through the SPI port. If CMOS operation is desired,
connect Pin 44 to AGND.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to the analog ground (AGND) to achieve
the best electrical and thermal performance. A continuous,
exposed (no solder mask) copper plane on the PCB should mate
to the AD9255 exposed paddle, Pin 0. The copper plane
should have several vias to achieve the lowest possible resistive
thermal path for heat dissipation to flow through the bottom of
the PCB. Fill or plug these vias with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only one
tie point between the ADC and the PCB. For detailed information
about packaging and PCB layout of chip scale packages, see the
AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
VCM
Decouple the VCM pin to ground with a 0.1 F capacitor, as
shown in Figure 67.
RBIAS
The AD9255 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
Decouple the VREF pin externally to ground with a low ESR,
1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic
capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9255 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
Rev. A | Page 40 of 44
Page 41
AD9255
OUTLINE DIMENSIONS
PIN 1
INDICATOR
7.10
7.00 SQ
6.90
6.85
6.75 SQ
6.65
0.60 MAX
0.50
REF
0.60 MAX
36
37
EXPOSED
(BOTT OM VIEW)
PAD
0.30
0.23
0.18
PIN 1
1
INDICATOR
*
5.65
5.50 SQ
5.35
48
1.00
0.85
0.80
SEATING
PLANE
12° MAX
TOP VIEW
25
0.50
0.40
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.80 MAX
0.65 TYP
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
24
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
12
13
0.25 MIN
120109-B
Figure 85. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9255BCPZ-125 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8
AD9255BCPZRL7-125 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8
AD9255BCPZ-105 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8
AD9255BCPZRL7-105 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8
AD9255BCPZ-80 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8
AD9255BCPZRL7-80 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8
AD9255-125EBZ Evaluation Board
AD9255-105EBZ Evaluation Board
AD9255-80EBZ Evaluation Board