Page 1
Complete 14-Bit, 1.25 MSPS
a
FEATURES
Monolithic 14-Bit, 1.25 MSPS A/D Converter
Low Power Dissipation: 60 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 78.0 dB
Spurious-Free Dynamic Range: 88.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Pin MQFP
PRODUCT DESCRIPTION
The AD9241 is a 1.25 MSPS, single supply, 14-bit analog-todigital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external reference can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correction logic to guarantee no missing codes over the full operating
temperature range.
The input of the AD9241 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and dataacquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9241 performs well in communication systems employing Direct-IF Down Conversion since the SHA in the differential input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 0.625 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an overflow condition which can be used with the most significant bit
to determine low or high overflow.
Monolithic A/D Converter
AD9241
FUNCTIONAL BLOCK DIAGRAM
CLK
SHA
VINA
VINB
CML
CAPT
CAPB
VREF
SENSE
MODE
SELECT
MDAC1
GAIN = 16
5
5
REFCOM
MDAC2
GAIN = 8
4
A/DA/D
4
DIGITAL CORRECTION LOGIC
OUTPUT BUFFERS
1V
AD9241
AVSS
PRODUCT HIGHLIGHTS
The AD9241 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-pin Metric Quad
Flatpack.
Low Power and Single Supply
The AD9241 consumes only 60 mW on a single +5 V power
supply.
Excellent DC Performance Over Temperature
The AD9241 provides no missing codes, and excellent temperature drift performance over the full operating temperature range.
Excellent AC Performance and Low Noise
The AD9241 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
Flexible Analog Input Range
The versatile onboard sample-and-hold (SHA) can be configured
for either single-ended or differential inputs of varying input spans.
Flexible Digital Outputs
The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.
DVDDAVDD
DRVDD
MDAC3
GAIN = 8
4
A/D
4
14
DVSS
DRVSS
A/D
4
OTR
BIT 1
(MSB)
BIT 14
(LSB)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
Page 2
AD9241–SPECIFICATIONS
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
DC SPECIFICATIONS
T
to T
MIN
unless otherwise noted)
MAX
Parameter AD9241 Units
RESOLUTION 14 Bits min
MAX CONVERSION RATE 1.25 MHz min
INPUT REFERRED NOISE
VREF = 1 V 0.9 LSB rms typ
VREF = 2.5 V 0.36 LSB rms typ
ACCURACY
Integral Nonlinearity (INL) ±2.5 LSB typ
Differential Nonlinearity (DNL) ±0.6 LSB typ
±1.0 LSB max
±2.5 LSB typ
±0.7 LSB typ
INL
DNL
1
1
No Missing Codes 14 Bits Guaranteed
Zero Error (@ +25°C) 0.3 % FSR max
Gain Error (@ +25°C)
Gain Error (@ +25°C)
2
3
1.5 % FSR max
0.75 % FSR max
TEMPERATURE DRIFT
Zero Error 3.0 ppm/°C typ
Gain Error
Gain Error
2
3
20.0 ppm/°C typ
5.0 ppm/°C typ
= 1.25 MSPS, VREF = 2.5 V, VINB = 2.5 V,
SAMPLE
POWER SUPPLY REJECTION 0.1 % FSR max
ANALOG INPUT
Input Span (with VREF = 1.0 V) 2 V p-p min
Input Span (with VREF = 2.5 V) 5 V p-p max
Input (VINA or VINB) Range 0 V min
AVDD V max
Input Capacitance 16 pF typ
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) 1 Volts typ
Output Voltage Tolerance (1 V Mode) ±14 mV max
Output Voltage (2.5 V Mode) 2.5 Volts typ
Output Voltage Tolerance (2.5 V Mode) ±35 mV max
Load Regulation
4
5.0 mV max
REFERENCE INPUT RESISTANCE 5 kΩ typ
POWER SUPPLIES
Supply Voltages
AVDD +5 V (±5% AVDD
DVDD +5 V (±5% DVDD
DRVDD +5 V (± 5% DRVDD
Supply Current
IAVDD 13.0 mA max (10 mA typ )
IDRVDD 1.0 mA max (1 mA typ )
IDVDD 3.0 mA max (2 mA typ )
POWER CONSUMPTION 65 mW typ
85 mW max
NOTES
1
VREF =1 V.
2
Including internal reference.
3
Excluding internal reference.
4
Load regulation with 1 mA load current (in addition to that required by the AD9241).
Specification subject to change without notice.
Operating)
Operating)
Operating)
–2–
REV. 0
Page 3
AD9241
AC SPECIFICATIONS
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
Differential Input, T
MIN
to T
unless otherwise noted)
MAX
= 1.25 MSPS, VREF = 2.5 V, AIN = –0.5 dBFS, AC Coupled/
SAMPLE
Parameter AD9241 Units
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
= 100 kHz 78.0 dB typ
f
INPUT
= 500 kHz 74.5 dB min
f
INPUT
77.0 dB typ
EFFECTIVE NUMBER OF BITS (ENOB)
f
= 100 kHz 12.7 Bits typ
INPUT
= 500 kHz 12.1 Bits min
f
INPUT
12.5 Bits typ
SIGNAL-TO-NOISE RATIO (SNR)
f
= 100 kHz 79.0 dB typ
INPUT
= 500 kHz 75.5 dB min
f
INPUT
79.0 dB typ
TOTAL HARMONIC DISTORTION (THD)
f
= 100 kHz –88.0 dB typ
INPUT
= 500 kHz –77.5 dB max
f
INPUT
–88.0 dB typ
SPURIOUS FREE DYNAMIC RANGE
f
= 100 kHz 88.0 dB typ
INPUT
f
= 500 kHz 86.0 dB typ
INPUT
DYNAMIC PERFORMANCE
Full Power Bandwidth 25 MHz typ
Small Signal Bandwidth 25 MHz typ
Aperture Delay 1 ns typ
Aperture Jitter 4 ps rms typ
Acquisition to Full-Scale Step (0.0025%) 240 ns typ
Overvoltage Recovery Time 167 ns typ
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(AVDD = +5 V, DVDD = +5 V, T
MIN
to T
unless otherwise noted)
MAX
Parameters Symbol AD9241 Units
LOGIC INPUTS
High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current (V
Low Level Input Current (V
= DVDD) I
IN
= 0 V) I
IN
Input Capacitance C
IH
IL
IH
IL
IN
+3.5 V min
+1.0 V max
±10 µA max
±10 µA max
5 pF typ
LOGIC OUTPUTS (with DRVDD = 5 V)
High Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
Low Level Output Voltage (I
Output Capacitance C
= 50 µA) V
OH
= 0.5 mA) V
OH
= 1.6 mA) V
OL
= 50 µA) V
OL
OH
OH
OL
OL
OUT
+4.5 V min
+2.4 V min
+0.4 V max
+0.1 V max
5 pF typ
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (I
Low Level Output Voltage (I
Specifications subject to change without notice.
= 50 µA) V
OH
= 50 µA) V
OL
OH
OL
+2.4 V min
+0.7 V max
REV. 0
–3–
Page 4
AD9241
(T
to T
SWITCHING SPECIFICATIONS
MIN
Parameters Symbol AD9241 Units
Clock Period
CLOCK Pulse Width High t
CLOCK Pulse Width Low t
Output Delay t
1
t
C
CH
CL
OD
Pipeline Delay (Latency) 3 Clock Cycles
NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
Specifications subject to change without notice.
ANALOG
INPUT
INPUT
CLOCK
DATA
OUTPUT
S1
t
CH
S2
t
C
t
CL
S3
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter to Min Max Units
AVDD AVSS –0.3 +6.5 V
DVDD DVSS –0.3 +6.5 V
AVSS DVSS –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
DRVSS AVSS –0.3 +0.3 V
REFCOM AVSS –0.3 +0.3 V
CLK DVSS –0.3 DVDD
Digital Outputs DRVSS –0.3 DRVDD
VINA, VINB AVSS –0.3 AVDD
VREF AVSS –0.3 AVDD
SENSE AVSS –0.3 AVDD
CAPB, CAPT AVSS –0.3 AVDD
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9241 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, CL = 20 pF)
MAX
800 ns min
360 ns min
360 ns min
8 ns min
13 ns typ
19 ns max
THERMAL CHARACTERISTICS
S4
t
OD
DATA 1
Thermal Resistance
44-Pin MQFP
θ
= 53.2°C/W
JA
θ
= 19°C/W
JC
ORDERING GUIDE
Temperature Package Package
Model Range Description Option*
AD9241AS –40
o
C to +85oC 44-Pin MQFP S-44
AD9241EB Evaluation Board
*S = Metric Quad Flatpack.
PIN CONNECTION
NC
NC
VINB
1
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
DVSS
AVSS
DVDD
AVDD
DRVSS
DRVDD
CLK
NC
NC
NC
(LSB) BIT 14
NC = NO CONNECT
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
121314 15 16 17 18 192021 22
BIT 13
(Not to Scale)
BIT 11
BIT 12
NC
VINA
CML
40 39 3841424344 36 35 3437
AD9241
TOP VIEW
BIT 8
BIT 9
BIT 10
WARNING!
NC
BIT 7
CAPT
NC
CAPB
NC
BIT 4
BIT 5
BIT 6
BIT 3
ESD SENSITIVE DEVICE
33
REFCOM
32
VREF
31
SENSE
30
NC
29
AVSS
28
AVDD
27
NC
NC
26
OTR
25
BIT 1 (MSB)
24
BIT 2
23
–4–
REV. 0
Page 5
AD9241
PIN FUNCTION DESCRIPTIONS
Pin
Number Name Description
1 DVSS Digital Ground
2, 29 AVSS Analog Ground
3 DVDD +5 V Digital Supply
4, 28 AVDD +5 V Analog Supply
5 DRVSS Digital Output Driver Ground
6 DRVDD Digital Output Driver Supply
7 CLK Clock Input Pin
8–10 NC No Connect
11 BIT 14 Least Significant Data Bit (LSB)
12–23 BIT 13–BIT 2 Data Output Bits
24 BIT 1 Most Significant Data Bit (MSB)
25 OTR Out of Range
26, 27, 30 NC No Connect
31 SENSE Reference Select
32 VREF Reference I/O
33 REFCOM Reference Common
34, 35, 38 NC No Connect
40, 43, 44
36 CAPB Noise Reduction Pin
37 CAPT Noise Reduction Pin
39 CML Common-Mode Level (Midsupply)
41 VINA Analog Input Pin (+)
42 VINB Analog Input Pin (–)
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full
scale. Gain error is the deviation of the actual difference
between first and last code transitions, and the ideal difference between first and last code transitions.
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
T
or T
MIN
POWER SUPPLY REJECTION
MAX
.
The specification shows the maximum change in full scale,
from the value with the supply at the minimum limit to the
value with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal; this
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TWO-TONE SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
REV. 0
–5–
Page 6
AD9241
Typical Differential AC Characterization Curves/Plots
80
75
70
65
60
55
SINAD – dB
50
45
40
0.01
–0.5dBFS
–6.0dBFS
–20dBFS
0.1
INPUT FREQUENCY – MHz
1.0
10.0
Figure 2. SINAD vs. Input Frequency
(Input Span = 5 V, V
80
75
70
65
60
55
SINAD – dB
50
45
40
0.01 0.1 10.01.0
INPUT FREQUENCY – MHz
CM
–0.5dBFS
–6.0dBFS
–20.0dBFS
= 2.5 V)
–40
–50
–60
–70
THD – dB
–80
–90
–100
0.01 0.1
–20.0dBFS
–6.0dBFS
–0.5dBFS
INPUT FREQUENCY – MHz
1.0
Figure 3. THD vs. Input Frequency
(Input Span = 5 V, V
–40
–50
–60
–70
THD – dB
–80
–90
–100
0.01 0.1 10.01.0
–6.0dBFS
INPUT FREQUENCY – MHz
CM
–20.0dBFS
–0.5dBFS
= 2.5 V)
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
1.25 MSPS, TA = +258C, Differential Input)
10.0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
AMPLITUDE – dB
–120
–130
–140
–150
–160
–170
0
3
5
8
100 200 300 400 500 600
FREQUENCY – kHz
Figure 4. Typical FFT, fIN > 500 kHz
(Input Span = 5 V, V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5
–110
AMPLITUDE – dB
–120
–130
–140
–150
–160
–170
0
100 200 300 400 500 600
FREQUENCY – kHz
8
2
3
2
CM
7
FUND
6
7
= 2.5 V)
FUND
=
SAMPLE
4
9
4
9
6
Figure 5. SINAD vs. Input Frequency
(Input Span = 2 V, V
–40
–50
–60
–70
THD – dB
–80
–90
–100
0.1 1.0 10.0
SAMPLE RATE – MSPS
5V SPAN
= 2.5 V)
CM
2V SPAN
Figure 8. THD vs. Sample Rate
= 0.3 MHz, AIN = –0.5 dBFS,
(f
IN
= 2.5 V)
V
CM
Figure 6. THD vs. Input Frequency
dBFS - 5V
dBc - 2V
AIN – dBFS
= 2.5 V)
CM
–9 –3
(Input Span = 2 V, V
110
100
90
dBc - 5V
80
70
dBFS - 5V
60
SFDR – dBc AND dBFS
50
40
–39 –33 –27 –21 –15
–45
Figure 9. Single Tone SFDR
= 0.6 MHz, VCM = 2.5 V)
(f
IN
–6–
Figure 7. Typical FFT, fIN > 500 kHz
(Input Span = 2 V, V
110
105
100
WORST CASE SPURIOUS – dBc AND dBFS
0
5V SPAN - dBFS
95
90
85
80
5V SPAN - dBc
75
70
65
60
–40 –35 0
INPUT POWER LEVEL (f1 = f2) – dBFS
CM
2V SPAN - dBFS
2V SPAN - dBc
–30 –25 –20 –15 –10 –5
Figure 10. Dual Tone SFDR
(f
= 0.5 MHz, f2 = 0.6 MHz,
1
= 2.5 V)
V
CM
= 2.5 V)
REV. 0
Page 7
AD9241
TEMPERATURE – 8C
V
REF
ERROR – V
0.01
–0.004
–0.01
–60 –40 140
–20 0 20 40 60 80 100 120
0.008
–0.002
–0.006
–0.008
0.002
0
0.006
0.004
Other Characterization Curves/Plots
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–0.5
INL – LSB
–1.0
–1.5
–2.0
–2.5
–3.0
0
CODE
Figure 11. Typical INL
(Input Span = 5 V)
90
85
80
75
–0.5dBFS
–6.0dBFS
70
SINAD – dB
65
–20.0dBFS
60
55
50
0.01 0.1 10.0
INPUT FREQUENCY – MHz
1.0
16383
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
DNL – LSB
–0.4
–0.6
–0.8
–1.0
0
Figure 12. Typical DNL
(Input Span = 5 V)
–40
–50
–60
–20dBFS
–70
THD – dB
–6dBFS
–80
–0.5dBFS
–90
–100
0.01 0.1 10.0
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
Single-Ended Input)
100%
HITS
CODE
INPUT FREQUENCY – MHz
1.0
16383
Figure 13. “Grounded-Input”
Histogram (Input Span = 5 V)
40
50
60
70
CMR – dB
80
90
0.01 0.1 10.0
= 1.25 MSPS, TA = +258C,
SAMPLE
12,901,627
1,137,700
N–1
N N+1
CODE
1.0
FREQUENCY – MHz
1,146,291
100
Figure 14. SINAD vs. Input Frequency
(Input Span = 2 V, V
90
85
80
75
70
65
60
SINAD – dB
55
50
45
40
0.01 0.1 10.0
INPUT FREQUENCY – MHz
Figure 17. SINAD vs. Input Frequency
(Input Span = 5 V, V
REV. 0
CM
–0.5dBFS
–6dBFS
–20dBFS
CM
= 2.5 V)
1.0
= 2.5 V)
Figure 15. THD vs. Input Frequency
(Input Span = 2 V, V
–40
–50
–60
–70
–20dBFS
THD – dB
–6dBFS
–80
–0.5dBFS
–90
–100
0.01 0.1 1.0
INPUT FREQUENCY – MHz
= 2.5 V)
CM
10.0
Figure 18. THD vs. Input Frequency
(Input Span = 5 V, V
= 2.5 V)
CM
–7–
Figure 16. CMR vs. Input Frequency
(Input Span = 2 V, V
= 2.5 V)
CM
Figure 19. Typical Voltage Reference
Error vs. Temperature
Page 8
AD9241
INTRODUCTION
The AD9241 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be configured to interface with +5 V or +3.3 V logic families.
The AD9241 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 20, a simplified model of the AD9241, highlights the relationship between the analog inputs, VINA, VINB, and the
reference voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF defines
the maximum input voltage to the A/D core. The minimum input
voltage to the A/D core is automatically defined to be –VREF.
VINA
VINB
AD9241
V
CORE
+VREF
A/D
CORE
–VREF
14
Figure 20. Equivalent Functional Input Circuit
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the difference
of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,
V
= VINA – VINB (1)
CORE
defines the output of the differential input stage and provides the
input to the A/D core.
The voltage, V
, must satisfy the condition,
CORE
≤
V
–VREF
≤ VREF (2)
CORE
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
to satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9241. The power
supplies bound the valid operating range for VINA and VINB.
The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V (3)
AVSS – 0.3 V < VINB < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equations 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9241, see
Table IV.
Refer to Table I and Table II for a summary of the various
analog input and reference configurations.
ANALOG INPUT OPERATION
Figure 21 shows the equivalent analog input of the AD9241,
which consists of a differential sample-and-hold amplifier
(SHA). The differential input structure of the SHA is highly
flexible, allowing the devices to be easily configured for either a
differential or single-ended input. The dc offset, or commonmode voltage, of the input(s) can be set to accommodate either
single-supply or dual supply systems. Also, note that the analog
inputs, VINA and VINB, are interchangeable, with the exception
that reversing the inputs to the VINA and VINB pins results in a
polarity inversion.
C
H
Q
S2
Q
S2
C
H
VINA
VINB
+
C
PIN
Q
C
S1
PAR
Q
S1
–
C
PIN
C
PAR
C
S
Q
C
H1
S
Figure 21. Simplified Input Circuit
–8–
REV. 0
Page 9
AD9241
The input SHA of the AD9241 is optimized to meet the performance requirements for some of the most demanding communication, imaging and data acquisition applications, while
maintaining low power dissipation. Figure 22 is a graph of the
full-power bandwidth of the AD9241, typically 40 MHz. Note
that the small signal bandwidth is the same as the full-power
bandwidth. The settling time response to a full-scale stepped
input is shown in Figure 23 and is typically less than 80 ns to
0.0025%. The low input referred noise of 0.36 LSB’s rms is
displayed via a grounded histogram and is shown in Figure 13.
2
0
–2
–4
–6
AMPLITUDE – dB
–8
–10
–12
0.01 1.0 10.0 100
0.1
FREQUENCY – MHz
Figure 22. Full-Power Bandwidth
16000
12000
8000
CODE
4000
0
0
SETTLING TIME – ns
70 80
6010 20 30 40 50
Figure 23. Settling Time
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two conditions: (1) the common-mode voltage is centered around midsupply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input
signal voltage span of the SHA is set at its lowest (i.e., 2 V input
span). This is due to the sampling switches, Q
switches whose R
resistance is very low but has some signal
ON
, being CMOS
S1
dependency causing frequency-dependent ac distortion while
the SHA is in the track mode. The R
resistance of a CMOS
ON
switch is typically lowest at its midsupply, but increases symmetrically as the input signal approaches either AVDD or
AVSS. A lower input signal voltage span centered at midsupply
reduces the degree of R
modulation.
ON
Figure 24 compares the AD9241’s THD vs. frequency performance for a 2 V input span with a common-mode voltage of
1 V and 2.5 V. Note the difference in the amount of degradation in THD performance as the input frequency increases.
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be dominated by static nonlinearities such as INL and DNL. It is
important to note that these dc static nonlinearities are independent of any R
–40
–45
–50
–55
–60
–65
THD – dB
–70
–75
–80
–85
0.01 0.1 10.0
modulation.
ON
VCM = 1V
FREQUENCY – MHz
VCM = 2.5V
1.0
Figure 24. THD vs. Frequency for VCM = 2.5 V and 1.0 V
(A
= –0.5 dB, Input Span = 2.0 V p-p)
IN
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differential input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancellation of both common-mode distortion and noise. In addition,
the required input signal voltage span is reduced by a factor of
two, which further reduces the degree of R
modulation and
ON
its effects on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 5 V input span) and matched
input impedance for VINA and VINB. Note that only a slight
degradation in dc linearity performance exists between the 2 V and
5 V input span as specified in AD9241 DC SPECIFICATIONS.
Referring to Figure 21, the differential SHA is implemented
using a switched-capacitor topology. Hence, its input impedance and its subsequent effects on the input drive source should
be understood to maximize the converter’s performance. The
combination of the pin capacitance, C
C
and the sampling capacitance, CS, is typically less than
PAR,
, parasitic capacitance
PIN
16 pF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on C
input voltage. This action of charging and discharging C
to the new
S
which
S,
is approximately 4 pF, averaged over a period of time and for a
given sampling frequency, F
pear to have a benign resistive component (i.e., 83 kΩ at F
, makes the input impedance ap-
S
=
S
1.25 MSPS). However, if this action is analyzed within a sampling period (i.e., T = <1/F
), the input impedance is dynamic
S
due to the instantaneous requirement of charging and discharging C
. A series resistor inserted between the input drive source
S
and the SHA input, as shown in Figure 25, provides effective
isolation.
REV. 0
–9–
Page 10
AD9241
V
CC
RS*
RS*
V
EE
10µF
0.1µF
*OPTIONAL SERIES RESISTOR
Figure 25. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several factors, including the AD9241 sampling rate, the selected op amp
and the particular application. In most applications, a 30 Ω to
50 Ω resistor is sufficient. Some applications may require a
larger resistor value to reduce the noise bandwidth or possibly
limit the fault current in an overvoltage condition. Other applications may require a larger resistor value as part of an antialiasing
filter. In any case, since the THD performance is dependent on
the series resistance and the above mentioned factors, optimizing this resistor value for a given application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance connected to VINA and VINB. The degree of improvement is dependent on the resistor value and the sampling rate. For series
resistor values greater than 100 Ω, the use of a matching
resistor is encouraged.
AD9241
VINA
VINB
VREF
SENSE
REFCOM
The noise or small-signal bandwidth of the AD9241 is the same
as its full-power bandwidth. For noise sensitive applications, the
excessive bandwidth may be detrimental and the addition of a
series resistor and/or shunt capacitor can help limit the wideband noise at the A/D’s input by forming a low-pass filter. Note,
however, that the combination of this series resistance with the
equivalent input capacitance of the AD9241 should be evaluated for those time-domain applications that are sensitive to the
input signal’s absolute settling time. In applications where harmonic distortion is not a primary concern, the series resistance
may be selected in combination with the SHA’s nominal 16 pF
of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possibly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capacitance of the AD9241, a lower series resistance can be selected
to establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts as a charge reservoir, sinking or sourcing the additional
charge required by the hold capacitor, C
, further reducing
H
current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9241 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response and distortion performance.
Table I. Analog Input Configuration Summary
Input Input Input Range (V) Figure
Connection Coupling Span (V) VINA
Single-Ended DC 2 0 to 2 1 32, 33 Best for stepped input response applications, suboptimum
2 × VREF 0 to VREF 32, 33 Same as above but with improved noise performance due to
5 0 to 5 2.5 32, 33 Optimum noise performance, excellent THD performance. Requires
2 × VREF 2.5 – VREF 2.5 39 Optimum THD performance with VREF = 1, noise performance
Single-Ended AC 2 or 0 to 1 or 1 or VREF 34 Suboptimum ac performance due to input common-mode
Differential AC or 2 2 to 3 3 to 2 29–31 Optimum full-scale THD and SFDR performance well beyond
DC the A/Ds Nyquist frequency.
1
VINA and VINB can be interchanged if signal inversion is required.
2 × VREF 0 to 2 × VREF level not biased at optimum midsupply level (i.e., 2.5 V).
5 0 to 5 2.5 34 Optimum noise performance, excellent THD performance.
2 × VREF 2.5 – VREF 2.5 35 Flexible input range, Optimum THD performance with
2 × VREF 2.5 – VREF/2 2.5 + VREF/2 29–31 Same as 2 V to 3 V input range with the exception that full-scale
5 1.25 to 3.75 3.75 to 1.25 29–31 Widest dynamic range (i.e., ENOBs) due to Optimum Noise
1
2 × VREF increase in dynamic range. Headroom/settling time require-
to improves while THD performance degrades as VREF increases
2.5 + VREF to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.
to VREF = 1. Noise performance improves while THD performance
2.5 + VREF degrades as VREF increases to 2.5 V.
to to THD and SFDR performance can be traded off for better noise
2.5 + VREF/2 2.5 – VREF/2 performance.
VINB
1
# Comments
THD and noise performance, requires ± 5 V op amp.
ments of ±5 V op amp should be evaluated.
op amp with VCC > +5 V due to insufficient headroom @ 5 V.
performance.
–10–
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Page 11
AD9241
REFERENCE OPERATION
The AD9241 contains an onboard bandgap reference that provides a pin-strappable option to generate either a 1 V or 2.5 V
output. With the addition of two external resistors, the user can
generate reference voltages other than 1 V and 2.5 V. Another
alternative is to use an external reference for designs requiring
enhanced accuracy and/or drift performance. See Table II for a
summary of the pin-strapping options for the AD9241 reference
configurations.
Figure 26 shows a simplified model of the internal voltage reference of the AD9241. A pin-strappable reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier,
A1, appears on the VREF pin. The voltage on the VREF pin
determines the full-scale input span of the A/D. This input span
equals,
Full-Scale Input Span = 2
AD9241
TO
A/D
5kΩ
5kΩ
DISABLE
1V
DISABLE
5kΩ
A2
5kΩ
LOGIC
A2
A1
LOGIC
A1
×
7.5kΩ
5kΩ
VREF
CAPT
CAPB
VREF
SENSE
REFCOM
Figure 26. Equivalent Reference Circuit
The voltage appearing at the VREF pin, and the state of the
internal reference amplifier, A1, are determined by the voltage
appearing at the SENSE pin. The logic circuitry contains two
comparators that monitor the voltage at the SENSE pin. The
comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to REFCOM, the switch is
connected to the internal resistor network thus providing a
VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a
short or resistor, the switch is connected to the SENSE pin. A
short will provide a VREF of 1.0 V while an external resistor
network will provide an alternative VREF between 1.0 V and
2.5 V. The second comparator controls internal circuitry that
will disable the reference amplifier if the SENSE pin is tied to
AVDD. Disabling the reference amplifier allows the VREF pin
to be driven by an external voltage reference.
The actual reference voltages used by the internal circuitry of
the AD9241 appear on the CAPT and CAPB pins. For proper
operation when using the internal or an external reference, it is
necessary to add a capacitor network to decouple these pins.
Figure 27 shows the recommended decoupling network. This
capacitive network performs the following three functions: (1) in
conjunction with the reference amplifier, A2, it provides a low
source impedance over a large frequency range to drive the A/D
internal circuitry, (2) it provides the necessary compensation for
A2, and (3) it bandlimits the noise contribution from the reference. The turn-on time of the reference voltage appearing between CAPT and CAPB is approximately 15 ms and should be
evaluated in any power-down mode of operation.
0.1µF
CAPT
AD9241
CAPB
0.1µF
10µF
0.1µF
Figure 27. Recommended CAPT/CAPB Decoupling Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM, and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respectively where the input span can be varied between 2 V and 5 V.
Note that those samples within the pipeline A/D during any
reference transition will be corrupted and should be discarded.
Table II. Reference Configuration Summary
Reference Input Span (VINA–VINB)
Operating Mode (V p-p) Required VREF (V) Connect To
INTERNAL 2 1 SENSE VREF
INTERNAL 5 2.5 SENSE REFCOM
INTERNAL 2 ≤ SPAN ≤ 5 AND 1 ≤ VREF ≤ 2.5 AND R1 VREF AND SENSE
SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM
EXTERNAL 2 ≤ SPAN ≤ 51 ≤ VREF ≤ 2.5 SENSE AVDD
(NONDYNAMIC) VREF EXT. REF.
EXTERNAL 2 ≤ SPAN ≤ 5 CAPT and CAPB SENSE AVDD
(DYNAMIC) Externally Driven VREF REFCOM
EXT. REF. 1 CAPT
EXT. REF. 2 CAPB
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–11–
Page 12
AD9241
DRIVING THE ANALOG INPUTS
INTRODUCTION
The AD9241 has a highly flexible input structure allowing it to
interface with single-ended or differential input interface circuitry. The applications shown in sections Driving the Analog
Inputs and Reference Configurations, along with the information presented in Input and Reference Overview of this data
sheet, give examples of both single-ended and differential operation. Refer to Tables I and II for a list of the different possible
input and reference configurations and their associated figures
in the data sheet.
The optimum mode of operation, analog input range and associated interface circuitry, will be determined by the particular
applications performance requirements as well as power supply
options. For example, a dc coupled single-ended input may be
appropriate for many data acquisition and imaging applications.
Also, many communication applications requiring a dc coupled
input for proper demodulation can take advantage of the excellent single-ended distortion performance of the AD9241. The
input span should be configured so the system’s performance
objectives and the headroom requirements of the driving op amp
are simultaneously met.
Alternatively, the differential mode of operation provides the
best THD and SFDR performance over a wide frequency range.
A transformer coupled differential input should be considered
for the most demanding spectral-based applications that allow
ac coupling (e.g., Direct IF to Digital Conversion). The dc
coupled differential mode of operation also provides an enhancement in distortion and noise performance at higher input spans.
Furthermore, it allows the AD9241 to be configured for a 5 V
span using op amps specified for +5 V or ± 5 V operation.
Single-ended operation requires that VINA be ac or dc coupled
to the input signal source, while VINB of the AD9241 be biased
to the appropriate voltage corresponding to a midscale code
transition. Note that signal inversion may be easily accomplished by transposing VINA and VINB.
Differential operation requires that VINA and VINB be simultaneously driven with two equal signals that are in and out of
phase versions of the input signal. Differential operation of the
AD9241 offers the following benefits: (1) Signal swings are
smaller and therefore linearity requirements placed on the input
signal source may be easier to achieve, (2) Signal swings are
smaller and therefore may allow the use of op amps that may
otherwise have been constrained by headroom limitations,
(3) Differential operation minimizes even-order harmonic products and (4) Differential operation offers noise immunity based
on the device’s common-mode rejection as shown in Figure 16.
As is typical of most CMOS devices, exceeding the supply limits
will turn on internal parasitic diodes resulting in transient currents within the device. Figure 28 shows a simple means of clamping a dc coupled input with the addition of two series resistors and
two diodes. Note that a larger series resistor could be used to limit
the fault current through D1 and D2, but should be evaluated
since it can cause a degradation in overall performance.
R
30Ω
AVDD
S1
D2
1N4148
D1
1N4148
R
20Ω
S2
AD9243
V
CC
V
EE
Figure 28. Simple Clamping Circuit
DIFFERENTIAL MODE OF OPERATION
Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-endedto-differential conversion. A single-ended-to-differential conversion
can be realized with an RF transformer or a dual op amp differential driver. The optimum method depends on whether the
application requires the input signal to be ac or dc coupled to
AD9241.
AC Coupling via an RF Transformer
In applications that do not need to be dc coupled, an RF transformer with a center tap is the best method of generating differential inputs for the AD9241. It provides all the benefits of
operating the A/D in the differential mode without contributing
additional noise or distortion. An RF transformer has the added
benefit of providing electrical isolation between the signal source
and the A/D.
Figure 29 shows the schematic of the suggested transformer
circuit. The circuit uses a Mini-Circuits RF transformer, model
#T4-6T, which has an impedance ratio of four (turns ratio of
2). The schematic assumes that the signal source has a 50 Ω
source impedance. The 1:4 impedance ratio requires the 200 Ω
secondary termination for optimum power transfer and VSWR.
The centertap of the transformer provides a convenient means
of level-shifting the input signal to a desired common-mode
voltage. Optimum performance can be realized when the centertap
is tied to CML of the AD9241 which is the common-mode bias
level of the internal SHA.
50Ω
MINI-CIRCUITS
T4-6T
200Ω
0.1µF
VINA
CML
AD9241
VINB
Figure 29. Transformer Coupled Input
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improvement in distortion performance at reduced output power levels
and signal swings. Hence, selecting a transformer with a higher
impedance ratio (i.e., Mini-Circuits T16-6T with a 1:16 impedance ratio) effectively “steps up” the signal level, further reducing the driving requirements of the signal source.
–12–
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Page 13
AD9241
DC Coupling with Op Amps
Applications that require dc coupling can also benefit by driving the AD9241 differentially. Since the signal swing requirements of each input is reduced by a factor of two in the differential
mode, the AD9241 can be configured for a 5 V input span in a
+5 V or ±5 V system. This allows various high performance op
amps specified for +5 V and ±5 V operation to be configured in
various differential driver topologies. The optimum op amp
driver topology depends on whether the common-mode voltage
of the single-ended-input signal requires level-shifting.
Figure 30 shows a cross-coupled differential driver circuit best
suited for systems in which the common-mode signal of the
input is already biased to approximately midsupply (i.e., 2.5 V).
The common-mode voltage of the differential output is set by
the voltage applied to the “+” input of A2. The closed loop
gain of this symmetrical driver can easily be set by R
and RF.
IN
For more insight into the operation of this cross-coupled driver,
please refer to the AD8042 data sheet.
1kΩ
R
V
+VIN
F
1kΩ
V
IN
R
A1
IN
1kΩ
1kΩ
1kΩ
A2
*OPTIONAL NOISE/BAND LIMITING CAPACITOR
AD8042
AD8042
1kΩ
CML
33Ω
CF*
V
–VIN
CML
33Ω
AVDD/2
0.1µF
VINA
AD9241
VINB
CML
Figure 30. Cross-Coupled Differential Driver
The driver circuit shown in Figure 31 is best suited for systems
in which the bipolar input signal is referenced to AGND and
requires proper level shifting. This driver circuit provides the
ability to level-shift the input signal to within the commonmode range of the AD9241. The two op amps are configured as
matched difference amplifiers, with the input signal applied to
opposing inputs to provide the differential output. The commonmode offset voltage is applied to the noninverting resistor network that provides the proper level-shifting. The circuit also
employs optional diodes and pull-up resistors that may help
improve the op amps’ distortion performance by reducing their
headroom requirements. Rail-to-rail output amplifiers such as
the AD8042 have sufficient headroom and do not require these
optional components.
390Ω
AVDD
0.1µF
AD8047
390Ω
V
390Ω
IN
390Ω
390Ω
390Ω
AD8047
390Ω
AVDD
0.1µF
390Ω
220.2Ω
220.2Ω
0.1µF
V
V
CML
CML
2.5kΩ
100Ω
1µF
–VIN
+VIN
0.1µF
OP113
33Ω
33Ω
VINA
AD9241
VINB
CML
Figure 31. Differential Driver with Level-Shifting
SINGLE-ENDED MODE OF OPERATION
The AD9241 can be configured for single-ended operation
using dc or ac coupling. In either case, the input of the A/D
must be driven from an operational amplifier that will not degrade the A/D’s performance. Because the A/D operates from a
single supply, it will be necessary to level-shift ground-based
bipolar signals to comply with its input requirements. Both dc
and ac coupling provide this necessary function, but each
method results in different interface issues that may influence
the system design and performance.
DC COUPLING AND INTERFACE ISSUES
Many applications require the analog input signal to be dc
coupled to the AD9241. An operational amplifier can be configured to rescale and level-shift the input signal to make it
compatible with the selected input range of the A/D. The input
range to the A/D should be selected on the basis of system
performance objectives as well as the analog power supply
availability since this will place certain constraints on the op
amp selection.
Many of the new high performance op amps are specified for
only ±5 V operation and have limited input/output swing capabilities. Hence, the selected input range of the AD9241 should
be sensitive to the headroom requirements of the particular op
amp to prevent clipping of the signal. Also, since the output of
a dual supply amplifier can swing below –0.3 V, clamping its
output should be considered in some applications.
In some applications, it may be advantageous to use an op amp
specified for single supply +5 V operation since it will inherently limit its output swing to within the power supply rails.
Rail-to-rail output amplifiers such as the AD8041 allow the
AD9241 to be configured with larger input spans, which improves the noise performance.
REV. 0
–13–
Page 14
AD9241
If the application requires the largest single-ended input range
(i.e., 0 V to 5 V) of the AD9241, the op amp will require larger
supplies to drive it. Various high speed amplifiers in the Op
Amp Selection Guide of this data sheet can be selected to
accommodate a wide range of supply options. Once again, clamping the output of the amplifier should be considered for these
applications. Alternatively, a single-ended-to-differential op amp
driver circuit using the AD8042 could be used to achieve the
5 V input span while operating from a single +5 V supply, as
discussed in the previous section.
Two dc coupled op amp circuits using a noninverting and inverting
topology are discussed below. Although not shown, the noninverting and inverting topologies can easily be configured as part
of an antialiasing filter by using a Sallen-Key or Multiple-Feedback topology, respectively. An additional R-C network can be
inserted between the op amp’s output and the AD9241 input to
provide a real pole.
Simple Op Amp Buffer
In the simplest case, the input signal to the AD9241 will already
be biased at levels in accordance with the selected input range.
It is merely a matter of providing an adequately low source impedance for the VINA and VINB analog input pins of the A/D. Figure
32 shows the recommended configuration for a single-ended drive
using an op amp. In this case, the op amp is shown in a noninverting unity gain configuration driving the VINA pin. The
internal reference drives the VINB pin. Note that the addition of
a small series resistor of 30 Ω to 50 Ω connected to VINA and
VINB will be beneficial in nearly all cases. Refer to section
Analog Input Operation for a discussion on resistor selection.
Figure 32 shows the proper connection for a 0 V to 5 V input
range. Alternative single ended input ranges of 0 V to 2 × VREF
can also be realized with the proper configuration of VREF
(refer to the section Using the Internal Reference).
+V
5V
0V
U1
–V
2.5V
10µF
R
S
R
S
0.1µF
AD9241
VINA
VINB
VREF
SENSE
Figure 32. Single-Ended AD9241 Op Amp Drive Circuit
Op Amp with DC Level Shifting
Figure 33 shows a dc-coupled level shifting circuit employing an
op amp, A1, to sum the input signal with the desired dc offset.
Configuring the op amp in the inverting mode with the given
resistor values results in an ac signal gain of –1. If the signal
inversion is undesirable, interchange the VINA and VINB connections to reestablish the original signal polarity. The dc voltage at VREF sets the common-mode voltage of the AD9241. For
example, when VREF = 2.5 V, the output level from the op amp
will also be centered around 2.5 V. The use of ratio matched,
thin-film resistor networks will minimize gain and offset errors.
Also, an optional pull-up resistor, R
, may be used to reduce the
P
output load on VREF to ±1 mA.
500Ω*
+V
CC
0.1µF
+VREF
–VREF
AVDD
VREF
0V
RP**
*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D
**OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE
DC
500Ω*
0.1µF
500Ω*
500Ω*
NC
7
2
3
1
A1
5
4
NC
R
S
6
VINA
AD9241
R
S
VINB
Figure 33. Single-Ended Input With DC-Coupled Level Shift
AC COUPLING AND INTERFACE ISSUES
For applications where ac coupling is appropriate, the op amp’s
output can easily be level-shifted to the common-mode voltage,
V
, of the AD9241 via a coupling capacitor. This has the
CM
advantage of allowing the op amps common-mode level to be
symmetrically biased to its midsupply level (i.e., (V
+ VEE)/2).
CC
Op amps that operate symmetrically with respect to their power
supplies typically provide the best ac performance as well as the
greatest input/output span. Hence, various high speed/performance
amplifiers that are restricted to +5 V/–5 V operation and/or
specified for +5 V single-supply operation can easily be configured for the 5 V or 2 V input span of the AD9241, respectively.
The best ac distortion performance is achieved when the A/D is
configured for a 2 V input span and common-mode voltage of
2.5 V. Note that differential transformer coupling, another form of
ac coupling, should be considered for optimum ac performance.
Simple AC Interface
Figure 34 shows a typical example of an ac-coupled, singleended configuration. The bias voltage shifts the bipolar, groundreferenced input signal to approximately VREF. The value for
C1 and C2
will depend on the size of the resistor, R. The ca-
pacitors, C1 and C2, are typically a 0.1 µF ceramic and 10 µF
tantalum capacitor in parallel to achieve a low cutoff frequency
while maintaining a low impedance over a wide frequency range.
The combination of the capacitor and the resistor form a highpass filter with a high-pass –3 dB frequency determined by the
equation,
f
= 1/(2 × π × R × (C1 + C2))
–3 dB
The low impedance VREF voltage source both biases the VINB
input and provides the bias voltage for the VINA input. Figure
34 shows the VREF configured for 2.5 V. Thus the input range
C1
C2
C2
R
R
R
C1
AD9241
S
VINA
S
VINB
VREF
SENSE
+VREF
–VREF
+5V
V
0V
IN
–5V
Figure 34. AC-Coupled Input
–14–
REV. 0
Page 15
AD9241
of the A/D is 0 V to 5 V. Other input ranges could be selected
by changing VREF, but the A/D’s distortion performance will
degrade slightly as the input common-mode voltage deviates
from its optimum level of 2.5 V.
Alternative AC Interface
Figure 35 shows a flexible ac coupled circuit that can be configured for different input spans. Since the common-mode voltage
of VINA and VINB are biased to midsupply independent of
VREF, VREF can be pin-strapped or reconfigured to achieve
input spans between 2 V and 5 V p-p. The AD9241’s CMRR,
along with the symmetrical coupling R-C networks, will reject
both power supply variations and noise. The resistors, R, establish the common-mode voltage. They may have a high value (e.g.,
5 kΩ) to minimize power consumption and establish a low cutoff
frequency. The capacitors, C1
and C2, are typically a 0.1 µF
ceramic and 10 µF tantalum capacitor in parallel to achieve a
low cutoff frequency while maintaining a low impedance over a
wide frequency range. R
isolates the buffer amplifier from the
S
A/D input. The optimum performance is achieved when VINA
and VINB are driven via symmetrical networks. The high-pass
f
point can be approximated by the equation,
–3 dB
= 1/(2 × π × R/2 × (C1 + C2))
f
–3 dB
+5V
V
IN
–5V
R
+5V
Figure 35. AC-Coupled Input-Flexible Input Span, V
+5V
C1
C2
R
R
R
R
R
C1
C2
AD9241
S
VINA
S
VINB
= 2.5 V
CM
OP AMP SELECTION GUIDE
Op amp selection for the AD9241 is highly dependent on a
particular application. In general, the performance requirements
of any given application can be characterized by either time
domain or frequency domain parameters. In either case, one
should carefully select an op amp that preserves the performance
of the A/D. This task becomes challenging when one considers
the high performance capabilities of the AD9241, coupled with
other external system level requirements such as power consumption and cost.
The ability to select the optimal op amp may be further complicated by limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op
amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op
amps will be more appropriate in systems where ac-coupling is
allowable. When dc-coupling is required, op amps without
headroom constraints, such as rail-to-rail op amps or those
where larger supplies can be used, should be considered. The
following section describes some op amps currently available
from Analog Devices. The system designer is always encouraged
to contact the factory or local sales office to be updated on
Analog Devices’ latest amplifier product offerings. Highlights of
the areas where the op amps excel, and where they may limit the
performance of the AD9241, are also included.
REV. 0
–15–
AD812: Dual, 145 MHz Unity GBW, Single-Supply Cur-
rent Feedback, +5 V to ±15 V Supplies
Best Applications: Differential and/or Low Impedance Input Drivers
Limits: THD above 1 MHz
AD8011: f
= 300 MHz, +5 V or ±5 V Supplies, Current
–3 dB
Feedback
Best Applications: Single-Supply, AC/DC-Coupled,
Good AC Specs, Low Noise, Low Power (5 mW)
Limits: THD above 5 MHz, Usable Input/Output
Range
AD8013: Triple, f
= 230 MHz, +5 V or ±5 V supplies,
–3 dB
Current Feedback, Disable Function
Best Applications: 3:1 Multiplexer, Good AC Specs
Limits: THD above 5 MHz, Input Range
AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%,
±5 V Supplies
Best Applications: Best AC Specs, Low Noise,
AC-Coupled
Limits: Usable Input/Output Range, Power
Consumption
AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%,
±5 V Supplies
Best Applications: Good AC Specs, Low Noise,
AC-Coupled
Limits: THD > 5 MHz, Usable Input Range
AD8041: Rail-to-Rail, 160 MHz Unity GBW, 55 ns Settling
to 0.01%, +5 V Supply, 26 mW
Best Applications: Low Power, Single-Supply Systems, DC-Coupled, Large Input Range
Limits: Noise with 2 V Input Range
AD8042: Dual AD8041
Best Applications: Differential and/or Low Impedance Input Drivers
Limits: Noise with 2 V Input Range
REFERENCE CONFIGURATIONS
The figures associated with this section on internal and external
reference operation do not show recommended matching series
resistors for VINA and VINB for the purpose of simplicity.
Please refer to section Driving the Analog Inputs, Introduction, for
a discussion of this topic. Also, the figures do not show the
decoupling network associated with the CAPT and CAPB pins.
Please refer to the Reference Operation section for a discussion of
the internal reference circuitry and the recommended decoupling
network shown in Figure 27.
USING THE INTERNAL REFERENCE
Single-Ended Input with 0 to 2 3 VREF Range
Figure 36 shows how to connect the AD9241 for a 0 V to 2 V or
0 V to 5 V input range via pin strapping the SENSE pin. An intermediate input range of 0 to 2 × VREF can be established using
the resistor programmable configuration in Figure 38 and connecting VREF to VINB.
In either case, both the common-mode voltage and input span
are directly dependent on the value of VREF. More specifically,
the common-mode voltage is equal to VREF while the input
span is equal to 2 × VREF. Thus, the valid input range extends
from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output
will be 0000 Hex; when VINA is ≥ 2 × VREF, the digital output
will be 3FFF Hex.
Page 16
AD9241
Shorting the VREF pin directly to the SENSE pin places the
internal reference amplifier in unity-gain mode and the resultant
VREF output is 1 V. Therefore, the valid input range is 0 V to
2 V. However, shorting the SENSE pin directly to the REFCOM
pin configures the internal reference amplifier for a gain of 2.5
and the resultant VREF output is 2.5 V. Thus, the valid input
range becomes 0 V to 5 V. The VREF pin should be bypassed
to the REFCOM pin with a 10 µF tantalum capacitor in parallel
with a low-inductance 0.1 µF ceramic capacitor.
2xVREF
0V
10µF
0.1µF
SHORT FOR 0 TO 2V
INPUT SPAN
SHORT FOR 0 TO 5V
INPUT SPAN
VINA
VINB
VREF
AD9241
SENSE
REFCOM
Figure 36. Internal Reference (2 V p-p Input Span,
= 1 V, or 5 V p-p Input Span, VCM = 2.5 V)
V
CM
Single-Ended or Differential Input, VCM = 2.5 V
Figure 37 shows the single-ended configuration that gives the
best SINAD performance. To optimize dynamic specifications,
center the common-mode voltage of the analog input at
approximately 2.5 V by connecting VINB to VREF, a lowimpedance 2.5 V source. As described above, shorting the
SENSE pin directly to the REFCOM pin results in a 2.5 V
reference voltage and a 5 V p-p input span. The valid range
for input signals is 0 V to 5 V. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in
parallel with a low inductance 0.1 µF ceramic capacitor.
This reference configuration could also be used for a differential
input wherein VINA and VINB are driven via a transformer as
shown in Figure 29. In this case, the common-mode voltage,
V
, is set at midsupply by connecting the transformers center
CM
tap to CML of the AD9241. VREF can be configured for 1 V or
2.5 V by connecting SENSE to either VREF or REFCOM
respectively. Note that the valid input range for each of the
differential inputs is one half of the single-ended input and thus
becomes V
– VREF/2 to VCM + VREF/2.
CM
ternal resistors and a bypass capacitor. Use the equation,
VREF = 1 V × (1 + R1/R2),
to determine appropriate values for R1 and R2. These resistors
should be in the 2 kΩ to 100 kΩ range. For the example shown,
R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above,
the resultant reference voltage on the VREF pin is 1.5 V. This
sets the input span to be 3 V p-p. To assure stability, place a
0.1 µF ceramic capacitor in parallel with R1.
The common-mode voltage can be set to VREF by connecting
VINB to VREF to provide an input span of 0 to 2 × VREF.
Alternatively, the common-mode voltage can be set to 2.5 V
by connecting VINB to a low impedance 2.5 V source. For
the example shown, the valid input signal range for VINA is
1 V to 4 V since VINB is set to an external, low impedance
2.5 V source. The VREF pin should be bypassed to the REFCOM
pin with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor.
4V
1V
10µF
2.5V
0.1µF
R1
2.5kΩ
R2
5kΩ
1.5V
C1
0.1µF
VINA
VINB
VREF
AD9241
SENSE
REFCOM
Figure 38. Resistor Programmable Reference (3 V p-p
Input Span, V
= 2.5 V)
CM
USING AN EXTERNAL REFERENCE
Using an external reference may enhance the dc performance
of the AD9241 by improving drift and accuracy. Figures 39
through 41 show examples of how to use an external reference
with the A/D. Table III is a list of suitable voltage references
from Analog Devices. To use an external reference, the user
must disable the internal reference amplifier and drive the VREF
pin. Connecting the SENSE pin to AVDD disables the internal reference amplifier.
Table III. Suitable Voltage References
5V
0V
2.5V
10µF
0.1µF
VINA
VINB
AD9241
VREF
SENSE
REFCOM
Figure 37. Internal Reference—5 V p-p Input Span,
= 2.5 V
V
CM
Resistor Programmable Reference
Figure 38 shows an example of how to generate a reference
voltage other than 1 V or 2.5 V with the addition of two ex-
Initial Operating
Output Drift Accuracy Current
Voltage (ppm/8C) % (max) (mA)
Internal 1.00 26 1.4 N/A
AD589 1.235 10–100 1.2–2.8 50
AD1580 1.225 50–100 0.08–0.8 50
REF191 2.048 5–25 0.1–0.5 45
Internal 2.50 26 1.4 N/A
REF192 2.50 5–25 0.08–0.4 45
REF43 2.50 10–25 0.06–0.1 600
AD780 2.50 3–7 0.04–0.2 1000
The AD9241 contains an internal reference buffer, A2 (see
Figure 26), that simplifies the drive requirements of an external
reference. The external reference must be able to drive a ≈5 kΩ
(±20%) load. Note that the bandwidth of the reference buffer is
–16–
REV. 0
Page 17
AD9241
deliberately left small to minimize the reference noise contribution. As a result, it is not possible to change the reference voltage rapidly in this mode without removing the CAPT/CAPB
Decoupling Network and driving these pins directly.
Variable Input Span with V
CM
= 2.5 V
Figure 39 shows an example of the AD9241 configured for an
input span of 2 × VREF centered at 2.5 V. An external 2.5 V
reference drives the VINB pin thus setting the common-mode
voltage at 2.5 V. The input span can be independently set by a
voltage divider consisting of R1 and R2, which generates the
VREF signal. A1 buffers this resistor network and drives VREF.
Choose this op amp based on accuracy requirements. It is
essential that a minimum of a 10 µF capacitor in parallel with a
0.1 µF low inductance ceramic capacitor decouple the reference
output to ground.
2.5V+VREF
2.5V–VREF
+5V
0.1µF
2.5V
2.5V
REF
0.1µF
22µF
R1
R2
0.1µF
A1
+5V
VINA
VINB
AD9241
VREF
SENSE
Figure 39. External Reference, VCM = 2.5 V (2.5 V on VINB,
Resistor Divider to Make VREF)
Single-Ended Input with 0 to 2 3 VREF Range
Figure 40 shows an example of an external reference driving
both VINB and VREF. In this case, both the common mode
voltage and input span are directly dependent on the value of
VREF. More specifically, the common-mode voltage is equal to
VREF while the input span is equal to 2 × VREF. Thus, the
valid input range extends from 0 to 2 × VREF. For example, if
the REF191, a 2.048 external reference, was selected, the valid
input range extends from 0 V to 4.096 V. In this case, 1 LSB of
the AD9241 corresponds to 0.250 mV. It is essential that a
minimum of a 10 µF capacitor in parallel with a 0.1 µF low induc-
tance ceramic capacitor decouple the reference output to ground.
+5V
0.1µF
2xREF
0V
VREF
10µF
0.1µF
0.1µF
+5V
VINA
VINB
AD9241
VREF
SENSE
Figure 40. Input Range = 0 V to 2 × VREF
Low Cost/Power Reference
The external reference circuit shown in Figure 41 uses a low
cost 1.225 V external reference (e.g., AD580 or AD1580) along
with an op amp and transistor. The 2N2222 transistor acts in
conjunction with 1/2 of an OP282 to provide a very low impedance drive for VINB. The selected op amp need not be a high
speed op amp and may be selected based on cost, power and
accuracy.
+5V
1kΩ
7.5kΩ
3.75V
1.25V
1kΩ
1/2
OP282
AD1580
+5V
0.1µF
1kΩ
820Ω
10µF
316Ω
2N2222
0.1µF
10µF
+5V
0.1µF
1.225V
VINA
VINB
AD9241
VREF
SENSE
Figure 41. External Reference Using the AD1580 and Low
Impedance Buffer
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
The AD9241 output data is presented in positive true straight
binary for all input ranges. Table IV indicates the output data
formats for various input ranges, regardless of the selected input
range. A twos-complement output data format can be created
by inverting the MSB.
Table IV. Output Data Format
Input (V) Condition (V) Digital Output OTR
VINA –VINB < – VREF 00 0000 0000 0000 1
VINA –VINB = – VREF 00 0000 0000 0000 0
VINA –VINB = 0 10 0000 0000 0000 0
VINA –VINB = + VREF – 1 LSB 11 1111 1111 1111 0
VINA –VINB ≥ + VREF 11 1111 1111 1111 1
OTR DATA OUTPUTS
111111 1111 1111
1
111111 1111 1111
0
111111 1111 1110
0
000000 0000 0001
0
000000 0000 0000
0
000000 0000 0000
1
OTR
–FS+1/2 LSB
–FS
+FS –1 1/2 LSB
+FS
+FS –1/2 LSB–FS –1/2 LSB
Figure 42. Output Data Format
Out Of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the converter. OTR is a digital
output that is updated along with the data output corresponding
to the particular sampled analog input voltage. Hence, OTR has
the same pipeline delay (latency) as the digital data. It is LOW
when the analog input voltage is within the analog input range.
REV. 0
–17–
Page 18
AD9241
It is HIGH when the analog input voltage exceeds the input
range as shown in Figure 42. OTR will remain HIGH until the
analog input returns within the input range and another conversion is completed. By logical ANDing OTR with the MSB and
its complement, overrange high or underrange low conditions
can be detected. Table V is a truth table for the over/underrange
circuit in Figure 43, which uses NAND gates. Systems requiring
programmable gain conditioning of the AD9241 input signal
can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for
digital offset and gain calibration.
Table V. Out-of-Range Truth Table
OTR MSB Analog Input Is
0 0 In Range
0 1 In Range
1 0 Underrange
1 1 Overrange
MSB
OTR
MSB
OVER = “1”
UNDER = “1”
Figure 43. Overrange or Underrange Logic
Digital Output Driver Considerations (DRVDD)
The AD9241 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V
respectively. The AD9241 output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause glitches on the
supplies and may affect SINAD performance. Applications
requiring the AD9241 to drive large capacitive loads or large
fanout may require additional decoupling capacitors on DRVDD.
In extreme cases, external buffers or latches may be required.
Clock Input and Considerations
The AD9241 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulse width
high and low (t
and tCL) specifications for the given A/D, as
CH
defined in the Switching Specifications section at the beginning
of the data sheet, to meet the rated performance specifications.
For example, the clock input to the AD9241 operating at 1.25
MSPS may have a duty cycle between 45% to 55% to meet this
timing requirement since the minimum specified t
and tCL is
CH
360 ns. For clock rates below 1.25 MSPS, the duty cycle may
deviate from this range to the extent that both t
and tCL are
CH
satisfied.
All high speed, high resolution A/Ds are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
) due only to aperture jitter (tA) can be
IN
calculated with the following equation:
SNR = 20 log
In the equation, the rms aperture jitter, t
[1/(2 π f
10
)]
IN tA
, represents the root-
A
sum square of all the jitter sources including the clock input,
analog input signal and A/D aperture jitter specification. For
example, if a 1.0 MHz full-scale sine wave is sampled by an A/D
with a total rms jitter of 15 ps, the SNR performance of the A/D
will be limited to 80.5 dB. Undersampling applications are
particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9241. As such, supplies for clock drivers should be separated
from the A/D output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing or other method), it
should be retimed by the original clock at the last step.
Most of the power dissipated by the AD9241 is from the analog
power supply. However, lower clock speeds will slightly reduce
digital current. Figure 44 shows the relationship between power
and clock rate.
150
140
130
120
110
100
POWER – mW
90
80
70
60
5V p-p
2V p-p
6
5
43210
CLOCK RATE – MHz
78910
Figure 44. AD9241 Power Consumption vs. Clock
Frequency
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.
These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from coupling
onto the input signal. Digital signals should not be run in parallel with input signal traces, and should be routed away from the
input circuitry. While the AD9241 features separate analog and
digital ground pins, it should be treated as an analog component. The AVSS, DVSS and DRVSS pins must be joined together directly under the AD9241. A solid ground plane under
the A/D is acceptable if the power and ground return currents
are carefully managed. Alternatively, the ground plane under
–18–
REV. 0
Page 19
AD9241
0.1µF
CML
AD9241
the A/D may contain serrations to steer currents in predictable
directions where cross-coupling between analog and digital
would otherwise be unavoidable. The AD9241/EB ground layout shown in Figure 52 depicts the serrated type of arrangement. The analog and digital grounds are connected by a jumper
below the A/D.
Analog and Digital Supply Decoupling
The AD9241 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals.
120
100
80
PSRR – dBFS
60
40
DVDD
FREQUENCY – kHz
AVDD
100101
1000
Figure 45. PSRR vs. Frequency
Figure 45 shows the power supply rejection ratio vs. frequency
for a 200 mV p-p ripple applied to both AVDD and DVDD.
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
possible. Figure 46 shows the recommended decoupling for the
analog supplies; 0.1 µF ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Note
that the AVDD and AVSS pins are co-located on the AD9241
to simplify the layout of the decoupling capacitors and provide
the shortest possible PCB trace lengths. The AD9241/EB power
plane layout shown in Figure 53 depicts a typical arrangement
using a multilayer PCB.
The CML is an internal analog bias point used internally by the
AD9241. This pin must be decoupled with at least a 0.1 µF
capacitor as shown in Figure 47. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is to
be used for any external biasing.
Figure 47. CML Decoupling
The digital activity on the AD9241 chip falls into two general
categories: correction logic and output drivers. The internal
correction logic draws relatively small surges of current, primarily during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits: large capacitive loads are to be avoided. Note that
the internal correction logic of the AD9241 is referenced DVDD
while the output drivers are referenced to DRVDD.
The decoupling shown in Figure 48 (a 0.1 µF ceramic chip
capacitor) is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionally and/or using external buffers/
latches.
DVDD
DRVDD
DVSS
AD9241
0.1µF
DRVSS
0.1µF
Figure 48. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. Refer to the AD9241/EB schematic
and layouts in Figures 49–53 for more information regarding the
placement of decoupling capacitors.
REV. 0
AVDD
0.1µF
AVSS
AD9241
AVDD
0.1µF
AVSS
Figure 46. Analog Supply Decoupling
–19–
Page 20
AD9241
2
3
AD817
V
EE
U3
A
R7
1kΩ
C16
0.1µF
R8
316Ω
A
Q1
2N2222
A
C17
10µF
16V
A
C18
0.1µF
R6
820Ω
+5VA
TP25
R4
50Ω
JP10
R3
15kΩ
A
C12
0.1µF
A
R5
10kΩ
C13
10µF
16V
A
V
IN
V
OUT
GND
6
2
4
REF43
A
EXTERNAL REFERENCE DRIVE
U2
VCC
C14
0.1µF
6
7
4
V
CC
A
C15
0.1µF
C19
0.1µF
6
7
2
3
4
V
CC
AD845
A
C21
0.1µF
V
EE
U4
A
R11
500Ω
C20
0.1µF
A
R14
10kΩ
A
CW
R13
10kΩ
BUFFER
JP23
R10
500Ω
1
2
3
A
B
JP24
DIRECT COUPLE OPTION
C38
?
AC COUPLE OPTION
JP14
JP13
A
R9
50Ω
A
J1
VIN
R12
33Ω
R15
33Ω
+5VA
A
D2
1N5711
D1
1N5711
AC COUPLE OPTION
+5VA
A
D4
1N5711
D3
1N5711
R39
?
2J8
4J8
6J8
8J8
10 J8
12 J8
14 J8
16 J8
18 J8
20 J8
22 J8
24
J8
26
J8
39J828J829
J8
30J831
J8
32J834 J8
35J836J837J838 J8
NC
NC
NC
+5VA
C26
0.1µF
U8
DECOUPLING
A
11
10
U8
98
U8
3
4
U8
1
2
U8
13
12
U8
A
+5VD
C22
0.1µF
U5
DECOUPLING
5
6
U5
12
U5
3
4
U5
SPARE GATES
JP18
JP17
R20
22.1Ω
13
J8
TP10
R21
22.1Ω
11
J8
TP11
R22
22.1Ω
9
J8
TP12
R23
22.1Ω
7
J8
TP13
R24
22.1Ω
5J8
TP14
R25
22.1Ω
3J8
TP15
R26
22.1Ω
1
J8
TP16
R27
22.1Ω
33
J8
TP3
R28
22.1Ω
27
J8
TP4
R29
22.1Ω
25
J8
TP5
R30
22.1Ω
23
J8
TP17
R31
22.1Ω
21 J8
TP6
R32
22.1Ω
19
J8
TP7
R33
22.1Ω
17
J8
TP8
R34
22.1Ω
15
J8
TP9
11121314151617
18
C24
0.1µF
+DRVDD
74HC541N
20
Y7Y6Y5Y4Y3Y2Y1
Y0
+5VD
U6
G1G2A7A6A5A4A3A2A1A0GND
1199876543
2
10
D7D8D9
D10
D11
D12
D13
11121314151617
18
C25
0.1µF
+DRVDD
74HC541N
20
Y7Y6Y5Y4Y3Y2Y1
Y0
+5VD
U7
G1G2A7A6A5A4A3A2A1A0GND
1199876543
2
10
CLK
D0D1D2D3D4D5D6
A
J9
CLKIN
U5
13 12
U5
98
JP15
CLKB
JP16
CLK
U5
11 10
U8
65
C23
0.1µF
TP2
A
R19
50Ω
R40?R41
?
A
R16
5kΩ
+5VA
R18
5kΩ
R17
1kΩ
CW
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
BIT13
BIT14
OTRVREF
SENSE
REFCOM
CAPT
CAPB
CML
VINA
VINB
U1
AD9241MQFP
AVDD2
AVDD1
AVSS2
AVSS1
32
31
33
37
36
394142
28
42
29
TP24
C8
0.1µF
A
A
JP7
+5VA
C9
0.1µF
A
252423222120191817161514131211
D13
D12
D11
D10D9D8D7D6D5D4D3D2D1D0
5
7
ADC_CLK
C43
0.1µF
C10
0.1µF
C11
0.1µF
+DRVDD
C2
0.1µF
+
C1
10µF
16V
A
JP6
JP3
+5VA
JP4
JP5
R1
10kΩ
R2
10kΩ
A
C41
0.1µF
JP2
TPC
TPD
A
C6
0.1µF
+
C5
10µF
16V
C3
0.1µF
C4
0.1µF
A
CML
C7
0.1µF
A
VINA2
VINA1
JP11
BA
321
VINB2
VINB1
JP12
BA
321
JP8
+5VD
D13
ADC_CLK
A
DRVSS
DVSS
DRVDD
DVDD
T1
6
5
4
1
2
3
PRI SEC
R36
200Ω
A
C36
15pF
R37
33Ω
R38
33Ω
VINA1
VINB1
A
C37
15pF
JP21
TPC
JP22
TPD
JP1
CML
C42
0.1µF
R35
50Ω
A
A
J10
AIN
A
TP26
SJ6
40
J8
AA
+
C28
22µF
25V
C32
0.1µF
L1
TP18
J2+5A
AA
+
C29
22µF
25V
C33
0.1µF
L2
TP19
J3+5D
AA
+
C30
22µF
25V
C34
0.1µF
L3
TP20
J4+VCC
AA
+
C31
22µF
25V
C35
0.1µF
L4
TP21
J5–VEE
+C39
22µF
25V
C40
0.1µF
L5
TP27
J11
+5_OR _+3
+DRVDD
VEE
VCC
+5VD
+5VA
J6
TP23
J7
A
JG1-WIRE ETCH
CKT SIDE
5 SETS OF
PADS TO
CONNECT
GROUNDS
JG1
SJ1
SJ2
SJ3
SJ4
SJ5
AGND
DGND
TP22
TP1
1
63
CLK
VINA2
VINB2
TPD
TPD
TPC
74HC14
74HC04
Figure 49. Evaluation Board Schematic
–20–
REV. 0
Page 21
AD9241
Figure 50. Evaluation Board Component Side Layout (Not to Scale)
REV. 0
Figure 51. Evaluation Board Solder Side Layout (Not to Scale)
–21–
Page 22
AD9241
Figure 52. Evaluation Board Ground Plane Layout (Not to Scale)
Figure 53. Evaluation Board Power Plane Layout (Not to Scale)
–22–
REV. 0
Page 23
1.03 (0.041)
0.73 (0.029)
SEATING
PLANE
OUTLINE DIMENSIONS
Dimensions shown in mm and (inches).
44-Pin Metric Quad Flatpack (MQFP)
(S-44)
13.45 (0.529)
44
12.95 (0.510)
10.1 (0.398)
9.90 (0.390)
TOP VIEW
(PINS DOWN)
34
33
2.45 (0.096)
MAX
0
°
MIN
1
AD9241
8.45 (0.333)
8.3 (0.327)
0.25 (0.01)
MIN
0.23 (0.009)
0.13 (0.005)
2.1 (0.083)
1.95 (0.077)
11
12
0.8 (0.031)
BSC
23
22
0.45 (0.018)
0.3 (0.012)
REV. 0
–23–
Page 24
C2961–10–4/97PRINTED IN U.S.A.
–24–
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